Semiconductor structure and forming method thereof

Abstract

A method of forming a semiconductor structure includes forming a first gate dielectric and a second gate dielectric on a first semiconductor channel region and a second semiconductor channel region, the second semiconductor channel region overlapping the first semiconductor channel region; a first dipole film is formed on the first gate dielectric, where the first dipole film includes a first dipole dopant of the first type, and a second dipole film is formed on the second gate dielectric. A drive-in process is performed to drive dipole dopants in the first dipole film and the second dipole film into the first gate dielectric and the second gate dielectric, respectively. And removing the first dipole film and the second dipole film. A gate electrode is formed on the first gate dielectric and the second gate dielectric to form a first transistor and a second transistor. The embodiment of the invention also relates to a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor structures and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements on the semiconductor substrate.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise and should be addressed. Summary of the invention

[0004] An embodiment of the present disclosure provides a method for forming a semiconductor structure, comprising: forming a first semiconductor channel region and a second semiconductor channel region, wherein the second semiconductor channel region overlaps with the first semiconductor channel region; forming a first gate dielectric on the first semiconductor channel region; forming a second gate dielectric on the second semiconductor channel region; forming a first dipole film on the first gate dielectric, wherein the first dipole film includes a first dipole dopant of a first type; forming a second dipole film on the second gate dielectric, wherein the second dipole film includes a second dipole dopant of a second type opposite to the first type; performing a drive-in process to drive the dipole dopants in the first dipole film and the second dipole film into the first gate dielectric and the second gate dielectric, respectively; removing the first dipole film and the second dipole film; and forming gate electrodes on the first gate dielectric and the second gate dielectric, wherein the first gate dielectric and a lower portion of the gate electrode are included in a first transistor, and the second gate dielectric and an upper portion of the gate electrode are included in a second transistor.

[0005] Another embodiment of the present disclosure provides a semiconductor structure, comprising:

[0006] a lower transistor comprising: a first semiconductor channel region; a first gate dielectric located on the first semiconductor channel region; and a first portion of a gate electrode located on the first gate dielectric; and

[0007] An upper transistor, wherein the lower transistor and the upper transistor include an n-type transistor and a p-type transistor, and wherein the upper transistor includes: a second semiconductor channel region overlapping the first semiconductor channel region; a second gate dielectric located on the second semiconductor channel region; and a second portion of the gate electrode, the second portion of the gate electrode being located on the second gate dielectric, wherein the first portion and the second portion are portions of a continuous gate electrode.

[0008] Another embodiment of the present disclosure provides a semiconductor structure, comprising:

[0009] a lower transistor comprising: a first semiconductor channel region; a first gate dielectric located on the first semiconductor channel region; and a first source / drain region connected to the first semiconductor channel region; and

[0010] an upper transistor, the upper transistor comprising: a second semiconductor channel region overlapping the first semiconductor channel region; a second gate dielectric located on the second semiconductor channel region; and a second source / drain region, the second source / drain region connected to the second semiconductor channel region, wherein the first source / drain region and the second source / drain region have opposite conductivity types; and

[0011] A common gate electrode continuously extends from a first level lower than the first semiconductor channel region to a second level higher than the second semiconductor channel region, wherein the common gate electrode includes an intermediate bandgap work function layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0013] Figure 1 A perspective view of an example complementary field effect transistor (CFET) is shown in accordance with some embodiments.

[0014] Figures 2 to 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B and Fig.23A , Fig. 23B , Fig.24A and Fig. 24B is a diagram of an intermediate stage in the fabrication of a CFET according to some embodiments.

[0015] Figures 9 to 15A and Fig. 15B is a diagram of an intermediate stage in the fabrication of a gate stack of a CFET according to some embodiments.

[0016] Figures 16 to 22A and Fig. 22B is a diagram of an intermediate stage in the fabrication of a gate stack of a CFET according to some embodiments.

[0017] Fig.25 The relationship between the effective work function, threshold voltage, and dipole doping for a PFET and an NFET according to some embodiments is shown.

[0018] Fig.26 A dipole dopant profile in a gate stack is shown in accordance with some embodiments.

[0019] Fig. 27 and Fig.28 Dipole films in different CFETs are shown according to some embodiments.

[0020] Figure 29 to Figure 32 A CFET according to an alternative embodiment is shown.

[0021] Fig.33 A flow chart for forming a CFET is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0023] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0024] A complementary field effect transistor (CFET) structure and a method for forming the same are provided. Throughout the description, the terms "FET" and "transistor" are used interchangeably. According to some embodiments, the CFET structure includes a plurality of NFETs and PFETs formed to have a plurality of threshold voltages. Each of the plurality of common p-type metal gates is shared by a pair of FETs (including an NFET and a PFET) in the same CFET structure. N-type dipole dopants and p-type dopants are used to optimize threshold voltage (Vt) adjustment. The threshold voltages of the PFET and the NFET are adjusted by doping the gate dielectrics of the NFET and the PFET with different dipole dopants.

[0025] It should be understood that although gate-all-around (GAA) transistors (such as nanostructure FETs) are discussed, the concepts of the present disclosure may also be applied to the formation of other types of transistors, such as planar transistors, fin field effect transistors (FinFETs), etc.

[0026] Figure 1 An example of a CFET 10 (including FETs (transistors) 10U and 10L) according to some embodiments is shown. Figure 1 is a three-dimensional view in which some components of the CFET are omitted for clarity of illustration.

[0027] The CFET includes a plurality of vertically stacked FETs. For example, the CFET may include a lower nanostructure FET 10L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type / n-type), the second device type being opposite to the first device type. The nanostructure FETs 10U and 10L include a semiconductor nanostructure 26' (including a lower semiconductor nanostructure 26'L and an upper semiconductor nanostructure 26'U), wherein the semiconductor nanostructure 26' is used as a channel region of the nanostructure FET. The lower semiconductor nanostructure 26'L is used for the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26'U is used for the upper nanostructure FET 10U.

[0028] The gate dielectric 78 surrounds the corresponding semiconductor nanostructure 26'. The gate electrode 80 (including the lower gate electrode 80L and the upper gate electrode 80U) is located above the gate dielectric 78. The source / drain region 62 (including the lower source / drain region 62L and the upper source / drain region 62U) is disposed on opposite sides of the gate dielectric 78 and the corresponding gate electrode 80. The source / drain region may refer to a source or a drain, either individually or collectively, depending on the context. An isolation feature (not shown) may be formed to separate the desired source / drain region 62 and / or the desired gate electrode 80.

[0029] Figure 1Reference cross sections used in subsequent figures are also shown. Cross section AA' is a vertical cross section that is parallel to the longitudinal axis of the semiconductor nanostructure 26' of the CFET and in the direction of current flow, for example, between the source / drain regions 62 of the CFET. Cross section BB' is a vertical cross section that is perpendicular to cross section AA' and along the longitudinal axis of the gate electrode 80 of the CFET. For clarity, subsequent figures may refer to these reference cross sections.

[0030] Figures 2 to 24A and Fig. 24B A cross-sectional view showing an intermediate stage in the formation of a CFET according to some embodiments (eg Figure 1 The corresponding process is also Fig.33 In the following discussion, unless otherwise indicated, a figure with a number followed by the letter "A" indicates a process flow along the same Figure 1 A vertical cross-sectional view of a cross section similar to the vertical reference cross-section AA' in FIG. A figure followed by the letter "B" shows a cross section along the same plane as Figure 1 A cross-sectional view of a similar cross section to the perpendicular reference cross section BB'.

[0031] exist Figure 2 In the present invention, a wafer 2 including a substrate 20 is provided. The substrate 20 may be a doped (e.g., with a p-type or n-type dopant) or undoped semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc. The SOI substrate may include a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. An insulator layer is provided on a substrate such as a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 20 may include silicon, germanium, carbon-doped silicon, III-V compound semiconductors, etc., or a combination thereof.

[0032] A multilayer stack 22 is formed over the substrate 20. The corresponding process is shown as follows Fig.33 Process 202 in process flow 200 is shown. Multilayer stack 22 includes alternating dummy semiconductor layers 24 (including dummy semiconductor layers 24A and 24B) and semiconductor layers 26 (including lower semiconductor layer 26L and upper semiconductor layer 26U). Lower semiconductor layer 26L and upper semiconductor layer 26U are used to form lower FET and upper FET, respectively.

[0033] Appropriate wells (not separately shown) may be formed in the lower semiconductor layer 26L and the upper semiconductor layer 26U. For example, the semiconductor layers 26L and 26U may be in-situ doped (when epitaxially grown) and / or implanted to a desired conductivity type.

[0034] In the illustrated example, the multilayer stack 22 includes six dummy semiconductor layers 24 and six semiconductor layers 26. It should be understood that the multilayer stack 22 may include any number of dummy semiconductor layers 24 and semiconductor layers 26. Each layer of the multilayer stack 22 may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by a process such as a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process, etc.

[0035] The dummy semiconductor layer 24A is formed of a first semiconductor material, and the dummy semiconductor layer 24B is formed of a second semiconductor material different from the first semiconductor material. The first semiconductor material and the second semiconductor material can be selected from candidate semiconductor materials of the substrate 20. The first semiconductor material and the second semiconductor material have high etching selectivity to each other. Thus, in subsequent processes, the dummy semiconductor layer 24B can be removed at a faster rate than the dummy semiconductor layer 24A.

[0036] The semiconductor layer 26 (including the lower semiconductor layer 26L and the upper semiconductor layer 26U) is formed of one or more semiconductor materials. The semiconductor material can be selected from the candidate semiconductor material of the substrate 20. The lower semiconductor layer 26L and the upper semiconductor layer 26U can be formed of the same semiconductor material, or can be formed of different semiconductor materials.

[0037] In some embodiments, the dummy semiconductor layer 24A is formed of or includes silicon germanium, the semiconductor layer 26 is formed of silicon, and the dummy semiconductor layer 24B may be formed of germanium or silicon germanium having a higher atomic percentage of germanium than that of the dummy semiconductor layer 24A.

[0038] exist Figure 3 In the embodiment, the multilayer stack 22 and the substrate 20 are patterned to form semiconductor strips 28. The corresponding process is shown as follows Fig.33Process 204 in the process flow 200 shown. Each semiconductor strip 28 includes a semiconductor strip 20' (part of the original substrate 20) and a multilayer stack 22', which is the remaining portion of the multilayer stack 22. The remaining portion 22' of the multilayer stack 22 is referred to as a nanostructure hereinafter, using the corresponding reference numeral followed by a "'" symbol. Therefore, the multilayer stack 22' includes a pseudo nanostructure 24'A, a pseudo nanostructure 24'B, a lower semiconductor nanostructure 26'L, an intermediate semiconductor nanostructure 26'M, and an upper semiconductor nanostructure 26'U. Etching can be performed by any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. Etching can be anisotropic. The pseudo nanostructure 24'A and the pseudo nanostructure 24'B can also be collectively referred to as a pseudo nanostructure 24'. The lower semiconductor nanostructure 26'L and the upper semiconductor nanostructure 26'U can also be collectively referred to as a semiconductor nanostructure 26'.

[0039] The lower semiconductor nanostructure 26'L will be used as the channel region of the lower nanostructure FET of the CFET. The upper semiconductor nanostructure 26'U will be used as the channel region of the upper nanostructure FET of the CFET. The intermediate semiconductor nanostructure 26'M is a semiconductor nanostructure 26' that is immediately above / below (e.g., in contact with the pseudo nanostructure 24'B) the pseudo nanostructure 24'B. The intermediate semiconductor nanostructure 26'M can be used for isolation and can be used or not used as the channel region of the CFET. Subsequently, the pseudo nanostructure 24'B will be replaced by the isolation structure. The isolation structure and the intermediate semiconductor nanostructure 26'M can define the boundaries of the lower nanostructure FET and the upper nanostructure FET.

[0040] exist Figure 4 In the embodiment, isolation regions 32 are formed above substrate 20 and between adjacent semiconductor strips 28. The corresponding process is shown as follows: Fig.33 Process 205 in process flow 200 is shown. Isolation region 32 may include a dielectric liner and a dielectric material located above the dielectric liner. Then, isolation region 32 is recessed. Some upper portions of semiconductor strips 28 (including multilayer stack 22 ′) protrude higher than the remaining isolation region 32 to form protruding fins 34.

[0041] Then, a dummy dielectric layer 36 is formed on the protruding fin 34. The corresponding process is shown as follows. Fig.33 Process 206 is shown in process flow 200. Dummy dielectric layer 36 may be formed of or include, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques.

[0042] A dummy gate layer 38 is formed over the dummy dielectric layer 36. The corresponding process is shown as follows. Fig.33 Process 208 in process flow 200 is shown. The dummy gate layer 38 may be deposited, for example, by physical vapor deposition (PVD), CVD, or other techniques, and then planarized, such as by a CMP process. The material of the dummy gate layer 38 may be conductive or non-conductive, and may be selected from a group including amorphous silicon, polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), etc. A mask layer 40 is formed over the planarized dummy gate layer 38, and may include, for example, silicon nitride, silicon oxynitride, etc.

[0043] Next, the mask layer 40 may be patterned by photolithography and etching processes to form a mask, which is then used to etch and pattern the dummy gate layer 38 and possibly the dummy dielectric layer 36 . Figure 5 The mask layer 40 , the dummy gate layer 38 , and the remaining portion of the dummy dielectric layer 36 form a dummy gate stack 42 .

[0044] exist Figure 5 In the embodiment, gate spacers 44 are formed over the multilayer stack 22' and on the exposed sidewalls of the dummy gate stack 42. The gate spacers 44 may be formed by conformally forming one or more dielectric layers and then anisotropically etching the dielectric layers. Applicable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, etc., which may be formed by deposition processes such as CVD, ALD, etc.

[0045] Then, source / drain recesses 46 are formed in semiconductor strips 28. The corresponding process is shown as follows. Fig.33 The process 210 in the process flow 200 is shown. The source / drain recess 46 is formed by etching and can extend through the multilayer stack 22' and into the semiconductor strip 20'. The bottom surface of the source / drain recess 46 can be located at the isolation region 32 ( Figure 4 ) above, below, or flush with the top surface of the isolation region 32. During the etching process, the gate spacers 44 and the dummy gate stack 42 mask portions of the semiconductor strips 28. The etching may include a single etching process or multiple etching processes. When the source / drain recesses 46 reach a desired depth, a timed etching process may be used to stop the etching of the source / drain recesses 46.

[0046] Then, the pseudo-nanostructure 24 ′A is recessed laterally, and a dielectric material is filled into the corresponding groove to form an inner spacer 54 , which is a dielectric spacer. Figure 6 The resulting structure is shown in . A dielectric isolation layer 56 is also formed to replace the pseudo nanostructure 24 'B.

[0047] Next, in the source / drain recess 46 ( Figure 5 ) forms a lower epitaxial source / drain region 62L in the lower portion of the . The corresponding process is shown as follows Fig.33 Process 212 in process flow 200 is shown. The lower epitaxial source / drain region 62L contacts the lower semiconductor nanostructure 26'L and does not contact the upper semiconductor nanostructure 26'U. The inner spacer 54 electrically insulates the lower epitaxial source / drain region 62L from the dummy nanostructure 24'A, which will be replaced by a replacement gate in a subsequent process.

[0048] The lower epitaxial source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the corresponding material may include silicon or carbon-doped silicon, which are doped with n-type dopants such as phosphorus, arsenic, etc. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the corresponding material may include silicon or silicon germanium, which are doped with p-type dopants such as boron, indium, etc. The lower epitaxial source / drain region 62L may be in-situ doped and may or may not be implanted with the corresponding p-type or n-type dopant.

[0049] A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed. The first CESL 66 may be formed of a dielectric material having a high etch selectivity to the etching of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which may be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 68 may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 68 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass, undoped silicate glass (USG), silicon oxide, etc.

[0050] The formation process may include depositing a conformal CESL layer, depositing a material for the first ILD 68, followed by a planarization process, and then an etch-back process. In some embodiments, the first ILD 68 is first etched, leaving the unetched first CESL 66. An anisotropic etching process is then performed to remove a portion of the first CESL 66 that is above the recessed first ILD 68. After the recess, the sidewalls of the upper semiconductor nanostructure 26'U are exposed.

[0051] Next, an upper epitaxial source / drain region 62U is formed in the upper portion of the source / drain recess 46. The corresponding process is shown as follows. Fig.33Process 214 of process flow 200 is shown. Depending on the desired conductivity type of upper epitaxial source / drain region 62A, the material of upper epitaxial source / drain region 62U may be selected from the same candidate group of materials used to form lower epitaxial source / drain region 62L.

[0052] The conductivity type of the upper epitaxial source / drain region 62U may be opposite to the conductivity type of the lower epitaxial source / drain region 62L. In other words, the upper epitaxial source / drain region 62U may be oppositely doped to the lower epitaxial source / drain region 62L. The upper epitaxial source / drain region 62U may be doped in situ, and / or may be implanted with n-type or p-type dopants.

[0053] Next, a second CESL 70 and a second ILD 72 are formed. The materials and formation methods may be similar to those of the first CESL 66 and the first ILD 68, respectively, and will not be discussed in detail herein. The formation process may include depositing layers for the second CESL 70 and the second ILD 72, and performing a planarization process to remove excess portions of the respective layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacers 44, and the dummy gate stack 42 are coplanar (within process variations). The planarization process may remove the mask 40, or may not remove the hard mask 40.

[0054] like Fig. 7A and Figure 7B As shown, the dummy gate stack 42 is then removed in one or more etching processes to form recesses 74. Each recess 74 exposes and / or is located in the multilayer stack 22' ( Figure 6 ) part. The corresponding process is shown as Fig.33 Process 216 in process flow 200 is shown.

[0055] Then, the pseudo nanostructure 24'A is removed by etching ( Figure 6 ) so that the groove 74 extends between the semiconductor nanostructures 26'. The corresponding process is also shown as Fig.33 Process 216 in the process flow 200 shown. In the etching process, the pseudo nanostructure 24'A is etched at a faster rate than the semiconductor nanostructure 26', the dielectric isolation layer 56, and the internal spacer 54. The etching may be isotropic. For example, when the pseudo nanostructure 24'A is formed of silicon germanium and the semiconductor nanostructure 26' is formed of silicon, the etching process may include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0056] exist Fig. 8A and Figure 8BIn the embodiment, the gate dielectric 78 is formed in the recess 74 and on the exposed semiconductor nanostructure 26'. The corresponding process is shown as follows Fig.33 Process 218 of process flow 200 is shown. A gate dielectric 78 is formed on the exposed surfaces of the exposed features including the semiconductor nanostructure 26' and the gate spacers 44. The gate dielectric 78 wraps around all (eg, four) sides of the semiconductor nanostructure 26'.

[0057] Figures 9 to 14 and Fig.15A Details for forming gate dielectric 78 and common gate electrode 80 (including 80U and 80L) are shown in accordance with some embodiments. Fig. 9 , three device regions 400, 500 and 600 are shown. Each device region is used to form a CFET including an upper FET and a lower FET. Each device region 400, 500 and 600 can be obtained from Figure 8B The region 86 shown is obtained. In the example shown, the upper FETs to be formed are PFETs having threshold voltages different from each other, and the lower FETs to be formed are NFETs having threshold voltages different from each other. The PFETs and NFETs in each of the device regions 400, 500, and 600 will share a common gate electrode, which may have a mid-gap work function.

[0058] refer to Fig. 9 , the gate dielectric 78 surrounds the nanostructures 26'U, 26'M and 26'L. The gate dielectrics 78 in the device regions 400, 500 and 600 are formed in a common process. For clarity, the gate dielectrics 78 are labeled as 78-400U and 78-400L, 78-500U and 78-500L, and 78-600U and 78-600L, and the suffixes are used to identify their corresponding device regions and their corresponding positions (upper "U" or lower "L"). Each gate dielectric 78 may include an interface layer 78IL, which may include an oxide, such as silicon oxide. The interface layer 78IL may have a thickness in a range between about 0.5nm and about 2nm. The interface layer 78IL may be formed by a thermal oxidation process and / or a deposition process.

[0059] The gate dielectric 78 may further include a high-k dielectric layer 78HK having a high dielectric constant (high-k) value greater than, for example, about 7.0, about 21, or more. Accordingly, the high-k dielectric layer 78HK is also identified as 78HK-400U and 78HK-400L, 78HK-500U and 78HK-500L, and 78HK-600U and 78HK-600L.

[0060] The high-k dielectric layer 78HK may be formed of or include a metal oxide or silicate of a metal selected from hafnium, zirconium, barium, titanium, lead, and combinations thereof. The formation method of the high-k dielectric layer 78HK may be selected from molecular beam deposition (MBD), ALD, PECVD, etc. The high-k dielectric layer 78HK may have a thickness in a range between about 1 nm and about 5 nm.

[0061] Dipolar films 82-1, 82-2 and 82-3 are deposited on the gate dielectric 78 in the device regions 400, 500 and 600, respectively. The corresponding process is shown as Fig.33 Process 220 in process flow 200 is shown. The dipole films 82-1, 82-2, and 82-3 may be formed by multiple conformal deposition processes and multiple patterning processes. The thickness of the dipole films 82-1, 82-2, and 82-3 may be in a range between about 0.3 nm and about 1.5 nm.

[0062] The dipole films 82-1, 82-2, and 82-3 include n-type dipole dopants, which, when doped into the gate dielectric of an n-type FET, can reduce the effective work function and thereby reduce the threshold voltage of the corresponding n-type FET. According to some embodiments, the dipole films 82-1, 82-2, and 82-3 can include a material selected from one or more of oxides, nitrides, and / or carbides of n-type dipole dopants such as La, Sr, Y, Er, Sc, Mg, etc., or combinations thereof.

[0063] The dipole films 82-1, 82-2 and 82-3 may have different dipole dopant concentrations DDC-1, DDC-2 and DDC-3, respectively. According to some embodiments, the dipole dopant concentrations DDC-1, DDC-2 and DDC-3 are getting higher, for example, with the relationship DDC-2=(2*DDC-1)~(2.5*DDC-1) and DDC-3=(3.5*DDC-1)~(4*DDC-1). Alternatively, the dipole films 82-1, 82-2 and 82-3 may have the same dipole dopant concentration and the same (or different) dipole dopants, wherein the dipole films 82-1, 82-2 and 82-3 are getting thicker.

[0064] refer to Fig.10 , a dummy filling region 84 is formed in the device regions 400, 500 and 600, and the dummy filling region 84 is a sacrificial region. The corresponding process is shown as follows Fig.33 In the process flow 200 shown in FIG. 222, according to some embodiments, the dummy fill region 84 is formed by Fig. 8A , Figure 8B and Fig.10The exposed parts of the structure shown are formed of a material with high etch selectivity. For example, the dummy fill region 84 can be formed of SiN, SiOC, SiO, SiOCN, SiCN, AlO, AlN, CoN, etc. The formation process may include depositing a fill material to completely fill the groove 74 ( Figure 8B ), a planarization process is performed to make the top surface of the filling material flush, and the filling material is etched back. The etching process is controlled so that the top surface of the dummy filling region 84 is located at a level between the top surface level and the bottom surface level of the dielectric isolation layer 56, and the top surface may be slightly higher or lower. Within the process variation, the dummy filling region 84 may have a flat top surface.

[0065] Next, if Fig.11 As shown, an isotropic etching process is performed. The etching process can be an isotropic wet etching process or a dry etching process. The etching chemistry is selected to etch the dipole films 82-1, 82-2 and 82-3, and the etching stops on the high-k dielectric layer 78HK. The corresponding process is shown as Fig.33 Process 224 in the process flow 200 is shown. Therefore, portions of the dipole films 82-1, 82-2, and 82-3 on the upper semiconductor nanostructure 26'U and the upper one of the middle semiconductor nanostructures 26'M are removed. Portions of the dipole films 82-1, 82-2, and 82-3 on the lower semiconductor nanostructure 26'L and the lower one of the middle semiconductor nanostructures 26'M are protected from being removed.

[0066] exist Fig.12 In FIG. 4 , dipole films 82-4, 82-5 and 82-6 are deposited on gate dielectric 78 in device regions 400, 500 and 600, respectively. The corresponding process is shown as follows: Fig.33 Process 226 of process flow 200 is shown. Hereinafter, dipole films 82-1, 82-2, 82-3, 82-4, 82-5, and 82-6 are referred to individually and collectively as dipole films 82.

[0067] The dipole films 82-4, 82-5, and 82-6 include a p-type dipole dopant, which, when doped into the gate dielectric of a p-type FET, can increase the effective work function and thereby reduce the threshold voltage of the corresponding p-type FET. According to some embodiments, the dipole films 82-4, 82-5, and 82-6 can include a material selected from one or more of oxides, nitrides, and / or carbides of a p-type dipole dopant such as Al, Ga, Zn, Ti, Ta, etc., or a combination thereof.

[0068] The dipole films 82-4, 82-5 and 82-6 can be formed by multiple conformal deposition processes (such as ALD, CVD, etc.) and multiple patterning processes. The dipole films 82-4, 82-5 and 82-6 have different dipole dopant concentrations DDC-4, DDC-5 and DDC-6, respectively. Throughout the description, the dipole dopant concentrations DDC-1, DDC-2, DDC-3, DDC-4, DDC-5 and DDC-6 are collectively referred to as dipole concentrations DDC. According to some embodiments, the dipole dopant concentrations DDC-4, DDC-5 and DDC-6 are getting higher and higher, for example, with the relationship DDC-5 = (2*DDC-4) ~ (2.5*DDC-4) and DDC-6 = (3.5*DDC-4) ~ (4*DDC-4). Alternatively, the dipole films 82 - 4 , 82 - 5 , and 82 - 6 may have the same dipole dopant concentration, with the dipole films 82 - 4 , 82 - 5 , and 82 - 6 becoming increasingly thicker.

[0069] In a subsequent process, the dummy filling region 84 is removed to expose the dipole films 82-1, 82-2 and 82-3. The corresponding process is shown as follows Fig.33 Process 228 in process flow 200 is shown. Fig.13 The resulting structure is shown in FIG. On the dummy fill region 84, there are some horizontal portions of the dipole film material. These portions of the dipole film material can be removed by an anisotropic etching process or a physical removal process (which is anisotropic) such as sputtering, where, for example, argon gas can be used. After removing the dummy fill region 84, all of the dipole films 82-1, 82-2, 82-3, 82-4, 82-5, and 82-6 are exposed.

[0070] Further references Fig.13 , an annealing process 88 is performed to drive the dipole dopants in the dipole film 82 into the corresponding underlying high-k dielectric layer 78HK. The corresponding process is shown as Fig.33 Process 230 in process flow 200 is shown. Annealing process 88 may be performed in a process gas such as N2, He, NH3, Ar, etc., or a mixture thereof. According to some embodiments, annealing process 88 is performed by a soak annealing process, a spike rapid thermal annealing process, etc. When the soak annealing process is adopted, the annealing duration may be in a range between about 5 seconds and about 5 minutes. The annealing temperature may be in a range between about 500° C. and about 850° C.

[0071] Annealing causes the dipole dopant in the dipole film 82 to be driven into the corresponding underlying high-k dielectric layer 78HK. A dopant film 82 having a higher dopant concentration DDC causes the corresponding underlying high-k dielectric layer 78HK-400, 78HK-500 and 78HK-600 to have a higher dopant atomic percentage DDC of the dipole dopant, and vice versa. The higher dopant concentration DDC in turn results in a greater adjustment of the threshold voltage of the corresponding FET. The dipole dopant atomic percentage and its ratio can be obtained by energy dispersive X-ray spectroscopy (EDS), electron energy loss spectroscopy (EELS) and / or secondary ion mass spectroscopy (SIMS). By forming a dipole film 82 with an appropriate concentration and / or an appropriate thickness, the desired dipole dopant atomic percentage can be achieved.

[0072] The dipole film 82 is then removed in an isotropic etching process. Fig.14 The resulting structure is shown in FIG. 1 , where the high-k dielectric layer 78HK is exposed. The corresponding process is shown as Fig.33 Process 232 in process flow 200 is shown.

[0073] Fig.15A The formation of the gate electrode 80 (including the gate electrodes 80U and 80L) is shown. The corresponding process is shown as follows Fig.33 Process 234 in the process flow 200 shown. The gate dielectric 78 and the corresponding gate electrode 80 are collectively referred to as a gate stack 90, and the gate stack 90 includes an upper gate stack 90U and a lower gate stack 90L. The upper FET and the lower FET in each of the device regions 400, 500 and 600 share a common gate electrode 80. The upper portion of the gate electrode 80 above the dielectric isolation layer 56 is referred to as the upper gate electrode 80U. The lower portion of the gate electrode below the dielectric isolation layer 56 is referred to as the lower gate electrode 80L. The gate electrode 80 may include multiple layers (including TiN, TaN, etc.) and may include one or more work function layers 80WF. The thickness of each layer in the gate electrode 80 may be in a range between about 2nm and about 5nm.

[0074] The work function layer 80WF surrounding each gate dielectric 78 may be physically separated from the work function layer 80WF surrounding other gate dielectrics 78. In this case, a (non-work function) fill metal region 80FM (such as tungsten, cobalt, ruthenium, etc.) may fill the space between the work function layers 80WF on adjacent gate dielectrics 78. Alternatively, the work function layer 80WF surrounding each gate dielectric 78 may be physically connected to the work function layer 80WF surrounding other gate dielectrics 78.

[0075] According to some embodiments, the work function layer 80WF has a mid-bandgap work function, which may be in the range between about 4.5 eV and about 4.6 eV, and may also be slightly larger or smaller, for example, in the range between about 4.4 eV and about 4.7 eV. The corresponding work function material may include TiAlN, TaAlN, TiSiN, TaSiN, etc.

[0076] The resulting FETs include an upper FET 10U-400 and a lower FET 10L-400 in the device region 400, an upper FET 10U-500 and a lower FET 10L-500 in the device region 500, and an upper FET 10U-600 and a lower FET 10L-600 in the device region 600. The upper FETs 10U-400, 10U-500, and 10U-600 are PFETs, and the lower FETs 10L-400, 10L-500, and 10L-600 are NFETs.

[0077] According to the embodiments of the present disclosure, by using a common gate electrode having an intermediate bandgap work function (or close to an intermediate bandgap work function) as the gate electrode of the upper FET and the lower FET, it is not necessary to etch back the lower gate electrode to form another gate electrode for the upper FET, thereby avoiding damage to the high-k dielectric layer of the upper FET during the etch back process.

[0078] Fig.25 The effect of doping with n-type dipole dopants and p-type dipole dopants to reduce the effective work function and the effect of doping on the threshold voltage of the corresponding FET are shown. The effective work function increases continuously in the direction of the arrow marked "eWF" (representing the effective work function). It should be understood that for NFETs, as the atomic percentage of the dipole dopant of the n-type dopant films 82-1, 82-2, and 82-3 increases, the effective work function gradually decreases, and the threshold voltages HVt-n, MVt-n, and LVt-n continue to decrease.

[0079] like Fig.25 As shown, the PFET has threshold voltages HVt-P, MVt-P, and LVt-P corresponding to the dipole films 82-4, 82-5, and 82-6. The PFET has threshold voltages HVt-P, MVt-P, and LVt-P corresponding to the dipole films 82-4, 82-5, and 82-6, respectively. The threshold voltages HVt-P, MVt-P, and LVt-P are continuously reduced.

[0080] Reference again Fig.15A, the PFETs 10U-400, 10U-500 and 10U-600 have a high threshold voltage HVt-P, an intermediate threshold voltage MVt-P and a low threshold voltage LVt-P, respectively. The NFETs 10L-400, 10L-500 and 10L-600 have a high threshold voltage HVt-N, an intermediate threshold voltage MVt-N and a low threshold voltage LVt-N, respectively.

[0081] Fig. 27 The table shows the following according to some embodiments: Fig.15A The top and bottom FETs are shown with their dipole films and corresponding threshold voltages.

[0082] Fig.26 As shown, for each PFET 10U-400, 10U-500 and 10U-600 and NFET 10L-400, 10L-500 and 10L-600 ( Fig.15A and Fig. 15B ), the peak dipole dopant atomic percentage may be at the interface between the high-k dielectric layer 78HK and the corresponding underlying interfacial layer 78IL. Alternatively, the peak dipole dopant atomic percentage may be within the high-k dielectric layer 78HK ( Fig.26 ), or within the interface layer 78IL. The position of the peak concentration may be slightly shifted to the left or right, for example, by a shift distance Δd less than about 1 nm.

[0083] Fig. 15B An embodiment is shown in which, in addition to Fig.15A In addition to the CFET shown, a plurality of CFETs are formed, and the plurality of CFETs are formed in the same Fig.15A The devices in FIG. 4 are located in device regions 400 ′, 500 ′, and 600 ′ in the same device die. Fig. 15B The structure shown is Fig.15A The structure is basically the same as in Fig. 15B The work function layers in the gate electrodes 80L' and 80U' in the embodiment are made of different work function materials and thus have different Fig.15A The gate electrodes 80L and 80U have different work functions. For example, Fig.15A The work function layer in the embodiment may have a work function at the lower end of the mid-bandgap work function, for example, close to about 4.5 eV or 4.4 eV. Fig. 15B The work function layer in the gate electrodes 80L′ and 80U′ shown may have a work function at the upper end of the mid-gap work function, for example, close to about 4.6 eV or 4.7 eV.

[0084] like Fig.15A and Fig. 15B The formation of the structures shown may share some common processes, such as Figures 2 to 14 Process shown. Fig.15A and Fig. 15B The formation of the work function layers in the Fig.15A and Fig. 15B Layers with different work functions. Fig.15A and Fig. 15B With the structure shown, NFETs may have more than three levels of threshold voltage, and PFETs may have more than three levels of threshold voltage. Thus, the levels of threshold voltage are increased while minimizing the increase in manufacturing cost.

[0085] Figures 16 to 21 and Fig.22A The formation of a CFET according to alternative embodiments is shown. These embodiments are similar to Figures 9 to 15A In the embodiments, except for Fig.22A In the example, the upper FET is an NFET and the lower FET is a PFET, which is consistent with Fig.15A The gate electrodes of the PFET and the NFET are also formed of the same work function material with an intermediate bandgap work function. Unless otherwise specified, the materials, structures, thicknesses, and formation processes according to these embodiments may be the same as those in the reference Figure 9 to Figure 1 5 The discussion is essentially the same and need not be repeated here.

[0086] refer to Fig.16 , a plurality of gate dielectrics 78 are formed in device regions 400, 500, and 600, respectively. Dipole films 82-4, 82-5, and 82-6 are formed, and the dipole films 82-4, 82-5, and 82-6 may have different dopant concentrations and / or different thicknesses, as discussed with reference to previous embodiments. According to some embodiments, the dipole films 82-4, 82-5, and 82-6 include p-type dopants, which is suitable for the case where the lower FET is a PFET.

[0087] refer to Fig.17 , forming a dummy filling region 84, and planarizing and etch-back the dummy filling region 84 to mask the dipole films 82-4, 82-5, and 82-6 in the lower FET region while exposing portions of the dipole films 82-4, 82-5, and 82-6 in the upper FET region.

[0088] Fig.18 The dipole films 82-4, 82-5 and 82-6 are shown removed from the upper FET region by etching. Thus, the high-k dielectric 78HK (including 78HK-400, 78HK-500 and 78HK-600) in the upper FET region is exposed. Next, as Fig.19As shown, dipole films 82-1, 82-2, and 82-3 are formed on the gate dielectric 78 in the upper FET region in the device regions 400, 500, and 600, respectively. The dipole films 82-1, 82-2, and 82-3 may include n-type dopants and may have different dopant concentrations (and / or different thicknesses), as discussed with reference to previous embodiments.

[0089] Fig. 20 The removal of the dummy fill regions 84 is shown, followed by an annealing process 88 to drive the dipole dopants in the dipole film 82 into the corresponding underlying high-k dielectric 78HK. Next, the dipole film 82 is removed in an etching process, exposing the underlying high-k dielectric layer 78HK. Fig.21 The resulting structure is shown in .

[0090] Fig.22A The formation of the gate electrode 80 (including gate electrodes 80U and 80L) of the CFET is shown. The resulting upper FETs 10U-400, 10U-500 and 10U-600 are NFETs, and the lower FETs 10L-400, 10L-500 and 10L-600 are PFETs. Fig.25 As shown, the threshold voltages of the upper FETs 10U-400, 10U-500 and 10U-600 are HVt-N, MVt-N and LVt-N, respectively, which are getting lower. The threshold voltages of the lower FETs 10L-400, 10L-500 and 10L-600 are HVt-P, MVt-P and LVt-P, respectively, which are also getting lower.

[0091] Fig.28 The table shows the following according to some embodiments: Fig.22A The top and bottom FETs are shown, along with their dipole membranes and corresponding threshold voltages.

[0092] Fig. 22B An embodiment is shown in which, in addition to Fig.22A In addition to the CFET shown, a plurality of CFETs are formed, and the plurality of CFETs are formed in the same Fig.22A The devices in FIG. 4 are located in device regions 400 ′, 500 ′, and 600 ′ in the same device die. Fig. 22B The structure shown is Fig.22A Basically the same, except Fig. 22B The work function layers in the gate electrodes 80L' and 80U' in the embodiment are made of different work function materials and thus have different Fig.22A The gate electrodes 80L and 80U have different work functions. For example, Fig.22AThe work function layer in the gate electrodes 80L and 80U in the embodiment may adopt a work function layer having a work function at the lower end of the mid-bandgap work function, for example, close to about 4.5 eV or 4.4 eV. Fig. 22B The work function layer in the gate electrodes 80L′ and 80U′ in FIG. 8 may adopt a work function layer having a work function at an upper end of the mid-gap work function, for example, close to about 4.6 eV or 4.7 eV.

[0093] like Fig.22A and Fig. 22B The formation of the structures shown may share common processes. Figures 2 to 14 Process shown. Fig.22A and Fig. 22B The formation of the work function layers in the Fig.22A and Fig. 22B Layers with different work functions. Fig.22A and Fig. 22B With the structure shown, NFETs may have more than three levels of threshold voltages, and PFETs may have more than three levels of threshold voltages. Thus, the levels of threshold voltages are increased while the increase in manufacturing cost is minimized.

[0094] Fig.23A and Fig. 23B 4 shows a cross-sectional view of an example CFET formed in a previous process. As previously described, each CFET in device regions 400, 500, 600, 400', 500' and 600' may be formed by Fig.23A and Fig. 23B The CFET shown in FIG. 8 shows a common gate electrode 80 including an upper electrode 80U and a lower electrode 80L (or an upper electrode 80U′ and a lower electrode 80L′) formed by the same process and the same material.

[0095] Also like Fig.23A and Fig. 23B As shown, a gate mask 92 is formed over the gate stack 90. ​​The formation process may include recessing the gate stack 90, filling the resulting recess with a dielectric material (such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbon oxynitride, etc.), and performing a planarization process to remove excess portions of the dielectric material over the second ILD 72. Silicide regions 94 and source / drain contact plugs 96U are formed to be electrically coupled to the source / drain regions 62U.

[0096] refer to Fig.24A and Fig. 24B, forming an etch stop layer (ESL) 104 and a third ILD 106. In some embodiments, the ESL 104 may include a dielectric material having a high etch selectivity to the etching of the third ILD 106, such as aluminum oxide, aluminum nitride, silicon oxycarbide, etc. The third ILD 106 may be formed using flowable CVD, ALD, etc., and the material may include PSG, BSG, BPSG, USG, etc., which may be deposited by any suitable method, such as CVD, PECVD, etc.

[0097] Fig.29 A sequential CFET structure according to some embodiments is shown. These embodiments are similar to the above embodiments, except that the lower FET 10L is formed first, and then a multilayer stack is bonded on the lower FET 10L. The upper FET 10U is then formed based on the bonded multilayer stack. The dielectric isolation layer 81 separates the lower FET 10L from the upper FET 10U.

[0098] Figure 30 to Figure 32 Channels and gate stacks of some example CFETs according to alternative embodiments are shown. Fig.30 A CFET is shown where the upper FET is a GAA FET and the lower FET is a FinFET. Fig.31 A CFET is shown where both the upper FET and the lower FET are FinFETs. Fig.32 A CFET is shown where the upper FET is a FinFET and the lower FET is a GAA FET. According to these embodiments, a dielectric isolation layer 81 separates the lower gate electrode 80L from the upper gate electrode 80U.

[0099] In such Figure 29 to Figure 32 In the illustrated embodiment, the lower gate electrode 80L and the upper gate electrode 80U, although formed in separate processes, can still be formed of the same material and have the same structure. The adjustment of the threshold voltage of the lower FET and the upper FET can be achieved by adjusting the p-type and n-type dipole dopants. The lower gate electrode 80L and the upper gate electrode 80U include the same mid-bandgap work function material.

[0100] Embodiments of the present disclosure have several advantageous features. By using a common gate electrode for the upper FET and the lower FET of the CFET, an etch-back process for recessing the lower gate electrode is not required. Since the etch-back process may damage the high-k dielectric, damage to the high-k dielectric is avoided. Adjustment of the threshold voltage of the PFET and the NFET is achieved by adjusting the doping concentration in the high-k dielectric layer.

[0101] According to some embodiments of the present disclosure, a method includes: forming a first semiconductor channel region and a second semiconductor channel region, wherein the second semiconductor channel region overlaps the first semiconductor channel region; forming a first gate dielectric on the first semiconductor channel region; forming a second gate dielectric on the second semiconductor channel region; forming a first dipole film on the first gate dielectric, wherein the first dipole film includes a first dipole dopant of a first type; forming a second dipole film on the second gate dielectric, wherein the second dipole film includes a second dipole dopant of a second type opposite to the first type; performing a drive-in process to drive the dipole dopants in the first dipole film and the second dipole film into the first gate dielectric and the second gate dielectric, respectively; removing the first dipole film and the second dipole film; and forming gate electrodes on the first gate dielectric and the second gate dielectric, wherein a lower portion of the first gate dielectric and the gate electrode are included in a first transistor, and an upper portion of the second gate dielectric and the gate electrode are included in a second transistor.

[0102] In an embodiment, the work function layer in the gate electrode has a mid-bandgap work function, and wherein the first transistor and the second transistor include an n-type transistor and a p-type transistor. In an embodiment, the first transistor is a p-type transistor, and the second transistor is an n-type transistor. In an embodiment, the first transistor is an n-type transistor, and the second transistor is a p-type transistor. In an embodiment, the method further includes forming a first source / drain region adjacent to the first semiconductor channel region; and forming a second source / drain region adjacent to the second semiconductor channel region, wherein the second source / drain region overlaps the first source / drain region.

[0103] In an embodiment, the method further comprises forming a third semiconductor channel region at the same height as the first semiconductor channel region; forming a third gate dielectric on the third semiconductor channel region; forming a third dipole film on the first gate dielectric, wherein the third dipole film comprises a first dipole dopant of the first type, and the third dipole film has a higher dipole dopant concentration than the first dipole film, wherein the additional dipole dopant in the third dipole film is driven into the third gate dielectric; and after the drive-in process, removing the third dipole film. In an embodiment, the first semiconductor channel region and the third semiconductor channel region are part of an upper transistor in a CFET structure.

[0104] In an embodiment, the method further comprises forming an additional gate electrode on the third gate dielectric, wherein the gate electrode and the additional gate electrode are formed in the same formation process. In an embodiment, forming the first dipole film and the second dipole film comprises depositing the first dipole film on the first gate dielectric and the second gate dielectric; removing the first dipole film from the second gate dielectric; and forming the second dipole film on the second gate dielectric.

[0105] In an embodiment, the method further includes forming a sacrificial layer after depositing the first dipole film; recessing the sacrificial layer to a level below the second gate dielectric, wherein the first dipole film is removed from the second gate dielectric after the recessing, and depositing the second dipole film after removing the first dipole film from the second gate dielectric; and removing the sacrificial layer.

[0106] According to some embodiments of the present disclosure, a structure includes: a lower transistor, which includes a first semiconductor channel region; a first gate dielectric, located on the first semiconductor channel region; and a first portion of a gate electrode, located on the first gate dielectric; and an upper transistor, wherein the lower transistor and the upper transistor include an n-type transistor and a p-type transistor, and wherein the upper transistor includes a second semiconductor channel region overlapping the first semiconductor channel region; a second gate dielectric, located on the second semiconductor channel region; and a second portion of the gate electrode, located on the second gate dielectric, wherein the first portion and the second portion are portions of a continuous gate electrode.

[0107] In an embodiment, the first portion and the second portion of the gate electrode include a work function layer having an intermediate bandgap work function. In an embodiment, the p-type transistor has a p-type effective work function, and the n-type transistor has an n-type effective work function. In an embodiment, the first gate dielectric includes a first dipole dopant of a first type, and the second gate dielectric includes a second dipole dopant of a second type opposite to the first type. In an embodiment, the first dipole dopant is an n-type dipole dopant selected from the group consisting of La, Sr, Y, Er, Sc, Mg, and combinations thereof. In an embodiment, the first dipole dopant is a p-type dipole dopant selected from the group consisting of Al, Ga, Zn, Ti, Ta, and combinations thereof. In an embodiment, the upper transistor is an n-type transistor, and the lower transistor is a p-type transistor.

[0108] According to some embodiments of the present disclosure, a structure includes: a lower transistor, which includes a first semiconductor channel region; a first gate dielectric, located on the first semiconductor channel region; and a first source / drain region, connected to the first semiconductor channel region; and an upper transistor, which includes a second semiconductor channel region overlapping the first semiconductor channel region; a second gate dielectric, located on the second semiconductor channel region; and a second source / drain region, connected to the second semiconductor channel region, wherein the first source / drain region and the second source / drain region have opposite conductivity types; and a common gate electrode, which extends continuously from a first level below the first semiconductor channel region to a second level above the second semiconductor channel region, wherein the common gate electrode includes an intermediate bandgap work function layer.

[0109] In an embodiment, the common gate electrode includes a lower portion serving as a first gate electrode of a lower transistor; and an upper portion serving as a second gate electrode of an upper transistor, wherein no interface is formed between the lower portion and the upper portion. In an embodiment, the first gate dielectric and the second gate dielectric include dipole dopants having opposite conductivity types.

[0110] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: forming a first semiconductor channel region and a second semiconductor channel region, wherein the second semiconductor channel region overlaps the first semiconductor channel region; forming a first gate dielectric on the first semiconductor channel region; forming a second gate dielectric on the second semiconductor channel region; forming a first dipole film on the first gate dielectric, wherein the first dipole film includes a first dipole dopant of a first type; forming a second dipole film on the second gate dielectric, wherein the second dipole film includes a second dipole dopant of a second type opposite to the first type; performing a drive-in process to drive the dipole dopants in the first dipole film and the second dipole film into the first gate dielectric and the second gate dielectric, respectively; removing the first dipole film and the second dipole film; and A gate electrode is formed on the first gate dielectric and the second gate dielectric, wherein the first gate dielectric and a lower portion of the gate electrode are included in a first transistor, and the second gate dielectric and an upper portion of the gate electrode are included in a second transistor.

2. The method according to claim 1, wherein: The work function layer in the gate electrode has a mid-gap work function, and wherein the first transistor and the second transistor include an n-type transistor and a p-type transistor.

3. The method according to claim 2, wherein: The first transistor is the p-type transistor, and the second transistor is the n-type transistor.

4. The method according to claim 2, wherein: The first transistor is the n-type transistor, and the second transistor is the p-type transistor.

5. The method according to claim 1, further comprising: forming a first source / drain region adjacent to the first semiconductor channel region; as well as A second source / drain region is formed adjacent to the second semiconductor channel region, wherein the second source / drain region overlaps the first source / drain region.

6. The method according to claim 1, further comprising: forming a third semiconductor channel region at the same height as the first semiconductor channel region; forming a third gate dielectric on the third semiconductor channel region; forming a third dipole film on the first gate dielectric, wherein the third dipole film includes the first dipole dopant of the first type and has a higher dipole dopant concentration than the first dipole film, wherein additional dipole dopant in the third dipole film is driven into the third gate dielectric; and After the drive-in process, the third dipole film is removed.

7. The method according to claim 6, wherein: The first semiconductor channel region and the third semiconductor channel region are part of an upper transistor in a complementary field effect transistor (CFET) structure.

8. The method according to claim 6, further comprising forming an additional gate electrode on the third gate dielectric, wherein: The gate electrode and the additional gate electrode are formed in the same formation process.

9. A semiconductor structure comprising: A lower transistor, the lower transistor comprising: a first semiconductor channel region; a first gate dielectric disposed on the first semiconductor channel region; and a first portion of a gate electrode disposed on the first gate dielectric; and an upper transistor, wherein the lower transistor and the upper transistor comprise an n-type transistor and a p-type transistor, and wherein the upper transistor comprises: a second semiconductor channel region, overlapping the first semiconductor channel region; a second gate dielectric disposed on the second semiconductor channel region; and A second portion of the gate electrode is located on the second gate dielectric, wherein the first portion and the second portion are parts of a continuous gate electrode.

10. A semiconductor structure comprising: A lower transistor, the lower transistor comprising: a first semiconductor channel region; a first gate dielectric disposed on the first semiconductor channel region; and a first source / drain region connected to the first semiconductor channel region; and an upper transistor, the upper transistor comprising: a second semiconductor channel region, overlapping the first semiconductor channel region; a second gate dielectric disposed on the second semiconductor channel region; and a second source / drain region connected to the second semiconductor channel region, wherein the first source / drain region and the second source / drain region have opposite conductivity types; and A common gate electrode continuously extends from a first level lower than the first semiconductor channel region to a second level higher than the second semiconductor channel region, wherein the common gate electrode includes an intermediate bandgap work function layer.

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