Array substrate, manufacturing method thereof and display panel

Abstract

The invention relates to an array substrate, a manufacturing method thereof and a display panel. The array substrate comprises a pixel arrangement area and a non-pixel arrangement area adjacent to the pixel arrangement area, and further comprises a first transistor arranged in the pixel arrangement area and a second transistor arranged in the non-pixel arrangement area. Wherein the first transistor comprises a first active part, the second transistor comprises a second active part, the material of the first active part comprises a metal oxide material, the material of the second active part comprises a metal oxide material, and the mobility of the second active part is greater than that of the first active part; the stability of the first transistor in the pixel arrangement area and the charging efficiency of the second transistor in the non-pixel arrangement area can be met at the same time.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, and a display panel. Background Art

[0002] With the development of display technology, people have higher and higher requirements for narrow borders of displays. In order to reduce the width of the display border, the existing technology is to make the gate driver on array (GOA) on the thin film transistor (TFT) array substrate, which can reduce the production process and reduce the cost. Since the gate driver chip (IC) is not required, the narrow border can be achieved and the integration of the TFT array substrate can be improved.

[0003] In a display, the thin film transistors in the pixel units in the display area and the thin film transistors in the gate drive circuit in the non-display area are generally made of the same active part material, resulting in the stability of the thin film transistors in the pixel units and the charging efficiency of the thin film transistors in the gate drive circuit cannot be met at the same time. Summary of the invention

[0004] The embodiments of the present application provide an array substrate and a manufacturing method thereof, and a display panel, which can meet the stability of a first transistor located in a pixel arrangement area and the charging efficiency of a second transistor located in a non-pixel arrangement area.

[0005] An embodiment of the present application provides an array substrate, the array substrate comprising a pixel arrangement area and a non-pixel arrangement area adjacent to the pixel arrangement area, the array substrate further comprising a first transistor disposed in the pixel arrangement area and a second transistor disposed in the non-pixel arrangement area;

[0006] The first transistor includes a first active portion, the second transistor includes a second active portion, a material of the first active portion includes a metal oxide material, a material of the second active portion includes a metal oxide material, and a mobility of the second active portion is greater than a mobility of the first active portion.

[0007] In one embodiment of the present application, the material of the first active portion includes indium gallium zinc oxide;

[0008] The material of the second active portion includes at least one of indium gallium zinc tin oxide, indium tin oxide, lanthanide rare earth doped metal oxide, indium gallium tin oxide and indium zinc tin oxide.

[0009] In one embodiment of the present application, the mobility of the second active portion is greater than or equal to 20 cm 2 / Vs.

[0010] In an embodiment of the present application, a ratio of the mobility of the second active portion to the mobility of the first active portion is greater than or equal to 2.

[0011] In one embodiment of the present application, the array substrate further includes:

[0012] A first semiconductor layer including the first active portion;

[0013] a second semiconductor layer disposed on one side of the first semiconductor layer, wherein the second semiconductor layer includes the second active portion;

[0014] A first insulating layer, disposed between the first semiconductor layer and the second semiconductor layer;

[0015] A second insulating layer is disposed on a side of the second semiconductor layer away from the first insulating layer, or is disposed on a side of the first semiconductor layer away from the first insulating layer;

[0016] Wherein, the thickness of the first insulating layer is smaller than the thickness of the second insulating layer.

[0017] In one embodiment of the present application, the first transistor further includes a first gate, and the second transistor further includes a second gate;

[0018] The first gate is arranged on a side of the second insulating layer away from the first active portion, the second gate is arranged on a side of the second insulating layer away from the second active portion, and the first gate and the second gate are arranged on the same layer.

[0019] In one embodiment of the present application, the array substrate further includes:

[0020] a substrate, disposed on a side of the first semiconductor layer away from the first insulating layer, and the second insulating layer is located on a side of the second semiconductor layer away from the first insulating layer;

[0021] The first conductive layer is disposed on a side of the second insulating layer away from the second semiconductor layer, and the first conductive layer includes the first gate and the second gate.

[0022] In one embodiment of the present application, the array substrate further includes:

[0023] a substrate, located on a side of the first semiconductor layer away from the first insulating layer, and the second insulating layer is located between the first semiconductor layer and the substrate;

[0024] The first conductive layer is disposed between the substrate and the second insulating layer, and the first conductive layer includes the first gate and the second gate.

[0025] In one embodiment of the present application, the first transistor further includes a first source and a first drain, and the second transistor further includes a second source and a second drain;

[0026] The array substrate further includes:

[0027] A second conductive layer is disposed on a side of the second semiconductor layer away from the first semiconductor layer;

[0028] The second conductive layer includes the first source, the first drain, the second source and the second drain, the first source and the first drain are connected to the first active part through the first insulating layer, and the second source and the second drain are connected to the second active part.

[0029] In one embodiment of the present application, the non-pixel arrangement area includes a drive circuit sub-area, and the array substrate includes a pixel circuit arranged in the pixel arrangement area, a gate drive circuit and a multiplexing circuit arranged in the drive circuit sub-area;

[0030] The pixel circuit includes the first transistor, and the gate driving circuit and the multiplexing circuit both include the second transistor.

[0031] According to the above-mentioned purpose of the present application, an embodiment of the present application further provides a method for manufacturing an array substrate, wherein the array substrate comprises a pixel arrangement area and a non-pixel arrangement area adjacent to the pixel arrangement area, and the method for manufacturing the array substrate comprises:

[0032] forming a first active portion of a first transistor in the pixel arrangement area, wherein a material of the first active portion includes a metal oxide material;

[0033] A second active portion of a second transistor is formed in the non-pixel arrangement area, wherein a material of the second active portion includes a metal oxide material, and a mobility of the second active portion is greater than a mobility of the first active portion.

[0034] In one embodiment of the present application, the step of forming a first active portion of a first transistor in the pixel arrangement area includes:

[0035] forming a first semiconductor layer on one side of the substrate, wherein the first semiconductor layer includes the first active portion;

[0036] The step of forming a second active portion of a second transistor in the non-pixel arrangement area comprises:

[0037] A second semiconductor layer is formed on a side of the first semiconductor layer away from the substrate, wherein the second semiconductor layer includes the second active portion.

[0038] In one embodiment of the present application, the method for manufacturing the array substrate further includes the following steps:

[0039] A first conductive layer is formed on a side of the second semiconductor layer away from the first semiconductor layer, the first conductive layer includes a first gate of the first transistor and a second gate of the second transistor, the first gate is located on a side of the first active portion away from the substrate, and the second gate is located on a side of the second active portion away from the substrate, wherein the first active portion includes a first channel arranged in alignment with the first gate and a first portion to be doped and a second portion to be doped connected to opposite sides of the first channel, and the second active portion includes a second channel arranged in alignment with the second gate and a third portion to be doped and a fourth portion to be doped connected to opposite sides of the second channel;

[0040] Conductivity treatment is performed on the first portion to be doped, the second portion to be doped, the third portion to be doped, and the fourth portion to be doped by using an ion implantation process.

[0041] According to the above-mentioned purpose of the present application, an embodiment of the present application further provides a display panel, and the display panel includes the array substrate.

[0042] The present application provides an array substrate and a manufacturing method thereof, and a display panel. A first transistor is arranged in a pixel arrangement area and a second transistor is arranged in a non-pixel arrangement area, and the material of the second active part of the second transistor and the material of the first active part of the first transistor both include metal oxides, and the mobility of the second active part is greater than the mobility of the first active part, thereby simultaneously satisfying the stability of the first transistor in the pixel arrangement area and the charging efficiency of the second transistor in the non-pixel arrangement area.

[0043] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0045] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0046] Figure 1A schematic diagram of a planar structure of an array substrate provided in an embodiment of the present application;

[0047] Figure 2 A schematic diagram of the structure of a first transistor provided in an embodiment of the present application;

[0048] Figure 3 A schematic diagram of the structure of a second transistor provided in an embodiment of the present application;

[0049] Figure 4 Another structural schematic diagram of the first transistor provided in an embodiment of the present application;

[0050] Figure 5 Another structural schematic diagram of the second transistor provided in an embodiment of the present application;

[0051] Figure 6 A schematic diagram of a first structure of an array substrate provided in an embodiment of the present application;

[0052] Figure 7 A second structural schematic diagram of an array substrate provided in an embodiment of the present application;

[0053] Figure 8 A third structural schematic diagram of the array substrate provided in an embodiment of the present application;

[0054] Fig. 9 A flow chart of a method for manufacturing an array substrate provided in an embodiment of the present application;

[0055] Fig.10 A schematic diagram of a manufacturing process of an array substrate provided in an embodiment of the present application;

[0056] Fig.11 A schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0057] Description of reference numerals:

[0058] 10. first semiconductor layer; 11. first active portion; 111. first channel; 112. first portion to be doped; 113. second portion to be doped; 101. pixel arrangement area; 102. non-pixel arrangement area; 1021. driving circuit sub-area;

[0059] 20, second semiconductor layer; 21, second active portion; 211, second channel; 212, third portion to be doped; 213, fourth portion to be doped;

[0060] 30. first conductive layer; 31. first gate; 32. second gate;

[0061] 40. second conductive layer; 41. first source electrode; 42. first drain electrode; 43. second source electrode; 44. second drain electrode;

[0062] 50, light shielding layer; 51, first light shielding portion; 52, second light shielding portion;

[0063] 60. Substrate;

[0064] 711, a first buffer layer; 712, a first gate insulating layer; 713, a first interlayer dielectric layer; 714, a first cover layer; 715, a third buffer layer; 716, a third cover layer;

[0065] 721, second buffer layer; 722, second gate insulating layer; 723, second interlayer dielectric layer; 724, second cover layer; 725, fourth buffer layer; 726, fourth cover layer;

[0066] 81 / 91, first insulating layer; 82 / 92, second insulating layer; 83 / 93, third insulating layer; 84, buffer layer; 85, cover layer;

[0067] 90. Display panel; 900. Array substrate. DETAILED DESCRIPTION

[0068] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0069] Please combine Figure 1 , Figure 2 as well as Figure 3 An embodiment of the present application provides an array substrate, which includes a pixel arrangement area 101 and a non-pixel arrangement area 102 adjacent to the pixel arrangement area 101, and the array substrate also includes a first transistor T1 arranged in the pixel arrangement area 101 and a second transistor T2 arranged in the non-pixel arrangement area 102.

[0070] The first transistor T1 includes a first active portion 11 , the second transistor T2 includes a second active portion 21 , the material of the first active portion 11 includes a metal oxide material, the material of the second active portion 21 includes a metal oxide material, and the mobility of the second active portion 21 is greater than the mobility of the first active portion 11 .

[0071] During the implementation of the application, the embodiment of the present application sets the first transistor T1 in the pixel arrangement area 101 and sets the second transistor T2 in the non-pixel arrangement area 102, and the material of the first active portion 11 of the first transistor T1 and the material of the second active portion 21 of the second transistor T2 are both metal oxides, and the mobility of the second active portion 21 is greater than the mobility of the first active portion 11, thereby simultaneously satisfying the stability of the first transistor T1 in the pixel arrangement area 101 and the charging efficiency of the second transistor T2 in the non-pixel arrangement area 102.

[0072] Specifically, please continue to combine Figure 1 , Figure 2 as well as Figure 3 The non-pixel arrangement area 102 includes a driving circuit sub-area 1021. The pixel arrangement area 101 of the array substrate is used to set a plurality of pixel circuits. The non-pixel arrangement area 102 of the array substrate can be used to set functional circuits and signal routing devices. For example, the driving circuit sub-area 1021 in the non-pixel arrangement area 102 can be used to set functional circuits such as gate driving circuits and multiplexing circuits.

[0073] The array substrate is also provided with a plurality of thin film transistors, and the plurality of thin film transistors can be distributed in pixel circuits, and functional circuits such as gate drive circuits and multiplexing circuits.

[0074] In some embodiments, the array substrate includes a first transistor T1 and a second transistor T2, the first transistor T1 includes a first active portion 11, a first gate 31, a first source 41 and a first drain 42; the second transistor T2 includes a second active portion 21, a second gate 32, a second source 43 and a second drain 44.

[0075] The material of the first active portion 11 includes metal oxide, and the material of the second active portion 21 includes metal oxide, so that the first transistor T1 and the second transistor T2 both have a small leakage current, and the first transistor T1 and the second transistor T2 both have good stability.

[0076] In addition, the mobility of the second active portion 21 is greater than the mobility of the first active portion 11, and thus the charging rate or charging efficiency of the second transistor T2 is higher than the charging rate or charging efficiency of the first transistor T1; that is, the second active portion 21 is prepared by using a metal oxide semiconductor material with relatively high mobility, and the first active portion 11 is prepared by using a metal oxide semiconductor material with relatively low mobility relative to the second active portion 21, and thus the first transistor T1 with high stability and the second transistor T2 with high charging efficiency can be obtained at the same time.

[0077] In the embodiment of the present application, the first transistor T1 is arranged in the pixel arrangement area 101, and the second transistor T2 is arranged in the driving circuit sub-area 1021, that is, the pixel circuit includes the first transistor T1, and the gate driving circuit and the multiplexing circuit can both include the second transistor T2, thereby achieving high stability of the thin film transistor in the pixel circuit and high charging efficiency of the thin film transistor in the gate driving circuit and the multiplexing circuit.

[0078] It should be noted that compared with the use of a low-temperature polycrystalline silicon active layer, the low-temperature polycrystalline silicon active layer needs to be formed through crystallization and multiple ion implantations, and both crystallization and ion implantation require corresponding equipment to operate. Therefore, the embodiment of the present application uses a metal oxide material with a higher mobility to prepare the second active part 21. On the basis of realizing an active layer with a higher mobility, it can effectively reduce the process cost and save process steps.

[0079] In some embodiments, the array substrate further includes a scan signal line, one end of which is connected to the gate drive circuit, and the other end of which extends into the pixel arrangement area 101 and is connected to the pixel circuit, and the gate drive circuit includes an output transistor connected to the scan signal line, and at least the output transistor in the gate drive circuit is the second transistor T2, so as to meet the signal output efficiency of the output transistor. Further, all thin film transistors in the gate drive circuit can be the second transistor T2; for example, the gate drive circuit can include a pull-up control module, a pull-up module, a pull-down module, and a pull-down maintenance module, then the thin film transistor in the pull-up control module, the thin film transistor in the pull-up module, the thin film transistor in the pull-down module, and the thin film transistor in the pull-down maintenance module can all be the second transistor T2.

[0080] In some embodiments, a ratio of the mobility of the second active portion 21 to the mobility of the first active portion 11 is greater than or equal to 2.

[0081] In some embodiments, the material of the first active portion 11 includes indium gallium zinc oxide (IGZO); and thus the mobility of the first active portion 11 may be 10 cm 2 / Vs; the material of the second active portion 21 includes at least one of indium gallium zinc tin oxide (IGZTO), indium tin oxide (IGO), lanthanide rare earth doped metal oxide (LnIZO), indium gallium tin oxide (IGTO) and indium zinc tin oxide (IZTO); the mobility of the second active portion 21 may be greater than or equal to 20cm 2 / Vs; Further preferably, the mobility of the second active portion 21 may be greater than or equal to 30cm 2 / Vs, and less than or equal to 50cm 2 / Vs, for example, can be 30cm 2 / Vs, 35cm 2 / Vs, 40cm 2 / Vs, 45cm 2 / Vs or 50cm 2 / Vs.

[0082] Furthermore, the following description is made in combination with thin film transistor structures in different regions.

[0083] In some embodiments, please refer to Figure 1 and Figure 2In the pixel arrangement area 101, the array substrate includes a substrate 60, a first light shielding portion 51 disposed on the substrate 60, a first buffer layer 711 disposed on the substrate 60 and covering the first light shielding portion 51, the first active portion 11 disposed on a side of the first buffer layer 711 away from the first light shielding portion 51, a first gate insulating layer 712 disposed on the first buffer layer 711 and covering the first active portion 11, and the first gate insulating layer 712 disposed on a side of the first gate insulating layer 712 away from the first active portion 11. The first source electrode 41 and the first drain electrode 42 are connected to the first active portion 11 through the first interlayer dielectric layer 713 and the first gate insulating layer 712.

[0084] In some embodiments, please refer to Figure 1 and Figure 3 In the non-pixel arrangement area 102, that is, in the driving circuit sub-area 1021, the array substrate includes a substrate 60, a second light shielding portion 52 disposed on the substrate 60, a second buffer layer 721 disposed on the substrate 60 and covering the second light shielding portion 52, a second active portion 21 disposed on a side of the second buffer layer 721 away from the second light shielding portion 52, a second gate insulating layer 722 disposed on the second buffer layer 721 and covering the second active portion 21, and a second gate insulating layer 722 disposed on the second gate insulating layer 722 away from the second active portion 21. The second gate 32 on one side, the second interlayer dielectric layer 723 arranged on the second gate insulating layer 722 and covering the second gate 32, the second source 43 and the second drain 44 arranged on the second interlayer dielectric layer 723, and the second covering layer 724 arranged on the second interlayer dielectric layer 723 and covering the second source 43 and the second drain 44, the second source 43 and the second drain 44 can pass through the second interlayer dielectric layer 723 and the second gate insulating layer 722 to connect with the two sides of the second active part 21.

[0085] It can be understood that the above embodiments respectively describe the film layer structure of the first transistor T1 in the pixel arrangement area 101 and the film layer structure of the second transistor T2 in the non-pixel arrangement area 102, and the pixel arrangement area 101 and the non-pixel arrangement area 102 are different areas on the array substrate, and thus the film layer structure in the first transistor T1 and the film layer structure in the second transistor T2 can be partially the same, for example, the first buffer layer 711 and the second buffer layer 721 can be the same film layer, the first light shielding portion 51 and the second light shielding portion 52 can be the same film layer, the first gate insulating layer 712 and the second gate insulating layer 722 can be the same film layer, the first gate 31 and the second gate 32 can belong to the same film layer, the first source 41, the first drain 42, the second source 43 and the second drain 44 can belong to the same film layer, and the first covering layer 714 and the second covering layer 724 can be the same film layer.

[0086] In some embodiments, Figure 2 as well as Figure 3 In the array substrate shown in the figure, the first active portion 11 and the second active portion 21 can be conductively formed by ion implantation, and the first gate 31 and the second gate 32 are used as barrier layers, respectively, so that short channels can be formed in the first active portion 11 and the second active portion 21 to further improve the charging efficiency of the first transistor T1 and the second transistor T2. The ion implantation element can be B, Ne, P or Ar, and the ion implantation concentration is about 1E15cm -3 , and the specific element type and ion implantation concentration can be selected according to actual needs and are not limited here.

[0087] It should be noted that, in the above embodiment, both the first transistor T1 and the second transistor T2 are top-gate structures, and the first transistor T1 and the second transistor T2 may also be bottom-gate structures, as described below.

[0088] In some embodiments, please combine 1, Figure 4 as well as Figure 5 In the pixel arrangement area 101, the array substrate includes a substrate 60, the first gate 31 arranged on the substrate 60, a third buffer layer 715 arranged on the substrate 60 and covering the first gate 31, the first active portion 11 arranged on the side of the third buffer layer 715 away from the first gate 31, the first source 41 and the first drain 42 arranged on the first active portion 11 and the third buffer layer 715, and a third covering layer 716 covering the first source 41 and the first drain 42.

[0089] In the non-pixel arrangement area 102, the array substrate includes a substrate 60, the second gate 32 arranged on the substrate 60, a fourth buffer layer 725 arranged on the substrate 60 and covering the second gate 32, the second active portion 21 arranged on the side of the fourth buffer layer 725 away from the second gate 32, the second source 43 and the second drain 44 arranged on the second active portion 21 and the fourth buffer layer 725, and a fourth covering layer 726 covering the second source 43 and the second drain 44.

[0090] It can be understood that the above embodiments respectively describe the film layer structure of the first transistor T1 in the pixel arrangement area 101 and the film layer structure of the second transistor T2 in the non-pixel arrangement area 102, and the pixel arrangement area 101 and the non-pixel arrangement area 102 are different areas on the array substrate, and thus the film layer structure in the first transistor T1 and the film layer structure in the second transistor T2 can be partially the same, for example, the third buffer layer 715 and the fourth buffer layer 725 can be the same film layer, the first gate 31 and the second gate 32 can belong to the same film layer, the first source 41, the first drain 42, the second source 43 and the second drain 44 can belong to the same film layer, and the third covering layer 716 and the fourth covering layer 726 can be the same film layer.

[0091] It should be noted that, in the above embodiment, a partial film layer structure in the first transistor T1 and a partial film layer structure in the second transistor T2 may be the same film layer or belong to the same film layer, thereby saving process steps and reducing process costs.

[0092] In continuation of the above, the corresponding relationship between the film layer structure of the first transistor T1 and the film layer structure of the second transistor T2 is described in detail below in conjunction with specific embodiments.

[0093] Please combine Figure 1 as well as Figure 6In a specific embodiment, the array substrate includes the substrate 60, a light-shielding layer 50 disposed on the substrate 60, a buffer layer 84 disposed on the substrate 60 and covering the light-shielding layer 50, a first semiconductor layer 10 disposed on the buffer layer 84, a first insulating layer 81 disposed on the buffer layer 84 and covering the first semiconductor layer 10, a second semiconductor layer 20 disposed on the first insulating layer 81, a second insulating layer 82 disposed on the first insulating layer 81 and covering the second semiconductor layer 20, a first conductive layer 30 disposed on the second insulating layer 82, a third insulating layer 83 disposed on the second insulating layer 82 and covering the first conductive layer 30, a second conductive layer 40 disposed on the third insulating layer 83, and a covering layer 85 disposed on the third insulating layer 83 and covering the second conductive layer 40.

[0094] The light shielding layer 50 includes a first light shielding portion 51 located in the pixel arrangement area 101 and a second light shielding portion 52 located in the driving circuit sub-area 1021 .

[0095] The first semiconductor layer 10 includes the first active portion 11 which is disposed on a side of the buffer layer 84 away from the first light shielding portion 51 and located in the pixel arrangement area 101 .

[0096] The second semiconductor layer 20 includes the second active portion 21 which is disposed on a side of the first insulating layer 81 away from the second light shielding portion 52 and located in the driving circuit sub-region 1021 .

[0097] In this embodiment, the material of the first active portion 11 includes metal oxide, and the material of the second active portion 21 includes metal oxide, so that the first transistor T1 and the second transistor T2 both have a small leakage current, and the first transistor T1 and the second transistor T2 both have good stability.

[0098] In addition, the mobility of the second active portion 21 is greater than the mobility of the first active portion 11, and thus the charging rate or charging efficiency of the second transistor T2 is higher than the charging rate or charging efficiency of the first transistor T1; that is, the second active portion 21 is prepared by using a metal oxide semiconductor material with relatively high mobility, and the first active portion 11 is prepared by using a metal oxide semiconductor material with relatively low mobility relative to the second active portion 21, and thus the first transistor T1 with high stability and the second transistor T2 with high charging efficiency can be obtained at the same time.

[0099] In the embodiment of the present application, the first transistor T1 is arranged in the pixel arrangement area 101, and the second transistor T2 is arranged in the driving circuit sub-area 1021, that is, the pixel circuit includes the first transistor T1, and the gate driving circuit and the multiplexing circuit can both include the second transistor T2, thereby achieving high stability of the thin film transistor in the pixel circuit and high charging efficiency of the thin film transistor in the gate driving circuit and the multiplexing circuit.

[0100] The first conductive layer 30 includes the first gate 31 disposed on the side of the second insulating layer 82 away from the first active portion 11 and the second gate 32 disposed on the side of the second insulating layer 82 away from the second active portion 21, and the first gate 31 is located in the pixel arrangement area 101, and the second gate 32 is located in the driving circuit sub-area 1021.

[0101] The second conductive layer 40 includes the first source 41, the first drain 42, the second source 43 and the second drain 44 which are arranged on the side of the third insulating layer 83 away from the second insulating layer 82, the first source 41 and the first drain 42 are located in the pixel arrangement area 101, the first source 41 and the first drain 42 are connected to the first active portion 11 through the first insulating layer 81, the second insulating layer 82 and the third insulating layer 83, the second source 43 and the second drain 44 are located in the non-pixel arrangement area 101, the second source 43 and the second drain 44 are connected to the second active portion 21 through the second insulating layer 82 and the third insulating layer 83.

[0102] The first insulating layer 81 is located between the first semiconductor layer 10 and the second semiconductor layer 20 , and the second insulating layer 82 is located on a side of the second semiconductor layer 20 away from the first insulating layer 81 and between the second semiconductor layer 20 and the first conductive layer 30 .

[0103] Since different materials are used to form the first active portion 11 and the second active portion 21 in the embodiment of the present application, the first active portion 11 and the second active portion 21 are respectively located in different semiconductor film layers, and thus the first insulating layer 81 is required to separate the first semiconductor layer 10 and the second semiconductor layer 20; in addition, the second insulating layer 82 is required to separate the first conductive layer 30 and the second semiconductor layer 20. Therefore, in the present embodiment, the first insulating layer 81 is located between the first semiconductor layer 10 and the second semiconductor layer 20, and the second insulating layer 82 is located on the side of the second semiconductor layer 20 away from the first semiconductor layer 10; then the first insulating layer 81 and the second insulating layer 82 are provided between the first gate 31 and the first active portion 11. In order to avoid an excessively large distance between the first gate 31 and the first active portion 11, in the embodiment of the present application, the thickness of the first insulating layer 81 is less than the thickness of the second insulating layer 82, and thus the distance between the first gate 31 and the first active portion 11 can be reduced by reducing the first insulating layer 81, so that the first transistor T1 can be effectively switched on and off.

[0104] Please combine Figure 1 as well as Figure 7 In another specific embodiment, the array substrate includes the substrate 60, a first conductive layer 30 arranged on the substrate 60, a second insulating layer 92 arranged on the substrate 60 and covering the first conductive layer 30, a first semiconductor layer 10 arranged on the second insulating layer 92, a first insulating layer 91 arranged on the second insulating layer 92 and covering the first semiconductor layer 10, a second semiconductor layer 20 arranged on the first insulating layer 91, a second conductive layer 40 arranged on the first insulating layer 91 and the second semiconductor layer 20, and a third insulating layer 93 covering the second conductive layer 40.

[0105] The first conductive layer 30 is disposed between the substrate 60 and the second insulating layer 92 , and the first conductive layer 30 includes the first gate 31 disposed in the pixel arrangement area 101 and the second gate 32 disposed in the driving circuit sub-area 1021 .

[0106] The first semiconductor layer 10 includes the first active portion 11 disposed on a side of the second insulating layer 92 away from the first gate 31 , and the first active portion 11 is located in the pixel arrangement area 101 .

[0107] The second semiconductor layer 20 includes a second active portion 21 disposed on a side of the first insulating layer 91 away from the second gate 32 , and the second active portion 21 is located in the driving circuit sub-area 1021 .

[0108] In this embodiment, the material of the first active portion 11 includes metal oxide, and the material of the second active portion 21 includes metal oxide, so that the first transistor T1 and the second transistor T2 both have a small leakage current, and the first transistor T1 and the second transistor T2 both have good stability.

[0109] In addition, the mobility of the second active portion 21 is greater than the mobility of the first active portion 11, and thus the charging rate or charging efficiency of the second transistor T2 is higher than the charging rate or charging efficiency of the first transistor T1; that is, the second active portion 21 is prepared by using a metal oxide semiconductor material with relatively high mobility, and the first active portion 11 is prepared by using a metal oxide semiconductor material with relatively low mobility relative to the second active portion 21, and thus the first transistor T1 with high stability and the second transistor T2 with high charging efficiency can be obtained at the same time.

[0110] In the embodiment of the present application, the first transistor T1 is arranged in the pixel arrangement area 101, and the second transistor T2 is arranged in the driving circuit sub-area 1021, that is, the pixel circuit includes the first transistor T1, and the gate driving circuit and the multiplexing circuit can both include the second transistor T2, thereby achieving high stability of the thin film transistor in the pixel circuit and high charging efficiency of the thin film transistor in the gate driving circuit and the multiplexing circuit.

[0111] The second conductive layer 40 includes the first source 41, the first drain 42, the second source 43 and the second drain 44 which are arranged on the side of the first insulating layer 91 away from the second insulating layer 92, the first source 41 and the first drain 42 are located in the pixel arrangement area 101 and are connected to the first active portion 11 through the first insulating layer 81, and the second source 43 and the second drain 44 are located in the non-pixel arrangement area 101 and are connected to the second active portion 21.

[0112] The first insulating layer 91 is located between the first semiconductor layer 10 and the second semiconductor layer 20 , and the second insulating layer 92 is located on a side of the first semiconductor layer 10 away from the first insulating layer 91 and between the first semiconductor layer 10 and the first conductive layer 30 .

[0113] Since the first transistor T1 and the second transistor T2 in the embodiment of the present application use different materials to form the first active portion 11 and the second active portion 21, the first active portion 11 and the second active portion 21 are respectively located in different semiconductor film layers, and the first insulating layer 91 is required to separate the first semiconductor layer 10 and the second semiconductor layer 20; in addition, the second insulating layer 92 is required to separate the first conductive layer 30 and the first semiconductor layer 10, and the first insulating layer 91 and the second insulating layer 92 are provided between the second gate 32 and the second active portion 21. In order to avoid the distance between the second gate 32 and the second active portion 21 being too large, in the embodiment of the present application, the thickness of the first insulating layer 91 is less than the thickness of the second insulating layer 92, and the distance between the second gate 32 and the second active portion 21 can be reduced by reducing the first insulating layer 91, so that the first transistor T1 can be effectively turned on and off.

[0114] Please combine Figure 1 as well as Figure 8 In another specific embodiment, this embodiment and Figure 7 The difference between the illustrated embodiments is that the second conductive layer 40 is disposed on the second insulating layer 92 and covered by the first insulating layer 91 , the second conductive layer 40 includes the first source 41 and the first drain 42 , and the first source 41 and the first drain 42 are connected to the first active portion 11 .

[0115] The second source electrode 43 and the second drain electrode 44 are disposed on a side of the first insulating layer 91 away from the second insulating layer 92 , and are connected to two sides of the second active portion 21 .

[0116] As described above, in the embodiment of the present application, the first transistor T1 is arranged in the pixel arrangement area 101 and the second transistor T2 is arranged in the driving circuit sub-area 1021, and the material of the first active portion 11 of the first transistor T1 and the material of the second active portion 21 of the second transistor T2 are both metal oxides, and the mobility of the second active portion 21 is greater than the mobility of the first active portion 11, thereby simultaneously satisfying the stability of the first transistor T1 in the pixel arrangement area 101 and the charging efficiency of the second transistor T2 in the driving circuit sub-area 1021; at the same time, by preparing some devices in the first transistor T1 and the second transistor T2 in the same film layer in the array substrate, it is possible to save process steps and reduce process costs.

[0117] In addition, please combine Fig. 9 as well as Fig.10The present application also provides a method for manufacturing an array substrate, wherein the array substrate includes a pixel arrangement area 101 and a non-pixel arrangement area 102 adjacent to the pixel arrangement area. The method for manufacturing the array substrate includes:

[0118] S10 , forming a first active portion 11 of a first transistor T1 in the pixel arrangement area 101 , wherein a material of the first active portion 11 includes a metal oxide material.

[0119] S20 , forming a second active portion 21 of the second transistor T2 in the non-pixel arrangement area 102 , wherein the material of the second active portion 21 includes a metal oxide material, and the mobility of the second active portion 21 is greater than the mobility of the first active portion.

[0120] Specifically, in step S10 , the substrate 60 is provided, and a light shielding layer 50 is formed on the substrate 60 . The light shielding layer 50 includes a first light shielding portion 51 located in the pixel arrangement area 101 and a second light shielding portion 52 located in the non-pixel arrangement area 102 .

[0121] Next, a buffer layer 84 is formed on the substrate 60 to cover the first light shielding portion 51 and the second light shielding portion 52 .

[0122] Then, a first semiconductor layer 10 is formed on a side of the buffer layer 84 away from the substrate 60 . The first semiconductor layer 10 includes the first active portion 11 of the first transistor T1 . The material of the first active portion 11 includes a metal oxide material.

[0123] In some embodiments, the material of the first active portion 11 includes Indium Gallium Zinc Oxide (IGZO).

[0124] Next, a first insulating layer 81 is formed on a side of the first semiconductor layer 10 away from the buffer layer 84 , and the first insulating layer 81 covers the first active portion 11 .

[0125] In step S20, a second semiconductor layer 20 is formed on a side of the first insulating layer 81 away from the first semiconductor layer 10, and the second semiconductor layer 20 includes a second active portion 21 of the second transistor T2, and the material of the second active portion 21 includes a metal oxide material, and the mobility of the second active portion 21 is greater than the mobility of the first active portion 11.

[0126] In some embodiments, the material of the second active portion 21 includes at least one of indium gallium zinc tin oxide (IGZTO), indium tin oxide (IGO), lanthanum rare earth doped metal oxide (LnIZO), indium gallium tin oxide (IGTO) and indium zinc tin oxide (IZTO).

[0127] A second insulating layer 82 is formed on the first insulating layer 81 , and the second insulating layer 82 covers the second active layer 21 .

[0128] Then, a first conductive layer 30 is formed on a side of the second semiconductor layer 20 away from the first semiconductor layer 10 .

[0129] Specifically, a first conductive layer 30 is formed on a side of the second insulating layer 82 away from the second semiconductor layer 20, and the first conductive layer 30 includes a first gate 31 of the first transistor T and a second gate 32 of the second transistor T2, the first gate 31 is located on a side of the first active portion 11 away from the substrate 60, and the second gate 32 is located on a side of the second active portion 21 away from the substrate 60, wherein the first active portion 11 includes a first channel 111 arranged in alignment with the first gate 31 and a first portion to be doped 112 and a second portion to be doped 113 connected to opposite sides of the first channel 111, and the second active portion 21 includes a second channel 211 arranged in alignment with the second gate 32 and a third portion to be doped 212 and a fourth portion to be doped 213 connected to opposite sides of the second channel 211.

[0130] Next, a third insulating layer 83 is formed on the second insulating layer 82 to cover the first gate 31 and the second gate 32 .

[0131] A second conductive layer 40 is formed on the third insulating layer 83, and the fourth conductive layer 40 includes a first source 41 and a first drain 42 arranged in the pixel arrangement area 101, and a second source 43 and a second drain 44 arranged in the non-pixel arrangement area 102; wherein the first source 41 and the first drain 42 are connected to the first active portion 11 through the first insulating layer 81, the second insulating layer 82 and the third insulating layer 83, and the second source 43 and the second drain 44 are connected to the second active portion 21 through the second insulating layer 82 and the third insulating layer 83.

[0132] A covering layer 85 covering the first source electrode 41 , the first drain electrode 42 , the second source electrode 43 , and the second drain electrode 44 is formed on a side of the third insulating layer 83 away from the second insulating layer 82 .

[0133] In some embodiments, the method for manufacturing the array substrate also includes: using an ion implantation process and using the first gate 31 and the second gate 32 as barrier layers to perform conductor processing on the first portion to be doped 112, the second portion to be doped 113, the third portion to be doped 212 and the fourth portion to be doped 213, thereby forming a short channel in the first active portion 11 and the second active portion 21 to further improve the charging efficiency of the first transistor T1 and the second transistor T2.

[0134] It is understandable that the method for manufacturing the array substrate in the above embodiment is described as the first transistor T1 and the second transistor T2 being a top-gate structure, and the following description is based on the first transistor T1 and the second transistor T2 being a bottom-gate structure.

[0135] For details, please refer to Figure 1 , Figure 7 as well as Fig. 9 In step S10 , the first conductive layer 30 is formed on the substrate 60 , and the first conductive layer 30 includes a first gate 31 located in the pixel arrangement area 101 and a second gate 32 located in the non-pixel arrangement area 102 .

[0136] Next, a second insulating layer 92 is formed on the substrate 60 to cover the first gate 31 and the second gate 32 .

[0137] Then, the first semiconductor layer 10 is formed on the second insulating layer 92 . The first semiconductor layer 10 includes a first active portion 11 formed on a side of the second insulating layer 92 away from the first gate 31 . The material of the first active portion 11 includes a metal oxide material.

[0138] A first insulating layer 91 covering the first active portion 11 is formed on the second insulating layer 92 .

[0139] In step S20, the second semiconductor layer 20 is formed on the first insulating layer 91, and the second semiconductor layer 20 includes the second active portion 21 formed on the side of the first insulating layer 91 away from the second gate 32, the material of the second active portion 21 includes a metal oxide material, and the mobility of the second active portion 21 is greater than the mobility of the first active portion 11.

[0140] Then, the second conductive layer 40 is formed on the first insulating layer 91 and the second semiconductor layer 20, and the second conductive layer 40 includes a first source 41, a first drain 42, a second source 43 and a second drain 44, and the first source 41 and the first drain 42 pass through the first insulating layer 91 to connect with the opposite sides of the first active part 11, and the second source 43 and the second drain 44 are connected with the opposite sides of the second active part 21.

[0141] A third insulating layer 93 is formed on the first conductive layer 40 to cover the first source electrode 41 , the first drain electrode 42 , the second source electrode 43 , and the second drain electrode 44 .

[0142] In addition, in another embodiment of the present application, please refer to Figure 1 , Figure 8 as well as Fig. 9 , this embodiment and Figure 7 The difference between the illustrated embodiments is that after forming the first semiconductor layer 10 , the first conductive layer 40 is formed on the first semiconductor layer 10 , and the first conductive layer 40 includes a first source 41 and a first drain 42 connected to opposite sides of the first active portion 11 .

[0143] Then, a first insulating layer 91 covering the first active portion 11 , the first source 41 , and the first drain 42 is formed.

[0144] In step S20, the second semiconductor layer 20 is formed on the first insulating layer 91, and the second semiconductor layer 20 includes the second active portion 21 formed on the side of the first insulating layer 91 away from the second gate 32, the material of the second active portion 21 includes a metal oxide material, and the mobility of the second active portion 21 is greater than the mobility of the first active portion 11.

[0145] Then, a second source electrode 43 and a second drain electrode 44 are formed on the first insulating layer 91 and the second semiconductor layer 20 , and the second source electrode 43 and the second drain electrode 44 are connected to opposite sides of the second active portion 21 .

[0146] Next, a third insulating layer 93 is formed on the first conductive layer 40 to cover the second source 43 and the second drain 44 .

[0147] Also, please refer to Fig.11 The embodiment of the present application further provides a display panel 90, and the display panel 90 includes the array substrate 900 described in the above embodiment.

[0148] In some embodiments, the display panel 90 may be an organic light emitting diode display panel, and the display panel further includes film layers such as an anode layer, an organic light emitting layer, a cathode layer, and an encapsulation layer disposed on the array substrate 900.

[0149] In some embodiments, the display panel 90 can be a liquid crystal display panel, and the display panel also includes a pixel electrode arranged on the array substrate 900, a liquid crystal layer arranged on the side of the pixel electrode away from the array substrate 900, a color film substrate arranged on the side of the liquid crystal layer away from the array substrate 900, and a common electrode arranged on the array substrate 900 and / or the color film substrate.

[0150] It can be understood that, since the display panel 90 has the same array substrate 900 as that in the above embodiment, the display panel 90 has the same beneficial effects as the array substrate 900 described in the above embodiment, which will not be described in detail herein.

[0151] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0152] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0153] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0154] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. An array substrate, characterized in that: The array substrate includes a pixel arrangement area and a non-pixel arrangement area adjacent to the pixel arrangement area, and the array substrate also includes a first transistor arranged in the pixel arrangement area and a second transistor arranged in the non-pixel arrangement area; The first transistor includes a first active portion, the second transistor includes a second active portion, a material of the first active portion includes a metal oxide material, a material of the second active portion includes a metal oxide material, and a mobility of the second active portion is greater than a mobility of the first active portion.

2. The array substrate according to claim 1, characterized in that: The material of the first active portion includes indium gallium zinc oxide; The material of the second active portion includes at least one of indium gallium zinc tin oxide, indium tin oxide, lanthanide rare earth doped metal oxide, indium gallium tin oxide and indium zinc tin oxide.

3. The array substrate according to claim 1, characterized in that: The mobility of the second active portion is greater than or equal to 20 cm 2 / Vs.

4. The array substrate according to claim 1, characterized in that: A ratio of the mobility of the second active portion to the mobility of the first active portion is greater than or equal to 2.

5. The array substrate according to any one of claims 1 to 4, characterized in that: The array substrate further includes: A first semiconductor layer including the first active portion; a second semiconductor layer disposed on one side of the first semiconductor layer, wherein the second semiconductor layer includes the second active portion; A first insulating layer, disposed between the first semiconductor layer and the second semiconductor layer; A second insulating layer is disposed on a side of the second semiconductor layer away from the first insulating layer, or is disposed on a side of the first semiconductor layer away from the first insulating layer; Wherein, the thickness of the first insulating layer is smaller than the thickness of the second insulating layer.

6. The array substrate according to claim 5, characterized in that: The first transistor further includes a first gate, and the second transistor further includes a second gate; The first gate is arranged on a side of the second insulating layer away from the first active portion, the second gate is arranged on a side of the second insulating layer away from the second active portion, and the first gate and the second gate are arranged on the same layer.

7. The array substrate according to claim 6, characterized in that: The array substrate further includes: a substrate, disposed on a side of the first semiconductor layer away from the first insulating layer, and the second insulating layer is located on a side of the second semiconductor layer away from the first insulating layer; The first conductive layer is disposed on a side of the second insulating layer away from the second semiconductor layer, and the first conductive layer includes the first gate and the second gate.

8. The array substrate according to claim 6, characterized in that: The array substrate further includes: a substrate, located on a side of the first semiconductor layer away from the first insulating layer, and the second insulating layer is located between the first semiconductor layer and the substrate; The first conductive layer is disposed between the substrate and the second insulating layer, and the first conductive layer includes the first gate and the second gate.

9. The array substrate according to claim 5, characterized in that: The first transistor further includes a first source and a first drain, and the second transistor further includes a second source and a second drain; The array substrate further includes: A second conductive layer is disposed on a side of the second semiconductor layer away from the first semiconductor layer; The second conductive layer includes the first source, the first drain, the second source and the second drain, the first source and the first drain are connected to the first active part through the first insulating layer, and the second source and the second drain are connected to the second active part.

10. The array substrate according to any one of claims 1 to 4, characterized in that: The non-pixel arrangement area includes a driving circuit sub-area, and the array substrate includes a pixel circuit arranged in the pixel arrangement area, a gate driving circuit and a multiplexing circuit arranged in the driving circuit sub-area; The pixel circuit includes the first transistor, and the gate driving circuit and the multiplexing circuit both include the second transistor.

11. A method for manufacturing an array substrate, characterized in that: The array substrate includes a pixel arrangement area and a non-pixel arrangement area adjacent to the pixel arrangement area, and the manufacturing method of the array substrate includes: forming a first active portion of a first transistor in the pixel arrangement area, wherein a material of the first active portion includes a metal oxide material; A second active portion of a second transistor is formed in the non-pixel arrangement area, wherein a material of the second active portion includes a metal oxide material, and a mobility of the second active portion is greater than a mobility of the first active portion.

12. The method for manufacturing an array substrate according to claim 11, characterized in that: The step of forming a first active portion of a first transistor in the pixel arrangement area comprises: forming a first semiconductor layer on one side of the substrate, wherein the first semiconductor layer includes the first active portion; The step of forming a second active portion of a second transistor in the non-pixel arrangement area comprises: A second semiconductor layer is formed on a side of the first semiconductor layer away from the substrate, wherein the second semiconductor layer includes the second active portion.

13. The method for manufacturing an array substrate according to claim 12, characterized in that: The method for manufacturing the array substrate further comprises the following steps: A first conductive layer is formed on a side of the second semiconductor layer away from the first semiconductor layer, the first conductive layer includes a first gate of the first transistor and a second gate of the second transistor, the first gate is located on a side of the first active portion away from the substrate, and the second gate is located on a side of the second active portion away from the substrate, wherein the first active portion includes a first channel arranged in alignment with the first gate and a first portion to be doped and a second portion to be doped connected to opposite sides of the first channel, and the second active portion includes a second channel arranged in alignment with the second gate and a third portion to be doped and a fourth portion to be doped connected to opposite sides of the second channel; Conductivity treatment is performed on the first portion to be doped, the second portion to be doped, the third portion to be doped, and the fourth portion to be doped by using an ion implantation process.

14. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 10.

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