Display device and method for manufacturing display device

Abstract

A display device and a method for manufacturing the same are provided. The display device includes a first electrode disposed on a substrate, a buffer layer disposed on the first electrode, a first transistor including a first active layer disposed on the buffer layer and a first gate electrode disposed on a portion of the first active layer, a second electrode disposed on the buffer layer and electrically connected to the first electrode, a first gate insulating layer disposed between the first active layer and the first gate electrode, and a second gate insulating layer disposed between the buffer layer and the second electrode, an area of a top surface of the first gate insulating layer may be larger than an area of a bottom surface of the first gate electrode in a plan view, and the first gate insulating layer protrudes to the outside of the first gate electrode, the second gate insulating layer and the first gate insulating layer including the same material.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0149569 filed in the Korean Intellectual Property Office on November 2, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a method for manufacturing the display device. Background Art

[0004] With the development of multimedia technology, the importance of display devices has gradually increased. Following this trend, various display devices including light-emitting display devices are being developed. Summary of the invention

[0005] Aspects of the present disclosure provide a display device and a method for manufacturing the display device capable of improving operating characteristics of a transistor and simplifying a manufacturing process.

[0006] However, aspects of the present disclosure may not be limited to the aspects described herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0007] According to aspects of the present disclosure, a display device is provided, which may include: a first electrode arranged on a substrate, a buffer layer arranged on the first electrode, a first transistor including a first active layer arranged on the buffer layer and a first gate electrode arranged on a portion of the first active layer, a second electrode arranged on the buffer layer and electrically connected to the first electrode, a first gate insulating layer arranged between the first active layer and the first gate electrode, and a second gate insulating layer arranged between the buffer layer and the second electrode, wherein in a plan view, an area of ​​a top surface of the first gate insulating layer may be larger than an area of ​​a bottom surface of the first gate electrode, and the first gate insulating layer may protrude outside the first gate electrode, and the second gate insulating layer and the first gate insulating layer may include the same material.

[0008] In an embodiment and in a plan view, the first active layer may include a channel region overlapping the first gate electrode, and a source region and a drain region respectively positioned at both sides of the channel region, and in a longitudinal direction of the channel region, the first gate electrode may have a first length, and the first gate insulating layer may have a second length longer than the first length.

[0009] In an implementation and in a plan view, the first gate insulating layer may overlap only a portion of the first active layer and may expose another portion of the first active layer.

[0010] In an implementation, the first gate insulating layer and the second gate insulating layer may be separated from each other.

[0011] In an embodiment, the display device may further include a second transistor and a third gate insulating layer, the second transistor including a second active layer disposed on the buffer layer and a second gate electrode disposed on a portion of the second active layer, the third gate insulating layer disposed between the second active layer and the second gate electrode, wherein in a plan view, an area of ​​a top surface of the third gate insulating layer may be larger than an area of ​​a bottom surface of the second gate electrode, and the third gate insulating layer may protrude outside the second gate electrode.

[0012] In an implementation, the third gate insulating layer and the first gate insulating layer may include the same material, and the third gate insulating layer may be separated from the first gate insulating layer.

[0013] In an embodiment and in a plan view, the first gate insulating layer may overlap only a portion of the first active layer and may expose another portion of the first active layer, and the third gate insulating layer may overlap only a portion of the second active layer and may expose another portion of the second active layer.

[0014] In an implementation and in a plan view, the first gate insulating layer may completely cover the first active layer, and the third gate insulating layer may overlap only a portion of the second active layer and may expose another portion of the second active layer.

[0015] In an implementation, the first gate insulating layer and the second gate insulating layer may be integral with each other.

[0016] In an embodiment, the first active layer and the second active layer may include the same oxide semiconductor.

[0017] In an embodiment, the display device may further include a barrier layer and a bottom gate electrode, the barrier layer being disposed between the first electrode and the buffer layer, the barrier layer may cover the first electrode in a plan view, and the bottom gate electrode may be disposed between the barrier layer and the buffer layer and may overlap with the first active layer in a plan view.

[0018] In an implementation, the second electrode may be electrically connected to the first electrode through a contact hole penetrating the barrier layer, the buffer layer, and the second gate insulating layer.

[0019] In an embodiment, the bottom gate electrode may face the first gate electrode with the first active layer disposed therebetween, and the bottom gate electrode may be electrically connected to an electrode of the first transistor.

[0020] In an implementation, the display device may further include a first insulating layer disposed on the buffer layer and covering the first active layer, the first gate insulating layer, the second gate insulating layer, the first gate electrode, and the second electrode.

[0021] In an embodiment, the first transistor may further include at least one of a source electrode disposed on the first insulating layer and electrically connected to a portion of the first active layer and a drain electrode disposed on the first insulating layer and electrically connected to another portion of the first active layer.

[0022] In an embodiment, the display device may further include: a second insulating layer disposed on the first insulating layer and covering the first transistor, a light emitting element layer including a light emitting element disposed on the second insulating layer, and an encapsulation layer covering the light emitting element layer.

[0023] According to aspects of the present disclosure, a method for manufacturing a display device can be provided, which includes: forming a first electrode on a substrate; forming a buffer layer on the substrate to cover the first electrode; forming an active layer on the buffer layer; forming a gate insulating layer on the buffer layer to cover the active layer; providing a mask on the gate insulating layer, the mask may overlap with a portion of each of the active layer and the first electrode; etching the gate insulating layer using the mask to expose another portion of the active layer and form a contact hole penetrating the gate insulating layer and the buffer layer, the contact hole may expose a portion of the first electrode; and forming a gate electrode and a second electrode on the gate insulating layer, the gate electrode may overlap with a portion of the active layer, and the second electrode may be electrically connected to a portion of the first electrode through the contact hole.

[0024] In an embodiment, the method may further include forming a barrier layer on the substrate to cover the first electrode and forming a bottom gate electrode on the barrier layer before forming the buffer layer, wherein the buffer layer may be formed on the barrier layer to cover the bottom gate electrode.

[0025] In an implementation, the contact hole may be formed to penetrate the gate insulating layer, the buffer layer, and the barrier layer.

[0026] In an embodiment, etching the gate insulating layer using a mask may form a first gate insulating layer overlapping a portion of the active layer and a second gate insulating layer overlapping a portion of the first electrode.

[0027] A display device according to an embodiment may include: a transistor including an active layer and a gate electrode on the active layer; and a gate insulating layer disposed between the active layer and the gate electrode and protruding to the outside of the gate electrode, while including a top surface having an area larger than that of the bottom surface of the gate electrode. The gate insulating layer may cover not only a channel region of the active layer overlapping with the gate electrode, but also a portion of each of the source region and the drain region that does not overlap with the gate electrode. Accordingly, the effective channel length of the transistor may be fully ensured, and the operating characteristics of the transistor may be improved and / or ensured.

[0028] In an embodiment, the gate electrode and the gate insulating layer may be separately patterned through separate etching processes using different masks. Accordingly, the gate electrode and the active layer of the transistor may be stably insulated, and a short circuit defect of the transistor may be prevented.

[0029] In an embodiment, the display device may further include a first electrode disposed below the transistor and a second electrode disposed on the first electrode and electrically connected to the first electrode. The gate insulating layer may be etched in a mask process to form a contact hole connecting the first electrode and the second electrode. Accordingly, the mask process for patterning the gate electrode and the mask process for patterning the gate insulating layer may be separated without adding an additional mask process. In addition, without adding an additional mask process, the gate insulating layer may be etched differently and / or selectively as needed for each transistor.

[0030] According to the display device and the method for manufacturing the display device according to the embodiment, it is possible to simplify and / or streamline the manufacturing process of the display device while improving the operating characteristics of the transistor belonging to the display device. Therefore, the manufacturing efficiency of the display device can be improved.

[0031] However, the effects according to the embodiments of the present disclosure may not be limited to those exemplified above, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0033] Figure 1 is a plan view showing a display device according to an embodiment;

[0034] Figure 2 It is shown Figure 1 A plan view of a display panel;

[0035] Figure 3 is a schematic cross-sectional view showing a display panel according to an embodiment;

[0036] Figure 4 is a schematic cross-sectional view showing a display panel according to an embodiment; and

[0037] Figures 5 to 12 is a schematic cross-sectional view illustrating a method for manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0038] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words as non-limiting examples of the device or method disclosed herein. However, it is apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments do not have to be exclusive, nor do they have to limit the present disclosure. For example, the specific shape, configuration, and characteristics of an embodiment can be used or implemented in another embodiment.

[0039] Unless otherwise specified, the embodiments shown should be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of various embodiments (hereinafter individually or collectively referred to as "elements") can be combined, separated, interchanged and / or rearranged in other ways without departing from the concept of the present invention.

[0040] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the embodiment can be implemented in different ways, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals and / or reference symbols represent the same elements.

[0041] When an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it may be directly on, directly connected to or directly coupled to another element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly" "on", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection and / or a fluid connection with or without an intervening element. In addition, the X-axis, Y-axis and Z-axis are not limited to the three axes of a rectangular coordinate system (such as an x-axis, a y-axis and a z-axis), and may be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0042] For the purpose of this disclosure, "at least one of A and B" may be interpreted as only A, only B, or a combination of A and B. In addition, "at least one of A, B, and C" and "at least one selected from the group consisting of A, B, and C" may be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0044] Spatially relative terms such as "beneath," "below," "under," "lower," "above," "upper," "over," "higher," "side" (e.g., as in "sidewall"), and the like may be used herein for descriptive purposes, and thus, to describe the relationship of one element to another element(s) as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, elements described as being "below" or "beneath" other elements or features would subsequently be oriented to be "above" the other elements or features. Thus, the term "below" is capable of encompassing both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and thus, the spatially relative descriptors used herein are interpreted accordingly.

[0045] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" as used herein are also intended to include the plural forms. In addition, when the terms "comprises", "comprising", "includes" and / or "including" are used in this specification, the existence of the stated features, wholes, steps, operations, elements, parts and / or clusters thereof is specified, but the existence or addition of one or more other features, wholes, steps, operations, elements, parts and / or clusters thereof is not excluded. It is also noted that, as used herein, the terms "substantially", "about" and other similar terms are used as terms of approximation rather than terms of degree, and thus, are utilized to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0046] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations as schematic illustrations of embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the embodiments disclosed herein should not necessarily be construed as limited to the shapes of the particular illustrated regions, but rather include deviations in shape resulting from, for example, manufacturing. In this manner, the regions illustrated in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and thus are not necessarily intended to be limiting.

[0047] Unless otherwise defined or implied herein, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that, unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal sense.

[0048] Figure 1 is a plan view showing a display device 100 according to an embodiment. Figure 2 It is shown Figure 1 FIG. 1 is a plan view of a display panel 110 .

[0049] Reference Figure 1 and Figure 2, the display device 100 may be a device for displaying a moving image or a still image. The display device 100 may be used as a display screen of various devices such as televisions, notebook computers, monitors, billboards, and Internet of Things (IoT) devices, and portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs). These may be presented as examples only, and the display device 100 may be applicable to various other types of electronic devices.

[0050] In an embodiment, the display device 100 may be a light-emitting display device, such as an organic light-emitting display including an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, or an ultra-small light-emitting display using an ultra-small light-emitting diode such as a micro or nano light-emitting diode (micro-LED or nano-LED), but is not limited thereto. For example, the display device 100 may be another type of display device other than the light-emitting display device. Hereinafter, an embodiment in which the display device 100 may be an organic light-emitting display device will be disclosed.

[0051] The display device 100 may include a display panel 110 including pixels PX, and a first driver 120 and a second driver 130 configured to supply a driving signal to the pixels PX. The display device 100 may also include additional components. For example, the display device 100 may also include a power supply section for supplying a power supply voltage to the pixels PX, the first driver 120 and the second driver 130, and a timing controller for controlling the operation of the first driver 120 and the second driver 130.

[0052] The display panel 110 may include a display area DA and a non-display area NDA. The display area DA may be an area including pixels PX to display an image. The non-display area NDA may be an area other than the display area DA, and an image may not be displayed in the non-display area NDA. In an embodiment, the non-display area NDA may be positioned around the display area DA and may surround the display area DA.

[0053] exist Figure 1 and Figure 2 In the embodiment, a first direction D1, a second direction D2, and a third direction D3 may be defined. In an embodiment, the first direction D1 may be a horizontal direction (e.g., a row direction or an X direction) of the display panel 110, and the second direction D2 may be a vertical direction (e.g., a column direction or a Y direction) of the display panel 110. The third direction D3 may be a thickness direction (e.g., a height direction or a Z direction) of the display panel 110.

[0054] In an embodiment, the display panel 110 may have a rectangular shape in a plan view. Figure 1 and Figure 2 The display panel 110 is shown to have a horizontal length longer than a vertical length, but the shape of the display panel 110 is not limited thereto. For example, the display panel 110 may have a shape with a vertical length longer than a horizontal length, a square shape, or the like. The display panel 110 may include angled corners or rounded corners.

[0055] The planar shape of the display panel 110 may not be limited to the quadrilateral shape shown, and it may be applied to other shapes. For example, the display panel 110 may have a non-quadrilateral polygonal shape, a circular shape, an elliptical shape, an atypical shape, or other shapes in a plan view.

[0056] In an embodiment, the display panel 110 may be substantially flat on a plane defined by the first direction D1 and the second direction D2, and may have a uniform thickness in the third direction D3. The display panel 110 may be provided in a three-dimensional shape having a bent surface or the like.

[0057] The display panel 110 may be provided as a rigid panel so as not to be substantially deformed, or as a flexible panel capable of being deformed to be at least partially folded, bent, or rolled. The display panel 110 may be provided to the display device 100 without being bent, or may be provided to the display device 100 while being partially bent.

[0058] The display panel 110 may include a substrate SUB and pixels PX disposed on the substrate SUB. The pixels PX may be disposed in a display area DA on the substrate SUB.

[0059] The substrate SUB may be a base member for manufacturing or providing the display panel 110, and may form a base surface of the display panel 110. The substrate SUB may include a display area DA and a non-display area NDA around the display area DA.

[0060] The display area DA may have various shapes according to the embodiment. For example, the display area DA may have a quadrilateral shape, a non-quadrilateral polygonal shape, a circular shape, an elliptical shape, an atypical shape, or other shapes. In an embodiment, the display area DA may have a shape corresponding to the shape of the display panel 110, but the present disclosure may not be limited thereto.

[0061] The pixels PX may be provided and / or arranged in the display area DA. For example, the display area DA may include a plurality of pixel areas in which corresponding pixels PX may be disposed.

[0062] In an embodiment, the display device 100 may be a light-emitting display device, and each pixel PX may include a light-emitting element positioned in a corresponding emission region and a pixel circuit electrically connected to the light-emitting element. When describing an embodiment, the term "connection" may include electrical connection and / or physical connection. Each pixel circuit may include a transistor (e.g., a driving transistor that generates a driving current corresponding to a data signal, and a pixel transistor including at least one switching transistor) and at least one capacitor (e.g., a storage capacitor).

[0063] The non-display area NDA may include a pad area PA in which a pad PD may be disposed, and may also selectively include a driving circuit area. The driving circuit area may be positioned on at least one side of the display area DA. At least one driver, pad PD and / or wiring may be disposed in the non-display area NDA.

[0064] At least one driver or a portion of the driver for driving the pixel PX may be provided in the driving circuit region. For example, circuit elements constituting the first driver 120 (e.g., driver transistors and driver capacitors constituting the stage circuit of the first driver 120) may be provided in the driving circuit region on the substrate SUB. In an embodiment, the circuit elements of the first driver 120 may be formed in the display panel 110 together with the pixel PX.

[0065] The pad PD may be disposed in the pad area PA. At least one circuit board 140 may be disposed and / or bonded to the pad area PA. In an embodiment, a plurality of circuit boards 140 electrically connected to different pads PD may be disposed on the pad area PA. The pad PD may include a signal pad and a power pad for transmitting a driving signal and a power supply voltage required for driving the pixel PX and / or the first driver 120 to the display panel 110.

[0066] The first driver 120 and the second driver 130 may generate a driving signal for controlling the operation timing, brightness, and the like of the pixel PX, and may supply the generated driving signal to the pixel PX. For example, the first driver 120 may be a gate driver including a scan driver, and may be electrically connected to the pixel PX through a corresponding gate line. The first driver 120 may supply a corresponding gate signal (for example, a control signal for controlling the driving timing of the pixel PX, which includes a scan signal and / or an emission control signal) to the pixel PX. The second driver 130 may be a data driver including a source driving circuit, and may be electrically connected to the pixel PX through a corresponding data line. The second driver 130 may supply a corresponding data signal to the pixel PX.

[0067] In an embodiment, at least one of the first driver 120 and the second driver 130 or a portion of at least one of the drivers may be embedded in the display panel 110. For example, the first driver 120 or a portion of the first driver 120 may be disposed and / or formed in the non-display area NDA and disposed on the substrate SUB of the display panel 110.

[0068] although Figure 1 It is shown that the first driver 120 may be formed at one side of the display area DA (e.g., in the non-display area NDA at the right side of the display area DA), but the embodiment may not be limited thereto. For example, the first driver 120 may be positioned only at the other side of the display area DA (e.g., in the non-display area NDA at the left side of the display area DA), or may be positioned at both sides of the display area DA (e.g., in the non-display area NDA at the left and right sides of the display area DA). A portion of the first driver 120 may be positioned in the non-display area NDA, and another portion of the first driver 120 may be positioned in a non-emission area inside the display area DA (e.g., an area between emission areas of the pixels PX).

[0069] In an embodiment, the other driver of the first driver 120 and the second driver 130 or a portion of the other driver may be disposed or formed outside the display panel 110 to be electrically connected to the display panel 110. For example, the second driver 130 may be implemented as a plurality of integrated circuit chips, which may be disposed on a circuit board 140 electrically connected to the pixels PX of the display panel 110. The second driver 130 may be implemented as at least one integrated circuit chip and mounted on the non-display area NDA of the display panel 110.

[0070] The circuit board 140 may be electrically connected to the display panel 110 through the pad PD. In an embodiment, the circuit board 140 may be a flexible film such as a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a chip on film (COF), but may not be limited thereto. In an embodiment, the circuit board 140 may be electrically connected to the timing controller and / or the power supply part through another circuit board, a connector, or the like.

[0071] Figure 3 is a schematic cross-sectional view showing a display panel 110 according to an embodiment. For example, Figure 3 A portion of the display area DA and a portion of the non-display area NDA of the display panel 110 are shown. Figure 3 A light emitting display panel including a light emitting element ED (eg, an organic light emitting diode) is shown as an example of the display panel 110 to which the embodiments may be applied.

[0072] Apart from Figure 1 and Figure 2In addition, refer to Figure 3 , the display panel 110 may include a substrate SUB (also referred to as a "base layer"), a panel circuit layer PCL, a light emitting element layer LEL, and an encapsulation layer ENL. The panel circuit layer PCL, the light emitting element layer LEL, and the encapsulation layer ENL may be disposed to overlap each other on the substrate SUB. For example, for the display area DA, the panel circuit layer PCL, the light emitting element layer LEL, and the encapsulation layer ENL may be sequentially disposed on the substrate SUB in a third direction D3. However, the embodiment may not be limited thereto, and the positions of the panel circuit layer PCL, the light emitting element layer LEL, and / or the encapsulation layer ENL may be changed.

[0073] In an embodiment, the display panel 110 may further include additional elements provided above and / or below the encapsulation layer ENL. For example, the display panel 110 may further include at least one of a sensor layer (e.g., a touch sensor layer), an optical layer (e.g., a color filter layer and / or a wavelength conversion layer), and a passivation layer (e.g., a passivation film, an insulating layer, an upper substrate, and / or a window). Each of the sensor layer, the optical layer, and / or the passivation layer may be provided above the encapsulation layer ENL, or may be provided between the light emitting element layer LEL and the encapsulation layer ENL.

[0074] The substrate SUB may be a base member for forming the display panel 110, and may be a rigid or flexible substrate (or film). In an embodiment, the substrate SUB may be a substrate including an insulating material such as glass or the like and having rigid characteristics, and may not be bent. The substrate SUB may be a flexible substrate including polyimide or another insulating material, and may be deformable to be bent, folded, or curled, and may be bent or may not be bent. The type and / or material of the substrate SUB may vary according to the embodiment.

[0075] The substrate SUB may include a display area DA and a non-display area NDA. In an embodiment, the display area DA may include a pixel area PXA corresponding to the pixel PX, and the non-display area NDA may include a driving circuit area DRA. For example, a pixel area PXA where the pixel PX may be disposed may be defined in the display area DA, and a driving circuit area DRA where the first driver 120 may be disposed may be defined in the non-display area NDA.

[0076] The panel circuit layer PCL may be disposed on the substrate SUB. The panel circuit layer PCL may include circuit elements including pixel transistors Tpx and driver transistors Tdr, and wiring (eg, signal lines and power lines). In an embodiment, the panel circuit layer PCL may further include additional conductive patterns (eg, bridge patterns).

[0077] The pixel transistor Tpx may be included in a pixel circuit of each pixel PX and may be located in the display area DA. For example, each pixel transistor Tpx may be disposed in a pixel area PXA in which a corresponding pixel PX may be located. Figure 3 , a pixel transistor Tpx (eg, a pixel transistor Tpx electrically connected to a light emitting element ED of a corresponding pixel PX) may be shown to represent the above-described pixel transistor Tpx, and this will be referred to as a “first transistor TFT1 ”.

[0078] The driver transistor Tdr may be included in the first driver 120 or the like, and may be positioned in the driving circuit area DRA. In an embodiment, the driving circuit area DRA may be positioned in the non-display area NDA. Figure 3 In the figure, only one driver transistor Tdr may be shown to represent the above-mentioned driver transistor Tdr, and this will be referred to as "second transistor TFT2".

[0079] Each transistor TFT (e.g., the first transistor TFT1 or the second transistor TFT2) may include an active layer (e.g., the first active layer ACT1 or the second active layer ACT2) and a gate electrode (e.g., the first gate electrode GE1 or the second gate electrode GE2) disposed on the active layer. In an embodiment, each transistor TFT may further include at least one of a bottom gate electrode (e.g., the first bottom gate electrode BG1 or the second bottom gate electrode BG2), a source electrode (e.g., the first source electrode SE1 or the second source electrode SE2), and a drain electrode (e.g., the first drain electrode DE1 or the second drain electrode DE2).

[0080] The pixel circuit of each pixel PX may further include at least one capacitor. For example, a first capacitor electrode CE1 (also referred to as a "capacitor electrode") may be disposed in each pixel region PXA. In an embodiment, at least one electrode of the first transistor TFT1 (e.g., the first bottom gate electrode BG1 and / or the first source electrode SE1) and / or the first active layer ACT1 of the first transistor TFT1 may form a capacitor between them and the first capacitor electrode CE1. Accordingly, at least one electrode of the first transistor TFT1 and / or the first active layer ACT1 may constitute a second capacitor electrode. For example, each pixel PX may include a capacitor (e.g., a storage capacitor) including a first capacitor electrode CE1 and a second capacitor electrode, and the second capacitor electrode and at least one electrode of the first transistor TFT1 and / or the first active layer ACT1 may be integrated with each other.

[0081] The panel circuit layer PCL may further include a plurality of insulating layers disposed on the substrate SUB. For example, the panel circuit layer PCL may include a barrier layer BRL, a buffer layer BFL, a gate insulating layer GI, a first insulating layer INS1 (e.g., an interlayer insulating layer), and a second insulating layer INS2 (e.g., a passivation layer) sequentially disposed on the substrate SUB in the third direction D3.

[0082] In an embodiment, at least one insulating layer provided in the panel circuit layer PCL may be completely disposed in the display area DA and / or the driving circuit area DRA. For example, the barrier layer BRL, the buffer layer BFL, the first insulating layer INS1, and the second insulating layer INS2 may be completely disposed in the display area DA and the driving circuit area DRA.

[0083] In an embodiment, the gate insulating layer GI may include an insulating pattern partially disposed in the display area DA and the driving circuit area DRA. For example, the gate insulating layer GI may include an insulating pattern disposed on a portion of each of the active layer of the pixel transistor Tpx and the active layer of the driver transistor Tdr. In an embodiment, the gate insulating layer GI may include a first gate insulating layer GI1 (also referred to as a "first gate insulating pattern") and a second gate insulating layer GI2 (also referred to as a "second gate insulating pattern") positioned in the display area DA, and a third gate insulating layer GI3 (also referred to as a "third gate insulating pattern") positioned in the driving circuit area DRA. However, embodiments may not be limited thereto. For example, the gate insulating layer GI may be completely disposed in the display area DA or the driving circuit area DRA.

[0084] The first gate insulating layer GI1 may be disposed on a portion of the first active layer ACT1 of the first transistor TFT1. The first gate insulating layer GI1 may expose another portion of the first active layer ACT1.

[0085] The second gate insulating layer GI2 may be positioned in the region of each pixel region PXA. In an embodiment, the second gate insulating layer GI2 may be disposed below at least the second electrode CE12 of the first capacitor electrode CE1. For example, the second gate insulating layer GI2 may be disposed between the second electrode CE12 of the first capacitor electrode CE1 and the buffer layer BFL. In an embodiment, the second gate insulating layer GI2 may be separated from the first gate insulating layer GI1 in each pixel region PXA and / or the display area DA. For example, the first gate insulating layer GI1 and the second gate insulating layer GI2 may be formed as separate patterns that can be separated from each other.

[0086] The third gate insulating layer GI3 may be disposed on a portion of the second active layer ACT2 of the second transistor TFT2. The third gate insulating layer GI3 may expose another portion of the second active layer ACT2. In an embodiment, the third gate insulating layer GI3 may be separated from the first gate insulating layer GI1 and / or the second gate insulating layer GI2. By way of example, the third gate insulating layer GI3 may be formed as an insulating pattern spaced apart from the first gate insulating layer GI1 and the second gate insulating layer GI2.

[0087] In an embodiment, the first gate insulating layer GI1, the second gate insulating layer GI2, and the third gate insulating layer GI3 may be simultaneously formed by a process of forming an insulating film using the same insulating material and a process of patterning the insulating film. Accordingly, the first gate insulating layer GI1, the second gate insulating layer GI2, and the third gate insulating layer GI3 may be disposed and / or formed at substantially the same layer and may include the same material.

[0088] In an embodiment, the gate insulating layer GI to be patterned into the first gate insulating layer GI1, the second gate insulating layer GI2, and / or the third gate insulating layer GI3 may be etched in a separate patterning process using a mask different from a mask used in a patterning process of the third conductive layer CDL3 forming the first gate electrode GE1, the second gate electrode GE2, and / or the second electrode CE12. Accordingly, regardless of the shape and / or size of the first gate electrode GE1, the second gate electrode GE2, and / or the second electrode CE12, the first gate insulating layer GI1, the second gate insulating layer GI2, and / or the third gate insulating layer GI3 may be formed in a desired shape and / or size. When the third conductive layer CDL3 and the gate insulating layer GI are sequentially (or substantially simultaneously) etched by using a mask used in the patterning process of the third conductive layer CDL3, as the mask degrades, byproducts that may appear as a result of the end of the pattern of the third conductive layer CDL3 (e.g., the first gate electrode GE1, the second gate electrode GE2, and / or the second electrode CE12) being exposed may adhere to the side surface of the pattern of the gate insulating layer GI (e.g., the first gate insulating layer GI1, the second gate insulating layer GI2, and / or the third gate insulating layer GI3), resulting in a short circuit defect (e.g., a short circuit defect between the first gate electrode GE1 and the first active layer ACT1). On the other hand, in the case where the etching process of the third conductive layer CDL3 and the etching process of the gate insulating layer GI are separated as in the present embodiment, the short circuit defect can be prevented. Accordingly, it is possible to prevent defects in the display device 100 and improve yield.

[0089] In an embodiment, the gate insulating layer GI may be etched in the step of forming the first contact hole CNT1 to be patterned into the first gate insulating layer GI1, the second gate insulating layer GI2 and / or the third gate insulating layer GI3. Accordingly, it is possible to reduce the manufacturing cost of the display device 100 and improve its manufacturing efficiency. For example, by etching the gate insulating layer GI in the mask process for forming the first contact hole CNT1, the mask process for patterning the third conductive layer CDL3 and the gate insulating layer GI can be separated without adding an additional mask process.

[0090] In an embodiment, the first gate insulating layer GI1 may have an area larger than that of the first gate electrode GE1, and may protrude outside the first gate electrode GE1. For example, in a plan view, the first gate insulating layer GI1 may include a top surface having an area larger than that of a bottom surface of the first gate electrode GE1, and may protrude outside the first gate electrode GE1. In an embodiment, in a longitudinal direction of the first channel region CH1 (for example, a direction extending from one end of the first channel region CH1 adjacent to the first source region SR1 to the other end of the first channel region CH1 adjacent to the first drain region DR1), the first gate electrode GE1 may have a first length L1, and the first gate insulating layer GI1 may have a second length L2 longer than the first length L1.

[0091] For example, in addition to the portion of the first active layer ACT1 overlapping with the first gate electrode GE1 (e.g., the portion including the first channel region CH1), the first gate insulating layer GI1 may also cover another portion of the first active layer ACT1 very close to the portion of the first active layer ACT1 (e.g., a portion of the first source region SR1 and a portion of the first drain region DR1 that may be adjacent to the first channel region CH1). Accordingly, the effective channel length of the first transistor TFT1 may be sufficiently ensured, and the operating characteristics of the first transistor TFT1 may be improved and / or ensured.

[0092] In an embodiment, the first gate insulating layer GI1 may not be disposed on the remaining portion of the first active layer ACT1 (e.g., another portion of the first source region SR1 and another portion of the first drain region DR1), thereby exposing the remaining portion of the first active layer ACT1. The remaining portion of the first active layer ACT1 may be covered by the first insulating layer INS1. Accordingly, the first source region SR1 and the first drain region DR1 may be easily and / or appropriately conductive.

[0093] In an embodiment, the second gate insulating layer GI2 may have an area larger than that of the second electrode CE12 provided in the third conductive layer CDL3, and may protrude outside the second electrode CE12. For example, in a plan view, the second gate insulating layer GI2 may include a top surface having an area larger than that of a bottom surface of the second electrode CE12, and may protrude outside the second electrode CE12.

[0094] In an embodiment, the third gate insulating layer GI3 may have an area larger than that of the second gate electrode GE2, and may protrude outside the second gate electrode GE2. For example, in a plan view, the third gate insulating layer GI3 may include a top surface having an area larger than that of the bottom surface of the second gate electrode GE2, and may protrude outside the second gate electrode GE2. For example, in the longitudinal direction of the second channel region CH2 (or in the longitudinal direction of the second active layer ACT2), the third gate insulating layer GI3 may have a length longer than that of the second gate electrode GE2.

[0095] For example, in addition to the portion of the second active layer ACT2 overlapping with the second gate electrode GE2 (e.g., the portion including the second channel region CH2), the third gate insulating layer GI3 may also cover another portion of the second active layer ACT2 very close to the portion of the second active layer ACT2 (e.g., a portion of the second source region SR2 and a portion of the second drain region DR2 that may be adjacent to the second channel region CH2). Therefore, the effective channel length of the second transistor TFT2 may be sufficiently ensured, and the operating characteristics of the second transistor TFT2 may be improved and / or ensured.

[0096] In an embodiment, the third gate insulating layer GI3 may not be disposed on the remaining portion of the second active layer ACT2 (e.g., another portion of the second source region SR2 and another portion of the second drain region DR2), thereby exposing the remaining portion of the second active layer ACT2. The remaining portion of the second active layer ACT2 may be covered by the first insulating layer INS1. Accordingly, the second source region SR2 and the second drain region DR2 may be easily and / or appropriately conductive.

[0097] The first transistor TFT1 may include a first active layer ACT1 (also referred to as a "first active pattern" or a "first semiconductor pattern") and a first gate electrode GE1. In an embodiment, the first transistor TFT1 may further include a first bottom gate electrode BG1 (also referred to as a "first lower electrode" or a "first light blocking pattern"). A buffer layer BFL may be disposed between the first bottom gate electrode BG1 and the first active layer ACT1. A first gate insulating layer GI1 may be disposed between the first active layer ACT1 and the first gate electrode GE1.

[0098] In an embodiment, the first transistor TFT1 may further include a first source electrode SE1 and a first drain electrode DE1 electrically connected to different portions of the first active layer ACT1, respectively. The first transistor TFT1 may not include an additional source electrode and / or drain electrode, and the first source region SR1 and / or the first drain region DR1 of the first active layer ACT1 may be electrically connected to another circuit element, wiring, and / or conductive pattern to function as a source electrode and / or drain electrode of the first transistor TFT1.

[0099] In an embodiment, the first transistor TFT1 may be an N-type transistor. For example, the first transistor TFT1 may be an N-type oxide transistor.

[0100] The first bottom gate electrode BG1 may include or be provided in a second conductive layer CDL2 on the substrate SUB. In an embodiment, the second conductive layer CDL2 may be disposed between the barrier layer BRL and the buffer layer BFL. The second conductive layer CDL2 may be covered by the buffer layer BFL.

[0101] The first bottom gate electrode BG1 may overlap the first active layer ACT1. For example, the first bottom gate electrode BG1 may be disposed below the first active layer ACT1 to overlap at least the first channel region CH1. By disposing the first bottom gate electrode BG1 below the first active layer ACT1, external light may be prevented from reaching the first active layer ACT1 (for example, the first channel region CH1), and operating characteristics of the first transistor TFT1 may be stabilized.

[0102] The first bottom gate electrode BG1 and the first active layer ACT1 may be spaced apart from each other with the buffer layer BFL disposed therebetween. The first bottom gate electrode BG1 may face the first gate electrode GE1 with the first active layer ACT1 disposed therebetween.

[0103] In an embodiment, the first bottom gate electrode BG1 may be electrically connected to an electrode of the first transistor TFT1. In an embodiment, the first transistor TFT1 may be a driving transistor of the pixel PX, and the first bottom gate electrode BG1 may be electrically connected to the first source electrode SE1. The first transistor TFT1 may be a switching transistor of the pixel PX, and the first bottom gate electrode BG1 may be electrically connected to the first gate electrode GE1. For example, the first bottom gate electrode BG1 may be electrically connected to the first source electrode SE1 or the first gate electrode GE1, and may be used as a back gate electrode for adjusting characteristics of the first transistor TFT1.

[0104] The first active layer ACT1 may include or be provided in a semiconductor layer SCL on the substrate SUB. In an implementation, the semiconductor layer SCL may be disposed on the buffer layer BFL and may be covered by the gate insulating layer GI and the first insulating layer INS1.

[0105] The first active layer ACT1 may include a first channel region CH1, and a first source region SR1 and a first drain region DR1 spaced apart from each other with the first channel region CH1 disposed therebetween. For example, the first source region SR1 and the first drain region DR1 may be positioned at both sides of the first channel region CH1, respectively. The first channel region CH1 may be a region that maintains semiconductor characteristics without becoming conductive. The first source region SR1 and the first drain region DR1, which may be regions that have become conductive, may have a higher carrier concentration (e.g., electron concentration) than that of the first channel region CH1.

[0106] The first active layer ACT1 may overlap the first bottom gate electrode BG1 and the first gate electrode GE1. For example, a portion of the first active layer ACT1 including the first channel region CH1 may overlap the first bottom gate electrode BG1 and the first gate electrode GE1.

[0107] In an embodiment, the first active layer ACT1 may include an oxide semiconductor. For example, the first active layer ACT1 may include at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), indium zinc oxide (IZO), indium oxide (InO), titanium oxide (TiO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc tin oxide (IZTO), and indium tin gallium zinc oxide (ITGZO), or other oxide semiconductors.

[0108] In an embodiment, the first active layer ACT1 may be made of a high-mobility oxide semiconductor (eg, having a thickness of about 20 cm 2 / Vs or about 30cm 2 / Vs or greater mobility) is formed. For example, the first active layer ACT1 may be formed of indium gallium zinc oxide (IGZO) or indium tin gallium zinc oxide (ITGZO), and may have a conductivity equal to or greater than about 30 cm 2 / Vs. In the case where the first active layer ACT1 is formed of such an oxide semiconductor having high mobility, the conductivity of the first source region SR1 and the first drain region DR1 can be appropriately and / or easily ensured without performing an additional doping process or the like. In the case where the first active layer ACT1 is formed of such an oxide semiconductor having high mobility, when the first transistor TFT1 is formed to a microscopic size (for example, including the size of the active layer having a width and / or length in the range of about several micrometers to tens of micrometers), the mobility of the first transistor TFT1 can be appropriately ensured.

[0109] The first gate insulating layer GI1 may be disposed on the first active layer ACT1. The first gate insulating layer GI1 may be disposed between the first active layer ACT1 and the first gate electrode GE1.

[0110] In an embodiment, the first gate insulating layer GI1 may be disposed only on a portion of the first active layer ACT1 overlapping the first gate electrode GE1, and may not be disposed on another portion of the first active layer ACT1. For example, the first gate insulating layer GI1 may cover a portion of the first active layer ACT1 including the first channel region CH1 while exposing the first source region SR1 and the first drain region DR1. However, embodiments may not be limited thereto. For example, the first gate insulating layer GI1 may be completely disposed in the display area DA.

[0111] Since the first gate insulating layer GI1 exposes the first source region SR1 and the first drain region DR1, the first source region SR1 and the first drain region DR1 may become appropriately and / or easily conductive in the manufacturing process of the display panel 110. For example, in the step of etching the gate insulating layer GI so that the first source region SR1 and the first drain region DR1 may be exposed, oxygen vacancies may appear in the first source region SR1 and the first drain region DR1 due to etching gas or the like. Accordingly, the first source region SR1 and the first drain region DR1 may be appropriately conductive in a subsequent process (for example, in a process of forming the first insulating layer INS1) without performing an additional doping process.

[0112] In an embodiment, in order to limit the carrier concentration of the first source region SR1 and the first drain region DR1 and / or the mobility of the first active layer ACT1 to an appropriate range, an oxygen supply layer may be formed between the first gate insulating layer GI1 and the first gate electrode GE1. As an example, the first transistor TFT1 may further include an oxygen supply layer including an oxide semiconductor, and the oxygen supply layer may be disposed between the first gate insulating layer GI1 and the first gate electrode GE1. The first active layer ACT1 and the oxygen supply layer of the first transistor TFT1 may include the same oxide semiconductor or different oxide semiconductors.

[0113] The first gate electrode GE1 may include or be provided in a third conductive layer CDL3 on the substrate SUB. In an embodiment, the third conductive layer CDL3 may be disposed on the gate insulating layer GI and may be covered by the first insulating layer INS1. For example, the first gate electrode GE1 may be disposed on the first gate insulating layer GI1 and covered by the first insulating layer INS1.

[0114] The first gate electrode GE1 may be disposed on the first active layer ACT1 to overlap the first channel region CH1. The first gate electrode GE1 and the first active layer ACT1 may be separated and / or spaced apart from each other with the first gate insulating layer GI1 disposed therebetween.

[0115] The first source electrode SE1 and the first drain electrode DE1 may include or be provided in a fourth conductive layer CDL4 on the substrate SUB. In an embodiment, the fourth conductive layer CDL4 may be disposed on the first insulating layer INS1 that completely covers the buffer layer BFL, the semiconductor layer SCL, the gate insulating layer GI, and the third conductive layer CDL3. The fourth conductive layer CDL4 may be covered by the second insulating layer INS2.

[0116] The first source electrode SE1 may be electrically connected to a portion of the first active layer ACT1. For example, the first source electrode SE1 may be electrically connected to the first source region SR1 through a second contact hole CNT2 penetrating the first insulating layer INS1. In an embodiment, the first source electrode SE1 may also be electrically connected to the first bottom gate electrode BG1 through a third contact hole CNT3 penetrating the buffer layer BFL and the first insulating layer INS1.

[0117] The first drain electrode DE1 may be electrically connected to another portion of the first active layer ACT1. For example, the first drain electrode DE1 may be electrically connected to the first drain region DR1 through a fourth contact hole CNT4 penetrating the first insulating layer INS1.

[0118] The second transistor TFT2 may include a second active layer ACT2 (also referred to as a "second active pattern" or a "second semiconductor pattern") and a second gate electrode GE2. In an embodiment, the second transistor TFT2 may further include a second bottom gate electrode BG2 (also referred to as a "second lower electrode" or a "second light blocking pattern"). A buffer layer BFL may be disposed between the second bottom gate electrode BG2 and the second active layer ACT2. A third gate insulating layer GI3 may be disposed between the second active layer ACT2 and the second gate electrode GE2.

[0119] In an embodiment, the second transistor TFT2 may further include a second source electrode SE2 and a second drain electrode DE2 electrically connected to different portions of the second active layer ACT2, respectively. The second transistor TFT2 may not include an additional source electrode and / or drain electrode, and the second source region SR2 and / or the second drain region DR2 of the second active layer ACT2 may be electrically connected to another circuit element, wiring and / or conductive pattern to serve as a source electrode and / or drain electrode of the second transistor TFT2.

[0120] In an embodiment, the second transistor TFT2 may be an N-type transistor. For example, the second transistor TFT2 may be an N-type oxide transistor.

[0121] The second bottom gate electrode BG2 may be included or provided in the second conductive layer CDL2 on the substrate SUB. For example, the second bottom gate electrode BG2 may be included or provided in the second conductive layer CDL2 together with the first bottom gate electrode BG1.

[0122] The second bottom gate electrode BG2 may overlap the second active layer ACT2. For example, the second bottom gate electrode BG2 may be disposed below the second active layer ACT2 to overlap at least the second channel region CH2. By disposing the second bottom gate electrode BG2 below the second active layer ACT2, external light may be prevented from reaching the second active layer ACT2 (for example, the second channel region CH2), and the operating characteristics of the second transistor TFT2 may be stabilized.

[0123] The second bottom gate electrode BG2 and the second active layer ACT2 may be spaced apart from each other with the buffer layer BFL disposed therebetween. The second bottom gate electrode BG2 may face the second gate electrode GE2 with the second active layer ACT2 disposed therebetween.

[0124] In an embodiment, the second bottom gate electrode BG2 may be electrically connected to an electrode of the second transistor TFT2. In a configuration, the second transistor TFT2 may be a buffer transistor (e.g., a pull-up or pull-down transistor) provided at the output terminal of the first driver 120 or a switch transistor other than the buffer transistor, and the second bottom gate electrode BG2 may be electrically connected to the second gate electrode GE2. For example, the second bottom gate electrode BG2 may be electrically connected to the second gate electrode GE2 and may be used as a back gate electrode for adjusting the characteristics of the second transistor TFT2.

[0125] The second active layer ACT2 may be included or provided in the semiconductor layer SCL on the substrate SUB. For example, the second active layer ACT2 may be disposed on the buffer layer BFL and may be covered by the third gate insulating layer GI3 and the first insulating layer INS1.

[0126] The second active layer ACT2 may include a second channel region CH2 and a second source region SR2 and a second drain region DR2 spaced apart from each other with the second channel region CH2 disposed therebetween. For example, the second source region SR2 and the second drain region DR2 may be positioned at both sides of the second channel region CH2, respectively. The second channel region CH2 may be a region that maintains semiconductor characteristics without becoming conductive. The second source region SR2 and the second drain region DR2, which may be a region that has become conductive, may have a carrier concentration higher than that of the second channel region CH2 (e.g., electron concentration).

[0127] The second active layer ACT2 may overlap the second bottom gate electrode BG2 and the second gate electrode GE2. For example, a portion of the second active layer ACT2 including the second channel region CH2 may overlap the second bottom gate electrode BG2 and the second gate electrode GE2.

[0128] In an embodiment, the second active layer ACT2 may include an oxide semiconductor. For example, the second active layer ACT2 may include an oxide semiconductor exemplified above as a material of the first active layer ACT1, or another oxide semiconductor. In an embodiment, the first active layer ACT1 and the second active layer ACT2 may include the same oxide semiconductor. For example, the first active layer ACT1 and the second active layer ACT2 may be simultaneously formed on the buffer layer BFL using the same oxide semiconductor. Accordingly, the manufacturing process of the display panel 110 may be simplified and / or streamlined, and the manufacturing efficiency may be improved.

[0129] The third gate insulating layer GI3 may be disposed on the second active layer ACT2. The third gate insulating layer GI3 may be disposed between the second active layer ACT2 and the second gate electrode GE2.

[0130] In an embodiment, the third gate insulating layer GI3 may be disposed only on a portion of the second active layer ACT2 overlapping the second gate electrode GE2, and may not be disposed on another portion of the second active layer ACT2. For example, the third gate insulating layer GI3 may cover a portion of the second active layer ACT2 including the second channel region CH2 while exposing the second source region SR2 and the second drain region DR2. However, embodiments may not be limited thereto. For example, the third gate insulating layer GI3 may completely cover the active layer provided in at least one driver transistor Tdr.

[0131] Since the third gate insulating layer GI3 exposes the second source region SR2 and the second drain region DR2, the second source region SR2 and the second drain region DR2 may become appropriately and / or easily conductive in the manufacturing process of the display panel 110. For example, in the step of etching the gate insulating layer GI so that the second source region SR2 and the second drain region DR2 may be exposed, oxygen vacancies may occur in the second source region SR2 and the second drain region DR2 due to etching gas or the like. Therefore, the second source region SR2 and the second drain region DR2 may be appropriately conductive in a subsequent process without performing an additional doping process.

[0132] The second gate electrode GE2 may be included or provided in the third conductive layer CDL3. For example, the second gate electrode GE2 may be disposed on the gate insulating layer GI (eg, the third gate insulating layer GI3), and may be covered by the first insulating layer INS1.

[0133] The second gate electrode GE2 may be disposed on a portion of the second active layer ACT2 to overlap the second channel region CH2. The second gate electrode GE2 and the second active layer ACT2 may be separated and / or spaced apart from each other with the third gate insulating layer GI3 disposed therebetween.

[0134] The second source electrode SE2 and the second drain electrode DE2 may be included or provided in the fourth conductive layer CDL4. For example, the second source electrode SE2 and the second drain electrode DE2 may be disposed on the first insulating layer INS1 and may be covered by the second insulating layer INS2.

[0135] The second source electrode SE2 may be electrically connected to a portion of the second active layer ACT2. For example, the second source electrode SE2 may be electrically connected to the second source region SR2 through a fifth contact hole CNT5 penetrating the first insulating layer INS1.

[0136] The second drain electrode DE2 may be electrically connected to another portion of the second active layer ACT2. For example, the second drain electrode DE2 may be electrically connected to the second drain region DR2 through a sixth contact hole CNT6 penetrating the first insulating layer INS1.

[0137] The first capacitor electrode CE1 may be a multilayer electrode including a first electrode CE11 and a second electrode CE12 included or provided in different conductive layers. As an example, the first electrode CE11 may be a first sub-electrode (or a lower electrode layer) of the first capacitor electrode CE1 included or provided in the first conductive layer CDL1, and the second electrode CE12 may be a second sub-electrode (or an upper electrode layer) of the first capacitor electrode CE1 included or provided in the third conductive layer CDL3 and electrically connected to the first electrode CE11. The first electrode CE11 and the second electrode CE12 may be electrically connected to each other through a first contact hole CNT1 penetrating a barrier layer BRL, a buffer layer BFL, and a gate insulating layer GI (e.g., a second gate insulating layer GI2) disposed between the first conductive layer CDL1 and the third conductive layer CDL3. However, the embodiment may not be limited thereto. For example, in the case where the display panel 110 does not include the first conductive layer CDL1, the first electrode CE11 may include or be provided in a conductive layer (e.g., the second conductive layer CDL2) on the blocking layer BRL, and the first electrode CE11 and the second electrode CE12 may be electrically connected to each other via a contact hole penetrating the buffer layer BFL and the gate insulating layer GI.

[0138] In an implementation, the second electrode CE12 may be electrically connected to the first gate electrode GE1. As an example, the second electrode CE12 and the first gate electrode GE1 may be provided in the third conductive layer CDL3 to be electrically connected to each other in a plan view, and may be integrated with each other.

[0139] In an embodiment, the display panel 110 may further include at least one wiring including a plurality of sub-wirings (or sub-wiring layers) included or provided in different conductive layers, having a structure similar to that of the first capacitor electrode CE1. For example, the display panel 110 may further include a multi-layer wiring including sub-wirings included or provided in the first conductive layer CDL1, the second conductive layer CDL2, and / or the third conductive layer CDL3.

[0140] Circuit elements and electrodes of the display area DA including the first transistor TFT1 and the first capacitor electrode CE1, circuit elements of the driving circuit area DRA including the second transistor TFT2, and wirings electrically connected to the pixel PX and / or the first driver 120 may be covered by the second insulating layer INS2.

[0141] The corresponding electrodes, conductive patterns and / or wirings included or provided in the conductive layer of the panel circuit layer PCL may include at least one conductive material. For example, the electrodes, conductive patterns and / or wirings included or provided in each of the first conductive layer CDL1, the second conductive layer CDL2, the third conductive layer CDL3 and the fourth conductive layer CDL4 may include copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg) and at least one of other metals, alloys thereof or other conductive materials. In an embodiment, the electrodes, conductive patterns and / or wirings included or provided in the same conductive layer may be formed synchronously using the same conductive material.

[0142] In an embodiment, each of the electrodes, conductive patterns and / or wirings included or provided in the conductive layer of the panel circuit layer PCL may have a single-layer or multi-layer structure. For example, each of the electrodes, conductive patterns and / or wirings included or provided in the first conductive layer CDL1, the second conductive layer CDL2, the third conductive layer CDL3 and the fourth conductive layer CDL4 may have a single-layer or multi-layer structure.

[0143] The second insulating layer INS2 may be disposed on the fourth conductive layer CDL4. For example, the second insulating layer INS2 may be disposed on the first insulating layer INS1 and may cover the fourth conductive layer CDL4.

[0144] In an embodiment, the second insulating layer INS2 may have a multi-layer structure including an inorganic insulating layer and an organic insulating layer. For example, the second insulating layer INS2 may include an inorganic layer IOL and an organic layer ORL sequentially disposed on the first insulating layer INS1.

[0145] In an embodiment, each of the blocking layer BRL, the buffer layer BFL, the gate insulating layer GI, the first insulating layer INS1, and the inorganic layer IOL may include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, another inorganic insulating material, or a combination thereof). For example, each of the blocking layer BRL, the buffer layer BFL, the gate insulating layer GI, the first insulating layer INS1, and the inorganic layer IOL may be a single-layer or multi-layer inorganic insulating layer.

[0146] In an embodiment, the organic layer ORL may include at least one organic insulating layer including an organic insulating material (eg, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, other organic insulating materials, or a combination thereof). A surface (eg, a top surface) of the organic layer ORL may be substantially flat.

[0147] The light emitting element layer LEL may be disposed on the panel circuit layer PCL. For example, the light emitting element layer LEL may be positioned at least in the display area DA, and may be disposed on the second insulating layer INS2.

[0148] The light emitting element layer LEL may include a light emitting element ED of the pixel PX. For example, the light emitting element layer LEL may include a pixel defining layer PDL (also referred to as a "bank") that separates emission regions of the pixel PX and a light emitting element ED positioned in each emission region. In an embodiment, the light emitting element layer LEL may further include a spacer SPC disposed on a portion of the pixel defining layer PDL.

[0149] Each light emitting element ED may include a first electrode ET1 positioned in a corresponding emission region, and a light emitting layer EML and a second electrode ET2 sequentially disposed on the first electrode ET1. The first electrode ET1 of the light emitting element ED may be electrically connected to at least one pixel transistor Tpx (eg, first transistor TFT1) included in the corresponding pixel PX.

[0150] The first electrode ET1 of the light emitting element ED may be a single-layer or multi-layer electrode including at least one conductive material. In an embodiment, the first electrode ET1 may include a metal material having a high reflectivity. For example, the first electrode ET1 may have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or a combination thereof, or may have a structure including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3) and silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni) or a combination thereof (e.g., ITO / Mg, ITO / Ag and ITO / Ag / ITO). In addition, the first electrode ET1 may include a multilayer structure including a compound of the above metal materials, for example, ITO / MgF 2 .

[0151] The light emitting layer EML of the light emitting element ED may include a polymer material or a low molecular material. Light emitted from the light emitting layer EML may contribute to image display.

[0152] The second electrode ET2 of the light emitting element ED may include a conductive material. In an embodiment, the second electrode ET2 may be a common layer formed across the entire display area DA to cover the light emitting layer EML and the pixel defining layer PDL. In an embodiment, the second electrode ET2 may be formed of a transparent conductive material capable of transmitting light (such as ITO, IZO, ZnO, ITZO, the like, or a combination thereof), or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), an alloy of magnesium (Mg) and silver (Ag), or a combination thereof).

[0153] The pixel defining layer PDL may have an opening corresponding to each emission region and may surround the emission region. For example, the pixel defining layer PDL may be formed to cover the edge of the first electrode ET1 of the light emitting element ED and may include an opening exposing the remaining portion of the first electrode ET1. In an embodiment, the pixel defining layer PDL may include at least one organic insulating layer including an organic insulating material.

[0154] The spacer SPC may be disposed on a portion of the pixel defining layer PDL. The spacer SPC may include at least one organic insulating layer including an organic insulating material. The spacer SPC and the pixel defining layer PDL may include the same material or different materials. The pixel defining layer PDL and the spacer SPC may be sequentially formed by separate mask processes, or may be synchronously formed using a halftone mask and / or may be integrated with each other.

[0155] The encapsulation layer ENL may be disposed on the light emitting element layer LEL. The encapsulation layer ENL may cover the light emitting element layer LEL in the display area DA, and may extend to the non-display area NDA to contact the panel circuit layer PCL. The encapsulation layer ENL may prevent oxygen or moisture from penetrating into the light emitting element layer LEL, and may reduce electrical and / or physical influences on the panel circuit layer PCL and the light emitting element layer LEL.

[0156] In an embodiment, the encapsulation layer ENL may include a first encapsulation layer ENL1, a second encapsulation layer ENL2, and a third encapsulation layer ENL3 sequentially disposed on the light emitting element layer LEL. Each of the first encapsulation layer ENL1 and the third encapsulation layer ENL3 may be an inorganic encapsulation layer including an inorganic material. The second encapsulation layer ENL2 may be an organic encapsulation layer including an organic material.

[0157] Figure 4 is a schematic cross-sectional view showing a display panel 110 according to an embodiment. For example, Figure 4 The first gate insulating layer GI1 is shown. Figure 3 Different implementations of the invention.

[0158] Apart from Figures 1 to 3 In addition, refer to Figure 4 , the first gate insulating layer GI1 may completely cover the first active layer ACT1. For example, the first gate insulating layer GI1 may completely cover the first active layer ACT1 except for a region where contact holes (e.g., the second contact hole CNT2 and the fourth contact hole CNT4) for connecting the first source region SR1 and the first drain region DR1 to the first source electrode SE1 and the first drain electrode DE1, respectively, and to the first active layer ACT1 may be formed.

[0159] In an embodiment, Figure 3 The first gate insulating layer GI1 and the second gate insulating layer GI2 may be integrated with each other. For example, the first gate insulating layer GI1 and the second gate insulating layer GI2 may be combined into one first gate insulating layer GI1, such as Figure 4 As shown in . As an example, a first gate insulating layer GI1 may be formed across each pixel area PXA and / or the display area DA.

[0160] In an embodiment, by etching the gate insulating layer GI in the step of forming the first contact hole CNT1, the gate insulating layer GI provided in each transistor region of the pixel region PXA and / or the driving circuit region DRA may be etched differently and / or selectively as needed without adding an additional mask process. For example, the first gate insulating layer GI1 may be formed on the active layer (e.g., the first active layer ACT1) of at least one pixel transistor Tpx provided in each pixel region PXA to completely cover the active layer, and the third gate insulating layer GI3 may be formed on the active layer (e.g., the second active layer ACT2) of at least one driver transistor Tdr provided in the driving circuit region DRA to expose another portion of the active layer.

[0161] In the same manner, for the pixel transistors Tpx disposed in the corresponding pixel area PXA, the gate insulating layer GI may be etched differently and / or selectively. For example, for some of the pixel transistors Tpx, each active layer may be completely covered by the gate insulating layer GI, while for other pixel transistors, the gate insulating layer GI may be partially disposed on each active layer.

[0162] Figures 5 to 12 is a schematic cross-sectional view showing a method for manufacturing the display device 100 according to an embodiment. For example, Figures 5 to 12 Sequentially shows the formation of Figure 3 The step of forming the first capacitor electrode CE1 and the first and second transistors TFT1 and TFT2 on the substrate SUB is one of the steps of manufacturing the display panel 110 .

[0163] Apart from Figures 1 to 4 In addition, refer to Figure 5 , a substrate SUB including a display area DA and a non-display area NDA may be prepared. In an embodiment, the display area DA defined on the substrate SUB may include a pixel area PXA, and the non-display area NDA may include a driving circuit area DRA.

[0164] Thereafter, a first conductive layer CDL1 including a first electrode CE11 may be formed on the substrate SUB. For example, the first electrode CE11 may be formed in each pixel area PXA of the display area DA on the substrate SUB.

[0165] The first electrode CE11 may be formed through a film forming process (eg, a deposition process) of forming a conductive film using the above at least one conductive material and a patterning process (eg, an etching process using a mask) of patterning the conductive film.

[0166] Thereafter, a barrier layer BRL may be formed on the substrate SUB to cover the first conductive layer CDL1. The barrier layer BRL may be formed in the display area DA and the non-display area NDA. The barrier layer BRL may be formed by an insulating film forming process (e.g., a deposition process) using at least one insulating material (e.g., an inorganic insulating material) exemplified above.

[0167] Apart from Figures 1 to 5 In addition, refer to Figure 6, a second conductive layer CDL2 including a first bottom gate electrode BG1 and a second bottom gate electrode BG2 may be formed on the barrier layer BRL. For example, on the substrate SUB, a first bottom gate electrode BG1 may be formed in each pixel region PXA of the display region DA, and a second bottom gate electrode BG2 may be formed in the drive circuit region DRA. The first bottom gate electrode BG1 and the second bottom gate electrode BG2 may be formed by a film formation process (e.g., a deposition process) of a conductive film using at least one conductive material exemplified above and a patterning process (e.g., an etching process using a mask) of the conductive film.

[0168] Thereafter, the buffer layer BFL may be formed on the barrier layer BRL to cover the second conductive layer CDL2. The buffer layer BFL may be formed through a film formation process using an insulating film of at least one insulating material (eg, an inorganic insulating material) exemplified above.

[0169] Apart from Figures 1 to 6 In addition, refer to Figure 7 , a semiconductor layer SCL including a first active layer ACT1 and a second active layer ACT2 may be formed on the buffer layer BFL. For example, on the substrate SUB, the first active layer ACT1 may be formed in each pixel area PXA of the display area DA, and the second active layer ACT2 may be formed in the driving circuit area DRA. The first active layer ACT1 may be formed to overlap with the first bottom gate electrode BG1, and the second active layer ACT2 may be formed to overlap with the second bottom gate electrode BG2.

[0170] In an embodiment, the first active layer ACT1 and the second active layer ACT2 may be formed simultaneously using the same oxide semiconductor. For example, the first active layer ACT1 and the second active layer ACT2 may be formed in the display area DA and the driving circuit area DRA, respectively, by a film formation process and a patterning process of a semiconductor layer using at least one oxide semiconductor exemplified above.

[0171] Apart from Figures 1 to 7 In addition, refer to Figure 8 , a gate insulating layer GI covering the semiconductor layer SCL may be formed on the buffer layer BFL. The gate insulating layer GI may be first formed on the entire surface of the substrate SUB including the display area DA and the driving circuit area DRA. For example, the gate insulating layer GI may be formed on the buffer layer BFL and the semiconductor layer SCL by an insulating film formation process using at least one insulating material described above (e.g., an inorganic insulating material such as silicon oxide).

[0172] Thereafter, a first mask M1 (e.g., a photoresist pattern) may be disposed on the gate insulating layer GI. The first mask M1 may be disposed at a position corresponding to each insulating pattern to be provided in the gate insulating layer GI (including the first gate insulating layer GI1, the second gate insulating layer GI2, and the third gate insulating layer GI3). For example, in each pixel area PXA of the display area DA, a first mask M1 overlapping a portion of the first active layer ACT1 and a portion of the first electrode CE11 may be disposed on the gate insulating layer GI. The first mask M1 may not be disposed on other portions of the first active layer ACT1 (e.g., portions in which the first source region SR1 and the first drain region DR1 may be formed) and another portion of the first electrode CE11 (e.g., portions in which the first contact hole CNT1 may be formed). In the drive circuit area DRA, a first mask M1 overlapping a portion of the second active layer ACT2 may be disposed on the gate insulating layer GI. The first mask M1 may not be disposed on other portions of the second active layer ACT2 (e.g., portions in which the second source region SR2 and the second drain region DR2 may be formed).

[0173] Apart from Figures 1 to 8 In addition, refer to Fig. 9 , using the first mask M1, the gate insulating layer GI may be etched, and the first contact hole CNT1 may be formed using the first mask M1. For example, by etching the gate insulating layer GI to expose another portion of the first active layer ACT1 that may not be covered by the first mask M1, the first gate insulating layer GI1 may be formed on a portion of the first active layer ACT1 positioned below the first mask M1. In the same manner, the third gate insulating layer GI3 may be formed on a portion of the second active layer ACT2 positioned below the first mask M1. In addition, by etching the gate insulating layer GI, the buffer layer BFL, and the barrier layer BRL to expose another portion of the first electrode CE11 that may not be covered by the first mask M1, the first contact hole CNT1 may be formed on the first electrode CE11. For example, the first contact hole CNT1 may be formed on the first electrode CE11 to penetrate the gate insulating layer GI, the buffer layer BFL, and the barrier layer BRL. The periphery of the first contact hole CNT1 may be covered by the first mask M1, and accordingly, the second gate insulating layer GI2 may be formed on the buffer layer BFL around the first contact hole CNT1. By way of example, the second gate insulating layer GI2 may be formed on a portion of the first electrode CE11. In the same manner, the second gate insulating layer GI2 may also be formed on another portion of the pixel area PXA covered by the first mask M1. In an embodiment, the process of etching the gate insulating layer GI and the process of forming the first contact hole CNT1 may be performed substantially simultaneously by a single mask process using the first mask M1. After etching the gate insulating layer GI and forming the first contact hole CNT1, the first mask M1 may be removed.

[0174] In the process of etching the gate insulating layer GI, the properties of the first active layer ACT1 and the second active layer ACT2 may be changed so that each of the first active layer ACT1 and the second active layer ACT2 has different characteristics at different portions thereof. Accordingly, each of the first active layer ACT1 and the second active layer ACT2 may be divided into a plurality of regions having different characteristics.

[0175] For example, at a portion where the first mask M1 may not be provided, oxygen vacancies may occur in the first active layer ACT1 due to etching gas or the like. Accordingly, the first active layer ACT1 may be divided into a plurality of regions (e.g., a first channel region CH1, a first source region SR1, and a first drain region DR1) having different characteristics. In an embodiment, oxygen vacancies may occur at a portion of the first active layer ACT1 that does not overlap with the first gate insulating layer GI1 (e.g., the first source region SR1 and the first drain region DR1), and may diffuse to a portion of a region overlapping with the first gate insulating layer GI1.

[0176] Similarly, oxygen vacancies may occur in the second active layer ACT2 at a portion that does not overlap with the third gate insulating layer GI3. Accordingly, the second active layer ACT2 may be divided into a plurality of regions (e.g., a second channel region CH2, a second source region SR2, and a second drain region DR2) having different characteristics. In an embodiment, oxygen vacancies may occur at a portion of the second active layer ACT2 that does not overlap with the third gate insulating layer GI3 (e.g., the second source region SR2 and the second drain region DR2), and may diffuse to a portion of the region overlapping with the third gate insulating layer GI3.

[0177] In an embodiment, the first gate insulating layer GI1 and the third gate insulating layer GI3 may be formed to have an area larger than that of the first gate electrode GE1 and the second gate electrode GE2 to be formed in a subsequent process, respectively. For example, in the longitudinal direction of the first active layer ACT1 and the second active layer ACT2 (or the longitudinal direction of the first channel region CH1 and the second channel region CH2), the first gate insulating layer GI1 and the third gate insulating layer GI3 may be formed to have a length longer than that of the first gate electrode GE1 and the second gate electrode GE2, respectively. For example, the first gate insulating layer GI1 and the third gate insulating layer GI3 may cover a wider portion of each of the first source region SR1, the first drain region DR1, the second source region SR2, and the second drain region DR2, adjacent to the first channel region CH1 and the second channel region CH2, respectively. Accordingly, the length and / or area of ​​the region in which the first source region SR1, the first drain region DR1, the second source region SR2, and the second drain region DR2 extend in the first active layer ACT1 and the second active layer ACT2, respectively, can be reduced, and the effective channel lengths of the first channel region CH1 and the second channel region CH2 can be sufficiently ensured. Therefore, the operating characteristics of the first transistor TFT1 and the second transistor TFT2 can be improved and / or ensured.

[0178] Apart from Figures 1 to 9 In addition, refer to Fig.10 , a third conductive layer CDL3 including a second electrode CE12 and a first gate electrode GE1 and a second gate electrode GE2 may be formed on the gate insulating layer GI. For example, the first gate electrode GE1, the second electrode CE12, and the second gate electrode GE2 may be formed on the first gate insulating layer GI1, the second gate insulating layer GI2, and the third gate insulating layer GI3, respectively. In an embodiment, the first gate electrode GE1 and the second gate electrode GE2 may be formed on a portion of the first gate insulating layer GI1 and a portion of the third gate insulating layer GI3, respectively. For example, the first gate electrode GE1 and the second gate electrode GE2 may be formed on a portion of the first active layer ACT1 and a portion of the second active layer ACT2, respectively, to overlap with the first channel region CH1 and the second channel region CH2, respectively. In an embodiment, the second electrode CE12 may be formed on a portion of the second gate insulating layer GI2. The second electrode CE12 may be electrically connected to the first electrode CE11 through the first contact hole CNT1.

[0179] The second electrode CE12 and the first gate electrode GE1 and the second gate electrode GE2 may be formed by a film forming process (e.g., a deposition process) of forming a conductive film using at least one conductive material described above and a patterning process of patterning the conductive film. For example, after a conductive film is formed on a substrate SUB on which a gate insulating layer GI or the like may be provided, a second mask M2 may be provided on the conductive film. Thereafter, by performing an etching process of the conductive film using the second mask M2, the second electrode CE12 and the first gate electrode GE1 and the second gate electrode GE2 may be formed. In an embodiment, the second electrode CE12 and the first gate electrode GE1 may be formed as substantially one and the same electrode. After etching the conductive film for forming the third conductive layer CDL3, the second mask M2 may be removed.

[0180] Apart from Figures 1 to 10 In addition, refer to Fig.11 , a first insulating layer INS1 covering the semiconductor layer SCL, the gate insulating layer GI, and the third conductive layer CDL3 may be formed on the buffer layer BFL. For example, the first insulating layer INS1 may be formed on the third conductive layer CDL3 to cover the first active layer ACT1 and the second active layer ACT2, the first gate insulating layer GI1, the second gate insulating layer GI2, and the third gate insulating layer GI3, the first gate electrode GE1 and the second gate electrode GE2, and the second electrode CE12. The first insulating layer INS1 may be formed entirely in the display area DA and the non-display area NDA (e.g., the driving circuit area DRA). The first insulating layer INS1 may be formed by a film formation process using an insulating film of at least one insulating material (e.g., an inorganic insulating material) exemplified above.

[0181] In the process of forming the first insulating layer INS1, hydrogen may flow into the first active layer ACT1 and the second active layer ACT2. In an embodiment, a heat treatment process (e.g., annealing) may be additionally performed on the first active layer ACT1 and the second active layer ACT2 before or after forming the first insulating layer INS1. Even in the heat treatment process, hydrogen may flow into the first active layer ACT1 and the second active layer ACT2.

[0182] Since hydrogen may be introduced into the first active layer ACT1 and the second active layer ACT2, the first active layer ACT1 and the second active layer ACT2 may partially become conductive (e.g., N-type) at a portion including a large number of oxygen vacancies. For example, the first source region SR1, the first drain region DR1, the second source region SR2, and the second drain region DR2 may become conductive.

[0183] Thereafter, a plurality of contact holes may be formed in the first insulating layer INS1. For example, a second contact hole CNT2, a fourth contact hole CNT4, a fifth contact hole CNT5, and a sixth contact hole CNT6 may be formed penetrating the first insulating layer INS1 and exposing a portion of a corresponding one of the first active layer ACT1 and the second active layer ACT2. In an embodiment, in the case where the first bottom gate electrode BG1 is electrically connected to the first source electrode SE1, a third contact hole CNT3 penetrating the first insulating layer INS1 and the buffer layer BFL and exposing a portion of the first bottom gate electrode BG1 may be further formed.

[0184] Apart from Figures 1 to 11 In addition, refer to Fig.12 , a fourth conductive layer CDL4 including a first source electrode SE1, a first drain electrode DE1, a second source electrode SE2, and a second drain electrode DE2 may be formed on the first insulating layer INS1. In an embodiment, at least one of the first source region SR1, the first drain region DR1, the second source region SR2, and the second drain region DR2 replaces at least one of the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2, and at least one of the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may not be formed.

[0185] Through the above process, a plurality of transistors TFT including a first transistor TFT1 and a second transistor TFT2 and a plurality of capacitor electrodes including a first capacitor electrode CE1 may be formed in the display area DA and the driving circuit area DRA. A plurality of wirings may also be formed in the conductive layer of the panel circuit layer PCL. In an embodiment, elements provided in the same conductive layer or the same semiconductor layer in the display panel 110 may be formed simultaneously.

[0186] After forming the transistor TFT, the capacitor electrode and / or the wiring, the formation of Figure 3 1. The process of forming the second insulating layer INS2 shown in FIG. For example, the second insulating layer INS2 may cover the transistor TFT, the capacitor electrode and / or the wiring. Thus, the panel circuit layer PCL of the display panel 110 may be formed.

[0187] In an embodiment, when the display panel 110 includes a light emitting element layer LEL and an encapsulation layer ENL disposed on the panel circuit layer PCL, the light emitting element layer LEL and the encapsulation layer ENL may be sequentially formed on the panel circuit layer PCL. Through the above process, the display panel 110 according to the embodiment and the display device 100 including the display panel 110 may be manufactured.

[0188] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications can be made to the embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed embodiments of the present disclosure may be used only in a general and descriptive sense, and not for a limiting purpose.

Claims

1. A display device, comprising: a first electrode, the first electrode being disposed on a substrate; a buffer layer, the buffer layer being disposed on the first electrode; a first transistor including a first active layer disposed on the buffer layer and a first gate electrode disposed on a portion of the first active layer; a second electrode, the second electrode being disposed on the buffer layer and electrically connected to the first electrode; a first gate insulating layer, the first gate insulating layer being disposed between the first active layer and the first gate electrode, wherein, in a plan view, An area of ​​a top surface of the first gate insulating layer is larger than an area of ​​a bottom surface of the first gate electrode, and The first gate insulating layer protrudes outside the first gate electrode; and A second gate insulating layer is disposed between the buffer layer and the second electrode, and the second gate insulating layer and the first gate insulating layer include the same material.

2. The display device according to claim 1, wherein: In the plan view, The first active layer includes a channel region overlapping the first gate electrode, and a source region and a drain region respectively positioned at both sides of the channel region, and In a longitudinal direction of the channel region, the first gate electrode has a first length, and the first gate insulating layer has a second length longer than the first length.

3. The display device according to claim 1, wherein: In a plan view, the first gate insulating layer overlaps only a portion of the first active layer and exposes another portion of the first active layer.

4. The display device according to claim 3, wherein: The first gate insulating layer and the second gate insulating layer are separated from each other.

5. The display device according to claim 1, further comprising: a second transistor including a second active layer disposed on the buffer layer and a second gate electrode disposed on a portion of the second active layer; as well as a third gate insulating layer, the third gate insulating layer being disposed between the second active layer and the second gate electrode, wherein, in a plan view, The area of ​​the top surface of the third gate insulating layer is larger than the area of ​​the bottom surface of the second gate electrode, and The third gate insulating layer protrudes to the outside of the second gate electrode.

6. The display device according to claim 5, wherein: The third gate insulating layer and the first gate insulating layer include the same material, and The third gate insulating layer is separated from the first gate insulating layer.

7. The display device according to claim 5, wherein: In the plan view, The first gate insulating layer overlaps only a portion of the first active layer and exposes another portion of the first active layer, and The third gate insulating layer overlaps only a portion of the second active layer and exposes another portion of the second active layer.

8. The display device according to claim 5, wherein: In the plan view, The first gate insulating layer completely covers the first active layer, and The third gate insulating layer overlaps only a portion of the second active layer and exposes another portion of the second active layer.

9. The display device according to claim 8, wherein: The first gate insulating layer and the second gate insulating layer are integral with each other.

10. The display device according to claim 5, wherein: The first active layer and the second active layer include the same oxide semiconductor.

11. The display device according to claim 1, further comprising: a barrier layer, the barrier layer being disposed between the first electrode and the buffer layer, and the barrier layer covering the first electrode in a plan view; as well as A bottom gate electrode is disposed between the barrier layer and the buffer layer, and the bottom gate electrode overlaps with the first active layer in a plan view.

12. The display device according to claim 11, wherein: The second electrode is electrically connected to the first electrode through a contact hole penetrating the barrier layer, the buffer layer, and the second gate insulating layer.

13. The display device according to claim 11, wherein: The bottom gate electrode faces the first gate electrode, wherein the first active layer is disposed between the bottom gate electrode and the first gate electrode, and The bottom gate electrode is electrically connected to an electrode of the first transistor.

14. The display device according to claim 1, further comprising: A first insulating layer is disposed on the buffer layer and covers the first active layer, the first gate insulating layer, the second gate insulating layer, the first gate electrode, and the second electrode.

15. The display device according to claim 14, wherein: The first transistor further includes at least one of the following: a source electrode disposed on the first insulating layer and electrically connected to a portion of the first active layer; and A drain electrode is disposed on the first insulating layer and is electrically connected to another portion of the first active layer.

16. The display device according to claim 14, further comprising: a second insulating layer, the second insulating layer being disposed on the first insulating layer and covering the first transistor; a light emitting element layer, the light emitting element layer comprising a light emitting element disposed on the second insulating layer; as well as A packaging layer covers the light emitting element layer.

17. A method for manufacturing a display device, comprising: forming a first electrode on a substrate; forming a buffer layer on the substrate to cover the first electrode; forming an active layer on the buffer layer; forming a gate insulating layer on the buffer layer to cover the active layer; disposing a mask on the gate insulating layer, the mask overlapping a portion of each of the active layer and the first electrode; etching the gate insulating layer using the mask to expose another portion of the active layer and to form a contact hole penetrating the gate insulating layer and the buffer layer, the contact hole exposing a portion of the first electrode; as well as A gate electrode and a second electrode are formed on the gate insulating layer, the gate electrode overlaps the portion of the active layer, and the second electrode is electrically connected to the portion of the first electrode through the contact hole.

18. The method for manufacturing a display device according to claim 17, further comprising: Before forming the buffer layer, a barrier layer is formed on the substrate to cover the first electrode, and a bottom gate electrode is formed on the barrier layer. Wherein, the buffer layer is formed on the barrier layer to cover the bottom gate electrode.

19. The method for manufacturing a display device according to claim 18, wherein: The contact hole is formed to penetrate the gate insulating layer, the buffer layer, and the barrier layer.

20. The method for manufacturing a display device according to claim 17, wherein: The gate insulating layer is etched using the mask to form a first gate insulating layer overlapping the portion of the active layer and a second gate insulating layer overlapping the portion of the first electrode.

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