Display panels and display devices

Abstract

This application discloses a display panel and display device including a first thin-film transistor (TFT) located in the display area. The first TFT includes a first gate and a second gate, with the first gate located on the side of the second gate away from the first electrode. The first gate includes a connected semiconductor portion and a conductor portion, with the conductor portion located on the side of the semiconductor portion closer to the second electrode. In the thickness direction of the display panel, the second gate overlaps with a first channel, and the semiconductor portion partially overlaps with both the first channel and the second gate. This application uses an overlapping semiconductor portion with the first channel and a conductor portion located near the output electrode of the first TFT. Because the semiconductor portion has a higher impedance and the conductor portion has a lower impedance, they work together to form a gradient potential to regulate the electric field distribution in the output region of the first TFT, thereby controlling the output saturation characteristics of the first TFT and improving its stability.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] In organic light-emitting diode (OLED) display panels, conventional IGZO thin-film transistors (TFTs) are used in the display area to achieve highly stable drive current output, while high-mobility oxide (OTFTs) are used in the gate drive circuit area to achieve smaller device size and higher driving capability. Compared to the gate drive circuit area, the display area has more layers of the gate insulating layer. The more layers of the gate insulating layer, the greater the variation in the uniformity of its stacking structure, which in turn affects the uniformity and stability of the TFTs. Furthermore, the high-mobility OTFTs in the gate drive circuit area are single-layer gate insulating layers. During the dry etching process of the gate insulating layer, the over-etching is relatively large, making it difficult to control the channel length. Additionally, the driving TFTs in the display area are single-gate controlled, making it impossible to control the output characteristics of the driving TFTs. Summary of the Invention

[0003] This application provides a display panel and display device that can control the output saturation characteristics of a first thin-film transistor and improve its stability.

[0004] This application provides a display panel, including a display area and a gate driving circuit area located on at least one side of the display area. The display panel includes:

[0005] substrate;

[0006] A first thin-film transistor is disposed within the display area. The first thin-film transistor includes a first gate, a first insulating layer, a first active layer, a second insulating layer, a second gate, a first electrode, and a second electrode. The first active layer includes a first contact portion, a first channel, and a second contact portion. The first gate is disposed on the substrate. The first insulating layer covers the first gate. The first active layer is disposed on the side of the first insulating layer away from the substrate. The second insulating layer is disposed on the side of the first active layer away from the substrate. The second gate is disposed on the side of the second insulating layer away from the substrate. The first electrode is connected to the first contact portion, and the second electrode is connected to the second contact portion.

[0007] Wherein, the first gate is located on the side of the second gate away from the first electrode, the first gate includes a connected semiconductor portion and a conductor portion, the conductor portion is located on the side of the semiconductor portion closer to the second electrode, in the thickness direction of the display panel, the second gate is disposed overlapping the first channel, and the semiconductor portion partially overlaps with both the first channel and the second gate.

[0008] Optionally, in some embodiments of this application, the carrier mobility of the semiconductor portion is greater than that of the first channel.

[0009] Optionally, in some embodiments of this application, in the thickness direction of the display panel, the conductor portion at least partially overlaps with the second contact portion, and the conductor portion partially overlaps with the second electrode.

[0010] Optionally, in some embodiments of this application, a portion of the first insulating layer covers the first gate to form a structure with a height difference, and the first active layer covers the first insulating layer to form the first channel with a height difference.

[0011] Optionally, in some embodiments of this application, the material of the first channel is a metal oxide semiconductor, the material of the first insulating layer is a first silicon oxide, the material of the second insulating layer is a second silicon oxide, and the oxygen content of the second silicon oxide is greater than the oxygen content of the first silicon oxide.

[0012] Optionally, in some embodiments of this application, the width of the second insulating layer is greater than the width of the second gate.

[0013] The edge of the second insulating layer extends at least 0.5 micrometers beyond the edge of the second gate.

[0014] Optionally, in some embodiments of this application, the display panel further includes a second thin-film transistor located in the gate driving circuit region. The second thin-film transistor includes a second active layer, an etch stop layer, a third insulating layer, a third gate, a third electrode, and a fourth electrode. The second active layer includes a third contact portion, a second channel, and a fourth contact portion. The second active layer is disposed on the substrate. The etch stop layer, the third insulating layer, and the third gate are stacked sequentially on the second active layer. The third gate overlaps with the second channel. The third electrode is connected to the third contact portion, and the fourth electrode is connected to the fourth contact portion.

[0015] The carrier mobility of the second channel is greater than that of the first channel. The second active layer and the first gate are disposed on the same layer. The material of the second channel is the same as that of the semiconductor portion.

[0016] Optionally, in some embodiments of this application, the conductivity of both the third contact portion and the fourth contact portion is greater than the conductivity of the conductor portion.

[0017] Optionally, in some embodiments of this application, the width of the etching barrier layer is greater than the width of the third insulating layer.

[0018] The edge of the etching barrier layer extends at least 0.5 micrometers beyond the edge of the third insulating layer.

[0019] Optionally, in some embodiments of this application, the etching barrier layer and the first insulating layer are made of the same material and are made using the same photomask; the third insulating layer and the second insulating layer are made of the same material and are made using the same photomask; the second active layer and the first gate are made using the same photomask; and the second gate and the third gate are made of the same material and are made using a single photomask.

[0020] Optionally, in some embodiments of this application, the display panel is an electroluminescent panel, and the second electrode is connected to the anode.

[0021] Accordingly, this application also provides a display device, including a display panel as described in any of the above embodiments.

[0022] The display panel and display device of this application embodiment include a first thin-film transistor located in the display area. The first thin-film transistor includes a first gate and a second gate. The first gate is located on the side of the second gate away from the first electrode. The first gate includes a semiconductor portion and a conductor portion connected together. The conductor portion is located on the side of the semiconductor portion close to the second electrode. In the thickness direction of the display panel, the second gate is disposed overlapping the first channel. The semiconductor portion simultaneously overlaps the first channel and the second gate portion.

[0023] Understandably, placing the first gate near the second electrode is intended to regulate the output saturation characteristics of the output region of the first thin-film transistor (TFT) and thus improve the output characteristics of the pixel driving transistor. By overlapping the semiconductor portion with the first channel and placing the conductor portion near the output electrode of the TFT, the potential of the semiconductor portion is relatively lower than that of the conductor portion due to the higher impedance of the semiconductor portion and the lower impedance of the conductor portion. This reduces the influence of the electric field of the first gate on the first channel, improving the lifespan of the TFT. Furthermore, since the first gate can form two different potentials, the electric field distribution in the output region of the TFT can be synergistically regulated to control the output saturation characteristics of the TFT and improve its stability. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application;

[0025] Figure 2 This is a partial structural schematic diagram of the display panel provided in an embodiment of this application;

[0026] Figure 3This is a schematic diagram of step B01 in the method for preparing a display panel provided in this application embodiment;

[0027] Figure 4 This is a schematic diagram of step B02 in the method for preparing a display panel provided in this application embodiment;

[0028] Figure 5 This is a schematic diagram of step B03 in the method for preparing a display panel provided in this application embodiment;

[0029] Figure 6 This is a schematic diagram of step B04 in the method for preparing a display panel provided in this application embodiment;

[0030] Figure 7 This is a schematic diagram of step B05 in the method for preparing a display panel provided in this application embodiment;

[0031] Figure 8 This is a schematic diagram of step B06 in the method for preparing a display panel provided in this application embodiment;

[0032] Figure 9 This is a schematic diagram of step B07 in the method for preparing a display panel provided in this application embodiment;

[0033] Figure 10 This is a schematic diagram of the structure of the display device provided in the embodiments of this application. Detailed Implementation

[0034] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific implementation methods described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, the embodiments can be combined with each other but will not be described in detail one by one. Unless otherwise stated, the directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device; the terms "first," "second," "third," etc. are only used as markings and do not impose numerical requirements or establish a sequence.

[0035] This application provides a display panel and a display device, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0036] Please refer to Figure 1 and Figure 2 This application provides a display panel 100, including a display area AA and a gate driving circuit area DA located on at least one side of the display area AA. The display panel 100 includes a substrate 11, a first thin-film transistor T1, and a second thin-film transistor T2. The first thin-film transistor T1 is disposed in the display area AA, and the second thin-film transistor T2 is disposed in the gate driving circuit area DA.

[0037] The first thin-film transistor T1 includes a first gate 101, a first insulating layer 102, a first active layer 103, a second insulating layer 104, a second gate 105, a first electrode 106, and a second electrode 107. The first active layer 103 includes a first contact portion 1a, a first channel 1b, and a second contact portion 1c. The first gate 101 is disposed on a substrate 11. The first insulating layer 102 covers the first gate 101. The first active layer 103 is disposed on the side of the first insulating layer 102 away from the substrate 11. The second insulating layer 104 is disposed on the side of the first active layer 103 away from the substrate 11. The second gate 105 is disposed on the side of the second insulating layer 104 away from the substrate 11. The first electrode 106 is connected to the first contact portion 1a, and the second electrode 107 is connected to the second contact portion 1c.

[0038] The first gate 101 is located on the side of the second gate 105 away from the first electrode 106. The first gate 101 includes a connected semiconductor portion y1 and a conductor portion y2, with the conductor portion y2 located on the side of the semiconductor portion y1 closer to the second electrode 107. In the thickness direction of the display panel 100, the second gate 105 overlaps with the first channel 1b, and the semiconductor portion y1 partially overlaps with both the first channel 1b and the second gate 105.

[0039] Optionally, the display panel 100 is an electroluminescent panel, and the second electrode 107 is connected to the anode 12. The following description uses the display panel 100 as an example of an electroluminescent panel.

[0040] It is understandable that the first gate 101 is positioned near the second electrode 107 to regulate the output saturation characteristics of the output region of the first thin-film transistor T1, thereby improving the output characteristics of the pixel driving transistor. By employing a semiconductor portion y1 overlapping with the first channel 1b and a conductor portion y2 positioned near the output of the first thin-film transistor T1, and considering that the impedance of the semiconductor portion y1 is higher than that of the conductor portion y2, the potential of the semiconductor portion y1 is relatively lower than that of the conductor portion y2. This reduces the influence of the electric field of the first gate 101 on the first channel 1b, improving the lifespan of the first thin-film transistor T1. Furthermore, since the first gate 101 can form two different potentials, the electric field distribution in the output region of the first thin-film transistor T1 can be synergistically regulated to control the output saturation characteristics of the first thin-film transistor T1 and improve its stability.

[0041] It should be noted that the second electrode 107 is the output electrode of the first thin-film transistor T1, and it is connected to the anode 12.

[0042] Optionally, the display panel 100 further includes an interlayer dielectric layer 13, a passivation layer 14, a planarization layer 15, a light-shielding layer 16, and a buffer layer 17. The interlayer dielectric layer 13 covers the second gate electrode 105 and the substrate 11. The first electrode 106 and the second electrode 107 are disposed on the side of the interlayer dielectric layer 13 away from the substrate 11. The passivation layer 14 covers the first electrode 106, the second electrode 107, and the interlayer dielectric layer 13. The planarization layer 15 covers the passivation layer 14. The anode 12 is disposed on the side of the planarization layer 15 away from the substrate 11. The light-shielding layer 16 is disposed on the substrate 11 and overlaps with the first thin-film transistor T1. The buffer layer 17 covers the light-shielding layer 16 and the substrate 11. The first gate electrode 101 is disposed on the side of the buffer layer 17 away from the substrate 11.

[0043] In some embodiments, the interlayer dielectric layer 13 can be omitted, so that the first electrode 106 and the second electrode 107 can be directly connected to the first active layer 103.

[0044] The display panel 100 also includes a light-emitting functional layer and a cathode, which are stacked sequentially on the anode 12.

[0045] Optionally, the material of the light-emitting functional layer can be an organic material, such as Alq3, bis(2-methyl-8-hydroxyquinoline-N1,O8)-(1,1'-biphenyl-4-hydroxy)aluminum (BAlq), DPVBi, Almq3, or 3-tert-butyl-9,10-bis(2-naphthyl)anthracene (TBADN).

[0046] The material of the light-emitting layer can also be an inorganic material, such as one or more selected from group IV semiconductor nanocrystals, group II-V semiconductor nanocrystals, group II-VI semiconductor nanocrystals, group IV-VI semiconductor nanocrystals, group III-V semiconductor nanocrystals, and group III-VI semiconductor nanocrystals. For example, it can be one or more of silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, indium arsenide quantum dots, and gallium nitride quantum dots.

[0047] Optionally, the material of the first active layer 103 includes at least an amorphous metal oxide material containing indium, gallium, and zinc. Optionally, the material of the first channel 1b is an amorphous metal oxide material containing indium, gallium, and zinc.

[0048] Optionally, the first thin-film transistor T1 and the second thin-film transistor T2 can each be either P-type or N-type. In the embodiments of this application, the first thin-film transistor T1 and the second thin-film transistor T2 are described as N-type.

[0049] Optionally, in some embodiments of this application, the carrier mobility of the semiconductor portion y1 is greater than that of the first channel 1b, such that the conductivity of the semiconductor portion y1 is greater than that of the first channel 1b.

[0050] It is important to understand that, according to the saturation current formula for thin-film transistors, as Vds gradually increases, the local electric field at the drain (output electrode) is pinched off due to the mutual cancellation of Vds and Vgs, resulting in the current no longer increasing with Vds and reaching a saturation state. By setting the first gate 101 close to the output electrode and at a certain potential, the local electric field in the output electrode region can be controlled, thereby increasing the saturation current. As part of the first gate 101, the semiconductor part y1 requires a certain conductivity to provide a potential, thereby forming an electric field to micro-control the saturation output characteristics of the thin-film transistor. Therefore, the conductivity of the semiconductor part y1 is set between that of the first channel 1b and the conductor part y2, so that the first gate 101 has a gradually changing potential to form a more suitable local electric field, thereby better controlling the saturation output characteristics of the first thin-film transistor T1.

[0051] Optionally, the material of the semiconductor part y1 can be an amorphous or polycrystalline high-mobility metal oxide material. The material of the conductor part y2 includes all the materials of the semiconductor part y1 plus conductive ions, which can be N-type or P-type ions.

[0052] Optionally, in some embodiments of this application, in the thickness direction of the display panel 100, the conductor portion y2 at least partially overlaps with the second contact portion 1c, and the conductor portion y2 partially overlaps with the second electrode 107.

[0053] It is understandable that by using conductor y2 to correspond to the second contact 1c, the second contact 1c is raised so that the second electrode 107 can be connected to the second contact 1c through a shallower through hole, which shortens the distance between the second electrode 107 and the second contact 1c and improves the signal transmission efficiency.

[0054] Optionally, in some embodiments of this application, a portion of the first insulating layer 102 covers the first gate 101 to form a structure with a height difference, and the first active layer 103 covers the first insulating layer 102 along the structure to form a first channel 1b with a height difference.

[0055] Understandably, the first gate 101 raises a portion of the first channel 1b, making the first channel 1b stepped, which increases the length of the first channel 1b, reduces the risk of leakage current, and thus improves the stability of the first thin-film transistor T1.

[0056] Optionally, in some embodiments of this application, the material of the first channel 1b is a metal oxide semiconductor, the material of the first insulating layer 102 is a first silicon oxide, the material of the second insulating layer 104 is a second silicon oxide, and the oxygen content of the second silicon oxide is greater than the oxygen content of the first silicon oxide.

[0057] It is understandable that the higher the oxygen content of the gate insulating layer, the lower the oxygen vacancy concentration. Oxygen vacancies are one of the main sources of charge carriers in oxide semiconductors. Reducing oxygen vacancies helps to reduce the concentration of charge carriers and thus reduce mobility.

[0058] In this embodiment of the application, the first insulating layer 102 and the second insulating layer 104 serve as gate insulating layers. The oxygen content of the first insulating layer 102 is less than that of the second insulating layer 104, which results in a larger carrier mobility in the second insulating layer 104 and a smaller carrier mobility in the first insulating layer 102. This allows for the regulation of carrier mobility and improvement of the stability of the first thin-film transistor T1.

[0059] Optionally, in some embodiments of this application, the thickness of the first insulating layer 102 is less than the thickness of the second insulating layer 104.

[0060] It is understandable that, under the same gate voltage and gate material, the smaller the thickness of the gate insulating layer, the larger the gate capacitance, and thus the lower the required threshold voltage. Therefore, given the relatively weak conductivity of the first gate 101, the electric field strength can be increased by reducing the thickness of the first insulating layer 102, thereby better controlling the output saturation characteristics of the first thin-film transistor T1.

[0061] Optional, please refer to Figure 2 In some embodiments of this application, the width L2 of the second insulating layer 104 is greater than the width L1 of the second gate 105.

[0062] Understandably, during the dry etching process of the second insulating layer 104, oxygen vacancies will diffuse towards the first channel 1b, causing the channel to shorten. Therefore, by setting the width of the second insulating layer 104 to be greater than the width of the second gate 105, oxygen vacancies are prevented from diffusing into the first channel 1b, allowing for precise control of the length of the first channel 1b and thus improving the stability of the first thin-film transistor T1.

[0063] Alternatively, the width L1 of the second gate 105 can be equal to the length of the first channel 1b.

[0064] Optionally, the edge of the second insulating layer 104 extends at least 0.5 micrometers beyond the edge of the second gate 105. This arrangement significantly reduces the risk of oxygen vacancies diffusing into the first channel 1b during the dry etching of the second insulating layer 104.

[0065] Optionally, the edge of the second insulating layer 104 may extend beyond the edge of the second gate 105 by 0.5 micrometers, 0.6 micrometers, 0.7 micrometers, 0.8 micrometers, 0.9 micrometers, or 1 micrometer.

[0066] Optionally, in some embodiments of this application, the display panel 100 further includes a second thin-film transistor T2 located in the gate driving circuit region DA. The second thin-film transistor T2 includes a second active layer 201, an etch stop layer 202, a third insulating layer 203, a third gate 204, a third electrode 205, and a fourth electrode 206. The second active layer 201 includes a third contact portion 2a, a second channel 2b, and a fourth contact portion 2c. The second active layer 201 is disposed on the substrate 11. The etch stop layer 202, the third insulating layer 203, and the third gate 204 are sequentially stacked on the second active layer 201. The third gate 204 overlaps with the second channel 2b. The third electrode 205 is connected to the third contact portion 2a, and the fourth electrode 206 is connected to the fourth contact portion 2c.

[0067] The carrier mobility of the second channel 2b is greater than that of the first channel 1b. The second active layer 201 and the first gate 101 are disposed on the same layer, and the material of the second channel 2b is the same as that of the semiconductor section y1.

[0068] It is understandable that the carrier mobility of the second channel 2b is greater than that of the first channel 1b, which makes the second thin-film transistor T2 located in the gate drive circuit region DA have a high mobility characteristic to meet the requirements of the gate drive circuit.

[0069] Secondly, in this embodiment, the second active layer 201 and the first gate 101 are formed using the same photomask process. On the one hand, this saves process steps and simplifies the structure of the display panel 100. On the other hand, using a high-mobility semiconductor material as the first gate 101 can optimize the local electric field formed by the first gate 101, so as to better control the output saturation characteristics of the first thin film transistor T1.

[0070] Optionally, the second active layer 201 is disposed on the side of the buffer layer 17 away from the substrate 11. The material of the second active layer 201 can be an amorphous or polycrystalline high-mobility metal oxide material.

[0071] Optionally, in some embodiments of this application, the conductivity of the third contact portion 2a and the fourth contact portion 2c is greater than the conductivity of the conductor portion y2.

[0072] The conductivity of the third contact portion 2a and the fourth contact portion 2c is greater than that of the first contact portion 1a and the second contact portion 1c.

[0073] It is understandable that the conductivity of the conductor portion y2 is between that of the second contact portion 1c and the semiconductor portion y1, so that the conductivity of the conductor portion y2 is not too large, and the amount of charge in the conductor portion y2 is not too large per unit time, so as to regulate the capacitance of the first gate 101 and thereby better adjust the output saturation characteristics of the first thin film transistor T1.

[0074] Secondly, the third contact portion 2a and the fourth contact portion 2c have higher conductivity, while the first contact portion 1a and the second contact portion 1c have lower conductivity, in order to further meet the requirements of the first thin film transistor T1 for high stability and the second thin film transistor T2 for high mobility.

[0075] Optionally, in some embodiments of this application, the width L3 of the etch stop layer 202 is greater than the width L4 of the third gate 204. The width L3 of the etch stop layer 202 is greater than the width of the third insulating layer 203.

[0076] Understandably, during the dry etching process, oxygen vacancies in the etch barrier layer 202 will diffuse towards the second channel 2b, causing the channel to shorten. Therefore, the width of the etch barrier layer 202 is set to be greater than the width of the third insulating layer 203 to prevent oxygen vacancies from diffusing into the second channel 2b, thus allowing precise control over the length of the second channel 2b.

[0077] Secondly, the thickness of the etching barrier layer 202 is less than the thickness of the third insulating layer 203. When the third insulating layer 203 is etched, the etching barrier layer 202 can block the etching gas from etching the second active layer 201. Subsequently, when the etching barrier layer 202 is dry etched, due to the smaller thickness of the etching barrier layer 202, its etching time is shorter, which can reduce the diffusion time of oxygen vacancies and thus more accurately control the length of the second channel 2b.

[0078] Optionally, in some embodiments, the edge of the etch barrier layer 202 extends at least 0.5 micrometers beyond the edge of the third gate 204. This arrangement significantly reduces the risk of oxygen vacancies diffusing into the second channel 2b during the etching of the etch barrier layer 202 in a dry etching process.

[0079] Optionally, the edge of the etch barrier layer 202 may extend beyond the edge of the third gate 204 by 0.5 micrometers, 0.6 micrometers, 0.7 micrometers, 0.8 micrometers, 0.9 micrometers, or 1 micrometer.

[0080] Optionally, in some embodiments of this application, the material of the second channel 2b is a metal oxide semiconductor, the material of the etching barrier layer 202 is the first silicon oxide, the material of the third insulating layer 203 is the second silicon oxide, and the oxygen content of the second silicon oxide is greater than the oxygen content of the first silicon oxide.

[0081] In this embodiment, the etch barrier layer 202 serves as the gate insulating layer that directly contacts the second channel 2b. The etch barrier layer 202 has a low oxygen content, which results in a higher mobility of the carrier channels in the etch barrier layer 202, thereby improving the mobility of the second thin-film transistor T2.

[0082] Optionally, in some embodiments, the etching barrier layer 202 and the first insulating layer 102 may each be a single film layer or may be formed by stacking at least two film layers.

[0083] Optionally, in some embodiments of this application, the etch barrier layer 202 and the first insulating layer 102 are made of the same material and are made using the same photomask; the third insulating layer 203 and the second insulating layer 104 are made of the same material and are made using the same photomask; the second active layer and the first gate 101 are made using the same photomask; and the second gate 105 and the third gate 204 are made of the same material and are made using a photomask.

[0084] It is understandable that forming a portion of the film layers of the first thin-film transistor T1 and the second thin-film transistor T2 using the same photomask process can save the number of photomasks and simplify the structure to the greatest extent.

[0085] Optionally, the method for manufacturing the display panel 100 in this embodiment includes the following steps:

[0086] like Figure 3 As shown, in step B01, a light-shielding layer 16, a buffer layer 17, a first semiconductor layer, and a first insulating material layer p1 are sequentially formed on the substrate 11.

[0087] Optionally, the material of the light-shielding layer 16 can be a laminated structure of molybdenum alloy and copper. The buffer layer 17 can be a single layer or a laminated structure, and the material of the buffer layer 17 is at least one of silicon oxynitride, silicon nitride, and silicon oxynitride.

[0088] The first semiconductor layer includes a first gate 101 located in the display area AA and a second active layer 201 located in the gate driving circuit area DA. The material of the first semiconductor layer may be an amorphous or polycrystalline high-mobility metal oxide material.

[0089] The first insulating material layer p1 may consist of a single film layer or a stack of at least two film layers. The material of the first insulating material layer p1 may be silicon oxide, which has a first oxygen content.

[0090] like Figure 4As shown, in step B02, a first active layer 103 and a second insulating material layer p2 are sequentially formed on the first insulating material layer p1, with a portion of the first active layer 103 covering the first gate 101. The second insulating material layer p2 covers both the first active layer 103 and the first insulating material layer p1.

[0091] Optionally, the first active layer 103 is an amorphous metal oxide material containing indium, gallium, and zinc. The second insulating material layer p2 can be made of silicon oxide, having a second oxygen content. The second oxygen content is greater than the first oxygen content.

[0092] like Figure 5 As shown, in step B03, a second gate 105 and a third gate 204 are formed on the second insulating material layer p2. The second gate 105 overlaps with the first channel 1b of the first active layer 103, and the third gate 204 overlaps with the second channel 2b of the second active layer 201.

[0093] Optionally, the materials for the second gate 105 and the third gate 204 can be formed using a metallic element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, neodymium, and cobalt, an alloy composed of any of the aforementioned metallic elements, or an alloy combining any of the aforementioned metallic elements. Furthermore, the second gate 105 and the third gate 204 can have a single-layer structure or a stacked structure of two or more layers.

[0094] like Figure 6 As shown, in step B04, the second insulating material layer and the first insulating material layer are sequentially patterned and etched to form the third insulating layer 203, the second insulating layer 104, the etch barrier layer 202, and the first insulating layer 102.

[0095] like Figure 7 As shown, in step B05, using the second gate 105 and the third gate 204 as masks, the first contact portion 1a and the second contact portion 1c of the first active layer 103, the third contact portion 2a and the fourth contact portion 2c of the second active layer 201, and the conductor portion y2 of the first gate 101 are simultaneously subjected to over-conducting treatment.

[0096] Optionally, conductor-enhancing processes can be performed using ion implantation. The implanted ions can be N-type or P-type, depending on the type of thin-film transistor.

[0097] like Figure 8 As shown, in step B06, an interlayer dielectric layer 13 and a source / drain metal layer are sequentially formed on the second gate 105 and the third gate 204. The source / drain metal layer includes a first electrode 106, a second electrode 107, a third electrode 205, and a fourth electrode 206.

[0098] The first electrode 106 and the second electrode 107 are each connected to the first active layer 103 through a via g1, and the third electrode 205 and the fourth electrode 206 are each connected to the second active layer 201 through a via g1.

[0099] Optionally, the via g1 can be formed using a dry etching method. It should be noted that the etching barrier layer 202 can also extend in the direction of the via g1 and partially overlap with the third electrode 205 and / or the fourth electrode 206.

[0100] Understandably, over-etching via g1 would increase its diameter, reducing the distance oxygen vacancies could diffuse towards the channel. Since the etch barrier layer 202 extends to the vicinity of via g1, if over-etching occurs and the diameter increases, the side of via g1 closest to the channel will be blocked by the etch barrier layer 202. This prevents the etching of the second active layer 201 covered by the etch barrier layer 202, reducing the risk of oxygen vacancies continuing to diffuse towards the channel and allowing for precise control of the length of the second channel 2b of the second active layer 201.

[0101] Optionally, the interlayer dielectric layer 13 can be a single layer or a stacked structure, and the material can be silicon oxide. The source / drain metal layer can be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, neodymium, and cobalt, an alloy with any of the above metal elements as its composition, or an alloy combining any of the above metal elements. Furthermore, the source / drain metal layer can have a single-layer structure or a stacked structure of two or more layers.

[0102] like Figure 9 As shown, in step B07, a passivation layer 14, a planarization layer 15, and an anode 12 are sequentially formed on the source / drain metal layer.

[0103] Please refer to Figure 10 Accordingly, this application also provides a display device 1000, including a display panel 100 as described in any of the above embodiments.

[0104] It should be noted that the structure of the display panel 100 of the display device 1000 in this application embodiment is similar to or the same as the structure of the display panel 100 of the above embodiments. For details, please refer to... Figures 1 to 9 Therefore, the relevant explanations will not be repeated here.

[0105] The display device 1000 of this application embodiment includes a first thin-film transistor T1 located in the display area AA. The first thin-film transistor T1 includes a first gate 101 and a second gate 105. The first gate 101 is located on the side of the second gate 105 away from the first electrode 106. The first gate 101 includes a connected semiconductor portion y1 and a conductor portion y2. The conductor portion y2 is located on the side of the semiconductor portion y1 closer to the second electrode 107. In the thickness direction of the display panel 100, the second gate 105 overlaps with the first channel 1b, and the semiconductor portion y1 partially overlaps with both the first channel 1b and the second gate 105.

[0106] It is understandable that the first gate 101 is positioned near the second electrode 107 to regulate the output saturation characteristics of the output region of the first thin-film transistor T1, thereby improving the output characteristics of the pixel driving transistor. By employing a semiconductor portion y1 overlapping with the first channel 1b and a conductor portion y2 positioned near the output of the first thin-film transistor T1, and considering that the impedance of the semiconductor portion y1 is higher than that of the conductor portion y2, the potential of the semiconductor portion y1 is relatively lower than that of the conductor portion y2. This reduces the influence of the electric field of the first gate 101 on the first channel 1b, improving the lifespan of the first thin-film transistor T1. Furthermore, since the first gate 101 can form two different potentials, the electric field distribution in the output region of the first thin-film transistor T1 can be synergistically regulated to control the output saturation characteristics of the first thin-film transistor T1 and improve its stability.

[0107] Optionally, the display device 1000 can be applied to and used in a variety of products, including, for example, televisions, laptop computers, monitors, billboards, Internet of Things (IoT) devices, and portable electronic devices including mobile phones, smartphones, tablet computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs).

[0108] Furthermore, the display device 1000 according to some embodiments can be applied to wearable devices and can be used within wearable devices, including smartwatches, watch phones, glasses-type displays, and head-mounted displays. Additionally, according to some embodiments, the display device 1000 can be applied to instrument panels for automobiles, displays in central dashboards or central information displays arranged on instrument panels, interior mirror displays replacing side mirrors in automobiles, and displays for entertainment systems arranged on the back of the front seats for rear-seat passengers in automobiles.

[0109] The above provides a detailed description of a display panel and display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, comprising a display area and a gate driving circuit area located on at least one side of the display area, characterized in that, The display panel includes: substrate; A first thin-film transistor is disposed within the display area. The first thin-film transistor includes a first gate, a first insulating layer, a first active layer, a second insulating layer, a second gate, a first electrode, and a second electrode. The second electrode is an output electrode. The first active layer includes a first contact portion, a first channel, and a second contact portion. The first gate is disposed on the substrate. The first insulating layer covers the first gate. The first active layer is disposed on the side of the first insulating layer away from the substrate. The second insulating layer is disposed on the side of the first active layer away from the substrate. The second gate is disposed on the side of the second insulating layer away from the substrate. The first electrode is connected to the first contact portion, and the second electrode is connected to the second contact portion. Wherein, the first gate is located on the side of the second gate away from the first electrode, the first gate includes a connected semiconductor portion and a conductor portion, the conductor portion is located on the side of the semiconductor portion closer to the second electrode, in the thickness direction of the display panel, the second gate overlaps with the first channel, the semiconductor portion partially overlaps with both the first channel and the second gate; in the thickness direction of the display panel, the conductor portion at least partially overlaps with the second contact portion, and the conductor portion partially overlaps with the second electrode.

2. The display panel according to claim 1, characterized in that, The carrier mobility of the semiconductor section is greater than that of the first channel.

3. The display panel according to claim 2, characterized in that, The first insulating layer partially covers the first gate to form a structure with a height difference, and the first active layer covers the first insulating layer to form the first channel with a height difference.

4. The display panel according to any one of claims 1-3, characterized in that, The material of the first channel is a metal oxide semiconductor, the material of the first insulating layer is a first silicon oxide, the material of the second insulating layer is a second silicon oxide, and the oxygen content of the second silicon oxide is greater than the oxygen content of the first silicon oxide.

5. The display panel according to any one of claims 1-3, characterized in that, The width of the second insulating layer is greater than the width of the second gate.

6. The display panel according to claim 3, characterized in that, The display panel further includes a second thin-film transistor located in the gate driving circuit region. The second thin-film transistor includes a second active layer, an etch stop layer, a third insulating layer, a third gate, a third electrode, and a fourth electrode. The second active layer includes a third contact portion, a second channel, and a fourth contact portion. The second active layer is disposed on the substrate. The etch stop layer, the third insulating layer, and the third gate are stacked sequentially on the second active layer. The third gate overlaps with the second channel. The third electrode is connected to the third contact portion, and the fourth electrode is connected to the fourth contact portion. The carrier mobility of the second channel is greater than that of the first channel. The second active layer and the first gate are disposed on the same layer. The material of the second channel is the same as that of the semiconductor portion.

7. The display panel according to claim 6, characterized in that, The conductivity of both the third contact portion and the fourth contact portion is greater than the conductivity of the conductor portion.

8. The display panel according to claim 6, characterized in that, The width of the etch barrier layer is greater than the width of the third gate.

9. The display panel according to any one of claims 6-8, characterized in that, The etching barrier layer and the first insulating layer are made of the same material and are made using the same photomask. The third insulating layer and the second insulating layer are made of the same material and are made using the same photomask. The second active layer and the first gate are made using the same photomask. The second gate and the third gate are made of the same material and are made using a single photomask.

10. The display panel according to any one of claims 1-3, characterized in that, The display panel is an electroluminescent panel, and the second electrode is connected to the anode.

11. A display device, characterized in that, Includes the display panel as described in any one of claims 1-10.

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