Display panel and display equipment

Abstract

The embodiment of the invention discloses a display panel and a display device, the thickness of a first insulating layer located at a first pole plate is smaller than the thickness of the first insulating layer located at a thin film transistor, the thin film transistor is covered based on the first insulating layer, and the first insulating layer is arranged between the first pole plate and a second pole plate of a capacitor structure. Therefore, the distance between the first polar plate and the second polar plate is shortened while the terrain of the capacitor structure area is reduced by reducing the thickness of the first insulating layer at the capacitor structure, so that the capacitance value of the capacitor structure is improved; in order to locally thin the first insulating layer, the capacitor structure corresponding to the first flat layer is provided with the first opening, and the thickness of the first flat layer is relatively large, so that the terrain of the capacitor structure area is greatly reduced, and the terrain of the capacitor structure area and the terrain of the non-device area are better balanced by filling the first opening with the second polar plate; and the capacitance value of the capacitor structure is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Inkjet printing OLED technology has extremely high requirements for the flatness of the terrain within the pixel. If the terrain difference within the pixel is large, the thickness uniformity of the dry film formed by the luminescent material ink after drying will be poor, which will lead to problems such as uneven brightness within the pixel and poor luminous efficiency of the device.

[0003] During the research and practice of the prior art, the inventors of the present application discovered that the pixel area of ​​the existing inkjet-printed OLED is covered with a capacitor area with a large plate area. Due to the requirements of high refresh rate and high resolution, the capacitor structure usually utilizes multiple layers of conductive film to increase the capacitance value. This results in the film layer of the capacitor area below the pixel area being higher, which easily causes a larger terrain step difference with other areas within the pixel, thereby affecting the flatness within the pixel. Summary of the invention

[0004] Embodiments of the present application provide a display panel and a display device, which can improve the flatness within a pixel and the capacitance value of a capacitor structure.

[0005] An embodiment of the present application provides a display panel, including a pixel area configured to emit light, the display panel including:

[0006] substrate;

[0007] A thin film transistor is disposed on the substrate;

[0008] a capacitor structure, disposed on the substrate and at least part of which is located in the pixel region, the capacitor structure comprising a first electrode plate and a second electrode plate disposed in different layers, the second electrode plate being located on a side of the first electrode plate away from the substrate;

[0009] a first insulating layer, covering the thin film transistor and located between the first electrode plate and the second electrode plate, wherein a thickness of the first insulating layer at the first electrode plate is less than a thickness of the first insulating layer at the thin film transistor;

[0010] a first flat layer covering the first insulating layer, wherein the first flat layer is provided with a first opening corresponding to the first electrode plate, the second electrode plate is filled in the first opening, and the thickness of the second electrode plate is less than or equal to the depth of the first opening;

[0011] a second planar layer, covering the first planar layer and the second electrode plate and filling the first opening; and

[0012] An anode is arranged on a side of the second planar layer away from the substrate and is electrically connected to the thin film transistor. In the thickness direction of the display panel, the anode is partially overlapped with the capacitor structure.

[0013] Optionally, in some embodiments of the present application, a first groove connected to the first opening is formed on the first insulating layer, and the first groove is located at least on one side of the first electrode plate;

[0014] A portion of the second electrode plate extends to fill the first groove and is disposed opposite to a side surface of the first electrode plate.

[0015] Optionally, in some embodiments of the present application, the display panel further includes an interlayer dielectric layer, and the interlayer dielectric layer is arranged on a side of the first electrode plate close to the substrate;

[0016] A second groove is formed on the interlayer dielectric layer. The first groove is a through groove penetrating the first insulating layer. The second groove is connected to the first groove. A portion of the second electrode plate extends to fill up the second groove.

[0017] Optionally, in some embodiments of the present application, the depth of the second groove is less than 1 / 3 of the thickness of the interlayer dielectric layer.

[0018] Optionally, in some embodiments of the present application, the second electrode plate includes a first transparent conductive portion and a metal reflective layer arranged on a side of the first transparent conductive portion away from the substrate, the first transparent conductive portion is arranged in the first groove and the second groove, and the metal reflective layer is arranged in the first opening.

[0019] Optionally, in some embodiments of the present application, the second electrode plate further includes a second transparent conductive portion, and the second transparent conductive portion is disposed on a side of the metal reflective layer away from the substrate.

[0020] Optionally, in some embodiments of the present application, the capacitor structure further includes a third electrode plate, the third electrode plate is arranged on a side of the interlayer dielectric layer close to the substrate, a first contact hole exposing the third electrode plate is opened on the interlayer dielectric layer, the first contact hole is covered with a metal part connected to the third electrode plate, the metal part is extended along the hole wall of the first contact hole, and a concave groove is formed on a side of the metal part away from the substrate;

[0021] The first insulating layer is provided with a second contact hole communicating with the recessed groove, and a portion of the second electrode plate fills the second contact hole and the recessed groove and is connected to the metal portion.

[0022] Optionally, in some embodiments of the present application, another first transparent conductive portion is disposed in the second contact hole and the recessed groove, and a material of the first transparent conductive portion includes metal oxide.

[0023] Optionally, in some embodiments of the present application, the surface roughness of the second electrode plate on a side close to the anode is greater than the surface roughness of the anode.

[0024] Optionally, in some embodiments of the present application, the capacitor structure further includes a third electrode plate and a fourth electrode plate, and the display panel further includes a buffer layer, a light shielding portion, and a second insulating layer;

[0025] The fourth electrode plate and the light-shielding portion are arranged in the same layer on the substrate, the buffer layer covers the fourth electrode plate and the light-shielding portion, the third electrode plate and the active layer of the thin film transistor are arranged in the same layer on a side of the buffer layer away from the substrate, the second insulating layer is arranged between the active layer of the thin film transistor and the gate of the thin film transistor, the interlayer dielectric layer covers the gate of the thin film transistor, the buffer layer and the third electrode plate, the source and drain of the thin film transistor and the first electrode plate are arranged in the same layer on a side of the interlayer dielectric layer away from the substrate, and the first insulating layer covers the interlayer dielectric layer, the source and drain of the thin film transistor and the first electrode plate.

[0026] Correspondingly, an embodiment of the present application further provides a display device, comprising a display panel as described in any one of the above embodiments.

[0027] The display panel and display device of the embodiments of the present application are based on the first insulating layer covering the thin film transistor and being arranged between the first electrode plate and the second electrode plate of the capacitor structure. Therefore, the thickness of the first insulating layer located at the capacitor structure is thinned to reduce the terrain of the capacitor structure area and shorten the distance between the first electrode plate and the second electrode plate, thereby increasing the capacitance value of the capacitor structure. In order to locally thin the first insulating layer, a first opening is provided at the capacitor structure corresponding to the first flat layer, and the thickness of the first flat layer is relatively large, so that the terrain of the capacitor structure area drops more. Therefore, the second electrode is filled in the first opening to better balance the terrain of the capacitor structure area and the non-device area, thereby increasing the capacitance value of the capacitor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0029] Figure 2 yes Figure 1 A magnified view of part A;

[0030] Figure 3is a schematic diagram of the connection between the second electrode plate and the third electrode plate in the display panel provided in an embodiment of the present application;

[0031] Figure 4 is a schematic diagram of step B105 of the method for preparing a display panel provided in an embodiment of the present application;

[0032] Figure 5 is a schematic diagram of step B106 of the method for preparing a display panel provided in an embodiment of the present application;

[0033] Figure 6 is a schematic diagram of step B107 of the method for preparing a display panel provided in an embodiment of the present application;

[0034] Figure 7 is a schematic diagram of step B108 of the method for preparing a display panel provided in an embodiment of the present application;

[0035] Figure 8 is a schematic diagram of step B109 of the method for preparing a display panel provided in an embodiment of the present application;

[0036] Fig. 9 It is a schematic diagram of the structure of the display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the various embodiments can be combined with each other but will not be repeated one by one, and in the absence of contrary instructions, the directional words used, such as "upper" and "lower", usually refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inside" and "outside" refer to the outline of the device; the terms "first", "second", "third", etc. are used only as markings, and no numerical requirements are imposed or order is established.

[0038] The embodiments of the present application provide a display panel and a display device, which are described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0039] Please refer to Figure 1 and Figure 2The embodiment of the present application provides a display panel 100, including a pixel area sx configured to emit light. The display panel 100 includes a substrate 101, a thin film transistor 11, a capacitor structure 12, a first insulating layer 102, a first planar layer 103, a second planar layer 104 and an anode 105.

[0040] The thin film transistor 11 is disposed on the substrate 101. The capacitor structure 12 is disposed on the substrate 101 and at least part of the capacitor structure 12 is located in the pixel region sx. The capacitor structure 12 includes a first electrode plate 121 and a second electrode plate 122 disposed in different layers, and the second electrode plate 122 is located on a side of the first electrode plate 121 away from the substrate 101.

[0041] The first insulating layer 102 covers the thin film transistor 11 and is located between the first electrode 121 and the second electrode 122. The thickness h1 of the first insulating layer 102 at the first electrode 121 is smaller than the thickness h2 of the first insulating layer 102 at the thin film transistor 11.

[0042] The first flat layer 103 covers the first insulating layer 102. The first flat layer 103 is provided with a first opening 10a corresponding to the first electrode 121, and the second electrode 122 is filled in the first opening 10a. The thickness of the second electrode 122 is less than or equal to the depth h3 of the first opening 10a. The second flat layer 104 covers the first flat layer 103 and the second electrode 122 and fills the first opening 10a.

[0043] The anode 105 is disposed on a side of the second planar layer 104 away from the substrate 101 and is electrically connected to the thin film transistor 11. In the thickness direction of the display panel 100, the anode 105 and the capacitor structure 12 are partially overlapped.

[0044] The display panel 100 of the embodiment of the present application is based on the first insulating layer 102 covering the thin film transistor 11 and being arranged between the first electrode 121 and the second electrode 122 of the capacitor structure 12. Therefore, the thickness of the first insulating layer 102 located at the capacitor structure 12 is thinned to reduce the terrain of the capacitor structure area c1 and shorten the distance between the first electrode 121 and the second electrode 122, thereby increasing the capacitance value of the capacitor structure 12. In order to partially thin the first insulating layer 102, a first opening 10a is provided at the capacitor structure 12 corresponding to the first flat layer 103, and the thickness of the first flat layer 103 is relatively large, so that the terrain of the capacitor structure area c1 is greatly reduced. Therefore, the second electrode 122 is filled in the first opening 10a to better balance the terrain of the capacitor structure area c1 and the non-device area c2, thereby increasing the capacitance value of the capacitor structure 12.

[0045] It should be understood that the capacitor structure 12 includes at least three layers of electrode plates, wherein the third electrode plate 123 is arranged on the side of the first electrode plate 121 close to the substrate 101. Therefore, by adding the second electrode plate 122, not only the capacitance value of the capacitor structure 12 can be increased, but also the potential difference between the capacitor structure area c1 and the non-device area c2 can be leveled.

[0046] It should be explained that the non-device region c2 refers to a region where no devices or wiring are provided, that is, a region including only the substrate and the insulating layer in the thickness direction of the display panel 100. In addition, the pixel region sx refers to a region formed by the boundary of the opening formed in the pixel definition layer to expose the anode 105, wherein the light-emitting material is provided in the opening.

[0047] In addition, it should be noted that, since the second electrode plate 122 is formed by inkjet printing, the interior of the second electrode plate 122 has a certain porosity, and the porosity of the second electrode plate 122 is greater than the porosity of the first electrode plate 121 and the porosity of the anode 105, combined with the first opening 10a; when the display panel 100 is applied to a curved display panel, the first opening 10a and the second electrode plate 122 with a larger porosity have better stress release performance, thereby improving the reliability of the curved display panel.

[0048] Optionally, the second electrode plate 122 includes a plurality of conductive particles, and the plurality of conductive particles are interconnected to form the second electrode plate 122 .

[0049] Optionally, the material of the light-emitting layer may be an organic material, such as Alq3, bis(2-methyl-8-hydroxyquinoline-N1,O8)-(1,1'-biphenyl-4-hydroxy)aluminum (BAlq), DPVBi, Almq3, 3-tert-butyl-9,10-di(2-naphthalene)anthracene (TBADN).

[0050] The material of the light-emitting layer may also be an inorganic material, for example, it may be one or more selected from group IV semiconductor nanocrystals, group II-V semiconductor nanocrystals, group II-VI semiconductor nanocrystals, group IV-VI semiconductor nanocrystals, group III-V semiconductor nanocrystals and group III-VI semiconductor nanocrystals, etc. As an example, it may be one or more selected from silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, indium arsenide quantum dots and gallium nitride quantum dots, etc.

[0051] That is, the display panel 100 of the embodiment of the present application may be an electroluminescent panel such as an organic light-emitting display panel, a quantum dot light-emitting display panel or a micro LED display panel.

[0052] Optionally, in some embodiments of the present application, a first groove 10 b connected to the first opening 10 a is formed on the first insulating layer 102 , and the first groove 10 b is located at least on one side of the first electrode plate 121 .

[0053] A portion of the second electrode plate 122 extends to fill the first groove 10 b and is disposed opposite to a side surface of the first electrode plate 121 .

[0054] It can be understood that in the thickness direction of the display panel 100, the first groove 10b and the first opening 10a are connected, so that the material of the second electrode 122 can fill the first groove 10b and the first opening 10a, while compensating for the step difference, increasing the overlapping area between the second electrode 122 and the first electrode 121, thereby increasing the capacitance value of the capacitor structure 12.

[0055] It should be understood that, compared with the method of forming the second electrode plate by vapor deposition, the second electrode plate at this time is attached to the sidewalls and bottom walls of the first groove 10b and the first opening 10a to form a concave-convex structure. In the embodiment of the present application, the second electrode plate 122 is formed by inkjet printing. Based on the formation method of inkjet printing, the second electrode plate 122 has better leveling properties, can fill the first groove 10b and the first opening 10a, while maintaining better flatness, thereby improving the flatness of the capacitor structure area c1.

[0056] Secondly, the second electrode plate 122 is formed by inkjet printing, and the thickness of the second electrode plate 122 can be flexibly adjusted by setting the size of the ink droplets and the number of printing times to better balance the terrain difference with the non-device area c2. In addition, the electrical properties of the capacitor structure 12 can also be adjusted by adjusting the conductive material of the ink droplets, thereby improving the heat dissipation, load and conductivity of the capacitor structure 12.

[0057] Optionally, in some embodiments of the present application, the display panel 100 further includes an interlayer dielectric layer 106 , and the interlayer dielectric layer 106 is disposed on a side of the first electrode plate 121 close to the substrate 101 .

[0058] A second groove 10c is formed on the interlayer dielectric layer 106. The first groove 10b is a through groove penetrating the first insulating layer 102. The second groove 10c is connected to the first groove 10b. A portion of the second electrode plate 122 extends to fill the second groove 10c.

[0059] It is understandable that the second groove 10 c is arranged so that part of the second electrode plate 122 extends into the interlayer dielectric layer 106 to keep the second electrode plate 122 and the side of the first electrode plate 121 overlapped to the maximum extent, thereby improving the capacitance value of the capacitor structure 12 .

[0060] Secondly, the provision of the first groove 10 b and the second groove 10 c allows a portion of the second electrode plate 122 to extend toward the substrate 101 , which partially increases the thickness of the second electrode plate 122 , thereby reducing the impedance of the second electrode plate 122 .

[0061] Optionally, in some embodiments of the present application, the depth h4 of the second groove 10 c is less than 1 / 3 of the thickness of the interlayer dielectric layer 106 .

[0062] It can be understood that, based on the fact that the second groove 10c and the locally thinned first insulating layer 102 are formed by the same mask, in order to avoid excessive thinning of the first insulating layer 102 resulting in a short circuit between the first electrode 121 and the second electrode 122, the depth of the second groove 10c should not be too deep. For example, the depth h4 of the second groove 10c is 1 / 3, 1 / 4, 1 / 5, 1 / 6, 1 / 7, 1 / 8, 1 / 9 or 1 / 10 of the thickness of the interlayer dielectric layer 106.

[0063] Optionally, in some embodiments of the present application, the second electrode plate 122 is a single-film structure.

[0064] Optionally, in some embodiments of the present application, the second electrode 122 includes a first transparent conductive portion 12a and a metal reflective layer 12b disposed on a side of the first transparent conductive portion 12a away from the substrate 101. The first transparent conductive portion 12a is disposed in the first groove 10b and the second groove 10c, and the metal reflective layer 12b is disposed in the first opening 10a.

[0065] It is understandable that, since the second electrode plate 122 is formed by inkjet printing, the multi-layer stacking structure of the second electrode plate 122 is formed by multiple printings, and the multiple printings can make up for the terrain defects of the previous printing by the next printing, thereby improving the flatness of the second electrode plate 122. Secondly, the metal reflective layer 12b is located on the side of the first transparent conductive portion 12a close to the anode 105, so that the metal reflective layer 12b is closer to the anode 105, so as to reflect the light passing through the anode 105 faster, thereby improving the light output efficiency of the pixel. On the other hand, the first transparent conductive portion 12a is located on the side of the metal reflective layer 12b close to the substrate 101, which can reduce the risk of corrosion of the metal reflective layer 12b.

[0066] Optionally, the conductivity of the metal reflective layer 12 b is stronger than the conductivity of the first transparent conductive portion 12 a.

[0067] Optionally, in some embodiments of the present application, the second electrode plate 122 further includes a second transparent conductive portion 12c, and the second transparent conductive portion 12c is disposed on a side of the metal reflective layer 12b away from the substrate 101.

[0068] It can be understood that the second transparent conductive portion 12c is provided to cover the metal reflective layer 12b so as to reduce the risk of corrosion of the metal reflective layer 12b.

[0069] Optionally, the first transparent conductive portion 12a and the second transparent conductive portion 12c are made of the same material, both of which are metal oxides. The material of the metal reflective layer 12b can be silver, aluminum or magnesium.

[0070] Optionally, in some embodiments of the present application, the surface roughness of the second electrode plate 122 on a side close to the anode 105 is greater than the surface roughness of the anode 105 .

[0071] It can be understood that, since the second electrode plate 122 includes the metal reflective layer 12b and the surface roughness of the second electrode plate 122 is relatively large, the light reflected by the metal reflective layer 12b can be diffusely reflected, thereby improving the light uniformity of the pixel area sx. Among them, since the second electrode plate 122 is printed by inkjet printing, when the solvent evaporates, the surface of the second electrode plate 122 will naturally form a concave-convex microstructure, thereby forming a rough surface of the second electrode plate 122 without the need for additional surface treatment processes.

[0072] Optionally, in some embodiments, the second transparent conductive portion 12 c may also be formed by directly oxidizing the side of the metal reflective layer 12 b away from the substrate 101 , so as to reduce the thickness of the second electrode plate 122 .

[0073] Optional, see Figure 3 In some embodiments of the present application, the capacitor structure 12 further includes a third electrode plate 123, which is disposed on a side of the interlayer dielectric layer 106 close to the substrate 101. A first contact hole j1 exposing the third electrode plate 123 is provided on the interlayer dielectric layer 106, and the first contact hole j1 is covered with a metal portion 125 connected to the third electrode plate 123. The metal portion 125 extends along the hole wall of the first contact hole j1, and a concave groove j3 is formed on a side of the metal portion 125 away from the substrate 101.

[0074] The first insulating layer 102 defines a second contact hole j2 communicating with the recessed groove j3 . A portion of the second electrode plate 122 fills up the second contact hole j2 and the recessed groove j3 and is connected to the metal portion 125 .

[0075] It is understandable that the metal part 125 is used to cover the first contact hole j1 to reduce the contact impedance and connection conductivity of the second electrode plate 122 and the third electrode plate 123. Secondly, the metal part 125 covering the first contact hole j1 can avoid over-engraving the third electrode plate 123 when forming the second contact hole j2 and avoid the second contact hole j2 being too deep, thereby improving the performance of the capacitor structure 12.

[0076] Optionally, in some embodiments of the present application, another first transparent conductive portion 12 a is disposed in the second contact hole j2 and the recessed groove j3 , and the material of the first transparent conductive portion 12 a includes metal oxide.

[0077] It can be understood that, based on the strong corrosion resistance of metal oxides, the first transparent conductive portion 12a made of metal oxide is used to connect the metal portion 125, which can improve the stability of the connection between the second electrode plate 122 and the first electrode plate 121.

[0078] Optionally, in some embodiments of the present application, the capacitor structure 12 further includes a third electrode plate 123 and a fourth electrode plate 124. The display panel 100 further includes a buffer layer 107, a light shielding portion 108 and a second insulating layer 109.

[0079] The fourth electrode plate 124 and the light shielding portion 108 are arranged on the substrate 101 in the same layer. The buffer layer 107 covers the fourth electrode plate 124 and the light shielding portion 108. The third electrode plate 123 and the active layer 111 of the thin film transistor 11 are arranged on the side of the buffer layer 107 away from the substrate 101. The second insulating layer 109 is arranged between the active layer 111 of the thin film transistor 11 and the gate 112 of the thin film transistor 11. The interlayer dielectric layer 106 covers the gate 112 of the thin film transistor 11, the buffer layer 107 and the third electrode plate 123. The source 113, the drain 114 and the first electrode plate 121 of the thin film transistor 11 are arranged on the side of the interlayer dielectric layer 106 away from the substrate 101. The first insulating layer 102 covers the interlayer dielectric layer 106, the source 113, the drain 114 and the first electrode plate 121 of the thin film transistor 11.

[0080] It is understandable that the addition of the fourth electrode plate 124 can increase the capacitance value of the capacitor structure 12. Secondly, the fourth electrode plate 124 and the light shielding portion 108 are arranged in the same layer, the third electrode plate 123 and the active layer 111 are arranged in the same layer, and the first electrode plate 121 and the source 113 and the drain 114 are arranged in the same layer, which can reduce the thickness of the display panel 100 and save the mask process.

[0081] Secondly, the distance between the first electrode 121 and the third electrode 123 is equal to the thickness of the interlayer dielectric layer 106, that is, the first electrode 121 and the third electrode 123 are only separated by the interlayer dielectric layer 106, which further reduces the height of the capacitor structure 12, thereby balancing the potential difference with the non-device area c2.

[0082] Optionally, in some embodiments, the display panel 100 further includes a first wiring 131 disposed in the same layer as the first electrode plate 121, and a second wiring 132 disposed in the same layer as the fourth electrode plate 124. The first wiring 131 and the second wiring 132 are both disposed in the package clearance area. It should be understood that the package clearance area refers to the area covered by the package layer. Among them, the first insulating layer 102 covers the first wiring 131, and the second flat layer 104 is provided with a second opening 10f, and the second opening 10f passes through the first flat layer 103 and corresponds to the package clearance area.

[0083] Optionally, in some embodiments, the display panel 100 further includes a patch cord 133 disposed between the first planar layer 103 and the second planar layer 104. One end of the patch cord 133 is connected to the anode 105, and the other end of the patch cord 133 is connected to the drain 114 of the thin film transistor 11.

[0084] The following will describe a method for preparing the display panel 100 according to an embodiment of the present application, which is as follows:

[0085] In step B101 , a light shielding layer and a buffer layer 107 are sequentially formed on the substrate 101 , wherein the light shielding layer includes a light shielding portion 108 , a fourth electrode plate 124 and a second wiring 132 .

[0086] Optionally, the substrate 101 may be a rigid substrate or a flexible substrate. The material of the substrate 101 includes one of glass, sapphire, silicon, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene diphthalate, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyether sulfone, aromatic fluorotoluene containing polyarylate, polycyclic olefin, polyimide or polyurethane.

[0087] Optionally, the shading layer can be a single-layer structure of an inorganic metal material, such as Cr (chromium), Mo (molybdenum), Mn (manganese), etc., or it can be a multi-layer structure, including a molybdenum-aluminum-molybdenum (Mo / Al / Mo) metal layer structure, an aluminum-molybdenum (Al / Mo) metal layer structure, a molybdenum-copper (Mo / Cu) metal layer structure, or a molybdenum-titanium-copper (Mo / Ti / Cu) metal layer structure, including but not limited to the above materials.

[0088] Then go to step B102.

[0089] In step B102 , a semiconductor layer, a second insulating layer 109 and a gate 112 are sequentially formed on the buffer layer 107 .

[0090] The semiconductor layer includes an active layer 111 and a third electrode 123. Optionally, the material of the semiconductor layer is a metal oxide, and the material may be, for example, an amorphous metal oxide material containing indium, gallium, or zinc.

[0091] It should be noted that the third electrode plate 123 and the source and drain portions of the active layer 111 are all conductive structures.

[0092] Then go to step B103.

[0093] In step B103 , an interlayer dielectric layer 106 , a first metal layer and a first contact hole j1 are sequentially formed on the gate 112 .

[0094] Optionally, the first metal layer includes a source electrode 113, a drain electrode 114, a first electrode plate 121, a metal portion 125 and a first wiring 131. The metal portion 125 covers the first contact hole j1.

[0095] Then go to step B104.

[0096] In step B104, a first insulating layer 102 and a first planarizing layer 103 are formed on the first metal layer.

[0097] Optionally, the interlayer dielectric layer 106, the buffer layer 107, the first insulating layer 102, and the second insulating layer 109 may be formed of a plurality of inorganic layers stacked in an alternating manner. For example, the interlayer dielectric layer 106, the buffer layer 107, the first insulating layer 102, and the second insulating layer 109 may be formed as a double layer formed by stacking inorganic layers including at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide, or a multilayer formed by alternately stacking inorganic layers including at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide. However, the present disclosure is not limited thereto, and the interlayer dielectric layer 106, the buffer layer 107, the first insulating layer 102, and the second insulating layer 109 may be formed as a single inorganic layer including the above insulating materials.

[0098] Furthermore, in one or more embodiments, the interlayer dielectric layer 106 may be made of an organic insulating material such as polyimide.

[0099] Optionally, the thickness of the first insulating layer 102 is between 3000 angstroms and 4000 angstroms, for example, 3000 angstroms, 3500 angstroms or 4000 angstroms.

[0100] The material of the first planar layer 103 may be an organic transparent film layer, such as transparent photoresist, acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0101] Optionally, the thickness of the first planar layer 103 is between 2 micrometers and 2.5 micrometers, for example, 2 micrometers, 2.1 micrometers, 2.2 micrometers, 2.3 micrometers, 2.4 micrometers or 2.5 micrometers.

[0102] In this embodiment, the first planar layer 103 is transparent photoresist as an example for description below, but the invention is not limited thereto.

[0103] Then go to step B105.

[0104] Please refer to Figure 4 In step B105, a multi-tone or grayscale mask template mk is used to expose the first flat layer 103. The fully transparent opening FT is used to expose the area where the via hole connecting the first metal layer and the first groove 10b are formed, the first transparent part 3T is used to expose the area where the first opening 10a is formed, and the second transparent part HT is used to expose the area where the second opening 10f is formed. The transmittance of the fully transparent opening FT, the second transparent part HT and the first transparent part 3T decreases in sequence. It should be explained that the transmittance of the fully transparent opening FT is 100%.

[0105] Then proceed to step B106.

[0106] Please refer to Figure 5 In step B106, a through hole 14a exposing the drain electrode 114 and a second contact hole j2 exposing the metal portion 125 are formed on the first planar layer 103, a first trench w1 is formed in the region of the first electrode plate 121, a through groove 14b is formed on the periphery of the first electrode plate 121, and a second trench w2 is formed in the region of the first wiring 131. Both the through hole 14a and the through groove 14b penetrate the first planar layer 103 and the first insulating layer 102.

[0107] The depth of the first groove w1 is greater than the depth of the second groove w2.

[0108] Then proceed to step B107.

[0109] Please refer to Figure 6 In step B107 , the first planar layer 103 is ashed, and the first planar layer 103 is thinned to completely remove the first planar layer 103 directly above the first electrode plate 121 , and the first planar layer 103 with a relatively thin thickness is retained directly above the first trace 131 .

[0110] Then proceed to step B108.

[0111] Please refer to Figure 7 In step B108 , the exposed first insulating layer 102 is etched to thin the portion of the first insulating layer 102 corresponding to the first electrode plate 121 .

[0112] Optionally, the thickness of the portion of the first insulating layer 102 corresponding to the first electrode plate 121 is between 1000 angstroms and 2000 angstroms, for example, 1000 angstroms, 1500 angstroms or 2000 angstroms.

[0113] Optionally, the first planar layer 103 and the first insulating layer 102 may be etched together by gas dry etching, so as to form the first opening 10a, the second opening 10f, the first groove 10b and the second groove 10c.

[0114] Optionally, the depth h4 of the second groove 10c is between 800 angstroms and 1200 angstroms, for example, 800 angstroms, 900 angstroms, 1000 angstroms, 1100 angstroms or 1200 angstroms.

[0115] Then proceed to step B109.

[0116] Please refer to Figure 8 In step B109 , a single-layer or multi-layer conductive filling layer is formed in the first opening 10 a , the first groove 10 b and the second groove 10 c by inkjet printing and vacuum drying process to form the second electrode 122 .

[0117] Optionally, the conductive filling layer of the first groove 10b and the second groove 10c may be a metal oxide, such as indium tin oxide, indium zinc oxide, etc. That is, the first transparent conductive portion 12a fills the first groove 10b, the second groove 10c and covers the bottom surface of the first opening 10a.

[0118] The material of the metal reflective layer 12b can be a single metal such as magnesium or silver, or an alloy-based high-reflective material.

[0119] Then proceed to step B110.

[0120] In step B110 , the connecting line 133 , the second planar layer 104 , and the anode 105 are sequentially formed on the first planar layer 103 .

[0121] Optionally, the gate 112, the first metal layer and the switching line 133 can each be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, neodymium, cobalt, an alloy containing any of the above metal elements as a component, or an alloy combining any of the above metal elements. In addition, the gate 112, the first metal layer and the switching line 133 can have a single-layer structure or a stacked structure of two or more layers.

[0122] The material of the second planar layer 104 may be an organic transparent film layer, such as transparent photoresist, acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0123] The second planarization layer 104 covers the first planarization layer 103 and the first opening 10a to planarize the entire display area and improve the planarity of the capacitor structure area c1 and the non-device area c2.

[0124] It should be understood that the display panel 100 of the present embodiment also forms a pixel definition layer, a light-emitting functional layer, a cathode and an encapsulation layer in sequence on the second flat layer 104. An opening including an anode 105 is formed on the pixel definition layer, and the light-emitting functional layer is arranged in the opening.

[0125] Please refer to Fig. 9 Accordingly, an embodiment of the present application further provides a display device 1000, comprising a display panel 100 as described in any one of the above embodiments.

[0126] It should be noted that the display panel 100 of the display device 1000 of the embodiment of the present application has a structure similar to or the same as that of the display panel 100 of any of the above embodiments, so it will not be described in detail here. Figures 1 to 8 Related explanation of .

[0127] The display device 1000 of the embodiment of the present application is based on the first insulating layer 102 covering the thin film transistor 11 and being arranged between the first electrode 121 and the second electrode 122 of the capacitor structure 12. Therefore, the thickness of the first insulating layer 102 located at the capacitor structure 12 is thinned to reduce the terrain of the capacitor structure area c1 and shorten the distance between the first electrode 121 and the second electrode 122, thereby increasing the capacitance value of the capacitor structure 12. In order to partially thin the first insulating layer 102, a first opening 10a is provided at the capacitor structure 12 corresponding to the first flat layer 103, and the thickness of the first flat layer 103 is relatively large, so that the terrain of the capacitor structure area c1 is greatly reduced. Therefore, the second electrode 122 is filled in the first opening 10a to better balance the terrain of the capacitor structure area c1 and the non-device area c2, thereby increasing the capacitance value of the capacitor structure 12.

[0128] Optionally, the display device 1000 can be applied to and used in various products, including, for example, televisions, notebook computers, monitors, billboards, Internet of Things devices, and portable electronic devices including mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players, navigation and ultra-mobile personal computers.

[0129] In addition, the display device 1000 according to some embodiments may be applied to a wearable device and may be used in a wearable device, including a smart watch, a watch phone, a glasses-type display, and a head-mounted display. In addition, according to some embodiments, the display device 1000 may be applied to an instrument panel for a car, a display screen in a central dashboard or a central information display arranged on a dashboard for a car, an interior mirror display replacing a side mirror of a car, and a display of an entertainment system arranged on the back of a front seat for rear seat passengers in a car.

[0130] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel comprising a pixel region configured to emit light, characterized in that: The display panel comprises: substrate; A thin film transistor is disposed on the substrate; a capacitor structure, disposed on the substrate and at least part of which is located in the pixel region, the capacitor structure comprising a first electrode plate and a second electrode plate disposed in different layers, the second electrode plate being located on a side of the first electrode plate away from the substrate; a first insulating layer, covering the thin film transistor and located between the first electrode plate and the second electrode plate, wherein a thickness of the first insulating layer at the first electrode plate is less than a thickness of the first insulating layer at the thin film transistor; a first flat layer covering the first insulating layer, wherein the first flat layer is provided with a first opening corresponding to the first electrode plate, the second electrode plate is filled in the first opening, and the thickness of the second electrode plate is less than or equal to the depth of the first opening; a second planar layer, covering the first planar layer and the second electrode plate and filling the first opening; and An anode is arranged on a side of the second planar layer away from the substrate and is electrically connected to the thin film transistor. In the thickness direction of the display panel, the anode is partially overlapped with the capacitor structure.

2. The display panel according to claim 1, characterized in that: A first groove connected to the first opening is formed on the first insulating layer, and the first groove is located at least on one side of the first electrode plate; A portion of the second electrode plate extends to fill the first groove and is disposed opposite to a side surface of the first electrode plate.

3. The display panel according to claim 2, characterized in that: The display panel further comprises an interlayer dielectric layer, and the interlayer dielectric layer is arranged on a side of the first electrode plate close to the substrate; A second groove is formed on the interlayer dielectric layer. The first groove is a through groove penetrating the first insulating layer. The second groove is connected to the first groove. A portion of the second electrode plate extends to fill up the second groove.

4. The display panel according to claim 3, characterized in that: The depth of the second groove is less than 1 / 3 of the thickness of the interlayer dielectric layer.

5. The display panel according to claim 3, characterized in that: The second electrode plate includes a first transparent conductive portion and a metal reflective layer disposed on a side of the first transparent conductive portion away from the substrate, the first transparent conductive portion is disposed in the first groove and the second groove, and the metal reflective layer is disposed in the first opening.

6. The display panel according to claim 5, characterized in that: The second electrode plate further includes a second transparent conductive portion, and the second transparent conductive portion is disposed on a side of the metal reflective layer away from the substrate.

7. The display panel according to any one of claims 5 to 6, characterized in that: The capacitor structure further includes a third electrode plate, which is arranged on a side of the interlayer dielectric layer close to the substrate, a first contact hole is opened on the interlayer dielectric layer to expose the third electrode plate, the first contact hole is covered with a metal part connected to the third electrode plate, the metal part is extended along the hole wall of the first contact hole, and a concave groove is formed on a side of the metal part away from the substrate; The first insulating layer is provided with a second contact hole communicating with the recessed groove, and a portion of the second electrode plate fills the second contact hole and the recessed groove and is connected to the metal portion.

8. The display panel according to claim 7, characterized in that: Another of the first transparent conductive parts is disposed in the second contact hole and the recessed groove, and the material of the first transparent conductive part includes metal oxide.

9. The display panel according to any one of claims 1 to 6, characterized in that: The surface roughness of the second electrode plate on a side close to the anode is greater than the surface roughness of the anode.

10. The display panel according to any one of claims 3 to 6, characterized in that: The capacitor structure further includes a third electrode plate and a fourth electrode plate, and the display panel further includes a buffer layer, a light shielding portion and a second insulating layer; The fourth electrode plate and the light-shielding portion are arranged in the same layer on the substrate, the buffer layer covers the fourth electrode plate and the light-shielding portion, the third electrode plate and the active layer of the thin film transistor are arranged in the same layer on a side of the buffer layer away from the substrate, the second insulating layer is arranged between the active layer of the thin film transistor and the gate of the thin film transistor, the interlayer dielectric layer covers the gate of the thin film transistor, the buffer layer and the third electrode plate, the source and drain of the thin film transistor and the first electrode plate are arranged in the same layer on a side of the interlayer dielectric layer away from the substrate, and the first insulating layer covers the interlayer dielectric layer, the source and drain of the thin film transistor and the first electrode plate.

11. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-10.

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