Display panel and display device

Abstract

Embodiments of the present application disclose a display panel and a display device. The thickness of the first insulating layer at the first electrode plate is smaller than the thickness of the first insulating layer at the thin film transistor. The first insulating layer covers the thin film transistor and is arranged between the first electrode plate and the second electrode plate of the capacitor structure. Therefore, by thinning the thickness of the first insulating layer at the capacitor structure, the height of the capacitor structure region is lowered, and the distance between the first electrode plate and the second electrode plate is shortened, thereby improving the capacitance of the capacitor structure. Furthermore, in order to locally thin the first insulating layer, the first opening is arranged at the capacitor structure corresponding to the first planar layer, and the thickness of the first planar layer is relatively large, so that the height of the capacitor structure region is lowered more. Therefore, by filling the second electrode plate in the first opening, the height of the capacitor structure region and the non-device region is better balanced, and the capacitance of the capacitor structure is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] Inkjet printing OLED technology has extremely high requirements for the flatness of the terrain within the pixel. If the terrain difference within the pixel is large, the uniformity of the dry film thickness formed after the luminescent material ink dries will be poor, which will lead to problems such as uneven luminous brightness within the pixel and reduced luminous efficiency of the device.

[0003] In the process of researching and practicing the existing technology, the inventors of this application discovered that the pixel area of ​​the existing inkjet printed OLED is covered by a capacitor area with a large plate area. Due to the requirements of high refresh rate and high resolution, the capacitor structure usually uses multiple conductive film layers to increase the capacitance value. This results in the film layer of the capacitor area below the pixel area being at a higher elevation, which can easily cause a large elevation difference extreme value with other areas in the pixel, thereby affecting the flatness of the pixel. Summary of the Invention

[0004] This application provides a display panel and display device that can improve the flatness within pixels and the capacitance value of capacitor structures.

[0005] This application provides a display panel including a pixel area configured to emit light, the display panel comprising:

[0006] substrate;

[0007] Thin-film transistors are disposed on the substrate;

[0008] A capacitor structure is disposed on the substrate and at least a portion of the capacitor structure is located within the pixel region. The capacitor structure includes a first electrode plate and a second electrode plate disposed in different layers, with the second electrode plate located on the side of the first electrode plate away from the substrate.

[0009] A first insulating layer covers the thin-film transistor and is located between the first electrode and the second electrode, wherein the thickness of the first insulating layer at the first electrode is less than the thickness of the first insulating layer at the thin-film transistor.

[0010] A first planarization layer covers the first insulating layer. The first planarization layer has a first opening corresponding to the first electrode plate. The second electrode plate is filled in the first opening. The thickness of the second electrode plate is less than or equal to the depth of the first opening.

[0011] A second planarization layer, covering the first planarization layer and the second electrode plate and filling the first opening; and

[0012] The anode is disposed on the side of the second planar layer away from the substrate and is electrically connected to the thin-film transistor. In the thickness direction of the display panel, the anode partially overlaps with the capacitor structure.

[0013] Optionally, in some embodiments of this application, a first groove communicating with the first opening is formed on the first insulating layer, and the first groove is located at least on one side of the first electrode plate;

[0014] The second electrode plate extends to fill the first groove and is positioned opposite to the side of the first electrode plate.

[0015] Optionally, in some embodiments of this application, the display panel further includes an interlayer dielectric layer disposed on the side of the first electrode plate near the substrate;

[0016] A second groove is formed on the interlayer dielectric layer. The first groove is a through groove that penetrates the first insulating layer. The second groove is connected to the first groove. A portion of the second electrode plate extends and fills the second groove.

[0017] Optionally, in some embodiments of this application, the depth of the second groove is less than 1 / 3 of the thickness of the interlayer dielectric layer.

[0018] Optionally, in some embodiments of this application, the second electrode plate includes a first transparent conductive portion and a metal reflective layer disposed on the side of the first transparent conductive portion away from the substrate. The first transparent conductive portion is disposed in the first groove and the second groove, and the metal reflective layer is disposed in the first opening.

[0019] Optionally, in some embodiments of this application, the second electrode plate further includes a second transparent conductive portion disposed on the side of the metal reflective layer away from the substrate.

[0020] Optionally, in some embodiments of this application, the capacitor structure further includes a third electrode plate, which is disposed on the side of the interlayer dielectric layer near the substrate. A first contact hole is formed on the interlayer dielectric layer to expose the third electrode plate. A metal portion connecting the third electrode plate is covered in the first contact hole. The metal portion extends along the hole wall of the first contact hole, and a recessed groove is formed on the side of the metal portion away from the substrate.

[0021] The first insulating layer has a second contact hole that communicates with the recessed groove, and a portion of the second electrode plate fills the second contact hole and the recessed groove and is connected to the metal part.

[0022] Optionally, in some embodiments of this application, another first transparent conductive portion is disposed within the second contact hole and the recessed groove, and the material of the first transparent conductive portion includes metal oxide.

[0023] Optionally, in some embodiments of this application, the surface roughness of the second electrode plate on the side closer to the anode is greater than the surface roughness of the anode.

[0024] Optionally, in some embodiments of this application, the capacitor structure further includes a third electrode plate and a fourth electrode plate, and the display panel further includes a buffer layer, a light-shielding portion, and a second insulating layer;

[0025] The fourth electrode plate and the light-shielding portion are disposed on the substrate in the same layer. The buffer layer covers the fourth electrode plate and the light-shielding portion. The third electrode plate and the active layer of the thin-film transistor are disposed on the side of the buffer layer away from the substrate in the same layer. The second insulating layer is disposed between the active layer of the thin-film transistor and the gate of the thin-film transistor. The interlayer dielectric layer covers the gate of the thin-film transistor, the buffer layer, and the third electrode plate. The source, drain, and first electrode plate of the thin-film transistor are disposed on the side of the interlayer dielectric layer away from the substrate in the same layer. The first insulating layer covers the interlayer dielectric layer, the source, drain, and first electrode plate of the thin-film transistor.

[0026] Accordingly, this application also provides a display device, including a display panel as described in any of the above embodiments.

[0027] The display panel and display device of this application embodiment are based on the first insulating layer covering the thin film transistor and disposed between the first electrode plate and the second electrode plate of the capacitor structure. Therefore, by thinning the thickness of the first insulating layer at the capacitor structure, the terrain of the capacitor structure region is reduced, while the distance between the first electrode plate and the second electrode plate is shortened, thereby increasing the capacitance value of the capacitor structure. Furthermore, since a first opening is provided at the capacitor structure corresponding to the first flattening layer in order to locally thin the first insulating layer, and the thickness of the first flattening layer is relatively large, the terrain of the capacitor structure region is reduced significantly. Therefore, by filling the first opening with the second electrode plate, the terrain of the capacitor structure region and the non-device region is better balanced, while simultaneously increasing the capacitance value of the capacitor structure. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application;

[0029] Figure 2 yes Figure 1 Enlarged view of section A;

[0030] Figure 3This is a schematic diagram showing the connection between the second electrode plate and the third electrode plate in the display panel provided in the embodiments of this application;

[0031] Figure 4 This is a schematic diagram of step B105 of the method for preparing a display panel provided in this application embodiment;

[0032] Figure 5 This is a schematic diagram of step B106 of the method for preparing a display panel provided in this application embodiment;

[0033] Figure 6 This is a schematic diagram of step B107 of the method for preparing a display panel provided in this application embodiment;

[0034] Figure 7 This is a schematic diagram of step B108 of the method for preparing a display panel provided in this application embodiment;

[0035] Figure 8 This is a schematic diagram of step B109 of the method for preparing a display panel provided in this application embodiment;

[0036] Figure 9 This is a schematic diagram of the structure of the display device provided in the embodiments of this application. Detailed Implementation

[0037] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific implementation methods described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, the embodiments can be combined with each other but will not be described in detail one by one. Unless otherwise stated, the directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device; the terms "first," "second," "third," etc. are only used as markings and do not impose numerical requirements or establish a sequence.

[0038] This application provides a display panel and a display device, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0039] Please refer to Figure 1 and Figure 2This application provides a display panel 100, including pixel areas sx configured to emit light. The display panel 100 includes a substrate 101, a thin-film transistor 11, a capacitor structure 12, a first insulating layer 102, a first planarization layer 103, a second planarization layer 104, and an anode 105.

[0040] A thin-film transistor 11 is disposed on a substrate 101. A capacitor structure 12 is disposed on the substrate 101, and at least a portion of the capacitor structure 12 is located within a pixel region sx. The capacitor structure 12 includes a first electrode 121 and a second electrode 122 disposed in different layers, with the second electrode 122 located on the side of the first electrode 121 away from the substrate 101.

[0041] The first insulating layer 102 covers the thin-film transistor 11 and is located between the first electrode 121 and the second electrode 122. The thickness h1 of the first insulating layer 102 at the first electrode 121 is less than the thickness h2 of the first insulating layer 102 at the thin-film transistor 11.

[0042] A first planarization layer 103 covers a first insulating layer 102. The first planarization layer 103 has a first opening 10a corresponding to the first electrode 121, and a second electrode 122 fills the first opening 10a. The thickness of the second electrode 122 is less than or equal to the depth h3 of the first opening 10a. A second planarization layer 104 covers the first planarization layer 103 and the second electrode 122 and fills the first opening 10a.

[0043] The anode 105 is disposed on the side of the second planarization layer 104 away from the substrate 101 and is electrically connected to the thin-film transistor 11. In the thickness direction of the display panel 100, the anode 105 partially overlaps with the capacitor structure 12.

[0044] The display panel 100 of this embodiment covers the thin-film transistor 11 with a first insulating layer 102 and is disposed between the first electrode 121 and the second electrode 122 of the capacitor structure 12. Therefore, by thinning the thickness of the first insulating layer 102 at the capacitor structure 12, the terrain of the capacitor structure region c1 is reduced, while the distance between the first electrode 121 and the second electrode 122 is shortened, thereby increasing the capacitance value of the capacitor structure 12. Furthermore, since the first opening 10a is provided at the capacitor structure 12 corresponding to the first flattening layer 103 in order to locally thin the first insulating layer 102, and the thickness of the first flattening layer 103 is relatively large, the terrain of the capacitor structure region c1 is reduced significantly. Therefore, by filling the first opening 10a with the second electrode 122, the terrain of the capacitor structure region c1 and the non-device region c2 is better balanced, while increasing the capacitance value of the capacitor structure 12.

[0045] It should be understood that the capacitor structure 12 includes at least three electrode plates, wherein the third electrode plate 123 is disposed on the side of the first electrode plate 121 close to the substrate 101. Therefore, by adding the second electrode plate 122, not only can the capacitance value of the capacitor structure 12 be increased, but the terrain difference between the capacitor structure region c1 and the non-device region c2 can also be leveled.

[0046] It should be explained that the non-device region c2 refers to the region where no devices or traces are disposed, that is, the region in the thickness direction of the display panel 100 that only includes the substrate and the insulating layer. Additionally, the pixel region sx refers to the region formed by the boundary of the opening of the exposed anode 105 formed in the pixel definition layer, wherein a light-emitting material is disposed in the opening.

[0047] In addition, it should be noted that since the second electrode plate 122 is formed by inkjet printing, the interior of the second electrode plate 122 has a certain porosity, and the porosity of the second electrode plate 122 is greater than that of the first electrode plate 121 and the anode 105. Combined with the first opening 10a, when the display panel 100 is applied to a curved display panel, the first opening 10a and the second electrode plate 122 with a larger porosity have better stress relief performance, thereby improving the reliability of the curved display panel.

[0048] Optionally, the second electrode 122 includes a plurality of conductive particles, which are interconnected to form the second electrode 122.

[0049] Optionally, the material of the light-emitting layer can be an organic material, such as Alq3, bis(2-methyl-8-hydroxyquinoline-N1,O8)-(1,1'-biphenyl-4-hydroxy)aluminum (BAlq), DPVBi, Almq3, or 3-tert-butyl-9,10-bis(2-naphthalene)anthracene (TBADN).

[0050] The material of the light-emitting layer can also be an inorganic material, such as one or more selected from group IV semiconductor nanocrystals, group II-V semiconductor nanocrystals, group II-VI semiconductor nanocrystals, group IV-VI semiconductor nanocrystals, group III-V semiconductor nanocrystals, and group III-VI semiconductor nanocrystals. For example, it can be one or more of silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, indium arsenide quantum dots, and gallium nitride quantum dots.

[0051] That is, the display panel 100 in the embodiments of this application can be an electroluminescent panel such as an organic light-emitting display panel, a quantum dot light-emitting display panel, or a micro LED display panel.

[0052] Optionally, in some embodiments of this application, a first groove 10b communicating with the first opening 10a is formed on the first insulating layer 102, and the first groove 10b is located at least on one side of the first electrode plate 121.

[0053] The second electrode plate 122 extends to fill the first groove 10b and is positioned opposite to the side of the first electrode plate 121.

[0054] It is understandable that the first groove 10b and the first opening 10a are connected in the thickness direction of the display panel 100, so that the material of the second electrode plate 122 can fill the first groove 10b and the first opening 10a. While compensating for the step difference, it increases the overlap area of ​​the second electrode plate 122 and the first electrode plate 121, thereby increasing the capacitance value of the capacitor structure 12.

[0055] It is important to understand that, compared to forming the second electrode plate using vapor deposition, this second electrode plate is attached to the sidewalls and bottom walls of the first groove 10b and the first opening 10a, forming an uneven structure. In this embodiment, the second electrode plate 122 is formed using inkjet printing. Based on this inkjet printing method, the second electrode plate 122 has better leveling properties, allowing it to fill the first groove 10b and the first opening 10a while maintaining better flatness, thereby improving the flatness of the capacitor structure region c1.

[0056] Secondly, the second electrode 122 is formed by inkjet printing. The thickness of the second electrode 122 can be flexibly adjusted by setting the size of the ink droplets and the number of printing cycles to better balance the potential difference with the non-device area c2. In addition, the electrical properties of the capacitor structure 12 can be adjusted by changing the conductive material of the ink droplets, thereby improving the heat dissipation, load, and conductivity of the capacitor structure 12.

[0057] Optionally, in some embodiments of this application, the display panel 100 further includes an interlayer dielectric layer 106, which is disposed on the side of the first electrode plate 121 near the substrate 101.

[0058] A second groove 10c is formed on the interlayer dielectric layer 106. The first groove 10b is a through groove that penetrates the first insulating layer 102. The second groove 10c connects to the first groove 10b. A portion of the second electrode plate 122 extends to fill the second groove 10c.

[0059] Understandably, the second groove 10c is designed so that a portion of the second electrode 122 extends into the interlayer dielectric layer 106 to maintain maximum overlap between the sides of the second electrode 122 and the first electrode 121, thereby increasing the capacitance value of the capacitor structure 12.

[0060] Secondly, the arrangement of the first groove 10b and the second groove 10c causes a portion of the second electrode plate 122 to extend toward the substrate 101, thereby locally increasing the thickness of the second electrode plate 122 and reducing the impedance of the second electrode plate 122.

[0061] Optionally, in some embodiments of this application, the depth h4 of the second groove 10c is less than 1 / 3 of the thickness of the interlayer dielectric layer 106.

[0062] It is understandable that, since the second groove 10c and the locally thinned first insulating layer 102 are formed by the same photomask, in order to avoid the first electrode 121 and the second electrode 122 being short-circuited due to excessive thinning of the first insulating layer 102, the depth of the second groove 10c should not be too deep. For example, the depth h4 of the second groove 10c is 1 / 3, 1 / 4, 1 / 5, 1 / 6, 1 / 7, 1 / 8, 1 / 9 or 1 / 10 of the thickness of the interlayer dielectric layer 106.

[0063] Optionally, in some embodiments of this application, the second electrode 122 is a single-film structure.

[0064] Optionally, in some embodiments of this application, the second electrode plate 122 includes a first transparent conductive portion 12a and a metal reflective layer 12b disposed on the side of the first transparent conductive portion 12a away from the substrate 101. The first transparent conductive portion 12a is disposed in the first groove 10b and the second groove 10c, and the metal reflective layer 12b is disposed in the first opening 10a.

[0065] It is understandable that, since the second electrode plate 122 is formed by inkjet printing, its multi-layered stacked structure is formed by multiple printing processes. These multiple printing processes compensate for any terrain defects in the previous printing, thereby improving the flatness of the second electrode plate 122. Secondly, the metal reflective layer 12b is located on the side of the first transparent conductive portion 12a closer to the anode 105, allowing it to be closer to the anode 105 and reflect light passing through it more quickly, thus improving the pixel's light extraction efficiency. Furthermore, the location of the first transparent conductive portion 12a on the side of the metal reflective layer 12b closer to the substrate 101 reduces the risk of corrosion to the metal reflective layer 12b.

[0066] Optionally, the conductivity of the metal reflective layer 12b is stronger than that of the first transparent conductive portion 12a.

[0067] Optionally, in some embodiments of this application, the second electrode plate 122 further includes a second transparent conductive portion 12c, which is disposed on the side of the metal reflective layer 12b away from the substrate 101.

[0068] It is understandable that the second transparent conductive part 12c is provided to cover the metal reflective layer 12b in order to reduce the risk of corrosion of the metal reflective layer 12b.

[0069] Optionally, the first transparent conductive portion 12a and the second transparent conductive portion 12c are made of the same material, both of which are metal oxides. The material of the metal reflective layer 12b can be silver, aluminum, or magnesium, etc.

[0070] Optionally, in some embodiments of this application, the surface roughness of the second electrode plate 122 on the side closer to the anode 105 is greater than the surface roughness of the anode 105.

[0071] It is understandable that, given that the second electrode 122 includes a metal reflective layer 12b and has a relatively large surface roughness, the light reflected by the metal reflective layer 12b can form diffuse reflection, improving the light emission uniformity of the pixel area sx. Furthermore, since the second electrode 122 is printed using inkjet printing, after the solvent evaporates, a microstructure with unevenness naturally forms on the surface of the second electrode 122, thus creating a rough surface without requiring additional surface treatment processes.

[0072] Optionally, in some embodiments, the second transparent conductive portion 12c may also be formed on the side of the directly oxidized metal reflective layer 12b away from the substrate 101, in order to reduce the thickness of the second electrode plate 122.

[0073] Optional, please refer to Figure 3 In some embodiments of this application, the capacitor structure 12 further includes a third electrode plate 123, which is disposed on the side of the interlayer dielectric layer 106 near the substrate 101. A first contact hole j1 is formed on the interlayer dielectric layer 106 to expose the third electrode plate 123, and a metal portion 125 connecting the third electrode plate 123 is covered within the first contact hole j1. The metal portion 125 extends along the wall of the first contact hole j1, and a recessed groove j3 is formed on the side of the metal portion 125 away from the substrate 101.

[0074] The first insulating layer 102 has a second contact hole j2 that connects to the recessed groove j3. Part of the second electrode plate 122 fills the second contact hole j2 and the recessed groove j3 and is connected to the metal part 125.

[0075] Understandably, covering the first contact hole j1 with the metal portion 125 reduces the contact resistance and conductivity of the second electrode plate 122 and the third electrode plate 123. Secondly, covering the first contact hole j1 with the metal portion 125 avoids over-cutting the third electrode plate 123 when forming the second contact hole j2 and prevents the second contact hole j2 from being too deep, thus improving the performance of the capacitor structure 12.

[0076] Optionally, in some embodiments of this application, another first transparent conductive portion 12a is disposed within the second contact hole j2 and the recessed groove j3, and the material of the first transparent conductive portion 12a includes metal oxide.

[0077] It is understandable that, based on the strong corrosion resistance of metal oxides, using the first transparent conductive part 12a of metal oxide to connect the metal part 125 can improve the stability of the connection between the second electrode plate 122 and the first electrode plate 121.

[0078] Optionally, in some embodiments of this application, the capacitor structure 12 further includes a third electrode 123 and a fourth electrode 124. The display panel 100 also includes a buffer layer 107, a light-shielding portion 108, and a second insulating layer 109.

[0079] The fourth electrode 124 and the light-shielding portion 108 are disposed on the substrate 101 in the same layer. A buffer layer 107 covers the fourth electrode 124 and the light-shielding portion 108. The third electrode 123 and the active layer 111 of the thin-film transistor 11 are disposed on the side of the buffer layer 107 away from the substrate 101 in the same layer. A second insulating layer 109 is disposed between the active layer 111 and the gate 112 of the thin-film transistor 11. An interlayer dielectric layer 106 covers the gate 112, the buffer layer 107, and the third electrode 123 of the thin-film transistor 11. The source 113, the drain 114, and the first electrode 121 of the thin-film transistor 11 are disposed on the side of the interlayer dielectric layer 106 away from the substrate 101 in the same layer. A first insulating layer 102 covers the interlayer dielectric layer 106, the source 113, the drain 114, and the first electrode 121 of the thin-film transistor 11.

[0080] Understandably, adding a fourth electrode plate 124 can increase the capacitance value of the capacitor structure 12. Secondly, the fourth electrode plate 124 and the light-shielding part 108 are arranged on the same layer, the third electrode plate 123 is arranged on the same layer as the active layer 111, and the first electrode plate 121 is arranged on the same layer as the source electrode 113 and the drain electrode 114, which can reduce the thickness of the display panel 100 and save on photomask manufacturing processes.

[0081] Secondly, the distance between the first electrode 121 and the third electrode 123 is equal to the thickness of the interlayer dielectric layer 106. That is, the first electrode 121 and the third electrode 123 are separated only by the interlayer dielectric layer 106, which further reduces the ground height of the capacitor structure 12, thereby balancing the ground height difference with the non-device region c2.

[0082] Optionally, in some embodiments, the display panel 100 further includes a first trace 131 disposed on the same layer as the first electrode plate 121 and a second trace 132 disposed on the same layer as the fourth electrode plate 124. Both the first trace 131 and the second trace 132 are located within the encapsulation clearance area. It should be understood that the encapsulation clearance area refers to the area covered by the encapsulation layer. Specifically, the first insulating layer 102 covers the first trace 131, and the second planarization layer 104 has a second opening 10f, which penetrates the first planarization layer 103 and corresponds to the encapsulation clearance area.

[0083] Optionally, in some embodiments, the display panel 100 further includes a connecting cable 133 disposed between the first planarization layer 103 and the second planarization layer 104. One end of the connecting cable 133 is connected to the anode 105, and the other end of the connecting cable 133 is connected to the drain 114 of the thin-film transistor 11.

[0084] The following describes the method for manufacturing the display panel 100 according to an embodiment of this application, as follows:

[0085] In step B101, a light-shielding layer and a buffer layer 107 are sequentially formed on the substrate 101. The light-shielding layer includes a light-shielding portion 108, a fourth electrode plate 124, and a second trace 132.

[0086] Optionally, the substrate 101 can be a rigid substrate or a flexible substrate. The material of the substrate 101 includes one of glass, sapphire, silicon, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene dicarboxylate, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyethersulfone, aromatic fluorotoluene containing polyarylate, polycyclic olefins, polyimide, or polyurethane.

[0087] Optionally, the light-shielding layer can be a single-layer inorganic metal material, such as Cr (chromium), Mo (molybdenum), Mn (manganese), etc., or it can be a multi-layer structure, including molybdenum-aluminum-molybdenum (Mo / Al / Mo) metal layer structure, aluminum-molybdenum (Al / Mo) metal layer structure, molybdenum-copper (Mo / Cu) metal layer structure, or molybdenum-titanium-copper (Mo / Ti / Cu) metal layer structure, including but not limited to the above materials.

[0088] Then proceed to step B102.

[0089] In step B102, a semiconductor layer, a second insulating layer 109, and a gate 112 are sequentially formed on the buffer layer 107.

[0090] The semiconductor layer includes an active layer 111 and a third electrode 123. Optionally, the semiconductor layer is made of a metal oxide, such as an amorphous metal oxide material containing indium, gallium, or zinc.

[0091] It should be noted that the source and drain portions of the third electrode plate 123 and the active layer 111 are both conductive structures.

[0092] Then proceed to step B103.

[0093] In step B103, an interlayer dielectric layer 106, a first metal layer, and a first contact hole j1 are sequentially formed on the gate 112.

[0094] Optionally, the first metal layer includes a source electrode 113, a drain electrode 114, a first electrode plate 121, a metal portion 125, and a first trace 131. The metal portion 125 covers the first contact hole j1.

[0095] Then proceed to step B104.

[0096] In step B104, a first insulating layer 102 and a first planarization layer 103 are formed on the first metal layer.

[0097] Optionally, the interlayer dielectric layer 106, buffer layer 107, first insulating layer 102, and second insulating layer 109 may be formed from a plurality of inorganic layers stacked in an alternating manner. For example, the interlayer dielectric layer 106, buffer layer 107, first insulating layer 102, and second insulating layer 109 may be formed as a bilayer by stacking inorganic layers comprising at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide, or as a multilayer by alternating stacking inorganic layers comprising at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide. However, this disclosure is not limited thereto, and the interlayer dielectric layer 106, buffer layer 107, first insulating layer 102, and second insulating layer 109 may be formed as a single inorganic layer comprising the aforementioned insulating material.

[0098] Furthermore, in one or more embodiments, the interlayer dielectric layer 106 may be made of an organic insulating material such as polyimide.

[0099] Optionally, the thickness of the first insulating layer 102 is between 3,000 angstroms and 4,000 angstroms, for example, it can be 3,000 angstroms, 3,500 angstroms or 4,000 angstroms.

[0100] The material of the first planarization layer 103 can be an organic transparent film layer, such as transparent photoresist, acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin, etc.

[0101] Optionally, the thickness of the first planarization layer 103 is between 2 micrometers and 2.5 micrometers, for example, it can be 2 micrometers, 2.1 micrometers, 2.2 micrometers, 2.3 micrometers, 2.4 micrometers or 2.5 micrometers.

[0102] In this embodiment, the first planarization layer 103 is described as a transparent photoresist, but it is not limited thereto.

[0103] Then proceed to step B105.

[0104] Please refer to Figure 4 In step B105, a multi-tone or grayscale mask mk is used to expose the first planarization layer 103. Specifically, the area forming the via region connecting the first metal layer and the first groove 10b is exposed using a full-transmittance aperture (FT) exposure process; the area forming the first opening 10a is exposed using a first light-transmitting portion (3T) exposure process; and the area forming the second opening 10f is exposed using a second light-transmitting portion (HT) exposure process. The transmittance of the full-transmittance aperture (FT), the second light-transmitting portion (HT), and the first light-transmitting portion (3T) decreases sequentially. It should be noted that the transmittance of the full-transmittance aperture (FT) is 100%.

[0105] Proceed to step B106.

[0106] Please refer to Figure 5 In step B106, a through hole 14a exposing the drain electrode 114 and a second contact hole j2 exposing the metal portion 125 are formed on the first planarization layer 103. A first groove w1 is formed in the region of the first electrode plate 121, a through groove 14b is formed on the outer periphery of the first electrode plate 121, and a second groove w2 is formed in the region of the first trace 131. Both the through hole 14a and the through groove 14b penetrate the first planarization layer 103 and the first insulating layer 102.

[0107] The depth of the first trench w1 is greater than the depth of the second trench w2.

[0108] Proceed to step B107.

[0109] Please refer to Figure 6 In step B107, the first planarization layer 103 is ashed, the first planarization layer 103 is thinned to completely remove the first planarization layer 103 directly above the first electrode plate 121, and a thinner first planarization layer 103 is retained directly above the first trace 131.

[0110] Proceed to step B108.

[0111] Please refer to Figure 7 In step B108, the exposed first insulating layer 102 is etched to thin the portion of the first insulating layer 102 corresponding to the first electrode plate 121.

[0112] Optionally, the thickness of the first insulating layer 102 corresponding to the portion of the first electrode 121 is between 1,000 angstroms and 2,000 angstroms, for example, it can be 1,000 angstroms, 1,500 angstroms or 2,000 angstroms.

[0113] Optionally, the first planarization layer 103 and the first insulating layer 102 can be etched together using a gas dry etching method to form the first opening 10a, the second opening 10f, the first groove 10b, and the second groove 10c.

[0114] Optionally, the depth h4 of the second groove 10c is between 800 angstroms and 1200 angstroms, for example, it can be 800 angstroms, 900 angstroms, 1000 angstroms, 1100 angstroms or 1200 angstroms.

[0115] Proceed to step B109.

[0116] Please refer to Figure 8 In step B109, a single or multiple conductive filling layers are formed in the first opening 10a, the first groove 10b and the second groove 10c by inkjet printing and vacuum drying processes to form the second electrode plate 122.

[0117] Optionally, the conductive filling layer of the first groove 10b and the second groove 10c can be a metal oxide, such as indium tin oxide or indium zinc oxide. That is, the first transparent conductive part 12a fills the first groove 10b, the second groove 10c and covers the bottom surface of the first opening 10a.

[0118] The material of the metal reflective layer 12b can be a single metal or alloy such as magnesium or silver, which are highly reflective.

[0119] Proceed to step B110.

[0120] In step B110, a transition wire 133, a second flattening layer 104, and an anode 105 are sequentially formed on the first flattening layer 103.

[0121] Optionally, the gate 112, the first metal layer, and the transition line 133 can each be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, neodymium, and cobalt, an alloy composed of any of the above metal elements, or an alloy combining any of the above metal elements. Furthermore, the gate 112, the first metal layer, and the transition line 133 can have a single-layer structure or a stacked structure of two or more layers.

[0122] The material of the second planarization layer 104 can be an organic transparent film layer, such as transparent photoresist, acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin, etc.

[0123] The second flattening layer 104 covers the first flattening layer 103 and the first opening 10a to flatten the entire display area and improve the flatness of the capacitor structure area c1 and the non-device area c2.

[0124] It should be understood that the display panel 100 in this embodiment of the application also sequentially forms a pixel definition layer, a light-emitting functional layer, a cathode, and an encapsulation layer on the second planarization layer 104. An opening including an anode 105 is formed on the pixel definition layer, and the light-emitting functional layer is disposed within the opening.

[0125] Please refer to Figure 9 Accordingly, this application also provides a display device 1000, including a display panel 100 as described in any of the above embodiments.

[0126] It should be noted that the display panel 100 of the display device 1000 in this application embodiment has a similar or identical structure to the display panel 100 of any of the above embodiments, so it will not be described again here. For details, please refer to the above description. Figures 1 to 8 The relevant explanation.

[0127] The display device 1000 of this application embodiment is based on a first insulating layer 102 covering a thin-film transistor 11 and between a first electrode 121 and a second electrode 122 disposed in a capacitor structure 12. Therefore, by thinning the thickness of the first insulating layer 102 at the capacitor structure 12, the terrain of the capacitor structure region c1 is reduced, while the distance between the first electrode 121 and the second electrode 122 is shortened, thereby increasing the capacitance value of the capacitor structure 12. Furthermore, since a first opening 10a is provided at the capacitor structure 12 corresponding to the first flattening layer 103 in order to locally thin the first insulating layer 102, and the thickness of the first flattening layer 103 is relatively large, the terrain of the capacitor structure region c1 is reduced significantly. Therefore, by filling the first opening 10a with the second electrode 122, the terrain of the capacitor structure region c1 and the non-device region c2 is better balanced, while simultaneously increasing the capacitance value of the capacitor structure 12.

[0128] Optionally, the display device 1000 can be applied to and used in a variety of products, including, for example, televisions, laptops, monitors, billboards, Internet of Things devices, and portable electronic devices including mobile phones, smartphones, tablet computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players, navigation devices, and ultra-mobile personal computers.

[0129] Furthermore, the display device 1000 according to some embodiments can be applied to wearable devices and can be used within wearable devices, including smartwatches, watch phones, glasses-type displays, and head-mounted displays. Additionally, according to some embodiments, the display device 1000 can be applied to instrument panels for automobiles, displays in central dashboards or central information displays arranged on instrument panels, interior mirror displays replacing side mirrors in automobiles, and displays for entertainment systems arranged on the back of the front seats for rear-seat passengers in automobiles.

[0130] The above provides a detailed description of a display panel and display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel comprising pixel areas configured to emit light, characterized in that, The display panel includes: substrate; Thin-film transistors are disposed on the substrate; A capacitor structure is disposed on the substrate and at least a portion of the capacitor structure is located within the pixel region. The capacitor structure includes a first electrode plate and a second electrode plate disposed in different layers, with the second electrode plate located on the side of the first electrode plate away from the substrate. A first insulating layer covers the thin-film transistor and is located between the first electrode and the second electrode, wherein the thickness of the first insulating layer at the first electrode is less than the thickness of the first insulating layer at the thin-film transistor. A first planarization layer covers the first insulating layer. The first planarization layer has a first opening corresponding to the first electrode plate. The second electrode plate is filled in the first opening. The thickness of the second electrode plate is less than or equal to the depth of the first opening. A second planarization layer, covering the first planarization layer and the second electrode plate and filling the first opening; and An anode is disposed on the side of the second planarization layer away from the substrate and electrically connected to the thin-film transistor. In the thickness direction of the display panel, the anode partially overlaps with the capacitor structure. The first insulating layer has a first groove communicating with the first opening, and the first groove is located at least on one side of the first electrode plate; The second electrode plate extends to fill the first groove and is disposed opposite to the side of the first electrode plate. The second electrode plate is configured to be formed by inkjet printing.

2. The display panel according to claim 1, characterized in that, The display panel further includes an interlayer dielectric layer, which is disposed on the side of the first electrode plate near the substrate; A second groove is formed on the interlayer dielectric layer. The first groove is a through groove that penetrates the first insulating layer. The second groove is connected to the first groove. A portion of the second electrode plate extends and fills the second groove.

3. The display panel according to claim 2, characterized in that, The depth of the second groove is less than 1 / 3 of the thickness of the interlayer dielectric layer.

4. The display panel according to claim 2, characterized in that, The second electrode plate includes a first transparent conductive portion and a metal reflective layer disposed on the side of the first transparent conductive portion away from the substrate. The first transparent conductive portion is disposed in the first groove and the second groove, and the metal reflective layer is disposed in the first opening.

5. The display panel according to claim 4, characterized in that, The second electrode plate further includes a second transparent conductive portion, which is disposed on the side of the metal reflective layer away from the substrate.

6. The display panel according to any one of claims 4-5, characterized in that, The capacitor structure further includes a third electrode plate, which is disposed on the side of the interlayer dielectric layer near the substrate. A first contact hole is formed on the interlayer dielectric layer to expose the third electrode plate. A metal part connecting the third electrode plate is covered in the first contact hole. The metal part extends along the hole wall of the first contact hole, and a recessed groove is formed on the side of the metal part away from the substrate. The first insulating layer has a second contact hole that communicates with the recessed groove, and a portion of the second electrode plate fills the second contact hole and the recessed groove and is connected to the metal part.

7. The display panel according to claim 6, characterized in that, Another first transparent conductive part is disposed in the second contact hole and the recessed groove, and the material of the first transparent conductive part includes metal oxide.

8. The display panel according to any one of claims 1-5, characterized in that, The surface roughness of the second electrode plate on the side closer to the anode is greater than that of the anode.

9. The display panel according to any one of claims 2-5, characterized in that, The capacitor structure also includes a third plate and a fourth plate, and the display panel also includes a buffer layer, a light-shielding part, and a second insulating layer; The fourth electrode plate and the light-shielding portion are disposed on the substrate in the same layer. The buffer layer covers the fourth electrode plate and the light-shielding portion. The third electrode plate and the active layer of the thin-film transistor are disposed on the side of the buffer layer away from the substrate in the same layer. The second insulating layer is disposed between the active layer of the thin-film transistor and the gate of the thin-film transistor. The interlayer dielectric layer covers the gate of the thin-film transistor, the buffer layer, and the third electrode plate. The source, drain, and first electrode plate of the thin-film transistor are disposed on the side of the interlayer dielectric layer away from the substrate in the same layer. The first insulating layer covers the interlayer dielectric layer, the source, drain, and first electrode plate of the thin-film transistor.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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