Display panel and display device

Abstract

The invention provides a display panel and a display device. The problem that in the prior art, power consumption of a display panel is high is solved. The display panel includes: a substrate; the plurality of functional layers are located on one side of the substrate and comprise a plurality of pixel circuits, first scanning signal lines S2 and data signal lines; the pixel circuit comprises a first transistor, a second transistor and a capacitor. A control electrode of the first transistor is connected with a first polar plate of the capacitor, a first electrode of the first transistor is connected with a second electrode of the second transistor, a first electrode of the second transistor is connected with a data signal line, and a control electrode of the second transistor is connected with a first scanning signal line; the orthographic projection of the second electrode of the first transistor on the substrate and the orthographic projection of the first scanning signal line on the substrate have overlapping areas, and the areas of the overlapping areas corresponding to at least part of the pixel circuits are different.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is considered to be the next generation of flat panel display technology after liquid crystal. It is popular among users for its excellent color and image quality. As users' demand for display increases, the power consumption of OLED display panels needs to be further reduced. Summary of the invention

[0003] In view of this, embodiments of the present application provide a display panel and a display device, which solve the problem of high power consumption of display panels in the prior art.

[0004] In a first aspect, the present application provides a display panel, comprising: a substrate; and a plurality of pixel circuits, a first scanning signal line and a data signal line located on one side of the substrate; wherein the pixel circuit comprises a first transistor, a second transistor and a capacitor; the control electrode of the first transistor is connected to the first electrode plate of the capacitor, the first electrode of the first transistor is connected to the second electrode of the second transistor, the first electrode of the second transistor is connected to the data signal line, and the control electrode of the second transistor is connected to the first scanning signal line; the orthographic projection of the second electrode of the first transistor on the substrate and the orthographic projection of the first scanning signal line on the substrate have an overlapping area, and the areas of the overlapping areas corresponding to at least some of the pixel circuits are not equal.

[0005] In combination with the first aspect, in some possible implementations, the display panel also includes multiple sub-pixels, which are located on the side of the pixel circuit away from the substrate, and the sub-pixels and the pixel circuit are electrically connected; the multiple sub-pixels include a first sub-pixel and a second sub-pixel, and the multiple pixel circuits include a first pixel circuit and a second pixel circuit; the area of ​​an overlapping region corresponding to the first pixel circuit connected to the first sub-pixel is smaller than the area of ​​an overlapping region corresponding to the second pixel circuit connected to the second sub-pixel; preferably, the multiple sub-pixels have different colors; preferably, the first sub-pixel includes a blue sub-pixel, and the second sub-pixel includes any one of a red sub-pixel and a green sub-pixel.

[0006] In combination with the first aspect, in some possible implementations, the multiple sub-pixels also include a third sub-pixel, and the multiple pixel circuits also include a third pixel circuit; the area of ​​the overlapping region corresponding to the first pixel circuit connected to the first sub-pixel is smaller than the area of ​​the overlapping region corresponding to the third pixel circuit connected to the third sub-pixel; preferably, the area of ​​the overlapping region corresponding to the third pixel circuit connected to the third sub-pixel is equal to the area of ​​the overlapping region corresponding to the second pixel circuit connected to the second sub-pixel.

[0007] In combination with the first aspect, in some possible implementations, the overlapping area corresponding to the second pixel circuit connected to the second sub-pixel and the overlapping area corresponding to the third pixel circuit connected to the third sub-pixel are axially symmetric; preferably, the second sub-pixel and the third sub-pixel are adjacent.

[0008] In combination with the first aspect, in some possible implementations, the multiple functional layers include a second semiconductor layer, and the second electrode of the first transistor is located in the second semiconductor layer; in the overlapping area, the areas of the second electrodes of the first transistors in at least some pixel circuits are not equal; preferably, the material of the second semiconductor layer includes indium gallium zinc oxide; preferably, the multiple functional layers also include a second metal layer, which is located on the side of the second semiconductor layer close to the substrate, and at least some of the first scanning signal lines are located in the second metal layer.

[0009] In combination with the first aspect, in some possible implementations, the pixel circuit also includes a third transistor, the first electrode of the third transistor and the second electrode of the first transistor are connected through a conductive via, and the orthographic projection of the conductive via on the substrate is located within the overlapping area; preferably, the display panel also includes a second scanning signal line located on one side of the substrate; the second electrode of the third transistor is connected to the control electrode of the first transistor, and the control electrode of the third transistor is connected to the second scanning signal line; preferably, the third transistor includes an indium gallium zinc oxide thin film transistor.

[0010] In combination with the first aspect, in some possible implementations, the orthographic projection of the first transistor on the substrate is located on one side of the first scanning signal line; in the extension direction of the first scanning signal line, the orthographic projection of the conductive via on the substrate is located on the side of the overlapping area away from the orthographic projection of the first transistor on the substrate.

[0011] In combination with the first aspect, in some possible implementations, the display panel also includes a third scanning signal line and a first initialization signal line, which are located on one side of the substrate; the pixel circuit also includes a fourth transistor, the first electrode of the fourth transistor is connected to the first initialization signal line, the second electrode of the fourth transistor is connected to the first electrode of the third transistor, and the control electrode of the fourth transistor is connected to the third scanning signal line; preferably, the fourth transistor includes an indium gallium zinc oxide thin film transistor.

[0012] In combination with the first aspect, in some possible implementations, the display panel also includes a high-voltage power supply signal line and a light-emitting control signal line; the pixel circuit also includes a fifth transistor and a sixth transistor, the control electrode of the fifth transistor is connected to the light-emitting control signal line, the first electrode of the fifth transistor is connected to the high-voltage power supply signal line and the second electrode plate of the capacitor, and the second electrode of the fifth transistor is connected to the first electrode of the first transistor; the control electrode of the sixth transistor is connected to the light-emitting control signal line, the first electrode of the sixth transistor is connected to the second electrode of the first transistor, and the second electrode of the sixth transistor is connected to the anode of the sub-pixel; the display panel also includes a second initialization signal line, a third initialization signal line and a fourth scanning signal line; the pixel circuit also includes a seventh transistor and an eighth transistor, the control electrode of the seventh transistor is connected to the fourth scanning signal line, the first electrode of the seventh transistor is connected to the second initialization signal line, and the second electrode of the seventh transistor is connected to the second electrode of the sixth transistor; the control electrode of the eighth transistor is connected to the fourth scanning signal line, the first electrode of the eighth transistor is connected to the third initialization signal line, and the second electrode of the eighth transistor is connected to the first electrode of the sixth transistor.

[0013] A second aspect of the present application provides a display device, comprising a display panel provided by any of the above embodiments.

[0014] According to the display panel and the display device provided by the embodiments of the present application, by setting the orthographic projection of the second electrode of the first transistor on the substrate and the orthographic projection of the first scanning signal line on the substrate to have an overlapping area, the areas of the overlapping areas corresponding to at least some pixel circuits are not equal. The unequal areas of the overlapping areas, that is, the unequal coupling capacitances between the second electrode of the first transistor and the first scanning signal line are not equal, the black state voltage of the display panel can be reduced, thereby reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a circuit diagram of a pixel circuit in the related art.

[0016] Figure 2 A schematic diagram of the cross-sectional structure of a display panel provided in one embodiment of the present application.

[0017] Figure 3a This is a wiring layout of a display panel provided in the first embodiment of the present application.

[0018] Figure 3b A wiring layout of a display panel provided in the second embodiment of the present application.

[0019] Figure 4a-Figure 4i FIG3 is a schematic diagram of a top view of the structure of a single film layer in the display panel.

[0020] Figure 5 A schematic diagram of the structure of a display device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0021] For display products, power consumption is a hard standard for evaluating product performance. Therefore, reducing the power consumption of display products has always been one of the research directions of technological innovation.

[0022] Black state voltage (VGMP) is one of the factors that affect power consumption. Reducing VGMP can reduce the high-voltage power supply signal output by the display driver chip, thereby helping to reduce the power consumption of the display driver chip. When reducing VGMP, other product parameters must also be taken into account and other parameters, such as white state voltage (VGSP), must not be deteriorated.

[0023] The embodiment of the present application reduces power consumption by differentially designing coupling capacitors in different pixel circuits, thereby reducing VGMP without affecting VGSP.

[0024] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0025] In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is understood that when a structure is referred to as being "on or under" another structure, the structure may be directly on or under the other structure, or there may be intermediate structures. The same reference numerals always indicate the same structure. The structures mentioned herein include any of a film layer, an element, a device, a component, and an assembly.

[0026] When a structure is referred to as being “connected” to another structure, the structure may be directly connected to the other structure or indirectly connected to the other structure with one or more intervening structures interposed therebetween.

[0027] Figure 1 FIG. 1 is a circuit diagram of a pixel circuit in the related art. Figure 1 As shown, the pixel circuit is an 8T1C pixel circuit, specifically including eight transistors and one capacitor Cst. The eight transistors are respectively denoted as transistor Ti, and i is 1 to 8 in sequence.

[0028] Among them, the control electrode of the first transistor T1 is connected to the first electrode of the capacitor Cst, the first electrode of the first transistor T1 is connected to the second electrode of the fifth transistor T5, and the second electrode of the first transistor T1 is connected to the first electrode of the sixth transistor T6. The first electrode of the second transistor T2 is connected to the data voltage signal line Data, the second electrode of the second transistor T2 is connected to the first electrode of the first transistor T1, and the control electrode of the second transistor T2 is connected to the first scanning signal line S1. The first electrode of the third transistor T3 is connected to the second electrode of the first transistor T1, the second electrode of the third transistor T3 is connected to the control electrode of the first transistor T1, and the control electrode of the third transistor T3 is connected to the second scanning signal line S2. The first electrode of the fourth transistor T4 is connected to the first initialization signal line Vref1, the second electrode of the fourth transistor T4 is connected to the second electrode of the first transistor T1, and the control electrode of the fourth transistor T4 is connected to the third scanning signal line S3. The control electrode of the fifth transistor T5 is connected to the light emitting control signal line Em, the first electrode of the fifth transistor T5 is connected to the high voltage power signal line Elvdd, and the second electrode of the fifth transistor T5 is connected to the first electrode of the first transistor T1. The control electrode of the sixth transistor T6 is connected to the light emitting control signal line Em, the first electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1, and the second electrode of the sixth transistor T6 is connected to the anode of the light emitting device OLED. The control electrode of the seventh transistor T7 is connected to the fourth scanning signal line S4, the first electrode of the seventh transistor T7 is connected to the second initialization signal line Vref2, and the second electrode of the seventh transistor T7 is connected to the anode of the light emitting device OLED. The control electrode of the eighth transistor T8 is connected to the fourth scanning signal line S4, the first electrode of the eighth transistor T8 is connected to the third initialization signal line Vref3, and the second electrode of the eighth transistor T8 is connected to the second electrode of the first transistor T1.

[0029] The high-voltage power signal line Elvdd is used to transmit the high-voltage power signal Vdd, and the low-voltage power signal line Elvss is used to transmit the low-voltage power signal Vss. The light-emitting control signal line Em is used to transmit the light-emitting control signal em. The data signal line Data is used to transmit the data signal Vdata. The first scan signal line S1 is used to transmit the first scan signal Scan1, the second scan signal line S2 is used to transmit the second scan signal Scan2, and the third scan signal line S3 is used to transmit the third scan signal Scan3. The first initialization signal line Vref1 is used to transmit the first initialization signal Vf1, the second initialization signal line Vref2 is used to transmit the second initialization signal Vf2, and the third initialization signal line Vref3 is used to transmit the third initialization signal Vf3.

[0030] For the convenience of description, the control electrode of the first transistor T1 is recorded as the first node G, the second electrode of the first transistor T1 is recorded as the second node D, and the first electrode of the first transistor T1 is recorded as the third node S.

[0031] Figure 1 The working process of the pixel circuit shown includes:

[0032] In the capacitor initialization stage, the second scan signal Scan2 and the third scan signal Scan3 are set to high potential, the third transistor T3 and the fourth transistor T4 are turned on, and the first initialization signal Vf1 resets the first node G and the second node D. The capacitor Cst is discharged, and the voltage Vg of the first node G=Vf1.

[0033] In the data writing stage, the third scan signal Scan3 is set to a low potential, and the fourth transistor T4 is turned off. The first scan signal Scan1 is set to a low potential, and the second transistor T2 is turned on. The data signal Vd is written, and the voltage Vs of the third node S is Vdd. When the first transistor T1 is turned off, the voltage difference Vgs between the first node G and the third node S is Vth, and the voltage Vg of the first node G is Vth+Vdd.

[0034] In the anode initialization stage, the fourth scan signal Scan4 is set to a low potential, the seventh transistor T7 and the eighth transistor T8 are turned on, and the second node D and the anode of the light emitting device OLED are reset respectively.

[0035] In the light-emitting stage, the light-emitting control signal em is set to a low potential, the fifth transistor T5 and the sixth transistor T6 are turned on, the high-voltage power supply signal Vdd is written into the light-emitting device OLED, and the light-emitting device OLED emits light. The driving current flowing through the light-emitting device OLED is I=1 / 2μCox(W / L)(Vdata-Vdd) 2 .

[0036] Generally speaking, the pixel circuit is presented in a display panel in a multi-layer stacked state. In this case, when there is overlap between different structures of the pixel circuit or between the pixel circuit and the signal line, a coupling capacitor is generated at the overlapping position, for example, a coupling capacitor C is generated between the first scanning signal line S1 and the second node D.

[0037] The inventor has found that in the data writing stage, the third transistor T3 is in an open state, and the control electrode and the second electrode of the first transistor T1 are connected. In this case, when the first scan signal Scan1 rises from a low potential to a high potential, the coupling capacitor C between the first scan signal line S1 and the second node D is coupled to the control electrode of the first transistor T1, so that the control electrode potential of the first transistor T1 is raised, resulting in a decrease in the driving current of the light-emitting device OLED. Therefore, by increasing the coupling capacitor C between the first scan signal line S1 and the second node D, the driving current I of the light-emitting device OLED can be reduced, thereby reducing VGMP. Conversely, by reducing the coupling capacitor C between the second scan signal line S2 and the second node D, the driving current I of the light-emitting device OLED can be increased, thereby increasing VGSP. It can be seen that when the coupling capacitor C increases, the driving circuit I decreases, the VGMP decreases, and the power consumption decreases; conversely, when the coupling capacitor C decreases, the driving circuit I increases, the VGSP increases, and the high-brightness mode is supported.

[0038] In view of this, the embodiment of the present application reduces power consumption by differentially setting the coupling capacitors C of different pixel circuits, thereby reducing VGMP without affecting VGSP.

[0039] It should be noted that the embodiments of the present application are only Figure 1 The 8T1C pixel circuit shown is used as an example for description, and the technical solution provided in the embodiment of the present application is also applicable to other pixel circuits, such as a 7T1C pixel circuit.

[0040] The technical solution of the embodiments of the present application is described in detail below with reference to the accompanying drawings.

[0041] Figure 2 A schematic diagram of the cross-sectional structure of a display panel provided in one embodiment of the present application. Figure 3a This is a wiring layout of a display panel provided in the first embodiment of the present application. Figure 3b A wiring layout of a display panel provided in the second embodiment of the present application. Figure 3a and Figure 3b They are shown respectively Figure 2 The partial film layer stacking structure of the display panel is shown. Figure 1-Figure 3bAs shown, the display panel includes: a substrate 11 and a plurality of pixel circuits 13 located on one side of the substrate 11, a first scanning signal line S1 and a data signal line Vdata. The pixel circuit 13 includes a first transistor T1, a second transistor T2 and a capacitor Cst. The control electrode of the first transistor T1 is connected to the first electrode plate of the capacitor Cst, the first electrode of the first transistor T1 is connected to the second electrode of the second transistor T2, the first electrode of the second transistor T2 is connected to the data signal line Vdata, and the control electrode of the second transistor T2 is connected to the first scanning signal line S1; the orthographic projection of the second electrode of the first transistor T1 on the substrate 11 and the orthographic projection of the first scanning signal line S1 on the substrate 11 have an overlapping area Q, and the areas of the overlapping areas Q corresponding to at least some of the pixel circuits 13 are not equal.

[0042] The area of ​​the overlapping region Q can represent the coupling capacitance C. The larger the area of ​​the overlapping region Q, the larger the coupling capacitance C. Therefore, by setting the areas of the overlapping regions Q corresponding to different pixel circuits 13 to be different, the coupling capacitances C corresponding to different pixel circuits 13 are made different.

[0043] In addition, since the driving currents of sub-pixels of different colors are different in magnitude, the sub-pixels with large driving current I have a greater impact on VGSP, so the coupling capacitor C corresponding to the pixel circuit connected to the sub-pixel with large driving current I can be set to be smaller, so that the driving circuit I is large enough to ensure that VGSP is large enough to support the high-brightness mode. At the same time, the sub-pixels with small driving current I have a greater impact on VGMP, so the coupling capacitor C corresponding to the pixel circuit connected to the sub-pixel with small driving current I can be set to be larger, so that the driving circuit is small enough to ensure that VGMP is small enough to reduce power consumption.

[0044] According to the display panel provided in the embodiment of the present application, by setting the areas of the overlapping regions Q corresponding to at least some pixel circuits 13 to be unequal, so that the coupling capacitors C corresponding to different pixel circuits 13 are unequal, it is possible to reduce VGMP while ensuring that VGSP is not reduced, that is, to reduce power consumption while supporting high-brightness mode.

[0045] In one embodiment, Figure 2 As shown, the display panel further includes a plurality of sub-pixels 12, which are located on the side of the conductive layer away from the substrate 11. The sub-pixels 12 are electrically connected to the pixel circuit 13. The plurality of sub-pixels 12 include a first sub-pixel and a second sub-pixel, and the plurality of pixel circuits 13 include a first pixel circuit 131 and a second pixel circuit 132. Figure 2 , Figure 3a and Figure 3b As shown, the area of ​​the overlapping region Q corresponding to the first pixel circuit 131 connected to the first sub-pixel is smaller than the area of ​​the overlapping region Q corresponding to the second pixel circuit 132 connected to the second sub-pixel.

[0046] Exemplarily, the colors of the plurality of sub-pixels 12 are different. For example, the first sub-pixel includes a blue sub-pixel B, and the second sub-pixel includes any one of a red sub-pixel R and a green sub-pixel G. Since the driving current I of the blue sub-pixel B is the largest among the red sub-pixel R, the green sub-pixel G and the blue sub-pixel B, the area of ​​the overlapping region Q corresponding to the pixel circuit 13 connected to the blue sub-pixel B is set to be smaller than the area of ​​the overlapping region Q corresponding to the pixel circuit 13 connected to other color sub-pixels (e.g., the red sub-pixel R or the green sub-pixel G), and the driving current of the blue sub-pixel B can be used to ensure that VGSP is large enough to support the high-brightness mode, and the driving current of the other color sub-pixels can be used to ensure that VGMP is small enough to reduce power consumption.

[0047] In one embodiment, in combination Figure 2 , Figure 3a and Figure 3b As shown, the plurality of sub-pixels 12 further include a third sub-pixel, and the plurality of pixel circuits 13 further include a third pixel circuit 133. The area of ​​the overlapping region Q corresponding to the first pixel circuit 131 connected to the first sub-pixel is smaller than the area of ​​the overlapping region Q corresponding to the third pixel circuit 133 connected to the third sub-pixel. Exemplarily, the first sub-pixel includes a blue sub-pixel B, the second sub-pixel includes a red sub-pixel R, and the third sub-pixel includes a green sub-pixel G.

[0048] Continuing with the above example, when the area of ​​the corresponding overlapping region Q of the first pixel circuit 131 connected to the first sub-pixel is smaller than the area of ​​the corresponding overlapping region Q of the second pixel circuit 132 connected to the second sub-pixel and the area of ​​the overlapping region Q corresponding to the third pixel circuit 133 connected to the third sub-pixel, the area of ​​the overlapping region Q corresponding to the second pixel circuit 132 connected to the second sub-pixel may be equal to the area of ​​the corresponding overlapping region Q of the third pixel circuit 133 connected to the third sub-pixel, or smaller than the area of ​​the overlapping region Q corresponding to the third pixel circuit 133 connected to the third sub-pixel, or larger than the area of ​​the overlapping region Q corresponding to the third pixel circuit 133 connected to the third sub-pixel.

[0049] In one embodiment, in combination Figure 3a and Figure 3b As shown, the overlapping region Q corresponding to the second pixel circuit 132 connected to the second sub-pixel and the overlapping region Q corresponding to the third pixel circuit 133 connected to the third sub-pixel are axially symmetrical. Exemplarily, the second sub-pixel and the third sub-pixel are adjacent.

[0050] In one embodiment, in combination Figure 3a and Figure 3b As shown, the pixel circuit further includes a third transistor T3 , a first electrode of the third transistor T3 and a second electrode of the first transistor T1 are connected via a conductive via H, and an orthographic projection of the conductive via H on the substrate 11 is located within the overlapping region Q.

[0051] Exemplarily, the display panel further includes a second scan signal line S2. A second electrode of the third transistor T3 is connected to a control electrode of the first transistor T1, and a control electrode of the third transistor T3 is connected to the second scan signal line S2.

[0052] Exemplarily, the third transistor T3 includes an indium gallium zinc oxide thin film transistor.

[0053] In one embodiment, in combination Figure 3a and Figure 3b As shown, in the extension direction of the first scan signal line S1, the orthographic projection of the first transistor T1 on the substrate 11 is located on one side of the first scan signal line S1. The orthographic projection of the conductive via H on the substrate 11 is located on the side of the overlap region Q away from the orthographic projection of the first transistor T1 on the substrate 11.

[0054] Exemplarily, the first scan signal line S1 extends along the first direction x. The orthographic projection of the first transistor T1 on the substrate 11 is located on one side of the first scan signal line S1 in the second direction y, and the second direction y is perpendicular to the first direction x. The overlapping region Q includes a first edge region and a second edge region that are arranged opposite to each other in the first direction x, and the distance between the first edge region and the first transistor T1 is smaller than the distance between the second edge region and the first transistor T1. The conductive via H is located in the second edge region.

[0055] In one embodiment, in combination Figure 3a and Figure 3b As shown, the display panel further includes a third scanning signal line S3 and a first initialization signal line Vref1. The pixel circuit 13 further includes a fourth transistor T4, a first electrode of the fourth transistor T4 is connected to the first initialization signal line Vref1, a second electrode of the fourth transistor T4 is connected to the first electrode of the third transistor T3, and a control electrode of the fourth transistor T4 is connected to the third scanning signal line S3. Exemplarily, the fourth transistor T4 includes an indium gallium zinc oxide thin film transistor.

[0056] In one embodiment, in combination Figure 3a and Figure 3b As shown, the display panel further includes a high-voltage power signal line Elvdd and a light-emitting control signal line Em. The pixel circuit 13 further includes a fifth transistor T5 and a sixth transistor T6. The control electrode of the fifth transistor T5 is connected to the light-emitting control signal line Em, the first electrode of the fifth transistor T5 is connected to the high-voltage power signal line Elvdd and the second electrode plate of the capacitor Cst, and the second electrode of the fifth transistor T5 is connected to the first electrode of the first transistor T1. The control electrode of the sixth transistor T6 is connected to the light-emitting control signal line Em, the first electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1, and the second electrode of the sixth transistor T6 is connected to the anode of the sub-pixel 12.

[0057] In one embodiment, in combination Figure 3a and Figure 3b As shown, the display panel further includes a second initialization signal line Vref2, a third initialization signal line Vref3 and a fourth scan signal line S4. The pixel circuit further includes a seventh transistor T7 and an eighth transistor T8. The control electrode of the seventh transistor T7 is connected to the fourth scan signal line S4, the first electrode of the seventh transistor T7 is connected to the second initialization signal line Vref2, and the second electrode of the seventh transistor T7 is connected to the second electrode of the sixth transistor T6. The control electrode of the eighth transistor T8 is connected to the fourth scan signal line S4, the first electrode of the eighth transistor T8 is connected to the third initialization signal line Vref3, and the second electrode of the eighth transistor T8 is connected to the first electrode of the sixth transistor T6.

[0058] Figure 4a-Figure 4i for Figure 2 The schematic diagram of the top view of a single film layer in the display panel is shown. Figure 2 and Figure 4a-Figure 4i As shown, the display panel includes a substrate 11, a plurality of functional layers located on one side of the substrate 11, and a sub-pixel 12 located on the side of the functional layer away from the substrate 11. The plurality of functional layers include a conductive layer, a semiconductor layer, and an insulating layer. An insulating layer is provided between adjacent conductive layers and between adjacent conductive layers and semiconductor layers. The plurality of functional film layers include a pixel circuit 13 and a plurality of signal lines. The sub-pixel 12 includes a stacked first pole An, a light-emitting layer EML, and a second pole Ca. Exemplarily, the first pole An is an anode and the second pole Ca is a cathode.

[0059] Specifically, see Figure 2 and Figure 4a The display panel includes a first semiconductor layer located on one side of the substrate 11. The material of the first semiconductor layer is p-si.

[0060] See also Figure 2 and Figure 4b The plurality of conductive layers include a first metal layer M1, which is located on the side of the first semiconductor layer away from the substrate 11. Figure 1 As shown in the circuit diagram, the gate of the first transistor T1, the first part third scanning signal line S3, the light emitting control signal line Em, the fourth scanning signal line S4, and the first part third initialization signal line Vref3 are all located in the first metal layer M1.

[0061] See also Figure 2 and Figure 4c The plurality of conductive layers further includes a second metal layer M2 located on a side of the first metal layer M1 away from the substrate 11. Figure 1As shown in the circuit diagram, the first scanning signal line S1, the first part of the second scanning signal line S2 and the second plate of the capacitor Cst are all located in the second metal layer M2. The second plate of the capacitor Cst overlaps with the gate of the first transistor T1 in the first metal layer M1, and the gate of the first transistor T1 serves as the first plate of the capacitor Cst.

[0062] See also Figure 2 and Figure 4d The display panel further includes a second semiconductor layer located on the side of the second metal layer M2 away from the substrate 11. The material of the second semiconductor layer may be indium gallium zinc oxide (IGZO). The second electrode of the first transistor T1 is located in the second semiconductor layer. In at least some of the pixel circuits 13, the area of ​​the second electrode of the first transistor T1 is different. For example, Figure 3a , Figure 3b and Figure 4d As shown, the display panel includes a first pixel circuit, a second pixel circuit, and a third pixel circuit. In the overlapping area Q, the area of ​​the second electrode of the first transistor T1 in the first pixel circuit is smaller than the area of ​​the second electrode of the first transistor T1 in the second pixel circuit. The area of ​​the second electrode of the first transistor T1 in the second pixel circuit is smaller than the area of ​​the second electrode of the first transistor T1 in the third pixel circuit.

[0063] See also Figure 2 and Figure 4e The multiple conductive layers further include a metal oxide layer, which is located on the side of the second semiconductor layer away from the substrate 11. The material of the metal oxide layer is, for example, nano-cesium tungsten oxide (GATO). Figure 1 As shown in the circuit diagram, the second portion second scanning signal line S2, the second portion third scanning signal line S3 and the first initialization signal line Vref1 are all located in the metal oxide layer.

[0064] The first part of the second scan signal line S2 in the second metal layer M2 and the second part of the second scan signal line S2 in the metal oxide layer constitute the second scan signal line S2. The first part of the third scan signal line S3 in the first metal layer M1 and the second part of the third scan signal line S3 in the metal oxide layer constitute the third scan signal line S3.

[0065] See also Figure 2 and Figure 4f The multiple conductive layers further include a third metal layer M3 located on the side of the metal oxide layer 23 away from the substrate 11. The first initialization signal line Vref1, the second initialization signal line Vref2 and the second part of the third initialization signal line Vref3 are all located in the third metal layer M3.

[0066] The first portion of the third initialization signal line Vref3 in the first metal layer M1 and the second portion of the third initialization signal line Vref3 in the third metal layer M3 constitute the third initialization signal line Vref3.

[0067] See also Figure 2 and Figure 4g The plurality of conductive layers further include a fourth metal layer M4, which is located on the side of the third metal layer M3 away from the substrate 11. The first portion of the high-voltage power signal line Elvdd is located on the fourth metal layer M4. At the same time, the fourth metal layer M4 may also be provided with a first portion of fan-out connection lines fiaa, which are connected to the data signal lines Data.

[0068] See also Figure 2 and Figure 4h The multiple conductive layers further include a fifth metal layer M5, which is located on the side of the fourth metal layer M4 away from the substrate 11. The second part of the high-voltage power signal line Elvdd, the second part of the fan-out connection line fiaa, and the data signal line Data are all located in the fifth metal layer M5.

[0069] The first part of the high-voltage power signal line Elvdd in the fourth metal layer M4 and the second part of the high-voltage power signal line Elvdd in the fifth metal layer M5 constitute the high-voltage power signal line Elvdd. The first part of the fan-out connection line fiaa in the fourth metal layer M4 and the second part of the fan-out connection line fiaa in the fifth metal layer M5 constitute the fan-out connection line fiaa.

[0070] See also Figure 2 and Figure 4i The plurality of conductive layers further include a shielding layer located between the first semiconductor layer and the substrate 11. The shielding layer is made of, for example, molybdenum. Exemplarily, the shielding layer is electrically connected to the high-voltage power signal line Elvdd.

[0071] Figure 5 This is a schematic diagram of the structure of a display device provided by an embodiment of the present application. Figure 5 As shown, the display device includes the display panel provided by any of the above embodiments.

[0072] The display device 500 is a product with an image display function. For example, the display device 500 can be used to display static images, such as pictures or photos. The display device 500 can also be used to display dynamic images, such as videos.

[0073] The display device 500 may be a laptop computer, a mobile phone, a handheld or portable computer, a camera, a camcorder, a vehicle-mounted smart central control screen, a calculator, a smart watch, a GPS navigator, an electronic photo, an electronic billboard or sign, a projector, etc.

[0074] In addition, the display device 500 may also have functions such as taking pictures, recording videos, fingerprint recognition, face recognition, etc. Accordingly, the display device 500 also includes at least one functional module for realizing the above functions, such as an under-screen camera, an under-screen fingerprint recognition sensor, etc.

[0075] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0076] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A display panel, characterized in that: include: substrate; and A plurality of functional layers located on one side of the substrate, the plurality of functional layers comprising a plurality of pixel circuits, a first scanning signal line and a data signal line; In which, the pixel circuit includes a first transistor, a second transistor and a capacitor; the control electrode of the first transistor is connected to the first electrode plate of the capacitor, the first electrode of the first transistor is connected to the second electrode of the second transistor, the first electrode of the second transistor is connected to the data signal line, and the control electrode of the second transistor is connected to the first scanning signal line; the orthographic projection of the second electrode of the first transistor on the substrate and the orthographic projection of the first scanning signal line on the substrate have an overlapping area, and the areas of the overlapping areas corresponding to at least part of the pixel circuits are not equal.

2. The display panel according to claim 1, characterized in that: It also includes a plurality of sub-pixels, which are located on a side of the pixel circuit away from the substrate, and the sub-pixels are electrically connected to the pixel circuit; the plurality of sub-pixels include a first sub-pixel and a second sub-pixel, and the plurality of pixel circuits include a first pixel circuit and a second pixel circuit; the area of ​​the overlapping region corresponding to the first pixel circuit connected to the first sub-pixel is smaller than the area of ​​the overlapping region corresponding to the second pixel circuit connected to the second sub-pixel; Preferably, the plurality of sub-pixels have different colors; Preferably, the first sub-pixel includes a blue sub-pixel, and the second sub-pixel includes any one of a red sub-pixel and a green sub-pixel.

3. The display panel according to claim 2, characterized in that: The plurality of sub-pixels further include a third sub-pixel, and the plurality of pixel circuits further include a third pixel circuit; an area of ​​the overlapping region corresponding to the first pixel circuit connected to the first sub-pixel is smaller than an area of ​​the overlapping region corresponding to the third pixel circuit connected to the third sub-pixel; Preferably, an area of ​​the overlapping region corresponding to the third pixel circuit connected to the third sub-pixel is equal to an area of ​​the overlapping region corresponding to the second pixel circuit connected to the second sub-pixel.

4. The display panel according to claim 3, characterized in that: The overlapping area corresponding to the second pixel circuit connected to the second sub-pixel and the overlapping area corresponding to the third pixel circuit connected to the third sub-pixel are axially symmetrical; Preferably, the second sub-pixel and the third sub-pixel are adjacent to each other.

5. The display panel according to claim 1, characterized in that: The plurality of functional layers include a second semiconductor layer, and the second electrode of the first transistor is located in the second semiconductor layer; in the overlapping region, the areas of the second electrodes of the first transistors in at least some of the pixel circuits are different; Preferably, the material of the second semiconductor layer includes indium gallium zinc oxide; Preferably, the plurality of functional layers further include a second metal layer located on a side of the second semiconductor layer close to the substrate, and at least part of the first scanning signal lines are located in the second metal layer.

6. The display panel according to claim 1, characterized in that: The pixel circuit further includes a third transistor, a first electrode of the third transistor and a second electrode of the first transistor are connected via a conductive via, and an orthographic projection of the conductive via on the substrate is located within the overlapping region; Preferably, the plurality of functional layers further include a second scanning signal line located on one side of the substrate; the second electrode of the third transistor is connected to the control electrode of the first transistor, and the control electrode of the third transistor is connected to the second scanning signal line; Preferably, the third transistor comprises an indium gallium zinc oxide thin film transistor.

7. The display panel according to claim 6, characterized in that: The orthographic projection of the first transistor on the substrate is located on one side of the first scanning signal line; in the extension direction of the first scanning signal line, the orthographic projection of the conductive via on the substrate is located on the side of the overlapping area away from the orthographic projection of the first transistor on the substrate.

8. The display panel according to claim 6, characterized in that: The plurality of functional layers further include a third scanning signal line and a first initialization signal line, which are located on one side of the substrate; the pixel circuit further includes a fourth transistor, a first electrode of the fourth transistor is connected to the first initialization signal line, a second electrode of the fourth transistor is connected to the first electrode of the third transistor, and a control electrode of the fourth transistor is connected to the third scanning signal line; Preferably, the fourth transistor comprises an indium gallium zinc oxide thin film transistor.

9. The display panel according to claim 1, characterized in that: The plurality of functional layers further include a high-voltage power signal line and a light-emitting control signal line; the pixel circuit further includes a fifth transistor and a sixth transistor, the control electrode of the fifth transistor being connected to the light-emitting control signal line, the first electrode of the fifth transistor being connected to the high-voltage power signal line and the second electrode plate of the capacitor, and the second electrode of the fifth transistor being connected to the first electrode of the first transistor; the control electrode of the sixth transistor being connected to the light-emitting control signal line, the first electrode of the sixth transistor being connected to the second electrode of the first transistor, and the second electrode of the sixth transistor being connected to the anode of the sub-pixel; Preferably, the multiple functional layers also include a second initialization signal line, a third initialization signal line and a fourth scanning signal line; the pixel circuit also includes a seventh transistor and an eighth transistor, the control electrode of the seventh transistor is connected to the fourth scanning signal line, the first electrode of the seventh transistor is connected to the second initialization signal line, and the second electrode of the seventh transistor is connected to the second electrode of the sixth transistor; the control electrode of the eighth transistor is connected to the fourth scanning signal line, the first electrode of the eighth transistor is connected to the third initialization signal line, and the second electrode of the eighth transistor is connected to the first electrode of the sixth transistor.

10. A display device, characterized in that: A display panel comprising any one of claims 1-9.

Images