Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device. The array substrate comprises: a substrate (1); a plurality of gate line groups (2); a plurality of data lines (3); a plurality of transistors (T); a first pixel electrode (41) and a second pixel electrode (42) located in a region formed by crossing the gate line group (2) and the data line (3); the orthographic projection of at least one of the plurality of common wires (5) on the substrate (1) is located between the orthographic projections of the adjacent grid line groups (2) on the substrate (1); the orthographic projection of at least one connecting line (6) in the plurality of connecting lines (6) on the substrate (1) is located in the orthographic projection of a gap between adjacent pixel electrode rows (400) on the substrate (1); and the insulating layer is positioned between the connecting line (6) and the common wire (5) and is provided with a plurality of first via holes (K1), and the orthographic projection of the first via holes (K1) on the substrate (1) is positioned on the orthographic projection of an area between two pixel edge extension lines (w1 and w2) of the pixel electrode (4) extending along the second direction (Y) on the substrate (1).

Description

Array substrate, display panel, and display device Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] Thin Film Transistor-Liquid Crystal Display (TFT-LCD) has a variety of commonly used display modes, such as twisted nematic (TN), vertically aligned (VA), fringe field switching (FFS), and in-plane switching (IPS). VA offers better dark state performance and contrast compared to other display modes.

[0003] Summary of the Invention

[0004] The present disclosure provides an array substrate, a display panel, and a display device. The array substrate includes:

[0005] substrate;

[0006] A plurality of gate line groups are located on one side of the substrate and extend along a first direction, wherein at least one gate line group among the plurality of gate line groups includes: two gate lines extending along the first direction;

[0007] a plurality of data lines extending along a second direction;

[0008] multiple transistors;

[0009] a plurality of pixel electrodes, the plurality of pixel electrodes comprising: a plurality of pixel electrode rows extending along the first direction and arranged along the second direction; at least one pixel electrode row of the plurality of pixel electrode rows comprising: a first pixel electrode and a second pixel electrode located in a region formed by the intersection of the gate line group and the data line and connected to the data line through the plurality of transistors, the second pixel electrode being located on a side of the first pixel electrode away from the connected data line;

[0010] A plurality of common lines are located on the same side of the substrate as the gate line groups, and an orthographic projection of at least one of the plurality of common lines on the substrate is located between orthographic projections of adjacent gate line groups on the substrate;

[0011] a plurality of connecting lines located on the same side of the substrate as the gate line group, wherein an orthographic projection of at least one connecting line among the plurality of connecting lines is within a gap between adjacent pixel electrode rows and within the orthographic projection of the substrate;

[0012] An insulating layer is located between the connecting line and the common routing line, and has a plurality of first via holes. The common routing line is connected to the connecting line at the first via holes so as to electrically connect at least a portion of the common routing line through the connecting line. The orthographic projection of the first via holes on the substrate is located in an area between two pixel edge extension lines of the pixel electrode extending along the second direction on the orthographic projection of the substrate.

[0013] In a possible implementation manner, the pixel electrode has a first symmetry axis extending along the second direction and passing through a central area of ​​the pixel electrode, and the first symmetry axis passes through a central area of ​​the first via hole.

[0014] In a possible implementation manner, the orthographic projection of the first via hole on the substrate is within the gap between adjacent pixel electrode rows.

[0015] In a possible implementation manner, the first via hole includes: a first sub-via hole and a second sub-via hole; the connecting line includes: a first sub-connecting line and a second sub-connecting line extending along the first direction;

[0016] The first sub-connecting line is electrically connected to the common line on one side of the gate line group through the first sub-via;

[0017] The second sub-connecting line is electrically connected to the common line on the other side of the gate line group through the second sub-via.

[0018] In one possible embodiment, the first sub-connecting line has a first protruding portion protruding toward a side of the pixel electrode, and the common line has a second protruding portion protruding toward a side of the gate line group. An orthographic projection of the first protruding portion on the substrate and an orthographic projection of the second protruding portion on the substrate have a first overlapping area, and the first sub-via is electrically connected in the first overlapping area.

[0019] The second sub-connecting line has a third protruding portion protruding toward the side of the pixel electrode, and the common line has a fourth protruding portion protruding toward the side of the gate line group. The orthographic projection of the third protruding portion on the substrate and the orthographic projection of the fourth protruding portion on the substrate have a second overlapping area, and are connected through the second sub-via in the second overlapping area.

[0020] In a possible implementation, the pixel electrode has a first concave portion at a position opposite to the first convex portion, and a gap exists between the first concave portion and the orthographic projection of the substrate; the gate line has a second concave portion at a position opposite to the second convex portion, and a gap exists between the second concave portion and the orthographic projection of the substrate;

[0021] The pixel electrode has a third concave portion at a position opposite to the third convex portion, and a gap exists between the third concave portion and the orthographic projection of the third convex portion on the substrate; the gate line has a fourth concave portion at a position opposite to the fourth convex portion, and a gap exists between the fourth concave portion and the orthographic projection of the fourth convex portion on the substrate.

[0022] In a possible implementation, the connecting line includes: a plurality of connecting rings sequentially distributed along the first direction, and a series connection portion connecting adjacent connecting rings; the connecting ring includes the first sub-connecting line and the second sub-connecting line.

[0023] In a possible implementation manner, the first sub-via and the second sub-via are located in different connection rings.

[0024] In a possible implementation manner, the first sub-via and the second sub-via are located in the same connecting ring.

[0025] In a possible implementation, the first pixel electrode has a first outer edge extending along the second direction away from a side of the second pixel electrode, and the second pixel electrode has a second outer edge extending along the second direction away from a side of the first pixel electrode;

[0026] The orthographic projection of the connecting ring on the substrate and a region between an extension line of the first outer edge and an extension line of the second outer edge are within the orthographic projection of the substrate.

[0027] In a possible implementation manner, the length of the connecting ring in the first direction is 1 to 2 times the length of the pixel electrode in the first direction;

[0028] The minimum line width of the first sub-connecting line is smaller than the maximum width of the gate line in the second direction; the minimum line width of the second sub-connecting line is smaller than the maximum width of the gate line in the second direction; the line width of the series portion is smaller than the maximum width of the gate line in the second direction.

[0029] In a possible implementation, an orthographic projection of an outer edge of the connecting ring along the first direction on the substrate overlaps with an orthographic projection of an outer edge of the gate line toward the pixel electrode on the substrate.

[0030] In a possible implementation manner, the connecting line and the pixel electrode are made of the same layer and material.

[0031] In a possible implementation, at least one transistor among the plurality of transistors includes: a gate electrically connected to the gate line, a first electrode electrically connected to the data line, and a second electrode electrically connected to the pixel electrode;

[0032] The second electrode of the transistor connected to the first pixel electrode and the second electrode of the transistor connected to the second pixel electrode are symmetrical with respect to the data line.

[0033] In a possible implementation, the second pole includes: a first portion and a second portion extending along the second direction and having extension lines that do not overlap, and a third portion extending along the first direction and connecting the first portion and the second portion;

[0034] A length of the third portion of the transistor connected to the first pixel electrode is substantially equal to a length of the third portion of the transistor connected to the second pixel electrode.

[0035] In a possible implementation manner, the orthographic projection of the first extension line of the transistor connected to the first pixel electrode on the substrate is located within the orthographic projection of the substrate within a gap between adjacent pixel electrodes.

[0036] In a possible implementation manner, an orthographic projection of the second portion on the substrate and an orthographic projection of the pixel electrode on the substrate have an overlapping area.

[0037] In a possible implementation, the second pole includes: a fourth portion extending along the second direction, and a fifth portion extending along the first direction and connected to one end of the fourth portion;

[0038] The orthographic projection of the fourth portion on the substrate has an overlapping area with the orthographic projection of the gap between adjacent pixel electrodes on the substrate.

[0039] In a possible implementation, the array substrate includes: a first common signal line located between adjacent gate line groups and extending along the first direction, and a first common signal extension line connected to one side of the first common signal line and extending along the second direction;

[0040] At least a portion of the first common signal extension line serves as the common line.

[0041] In one possible embodiment, the array substrate includes: a second common signal line group located between adjacent gate line groups and extending along the second direction, the second common signal line group including two second common signal lines located on different sides of the data line; the second common signal line including: a second common signal line main portion extending along the second direction, and a second common signal line branch portion extending from one end of the second common signal line main portion along the first direction;

[0042] At least a portion of the second common signal line serves as the common routing line, and the second common signal line is electrically connected to the connecting line through the second common signal line branch.

[0043] In a possible embodiment, the array substrate includes: a third common signal line located between adjacent gate line groups and extending along the second direction, the orthographic projection of the third common signal line on the substrate being located between the orthographic projection of the first pixel electrode on the substrate and the orthographic projection of the second pixel electrode on the substrate.

[0044] In a possible implementation manner, the common wiring and the gate lines are made of the same layer and material.

[0045] Based on the same inventive concept, an embodiment of the present disclosure also provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure, and also includes an opposing substrate arranged opposite to the array substrate, and the opposing substrate is provided with a common electrode layer on the side facing the array substrate.

[0046] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 is a schematic diagram showing the principle of the generation of head shake lines;

[0048] Figure 2 is a second schematic diagram of the principle of head shake pattern generation;

[0049] FIG3 is a schematic diagram of a head shake pattern;

[0050] FIG4A is a schematic diagram of an array substrate according to an embodiment of the present disclosure; ...

[0051] FIG4B is a schematic diagram of a single film layer where the gate lines are located in FIG4A;

[0052] FIG4C is a schematic diagram of a single film layer in FIG4A where the active layer is located;

[0053] FIG4D is a schematic diagram of a single film layer where the data line is located in FIG4A;

[0054] FIG4E is a schematic diagram of the first via hole in FIG4A ;

[0055] FIG4F is a schematic diagram of a single film layer where the pixel electrode is located in FIG4A ;

[0056] FIG5A is a second schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0057] FIG5B is a schematic diagram of a single film layer where the gate lines are located in FIG5A;

[0058] FIG5C is a schematic diagram of a single film layer in FIG5A where the active layer is located;

[0059] FIG5D is a schematic diagram of a single film layer where the data line is located in FIG5A;

[0060] FIG5E is a schematic diagram of the first via hole in FIG5A ;

[0061] FIG5F is a schematic diagram of a single film layer where the pixel electrode is located in FIG5A ;

[0062] FIG6A is a third schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0063] FIG6B is a schematic diagram of a single film layer where the gate lines are located in FIG6A;

[0064] FIG6C is a schematic diagram of a single film layer in the layer where the active layer is located in FIG6A;

[0065] FIG6D is a schematic diagram of a single film layer where the data line is located in FIG6A;

[0066] FIG6E is a schematic diagram of the first via hole in FIG6A ;

[0067] FIG6F is a schematic diagram of a single film layer where the pixel electrode is located in FIG6A ;

[0068] FIG7A is a fourth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0069] FIG7B is a schematic diagram of a single film layer where the gate lines are located in FIG7A;

[0070] FIG7C is a schematic diagram of a single film layer where the active layer is located in FIG7A;

[0071] FIG7D is a schematic diagram of a single film layer where the data line is located in FIG7A;

[0072] FIG7E is a schematic diagram of the first via hole in FIG7A ;

[0073] FIG7F is a schematic diagram of a single film layer where the pixel electrode is located in FIG7A ;

[0074] FIG8A is a schematic cross-sectional view corresponding to FIG7A along dotted line AA′;

[0075] FIG8B is a schematic cross-sectional view corresponding to the dashed line BB′ in FIG7A ;

[0076] FIG8C is a schematic cross-sectional view corresponding to the dashed line CC′ in FIG7A ;

[0077] FIG8D is a schematic cross-sectional view along dotted line DD′ in FIG7A ;

[0078] FIG9A is a fifth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0079] FIG9B is a schematic diagram of a single film layer where the gate lines are located in FIG7A;

[0080] FIG10 is an equivalent schematic diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0081] FIG11 is a schematic diagram of liquid crystal orientation in different regions provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0082] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0083] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0084] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0085] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0086] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0087] Dual gate design poses significant challenges to panel design and processing, primarily: 1. The reduced number of dates and increased number of gate lines make charging the panel more difficult; 2. The smaller the pixel area, the smaller the pixel's storage capacitance Ccs, while the pixel's parasitic capacitance remains almost unchanged, making it susceptible to parasitic capacitance (for example, coupling capacitance Cgs (the capacitance between the gate and the pixel, where the pixel can be understood as the pixel electrode and other structures electrically connected to the pixel electrode)), resulting in moving head noise defects; and for VA products, the storage capacitance is further reduced compared to Advanced Super Dimension Switch (ADS) products, making VA dual gate products even more susceptible to parasitic capacitance, resulting in moving head noise and other defects.

[0088] Specifically, in a dual-gate design, as shown in Figure 1, the signal applied to a long pixel has opposite polarity to the signal applied to its neighboring data lines (e.g., the first long pixel from left to right and the leftmost data line in Figure 1). When the data line (Data) signal coupled to the common electrode (COM) signal fluctuates, the long pixel appears brighter. The signal applied to a short pixel has the same polarity as the signal applied to its neighboring data lines (e.g., the first short pixel from left to right and the second data line from left to right in Figure 1). When the data line (Data) signal coupled to the common electrode (COM) signal fluctuates, the short pixel appears darker. Since half of the colors in space have the same polarity, averaging is not possible, requiring temporal averaging. However, when the head moves, several frames may be lost, further degrading the spatial averaging effect, as shown in Figure 2. When the head moves from side to side, rolling vertical streaks, known as head shakes, can be seen in the image, as shown in Figure 3.

[0089] In view of this, the present disclosure provides an array substrate, as shown in Figures 4A-4F, 5A-5F, 6A-6F, 7A-7F, and 8A-8C, wherein Figure 4A is one of the schematic diagrams of the array substrate provided in the present disclosure, Figure 4B is a schematic diagram of a single film layer in the layer where the gate line is located in Figure 4A, Figure 4C is a schematic diagram of a single film layer in the layer where the active layer is located in Figure 4A, Figure 4D is a schematic diagram of a single film layer in the layer where the data line is located in Figure 4A, and Figure 4E is a schematic diagram of the layer where the data line is located in Figure 4A. FIG4F is a schematic diagram of a single film layer where the pixel electrode in FIG4A is located, FIG5A is a second schematic diagram of an array substrate provided in an embodiment of the present disclosure, FIG5B is a schematic diagram of a single film layer where the gate line in FIG5A is located, FIG5C is a schematic diagram of a single film layer where the active layer in FIG5A is located, FIG5D is a schematic diagram of a single film layer where the data line in FIG5A is located, FIG5E is a schematic diagram of the first via hole in FIG5A, FIG5F is a schematic diagram of a single film layer where the pixel electrode in FIG5A is located, and FIG6A is a schematic diagram of the present disclosure. FIG6B is a schematic diagram of a single film layer in a layer where the gate line is located in FIG6A , FIG6C is a schematic diagram of a single film layer in a layer where the active layer is located in FIG6A , FIG6D is a schematic diagram of a single film layer in a layer where the data line is located in FIG6A , FIG6E is a schematic diagram of a first via hole in FIG6A , FIG6F is a schematic diagram of a single film layer in a layer where the pixel electrode is located in FIG6A , FIG7A is one of the schematic diagrams of an array substrate provided in an embodiment of the present disclosure, FIG7B is a schematic diagram of a single film layer in a layer where the gate line is located in FIG7A , FIG7C is a schematic diagram of a single film layer in a layer where the active layer is located in FIG7A , FIG7D is a schematic diagram of a single film layer in a layer where the data line is located in FIG7A , FIG7E is a schematic diagram of a first via hole in FIG7A , FIG7F is a schematic diagram of a single film layer in a layer where the pixel electrode is located in FIG7A , FIG8A is a schematic cross-sectional view corresponding to the dotted line AA' in FIG7A , FIG8B is a schematic cross-sectional view corresponding to the dotted line BB' in FIG7A , and FIG8C is a schematic cross-sectional view corresponding to the dotted line CC' in FIG7A . The array substrate includes:

[0090] Substrate 1;

[0091] A plurality of gate line groups 2 are located on one side of the substrate 1 and extend along a first direction X. At least one gate line group 2 among the plurality of gate line groups 2 includes: two gate lines 20 extending along the first direction X; specifically, the two gate lines 20 of the gate line group 2 can be a first gate line 21 and a second gate line 22;

[0092] A plurality of data lines 3 extending along a second direction Y;

[0093] A plurality of transistors T; the plurality of transistors T may include: a plurality of first transistors T1, and a plurality of second transistors T2;

[0094] A plurality of pixel electrodes 4, the plurality of pixel electrodes 4 including: a plurality of pixel electrode rows 400 extending along a first direction X and arranged along a second direction Y; at least one of the plurality of pixel electrode rows 400 including: a first pixel electrode 41 and a second pixel electrode 42 located in an area formed by the intersection of the gate line group 2 and the data line 3 and connected to the data line 3 through a plurality of transistors T, the second pixel electrode 42 being located on a side of the first pixel electrode 41 away from the connected data line 3; specifically, the first pixel electrode 41 and the second pixel electrode 42 may be connected to the same data line 3 through different transistors T, specifically, the first pixel electrode 41 is electrically connected to the data line 3 through the first transistor T1, and the second pixel electrode 42 is electrically connected to the data line 3 through the second transistor T2; the first pixel electrode 41 and the second pixel electrode 42 located in the same intersection area may serve as a pixel electrode group 40;

[0095] A plurality of common routing lines 5, wherein an orthographic projection of at least one of the plurality of common routing lines 5 on the substrate 1 is located between orthographic projections of adjacent gate line groups 2 on the substrate 1; that is, the plurality of common routing lines 5 may be located on different sides of the gate line group 2, and the common routing lines 5 on different sides of the gate line group 2 are disconnected at the location of the gate line group 2; for example, as shown in FIG4B , the plurality of common routing lines 5 include: a first common signal extension line 511 located on the upper side of the gate line group 2, and another first common signal extension line 511 located on the lower side of the gate line group 2, and the two first common signal extension lines 511 are disconnected at the gate line group 2;

[0096] A plurality of connecting lines 6 are located on the same side of the substrate 1 as the gate line group 2 , and an orthographic projection of at least one connecting line 6 on the substrate 1 and a gap between adjacent pixel electrode rows 400 are within the orthographic projection of the substrate 1 ;

[0097] The insulating layer is located between the connecting line 6 and the common routing line 5 and has a plurality of first via holes K. The common routing line 5 is connected to the connecting line 6 at the first via hole K so as to electrically connect at least a portion of the common routing line 5 through the connecting line 6. The orthographic projection of the first via hole K on the substrate 1 is the orthographic projection of the area between the two pixel edge extension lines of the pixel electrode 4 extending along the second direction Y on the substrate 1. As shown in FIG4A , the pixel electrode 4 has a first edge extension line w1 extending along the second direction Y, and a second edge extension line w2. The orthographic projection of the first via hole K on the substrate 1 is the orthographic projection of the area between the first edge extension line w1 and the second edge extension line w2 on the substrate 1.

[0098] In this common embodiment, the first via K1 that connects the common wiring 5 and the connecting line is located in the positive projection of the area between the two pixel edge extension lines extending along the second direction Y of the pixel electrode 4 on the substrate 1, that is, it is not located in the area corresponding to the vertical gap between adjacent pixel electrodes 4, thereby providing more arrangement space for the first transistor T1 connected to the first pixel electrode 41 and the second transistor T2 connected to the second pixel electrode 42, so that the coupling capacitance formed by the gate line 20 and the first pixel electrode 41 and the connected structure is roughly equal to the coupling capacitance formed by the gate line 20 and the second pixel electrode 42 and the connected structure, thereby improving the problem of bad shaking head ripples in the dual-gate structure display panel; moreover, the connecting line 6 is located in the gap between adjacent pixel electrode rows 400, which can shield the capacitance between the gate line 20 and the second electrode Tb, thereby improving the different effects of process fluctuations on the coupling capacitances of different pixels, thereby causing the shaking head ripple problem.

[0099] Specifically, as shown in Figure 5D, at least one transistor T among the multiple transistors T includes: a gate electrically connected to the gate line 20 (not shown in the figure, the gate line 20 can serve as a gate), a first electrode Ta electrically connected to the data line 3, a second electrode Tb electrically connected to the pixel electrode 4, and a connecting portion Tc connected to one end of the second electrode Tb; the connecting portion Tc is electrically connected to the pixel electrode 4 through a second via Q; the coupling capacitance formed by the gate line 20 and the first pixel electrode 41 and the connected structure may include: the capacitance between the gate line 20 and the first pixel electrode 41, and the capacitance between the gate line 20 and the second electrode 32 of the first transistor T1; the coupling capacitance formed by the gate line 20 and the second pixel electrode 42 and the connected structure may include: the capacitance between the gate line 20 and the second pixel electrode 42, and the capacitance between the gate line 20 and the second electrode 32 of the second transistor T2.

[0100] Specifically, as shown in Figures 4A and 4C, the transistor T may further include an active layer 7. The coupling capacitance formed between the gate line 20 and the first pixel electrode 41 and the connected structure may further include: a capacitance between the gate line 20 and the active layer 7 of the first transistor T1; the coupling capacitance formed between the gate line 20 and the second pixel electrode 42 and the connected structure may further include: a capacitance between the active layer 7 of the second transistor T2 connected to the second pixel electrode 42. Specifically, the capacitance generated between the gate line 20 and the active layer 7 may exist only during the period when the transistor T is turned on. During the period when the transistor T is turned off, it can be considered that the capacitance generated between the gate line 20 and the active layer 7 does not exist and does not affect the coupling capacitance. For example, when the first transistor T1 is turned on, the active layer 7 of the first transistor T1 is electrically connected to the second electrode Tb, and the second electrode Tb is electrically connected to the first pixel electrode 41. At this time, the coupling capacitance formed by the gate line 20 and the first pixel electrode 41 and the connected structure includes: the capacitance between the gate line 20 and the first pixel electrode 41, the capacitance between the gate line 20 and the second electrode Tb of the first transistor T1, and the capacitance formed between the gate line 20 and the active layer 7 of the first transistor T1; when the second transistor T2 is turned on, the active layer 7 is electrically connected to the second electrode Tb of the second transistor T2, and the second electrode Tb is electrically connected to the second pixel electrode 42. At this time, the coupling capacitance formed by the gate line 20 and the second pixel electrode 42 and the connected structure includes: the capacitance between the gate line 20 and the second type of pixel electrode 42, the capacitance between the gate line 20 and the second electrode 32 of the second transistor T2, and the capacitance between the gate line 20 and the active layer 7 of the second transistor T2.

[0101] It should be noted that, in the actual manufacturing process, it may be difficult to make the coupling capacitance formed between the gate line 20 and the first pixel electrode 41 and the connected structure completely equal to the coupling capacitance formed between the gate line 20 and the second pixel electrode 42 and the connected structure. Therefore, in the embodiment of the present disclosure, the difference between the two can be within the range of 0F to 0.0001F, that is, the two are considered to be roughly equal. Specifically, for example, the difference between the two is within the range of 0F to 0.00007F; specifically, for example, the difference between the two is 0; specifically, for example, the difference between the two is 0.00007F; specifically, for example, the difference between the two is 0.000061F; specifically, the difference between the two is 0.000036F. Specifically, for the coupling capacitance in the embodiment of the present disclosure, before manufacturing the array substrate, it can be obtained through software simulation.

[0102] Specifically, the material of the active layer 5 may be indium gallium zinc oxide (IGZO). The active layer 5 may also be made of amorphous silicon, low-temperature polysilicon, etc., which is not limited here.

[0103] In a possible embodiment, referring to Figures 4A to 4F and Figures 5A to 5F, the array substrate includes: a first common signal line 51 located between adjacent gate line groups 2 and extending along the first direction X, and a first common signal extension line 511 connected to one side of the first common signal line 51 and extending along the second direction Y; the orthographic projection of the first common signal line 51 on the substrate 1 passes through the center of the orthographic projection of the pixel electrode 4 on the substrate 1; at least a portion of the first common signal extension line 511 serves as a common routing line 5.

[0104] In one possible embodiment, as shown in Figures 9A and 9B, the array substrate may only include a first common signal extension line 511 for connecting to the connecting line 6; in another possible embodiment, as shown in Figures 5A and 5B, the array substrate may include, in addition to the first common signal extension line 511 for connecting to the connecting line 6, a first common signal extension line 511 not used for connecting to the connecting line 6. As shown in Figure 5B, in the corresponding second pixel electrode row, the two first common signal extension lines 511 on the left and right are used to connect to the connecting line 6, and the middle first common signal extension line 511 is not connected to the connecting line 6.

[0105] Specifically, referring to Figures 4A-4F, 5A-5F, 6A-6F, and 7A-7F, the extension lines of the two first common signal extension lines 511 located on different sides of the gate line group 2 and connected by the connecting line 6 may not overlap, that is, they may be staggered. For example, as shown in Figure 4A, the first common signal extension line 511 on the upper side of the gate line group 2 and the first common signal extension line 511 on the lower side of the gate line group 2 are not located in the same vertical direction, so as to avoid the second pole Tb of the transistor T.

[0106] In one possible embodiment, referring to Figures 5A-5F, 6A-6F, and 7A-7F, the array substrate further includes a common electrode portion 512 connected to the first common signal line 51; the orthographic projection of the common electrode portion 512 on the substrate 1 overlaps the orthographic projection of the connecting portion Tc on the substrate 1. Thus, a first storage capacitor is formed by the common electrode portion 512 and the connecting portion Tc.

[0107] In a possible embodiment, referring to Figures 5A-5F, 6A-6F, and 7A-7F, the orthographic projection shape of the common electrode portion 512 on the substrate 1 is similar to the orthographic projection shape of the connection portion Tc on the substrate 1; and the orthographic projection center of the common electrode portion 512 on the substrate 1 coincides with the orthographic projection center of the connection portion Tc on the substrate 1.

[0108] In a possible embodiment, referring to Figures 6A-6F, 7A-7F, and 8A-8C, the array substrate includes: a second common signal line group located between adjacent gate line groups 2 and extending along the second direction Y, the second common signal line group including two second common signal lines 52 located on different sides of the data line 3; at least one second common signal line 52 includes: a second common signal line main portion 521 extending along the second direction Y, and a second common signal line branch 522 extending from one end of the second common signal line main portion 521 along the first direction X; at least a portion of the second common signal line 52 serves as a common routing line, and the second common signal line 52 is electrically connected to the connecting line 6 through the second common signal line branch 522.

[0109] Specifically, referring to Figures 6A-6F, 7A-7F, and 8A-8C, the second common signal line branches 522 located on different sides of the gate line group 2 have the same extension direction. For example, as shown in Figure 6A, the second common signal line branch 522 on the upper side of the gate line group 2 extends to the right, and the second common signal line branch 522 on the lower side of the gate line group 2 also extends to the right. In this way, the two second common signal line branches 522 on different sides of the gate line group 2 are conveniently connected nearby.

[0110] Specifically, the second common signal line branches 522 located on different sides of the gate line group 2 have the same extension length in the first direction X. Specifically, the extension length of the second common signal line branches 522 located on different sides of the gate line group 2 in the first direction X is one quarter to three quarters of the extension length of the pixel electrode 4 in the first direction X. Specifically, the extension length of the second common signal line branches 522 located on different sides of the gate line group 2 in the first direction X is one half of the extension length of the pixel electrode 4 in the first direction X.

[0111] Specifically, the same second common signal line main portion 521 may be provided with second common signal line branches 522 at both ends of the extension direction, and the two second common signal line branches 522 connected to the same second common signal line main portion 521 both extend in the same side direction. As shown in FIG6A , the two second common signal line branches 522 connected to the same second common signal line main portion 521 both extend to the right side.

[0112] Specifically, the second common signal line branches 522 located on different sides of the gate line group 2 are all connected to the second common signal line main portion 521 on the same side of the data line 3. For example, as shown in 6A, the second common signal line branch 522 located on the upper side of the gate line group 2 is connected to the second common signal line main portion 521 on the right side of the data line 3; the second common signal line branch 522 located on the lower side of the gate line group 2 is also connected to the second common signal line main portion 521 on the right side of the data line 3.

[0113] In one possible implementation, referring to Figures 6A-6F, 7A-7F, and 8A-8C, the orthographic projection of the second common signal line 52 on the substrate 1 at least partially overlaps with the orthographic projection of the pixel electrode 4 on the substrate 1. In this way, a second storage capacitor is formed by the second common signal line 52 and the pixel electrode 4.

[0114] In a possible embodiment, referring to Figures 4A-4F, 5A-5F, 6A-6F, and 7A-7F, the array substrate includes: a third common signal line 53 located between adjacent gate line groups 2 and extending along the second direction Y, the orthographic projection of the third common signal line 53 on the substrate 1 is located between the orthographic projection of the first pixel electrode 41 on the substrate 1 and the orthographic projection of the second pixel electrode 42 on the substrate 1.

[0115] 4A and 4B , the orthographic projection of the third common signal line 53 on the substrate 1 partially overlaps with the orthographic projection of the pixel electrode 4 on the substrate 1. Thus, a third storage capacitor is formed by the third common signal line 53 and the pixel electrode 4.

[0116] In a possible implementation, referring to FIG. 4A-FIG . 4F , FIG. 5A-FIG . 5F , FIG. 6A-FIG . 6F , and FIG. 7A-FIG . 7F , the second common signal line 52 and the third common signal line 53 between adjacent gate line groups 2 are electrically connected to the first common signal line 51 .

[0117] Specifically, as shown in Figure 10, the first storage capacitor, the second storage capacitor and the third storage capacitor can form a storage capacitor Ccs, the drain of the transistor T (that is, the second electrode Tb) and the structure electrically connected to the drain (such as the pixel electrode 4, the active layer 7), and the gate line 20 can form a coupling capacitor Cgs, and Clc can be the capacitance generated by the liquid crystal between the array substrate and the opposite substrate.

[0118] In one possible embodiment, as shown in Figures 4A and 4D , the first common signal extension line 511 serves as the common routing line 5; the second electrode Tb of the transistor T connected to the first pixel electrode 41 and the second electrode Tb of the transistor T connected to the second pixel electrode 42 (i.e., the first transistor T1) are symmetrical about the data line 3 (optionally, the first pixel electrode 41 and the second pixel electrode 42 may not be connected to the same data line 3. In the row direction, the first pixel electrode 41 and the second pixel electrode 42 are alternately arranged, for example, the arrangement is the first pixel electrode 41, the second pixel electrode 42, the first pixel electrode 41, the second pixel electrode 42, etc., which are alternately arranged in sequence). Specifically, as shown in Figures 4A and 4D , the second electrode Tb of the transistor T connected to the first pixel electrode 41 (i.e., the second transistor T2) and the second electrode Tb of the transistor T connected to the second pixel electrode 42 have the same pattern shape and size. Specifically, for example, the second electrode Tb of the first transistor T1 and the second electrode Tb of the second transistor T2 both include: a first portion Tb1 and a second portion Tb2 extending along the second direction Y and whose extended lines do not overlap, and a third portion Tb3 extending along the first direction X and connecting the first portion Tb1 and the second portion Tb2; the first portion Tb1 of the first transistor T1 and the first portion Tb1 of the second transistor T2 have the same width in the first direction X and the same length in the second direction Y; the second portion Tb2 of the first transistor T1 and the second portion Tb2 of the second transistor T2 have the same width in the first direction X and the same length in the second direction Y; the third portion Tb3 of the first transistor T1 and the third portion Tb3 of the second transistor T2 have the same length in the first direction X and the same width in the second direction Y; specifically, the minimum distance between the third portion Tb3 of the first transistor T1 and the gate line 20 in the second direction Y is the same as the minimum distance between the third portion Tb3 of the second transistor T2 and the gate line 20 in the second direction Y.

[0119] In a possible implementation, as shown in FIG. 4A and FIG. 4D , a length c1 of the third portion Tb3 of the transistor T connected to the first pixel electrode 41 is substantially equal to a length c2 of the third portion Tb3 of the transistor T connected to the second pixel electrode 42 .

[0120] In one possible embodiment, in combination with Figures 4A and 4D and Figures 5A and 5D, the orthographic projection of the first portion of the Ta extension line of the transistor T connected to the first pixel electrode 41 (i.e., the first transistor T1) on the substrate 1 is located in the gap between adjacent pixel electrodes 4 and is within the orthographic projection of the substrate 1. That is, the first transistor T1 can be set at a position corresponding to the vertical gap between adjacent pixel electrodes 4, which is approximately the same as the setting position of the second transistor T2, and thus the third portion Tb3 of the first transistor T1 can be made substantially equal in length to the third portion Tb3 of the second transistor T2 in the first direction X. Specifically, the orthographic projection of the first portion of the Ta extension line of the transistor T connected to the second pixel electrode 42 (i.e., the second transistor T2) on the substrate 1 is located in the gap between adjacent pixel electrodes 4 and is within the orthographic projection of the substrate 1.

[0121] In one possible embodiment, referring to Figures 4A-4F, 5A-5F, 6A-6F, and 7A-7F, the orthographic projection of the second portion Tb2 on the substrate 1 has an overlapping area with the orthographic projection of the pixel electrode 4 on the substrate 1. Specifically, the second portion Tb2 extends along the second direction Y, and its orthographic projection on the substrate 1 passes through the center of the pixel electrode 4, so as to roughly overlap with the vertical dark line of the display panel in the middle of the pixel electrode 4. This avoids the situation where the vertical dark line in the middle is thicker overall when the two do not overlap, thereby affecting the aperture ratio of the display panel.

[0122] In one possible embodiment, as shown in Figures 6A-6F and 7A-7F, the second common signal line 52 serves as a common routing line; the second electrode Tb includes: a fourth portion Tb4 extending along the second direction Y, and a fifth portion Tb5 extending along the first direction X and connecting one end of the fourth portion Tb4; the orthographic projection of the fourth portion Tb4 on the substrate 1 overlaps with the orthographic projection of the gap between adjacent pixel electrodes 4 on the substrate 1. That is, the fourth portion Tb4 of the first transistor T1 and the fourth portion Tb4 of the second transistor T2 are both arranged at the vertical gap position between adjacent pixel electrodes 4 (that is, the third portion Tb3 similar to that in Figure 4A, which is closer to the gate line 20 and extends along the first direction X, is not provided, thereby reducing or eliminating the capacitance between the gate line 20 and the third portion Tb3), thereby improving the problem of head shaking lines in dual-gate structure display panels.

[0123] Specifically, referring to Figures 6A-6F and 7A-7F, the fourth portion Tb4 of the first transistor T1 and the fourth portion Tb4 of the second transistor T2 may both be located in the vertical gap between the first pixel electrode 41 and the second pixel electrode 42. The fifth portion Tb5 of the first transistor T1 may extend from the end of the fourth portion Tb4 toward a side closer to the data line 3 connected to the first transistor T1; and the fifth portion Tb5 of the second transistor T2 may extend from the end of the fourth portion Tb4 toward a side farther from the data line 3 connected to the second transistor T2.

[0124] Specifically, referring to Figures 6A to 6F and Figures 7A to 7F, the fifth portion Tb5 of the first transistor T1 extends along the first direction X and passes through the central area of ​​the pixel electrode 4 in the orthographic projection of the substrate 1; the fifth portion Tb5 of the second transistor T1 extends along the first direction X and passes through the central area of ​​the pixel electrode 4 in the orthographic projection of the substrate 1.

[0125] Specifically, referring to Figures 6A to 6F and Figures 7A to 7F, the extension length of the fourth portion Tb4 in the second direction Y may be one quarter to three quarters, and specifically one half, of the length of the pixel electrode 4 in the second direction Y. Specifically, the extension length of the fifth portion Tb5 in the first direction X may be one quarter to three quarters, and specifically one half, of the length of the pixel electrode 4 in the first direction X.

[0126] Specifically, the extension length of the fourth portion Tb4 of the first transistor T1 in the second direction Y is substantially equal to the extension length of the fourth portion Tb4 of the first transistor T2 in the second direction Y. Specifically, the extension length of the fifth portion Tb5 of the first transistor T1 in the first direction X is substantially equal to the extension length of the fifth portion Tb5 of the second transistor T2 in the first direction X.

[0127] In one possible embodiment, as shown in FIG4A , the pixel electrode 4 has a first symmetry axis L extending along the second direction Y and passing through the central region of the pixel electrode 4 . The first symmetry axis L passes through the central region of the first via hole K. That is, the first via hole K is located in the region corresponding to the center of the pixel electrode 4 , providing more space for disposing the first transistor T1 connected to the first pixel electrode 41 and the second transistor T2 connected to the second pixel electrode 42 .

[0128] In one possible embodiment, referring to Figures 4A to 4F, 5A to 5F, 6A to 6F, and 7A to 7F, the orthographic projection of the first via hole K on the substrate 1 and the gap between adjacent pixel electrode rows 400 are within the orthographic projection of the substrate 1. This prevents the normal display of the display panel from being affected when the first via hole K1 is disposed in the area where the pixel electrode 4 is located.

[0129] In a possible embodiment, referring to Figures 4A to 4F, 5A to 5F, 6A to 6F, and 7A to 7F, the first via K includes: a first sub-via K1, and a second sub-via K2; the connecting line 6 includes: a first sub-connecting line 61 and a second sub-connecting line 62 extending along the first direction X. Specifically, as shown in Figures 4A and 4E, the extension line of the first sub-connecting line 61 and the extension line of the second sub-connecting line 62 may not overlap, and the two may not be located in the same extension direction, and are staggered in the first direction X. Specifically, the orthographic projection of the first sub-connecting line 61 on the substrate 1 may be the same as that of the second sub-connecting line 62. The orthographic projection of the first gate line 21 on the substrate 1 partially overlaps, the orthographic projection of the first sub-connection line 61 on the substrate 1 may not overlap with the orthographic projection of the second gate line 22 on the substrate 1, the orthographic projection of the second sub-connection line 62 on the substrate 1 may partially overlap with the orthographic projection of the second gate line 22 on the substrate 1, and the orthographic projection of the second sub-connection line 62 on the substrate 1 may not overlap with the orthographic projection of the first gate line 21 on the substrate 1; the first sub-connection line 61 is electrically connected to the common routing line 5 on one side of the gate line group 2 through the first sub-via K1; the second sub-connection line 62 is electrically connected to the common routing line 5 on the other side of the gate line group 2 through the second sub-via K2.

[0130] Specifically, referring to FIG8D , FIG8D is a schematic cross-sectional view taken along the dashed line DD' in FIG7A . The first via K may be a half-hanging hole. Specifically, the first via K partially exposes the common trace 5 and partially exposes the substrate 1. The connecting wire 6 partially contacts the common trace 5 and partially contacts the substrate 1 at the first via K. In the disclosed embodiment, the common trace 5 and the connecting wire 6 are conductively connected via the half-hanging hole, thereby forming a stepped structure within the first via K. This serves to drain the alignment liquid, preventing it from sticking, improving the uniformity of the alignment liquid on the array substrate, and avoiding the appearance of moiré patterns on the screen, thereby improving display quality.

[0131] Specifically, as shown in FIG. 8A to FIG. 8D , the insulating layer may include one or a combination of the following film layers:

[0132] a gate insulating layer 11;

[0133] passivation layer 12;

[0134] Flat layer 13.

[0135] Specifically, the planarization layer 13 may be an organic film layer. Optionally, the passivation layer 12 may be a PVX layer, for example, including a silicon nitride material layer.

[0136] In a possible embodiment, referring to Figures 4A to 4F, the first sub-connecting line 61 has a first protruding portion 64 protruding toward the side of the pixel electrode 4, the common routing line 5 has a second protruding portion 54 protruding toward the side of the gate line group 2, the orthographic projection of the first protruding portion 64 on the substrate 1 has a first overlapping area with the orthographic projection of the second protruding portion 54 on the substrate 1, and is connected through the first sub-via K1 in the first overlapping area; the second sub-connecting line 62 has a third protruding portion 65 protruding toward the side of the pixel electrode 4, the common routing line 5 has a fourth protruding portion 55 protruding toward the side of the gate line group 2, the orthographic projection of the third protruding portion 65 on the substrate 1 has a second overlapping area with the orthographic projection of the fourth protruding portion 55 on the substrate 1, and is connected through the second sub-via K2 in the second overlapping area.

[0137] Specifically, when the first common signal extension line 511 is used as the common routing line 5, the second protrusion 54 and the fourth protrusion 55 can be connected to the end of the first common signal extension line 511; when the second common signal line 52 is used as the common routing line, the second protrusion 54 and the fourth protrusion 55 can be connected to the end of the second common signal line branch 52.

[0138] In a possible embodiment, referring to Figures 4A to 4F, the pixel electrode 4 has a first recess 43 at a position opposite to the first convex portion 64, and the first recess 43 has a gap between the orthographic projection of the substrate 1 and the orthographic projection of the first convex portion 64 on the substrate 1; the gate line 20 has a second recess 23 at a position opposite to the second convex portion 54, and the second recess 23 has a gap between the orthographic projection of the substrate 1 and the orthographic projection of the second convex portion 54 on the substrate 1; the pixel electrode 4 has a third recess 44 at a position opposite to the third convex portion 65, and the third recess 44 has a gap between the orthographic projection of the substrate 1 and the orthographic projection of the third convex portion 65 on the substrate 1; the gate line 20 has a fourth recess 24 at a position opposite to the fourth convex portion 55, and the fourth recess 24 has a gap between the orthographic projection of the substrate 1 and the orthographic projection of the fourth convex portion 54 on the substrate.

[0139] In one possible embodiment, as shown in Figures 4A-4F, 5A-5F, 6A-6F, and 7A-7F, the connecting line 6 includes: a plurality of connecting rings sequentially distributed along a first direction, and a series portion 63 connecting adjacent connecting rings; the connecting rings include a first sub-connecting line 61 and a second sub-connecting line 62. In this way, the connecting rings can shield the capacitance between the gate line 20 and the second electrode Tb, thereby improving the different effects of process fluctuations on the coupling capacitance of different pixels, which in turn causes the shaking head problem.

[0140] In a possible embodiment, referring to FIG. 5A and FIG. 5F , the array substrate further includes: an inner-ring bump 60 located within the connecting ring. The inner-ring bump 60 can be used to identify a specific pixel position. For example, the inner-ring bump 60 is used to identify the position of a red pixel, or to identify the position of a green pixel, or to identify the position of a blue pixel.

[0141] In a possible implementation, referring to FIG. 4A to FIG. 4F and FIG. 5A to FIG. 5F , the first sub-via K1 and the second sub-via K2 are located in different connection rings.

[0142] In a possible implementation, referring to FIG. 6A to FIG. 6F and FIG. 7A to FIG. 7F , the first sub-via K1 and the second sub-via K2 are located in the same connecting ring.

[0143] In a possible embodiment, referring to Figures 4F and 5F, the first pixel electrode 41 has a first outer edge a1 extending along the second direction Y away from the side of the second pixel electrode 42, and the second pixel electrode 42 has a second outer edge a2 extending along the second direction Y away from the side of the first pixel electrode 41; the area between the extension line of the first outer edge a1 and the extension line of the second outer edge a2 of the orthographic projection of the connecting ring on the substrate 1 is within the orthographic projection of the substrate 1.

[0144] In a possible embodiment, referring to Figures 4A to 4F, the length b1 of the connecting ring in the first direction X is 1 to 2 times the length b2 of the pixel electrode 4 in the first direction X; the minimum line width b3 of the first sub-connecting line 61 is smaller than the maximum width b4 of the gate line 20 in the second direction Y; the minimum line width b5 of the second sub-connecting line 62 is smaller than the maximum width b4 of the gate line 20 in the second direction Y; and the line width b6 of the series portion 63 is smaller than the maximum width b4 of the gate line 20 in the second direction Y.

[0145] In one possible embodiment, referring to Figures 4A-4F, 5A-5F, 6A-6F, and 7A-7F, the orthographic projection of the outer edge a3 of the connecting ring along the first direction X on the substrate 1 overlaps with the orthographic projection of the outer edge a4 of the gate line 20 toward the pixel electrode 4 on the substrate 1. In this way, the capacitance between the gate line 20 and the second electrode Tb can be shielded by the connecting line 6, thereby alleviating the different effects of process fluctuations on the coupling capacitance of different pixels, which in turn cause the shaking head problem.

[0146] In a possible embodiment, the connection line 6 is made of the same layer and material as the pixel electrode 4. In this way, the connection line 6 is formed at the same time as the pixel electrode 4, thereby simplifying the manufacturing process of the display panel and reducing the manufacturing cost of the display panel.

[0147] In a possible embodiment, the common lines 5 are made of the same layer and material as the gate lines 20. Thus, the common lines 5 are formed simultaneously with the gate lines 20 to simplify the manufacturing process of the display panel and reduce the manufacturing cost of the display panel.

[0148] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes an array substrate as provided in the embodiment of the present disclosure, and also includes an opposite substrate arranged opposite to the array substrate, and the opposite substrate is provided with a common electrode layer on the side facing the array substrate.

[0149] In one possible embodiment, a liquid crystal layer may be provided between the array substrate and the counter substrate. The liquid crystal layer has multiple liquid crystal regions in the region where the pixel electrode 4 is located, and the liquid crystal layers in different liquid crystal regions have different orientations in the initial state. Specifically, referring to FIG11 , for example, the liquid crystal layer has four liquid crystal regions in the region where the pixel electrode 4 is located. The orthographic projections of the four liquid crystal regions on the substrate 1 may be respectively located in the first region and the second region on one side of the orthographic projection of the first common signal line 51 on the substrate 1, and in the third region and the fourth region on the other side of the orthographic projection of the first common signal line 51 on the substrate 1. Specifically, the array substrate may have a first alignment film layer 81, and the counter substrate may be provided with a second alignment film layer 82. The orientations of the first alignment film layer 81 and the second alignment film layer 82 in different regions may be as shown in FIG11 , and the orientation of the first alignment film layer 81 may be perpendicular to the orientation of the second alignment film layer 82.

[0150] Specifically, the initial state of the liquid crystal layers in different liquid crystal regions can be understood as the deflection state of the liquid crystal layers in different liquid crystal regions when no electric field is applied, that is, the state when no voltage is formed between the pixel electrode 4 and the common electrode.

[0151] Specifically, in conjunction with Figures 8A, 8B, and 8C, the opposing substrate may further include an opposing substrate 90, and a black matrix layer 91 and a color filter layer (not shown in the figure) located on one side of the opposing substrate 90. Optionally, in a direction perpendicular to the substrate, the black matrix layer covers the data line and the second common signal line extending along the second direction on both sides of the data line, and may cover the pixel electrode or at least partially cover the pixel electrode. As well as the common electrode layer on the side of the color filter layer away from the substrate, optionally, the common electrode layer of the opposing substrate and the common wiring provided on the array substrate transmit the same common signal. Optionally, the common wiring may also be a signal different from that of the common electrode layer of the opposing substrate.

[0152] In one possible embodiment, in order to reduce the number of masks, the data line 3 and the active layer 5 can be formed using a single mask process, that is, the side of the data line 3 facing the substrate 1 can also include an active layer (the material of the active layer can be amorphous silicon, low-temperature polysilicon, or metal oxide, etc.).

[0153] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0154] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0155] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: substrate; A plurality of gate line groups are located on one side of the substrate and extend along a first direction, wherein at least one gate line group of the plurality of gate line groups comprises: two gate lines extending along the first direction; A plurality of data lines extending along a second direction; Multiple transistors; A plurality of pixel electrodes, the plurality of pixel electrodes comprising: a plurality of pixel electrode rows extending along the first direction and arranged along the second direction; at least one pixel electrode row among the plurality of pixel electrode rows comprising: a first pixel electrode and a second pixel electrode located in a region formed by the intersection of the gate line group and the data line and connected to the data line through the plurality of transistors, the second pixel electrode being located on a side of the first pixel electrode away from the connected data line; A plurality of common routing lines are located on the same side of the substrate as the gate line group, and an orthographic projection of at least one of the plurality of common routing lines on the substrate is located between orthographic projections of adjacent gate line groups on the substrate; A plurality of connection lines are located on the same side of the substrate as the gate line group, and an orthographic projection of at least one connection line among the plurality of connection lines is located in a gap between adjacent pixel electrode rows within the orthographic projection of the substrate; The insulating layer is located between the connecting line and the common wiring, and has a plurality of first via holes. The common wiring is connected to the connecting line at the first via holes so as to electrically connect at least part of the common wiring through the connecting line, and the first via holes are located in the orthographic projection of the substrate and in the area between two pixel edge extension lines of the pixel electrode extending along the second direction.

2. The array substrate according to claim 1, wherein: The pixel electrode has a first symmetry axis extending along the second direction and passing through a central area of ​​the pixel electrode, and the first symmetry axis passes through a central area of ​​the first via hole.

3. The array substrate according to claim 1 or 2, wherein: The orthographic projection of the first via hole on the substrate is within the orthographic projection of the substrate and the gap between adjacent pixel electrode rows.

4. The array substrate according to any one of claims 1 to 3, wherein: The first via hole includes: a first sub-via hole and a second sub-via hole; the connection line includes: a first sub-connection line and a second sub-connection line extending along the first direction; The first sub-connecting line is electrically connected to the common wiring on one side of the gate line group through the first sub-via; The second sub-connecting line is electrically connected to the common wiring on the other side of the gate line group through the second sub-via.

5. The array substrate according to claim 4, wherein: The first sub-connection line has a first convex portion protruding toward one side of the pixel electrode, the common wiring has a second convex portion protruding toward one side of the gate line group, the orthographic projection of the first convex portion on the substrate and the orthographic projection of the second convex portion on the substrate have a first overlapping area, and are connected through the first sub-via in the first overlapping area; The second sub-connecting line has a third protruding portion protruding toward the side of the pixel electrode, and the common line has a fourth protruding portion protruding toward the side of the gate line group. The orthographic projection of the third protruding portion on the substrate has a second overlapping area with the orthographic projection of the fourth protruding portion on the substrate, and is conductively connected through the second sub-via in the second overlapping area.

6. The array substrate according to claim 4 or 5, wherein: The pixel electrode has a first concave portion at a position opposite to the first convex portion, and a gap exists between the first concave portion and the orthographic projection of the substrate; the gate line has a second concave portion at a position opposite to the second convex portion, and a gap exists between the second concave portion and the orthographic projection of the substrate and the orthographic projection of the substrate; The pixel electrode has a third concave portion at a position opposite to the third convex portion, and a gap exists between the third concave portion and the orthographic projection of the substrate; the gate line has a fourth concave portion at a position opposite to the fourth convex portion, and a gap exists between the orthographic projection of the substrate and the orthographic projection of the fourth convex portion. gap.

7. The array substrate according to any one of claims 4 to 6, wherein: The connecting line includes: a plurality of connecting rings sequentially distributed along the first direction, and a series connection portion connecting adjacent connecting rings; the connecting ring includes the first sub-connecting line and the second sub-connecting line.

8. The array substrate according to claim 7, wherein: The first sub-via and the second sub-via are located in different connecting rings.

9. The array substrate according to claim 7, wherein: The first sub-via and the second sub-via are located in the same connecting ring.

10. The array substrate according to any one of claims 7 to 9, wherein: The first pixel electrode has a first outer edge extending along the second direction away from a side of the second pixel electrode, and the second pixel electrode has a second outer edge extending along the second direction away from a side of the first pixel electrode; The orthographic projection of the connecting ring on the substrate and a region between an extension line of the first outer edge and an extension line of the second outer edge are within the orthographic projection of the substrate.

11. The array substrate according to any one of claims 7 to 10, wherein: The length of the connecting ring in the first direction is 1 to 2 times the length of the pixel electrode in the first direction; The minimum line width of the first sub-connection line is smaller than the maximum width of the gate line in the second direction; the minimum line width of the second sub-connection line is smaller than the maximum width of the gate line in the second direction; the line width of the series portion is smaller than the maximum width of the gate line in the second direction.

12. The array substrate according to any one of claims 7 to 11, wherein: The orthographic projection of the outer edge of the connecting ring along the first direction on the substrate overlaps with the orthographic projection of the outer edge of the gate line toward the pixel electrode on the substrate.

13. The array substrate according to any one of claims 1 to 12, wherein: The connecting line and the pixel electrode are formed in the same layer and made of the same material.

14. The array substrate according to any one of claims 1 to 13, wherein: At least one transistor among the plurality of transistors comprises: a gate electrode electrically connected to the gate line, a first electrode electrically connected to the data line, and a second electrode electrically connected to the pixel electrode; The second electrode of the transistor connected to the first pixel electrode is connected to the second pixel electrode The second electrode of the transistor connected to the first electrode is symmetrical with respect to the data line.

15. The array substrate according to claim 14, wherein: The second pole includes: a first portion and a second portion extending along the second direction and having extension lines that do not overlap, and a third portion extending along the first direction and connecting the first portion and the second portion; A length of the third portion of the transistor connected to the first pixel electrode is substantially equal to a length of the third portion of the transistor connected to the second pixel electrode.

16. The array substrate according to claim 15, wherein: The orthographic projection of the first extension line of the transistor connected to the first pixel electrode on the substrate is within the orthographic projection of the substrate in a gap between adjacent pixel electrodes.

17. The array substrate according to claim 15 or 16, wherein: The orthographic projection of the second portion on the substrate has an overlapping area with the orthographic projection of the pixel electrode on the substrate.

18. The array substrate according to claim 14, wherein: The second pole includes: a fourth portion extending along the second direction, and a fifth portion extending along the first direction and connected to one end of the fourth portion; The orthographic projection of the fourth portion on the substrate has an overlapping area with the orthographic projection of the gap between adjacent pixel electrodes on the substrate.

19. The array substrate according to any one of claims 1 to 18, wherein: The array substrate comprises: a first common signal line located between adjacent gate line groups and extending along the first direction, and a first common signal extension line connected to one side of the first common signal line and extending along the second direction; At least a portion of the first common signal extension line serves as the common routing line.

20. The array substrate according to any one of claims 1 to 18, wherein: The array substrate comprises: a second common signal line group located between adjacent gate line groups and extending along the second direction, the second common signal line group comprising two second common signal lines respectively located on different sides of the data line; the second common signal line comprises: a second common signal line main portion extending along the second direction, and a second common signal line branch portion extending from one end of the second common signal line main portion along the first direction; At least part of the second common signal line is used as the common line, and the second common signal line The second common signal line branch is electrically connected to the connection line.

21. The array substrate according to any one of claims 1 to 20, wherein: The array substrate includes: a third common signal line located between adjacent gate line groups and extending along the second direction, the orthographic projection of the third common signal line on the substrate is located between the orthographic projection of the first pixel electrode on the substrate and the orthographic projection of the second pixel electrode on the substrate.

22. The array substrate according to any one of claims 1 to 21, wherein: The common wiring and the gate line are made of the same layer and material.

23. A display panel, wherein: It comprises the array substrate as claimed in any one of claims 1 to 22, and further comprises an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate is provided with a common electrode layer on a side facing the array substrate.

24. A display device, wherein: Comprising the display panel as claimed in claim 23.

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