Clock definer enhancements for external double data rate memory interfaces

Abstract

A memory interface circuit has a first differential receiver having a first input coupled to a first reference voltage source; a second differential receiver configured to receive a differential data strobe signal in the complementary signal pair; a third differential receiver having a first input coupled to a second reference voltage source and a second input configured to receive one of the complementary signal pairs; a clock generation circuit configured to generate a read clock signal, the generated read clock signal defining one or more edges in the read clock signal based on an output of the second differential receiver and using a defining signal output by the third differential receiver; and a data capture circuit clocked by the read clock signal and configured to capture data from the output of the first differential receiver using one or more edges in the read clock signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to pending U.S. non-provisional application No. 17 / 954,852, filed on September 28, 2022, and assigned to the assignee of the present application, and is hereby expressly incorporated by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] The present disclosure relates generally to clock and data recovery circuits and, more particularly, to including and calibrating multiple reference voltage sources in memory interface circuits. Background Art

[0004] Over the past few years, electronic device technology has experienced explosive growth. For example, better communications, hardware, larger networks, and more reliable protocols have driven the development of cellular and wireless communication technologies. Wireless service providers are now able to offer their customers an ever-expanding range of features and services, and provide users with unprecedented levels of access to information, resources, and communications. In order to keep pace with these service enhancements, mobile electronic devices (e.g., cell phones, tablet computers, notebook computers, etc.) have become more powerful and complex than ever before. Wireless devices may include high-speed bus interfaces for signal communication between hardware components.

[0005] For example, when integrated circuit (IC) devices need to reduce power consumption and footprint, high-speed serial buses have advantages over parallel communication links. In a serial interface, a serializer is used to convert data from parallel words into a serial bit stream and a deserializer is used at the receiver to convert the data back into parallel words. For example, a high-speed bus interface can be implemented using a peripheral component interconnect express (PCIe) bus, a universal serial bus (USB), or a serial advanced technology attachment (SATA), etc.

[0006] An IC device may include a memory interface having a physical layer circuit configured to read and write a double data rate random access memory device. The growing demand for higher data rates requires strict timing between circuits within the memory interface. The performance, accuracy, or reliability of the memory interface may depend on a calibration and training process that can accommodate voltage drift and other changes that may affect the operation of the memory interface. Therefore, there is a continuing need for new technologies that provide reliable training and calibration techniques for components that receive clock signals over high-speed data links. Summary of the invention

[0007] Certain aspects of the present disclosure relate to systems, apparatus, methods, and techniques for implementing and calibrating a memory interface circuit that can be used with a clock signal having a frequency that varies over a wide frequency range.

[0008] In various aspects of the present disclosure, a memory interface circuit has: a first differential receiver having a first input coupled to a first reference voltage source; a second differential receiver configured to receive a differential data strobe signal in a complementary signal pair; a third differential receiver having a first input coupled to a second reference voltage source and a second input configured to receive one of the complementary signal pair; a clock generation circuit configured to generate a read clock signal based on an output of the second differential receiver and to define one or more edges in the read clock signal using a definition signal output by the third differential receiver; and a data capture circuit clocked by the read clock signal and configured to capture data from the output of the first differential receiver using one or more edges in the read clock signal. A differential receiver in which one of a pair of inputs is coupled to a reference voltage source may be referred to herein as a pseudo differential receiver.

[0009] In various aspects of the present disclosure, a method for communicating with a memory device includes: coupling a first input of a first differential receiver to a first reference voltage source; configuring a second differential receiver to receive a differential data selection signal in the complementary signal pair; coupling a first input of a third differential receiver to a second reference voltage source; configuring a second input of the third differential receiver to receive one of the complementary signal pair; configuring a clock generation circuit to generate a read clock signal based on an output of the second differential receiver and to define one or more edges in the read clock signal using a definition signal output by the third differential receiver; and configuring a data capture circuit to capture data from the output of the first differential receiver using one or more edges in the read clock signal.

[0010] In various aspects of the present disclosure, an apparatus includes: a device for receiving a data signal, the device for receiving the data signal including a first differential receiver having a first input coupled to a first reference voltage source; a device for receiving a differential data strobe signal in a complementary signal pair; a device for generating a qualification signal by comparing one of the complementary signal pair with an output of a second reference voltage source; a device for generating a read clock signal based on an output of the device for receiving the differential data strobe signal; and a device for capturing data, configured to capture data from the output of the first differential receiver using one or more edges in the read clock signal. The edges in the read clock signal may be qualified using the qualification signal.

[0011] In various aspects of the present disclosure, a processor-readable storage medium stores or maintains code for configuring a voltage level provided by a first reference voltage source to a first input of a first differential receiver; configuring a second differential receiver to receive a differential data select signal in a complementary signal pair; configuring a voltage level provided by a second reference voltage source to a first input of a third differential receiver, the third differential receiver having a second input for receiving one of the complementary signal pair, configuring a clock generation circuit to generate a read clock signal based on an output of the second differential receiver and to define one or more edges in the read clock signal using a definition signal output by the third differential receiver and causing a data capture circuit to capture data from the output of the first differential receiver using one or more edges in the read clock signal.

[0012] In some aspects, the clock generation circuit includes a read capture window circuit configured to provide a qualified selection signal by gating the output of the second differential receiver with a pulse generated from an edge in the qualified signal. The clock generation circuit may include a calibration delay circuit configured to provide a read clock signal by applying a delay to the qualified selection signal.

[0013] In some aspects, the controller can be configured to train the second reference voltage source by monitoring the duty cycle of the qualifying signal for multiple values ​​of the control signal provided to the second reference voltage source. The control signal can configure the voltage level provided to the first input of the third differential receiver. The controller can be further configured to capture multiple samples of the voltage level of the qualifying signal, each of the multiple samples being captured at a different phase of the qualifying signal. The clock generation circuit can include a calibration delay circuit configured to provide a read clock signal by applying a delay to a qualifying selection signal provided by the clock generation circuit. The controller can be further configured to configure the calibration delay circuit to select the phase of the qualifying signal for each of the multiple samples by delaying the sampling edge in the qualifying signal. The data capture circuit can be used to capture multiple samples.

[0014] In certain aspects, the controller may be further configured to train the first reference voltage source, wherein the first reference voltage source and the second reference voltage source are trained independently of each other.

[0015] In certain aspects, the second reference voltage source provides a calibrated voltage level to the first input of the third differential receiver. The calibrated voltage level can be configured to obtain a 50% duty cycle in the defined signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The diagram illustrates example components and interconnections in a system on a chip (SoC) that may be suitable for implementing certain aspects of the present disclosure.

[0017] Figure 2 Various aspects of physical layer circuitry for reading data from a memory device over a data communications link are illustrated.

[0018] Figure 3 Certain aspects of an example of a memory interface that may be modified according to certain aspects of the present disclosure are illustrated.

[0019] Figure 4 The diagram shows the Figure 3 An example of the generation and use of a reference voltage used in a memory interface is shown.

[0020] Figure 5 A portion of a physical layer circuit including a voltage offset cancellation circuit is illustrated in accordance with certain aspects of the present disclosure.

[0021] Figure 6 It is a graphic Figure 5 Flowchart of the secondary training process of the physical layer circuit shown.

[0022] Figure 7 An example of using multiple voltage generators in a memory physical interface circuit configured according to certain aspects of the present disclosure is illustrated.

[0023] Figure 8 A memory interface configured in accordance with certain aspects of the present disclosure is illustrated.

[0024] Fig. 9 is a flow chart illustrating an example of a training process provided in accordance with certain aspects of the present disclosure.

[0025] Fig.10 The diagram corresponds to Fig. 9 The timing of the training process is shown.

[0026] Fig.11 The diagram corresponds to Fig. 9 The training process and Fig.10 An example of a pattern of timings illustrated in FIG.

[0027] Fig.12 is a flow chart illustrating an example of a method for communicating with a memory device in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION

[0028] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations, rather than being intended to represent the only configurations in which the concepts described herein may be practiced. In order to provide a thorough understanding of the various concepts, the specific embodiments include specific details. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some cases, in order to avoid confusing these concepts, known structures and components are shown in block diagram form.

[0029] Referring now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" as used herein means "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0030] The terms "computing device" and "mobile device" are used interchangeably herein to refer to any or all of a server, a personal computer, a smart phone, a cell phone, a tablet computer, a laptop computer, a netbook, an ultrabook, a palmtop, a personal data assistant (PDA), a wireless email receiver, a multimedia Internet-enabled cell phone, a global positioning system (GPS) receiver, a wireless game controller, and similar personal electronic devices that include a programmable processor. While various aspects are particularly useful in mobile devices (e.g., smart phones, laptop computers, etc.) with limited resources (e.g., processing power, battery, size, etc.), these aspects are generally useful in any computing device that can benefit from improved processor performance and reduced energy consumption.

[0031] The term "multi-core processor" as used herein refers to a single integrated circuit (IC) chip or chip package that contains two or more independent processing units or cores (e.g., CPU cores, etc.) configured to read and execute process instructions. The term "multiprocessor" as used herein refers to a system or device that includes two or more processing units configured to read and execute process instructions.

[0032] The term "system on chip" (SoC) as used herein refers to a single integrated circuit (IC) chip containing multiple resources and / or processors integrated on a single substrate. A single SoC may contain circuits for digital, analog, mixed signal, and radio frequency functions. A single SoC may also include any number of general and / or special processors (digital signal processors (DSPs), modem processors, video processors, etc.), storage boxes (e.g., read-only memory (ROM), random access memory (RAM), flash, etc.), and resources (e.g., timers, voltage regulators, oscillators, etc.), any one or all of which may be included in one or more cores.

[0033] The memory technology described herein may be applicable to storing instructions, procedures, control signals and / or data for use by or by a computer or other digital electronic device. Any reference to terms and / or technical details associated with a single type of memory, interface, standard or memory technology is for illustrative purposes only and is not intended to limit the scope of the claims to a particular memory system or technology unless specifically stated in the claim language. The complexity of mobile computing device architectures has grown and now typically includes multiple processor cores, SOCs, coprocessors, functional modules including dedicated processors (e.g., communication modem chips, GPS receivers, etc.), complex memory systems, complex electrical interconnects (e.g., buses and / or structures), and many other resources to execute complex and power-intensive software applications (e.g., video streaming applications, etc.).

[0034] Certain aspects of the present disclosure apply to input / output (I / O) circuits that provide an interface between core circuits and memory devices. Many mobile devices employ synchronous dynamic random access memory (SDRAM), including low-power double data rate SDRAM, which may be referred to as low-power DDR SDRAM, LPDDR SDRAM, or in some cases, LPDDRx, where x describes the technology generation of the LPDDR SDRAM. Next-generation LPDDR SDRAMs designed to operate at higher operating frequencies may employ lower voltage levels in the core of the SoC or memory device to mitigate the power increase associated with the higher operating frequency.

[0035] Process technologies used to manufacture semiconductor devices, including IC devices, are constantly improving. Process technologies include manufacturing methods used to manufacture IC devices and define transistor size, operating voltage, and switching speed. Features that are components of circuits in IC devices may be referred to as technology nodes and / or process nodes. The terms technology node, process node, and process technology may be used to characterize a specific semiconductor manufacturing process and corresponding design rules. Faster and more energy-efficient technology nodes are being developed by using smaller feature sizes to produce smaller transistors that enable the manufacture of higher density ICs.

[0036] Figure 1Example components and interconnections in a system on chip (SoC) 100 that may be suitable for implementing certain aspects of the present disclosure are illustrated. SoC 100 may include multiple heterogeneous processors, such as a central processing unit (CPU) 102, a modem processor 104, a graphics processor 106, and an application processor 108. Each processor 102, 104, 106, 108 may include one or more cores, and each processor / core may perform operations independently of the other processors / cores. Processors 102, 104, 106, 108 may be organized in close proximity to each other (e.g., on a single substrate, die, integrated chip, etc.) so that the processors can operate at a much higher frequency / clock rate than is possible if signals are transmitted off-chip. The proximity of the cores may also allow for sharing of on-chip memory and resources (e.g., voltage rails), as well as more coordinated cooperation between the cores.

[0037] SoC 100 may include system components and resources 110 for managing sensor data, analog-to-digital conversion, and / or wireless data transmission, as well as for performing other specialized operations (e.g., decoding high-definition video, video processing, etc.). System components and resources 110 may also include components such as voltage regulators, oscillators, phase-locked loops (PLLs), peripheral bridges, data controllers, system controllers, access ports, timers, and / or other similar components for supporting processors and software clients running on the computing device. System components and resources 110 may also include circuits for interfacing with peripheral devices (such as cameras, electronic displays, wireless communication devices, external memory chips, etc.).

[0038] SoC 100 may also include a universal serial bus (USB) or other serial bus controller 112, one or more memory controllers 114, and a centralized resource manager (CRM) 116. SoC 100 may also include input / output modules (not shown) for communicating with resources external to the SoC, each of which may be shared by two or more internal SoC components.

[0039] Processors 102, 104, 106, 108 may be interconnected to USB controller 112, memory controller 114, system components and resources 110, CRM 116, and / or other system components via interconnect / bus module 122, which may include an array of reconfigurable logic gates and / or implement a bus architecture. Communications may also be provided by a high-level interconnect, such as a high-performance network-on-chip (NOC).

[0040] The interconnect / bus module 122 may include or provide a bus master system that is configured to grant a SoC component (e.g., a processor, a peripheral device, etc.) exclusive control of the bus (e.g., transferring data in burst mode, block transfer mode, etc.) for a set duration, number of operations, number of bytes, etc. In some cases, the interconnect / bus module 122 may implement an arbitration scheme to prevent multiple master components from attempting to drive the bus at the same time. The memory controller 114 may be a dedicated hardware module that is configured to manage the flow of data into and out of the memory 124 via the memory interface / bus 126.

[0041] The memory controller 114 may include one or more processors configured to perform read and write operations on the memory 124. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform various functions described throughout the present disclosure. In some aspects, the memory 124 may be part of the SoC 100.

[0042] Figure 2 Various aspects of the physical layer (PHY) circuitry that enables SoC 200 to read data from memory device 240 via data communications link 250 are illustrated. Figure 2 In the illustrated example, a data channel 254 and a data strobe channel 252 are illustrated. The channels 252, 254 may include wires, metal traces, pads, pins, and other interconnects or interconnect elements. The data channel 254 provides a signal path between a data pin (DQ) in the data transceiver 204 in the SoC 200 and a corresponding data pin (DQ) in the data transceiver 244 in the memory device 240. The data strobe channel 252 provides a signal path for the components (RDQS_t and RDQS_c) of the differential receive data strobe signal 218 received from the data strobe transceiver 242 in the memory device 240 to the data strobe transceiver 202 in the SoC 200. The edges or transitions in the data strobe signal 218 received on the data strobe signal 252 provide timing information that can be used to capture data bits from the data signal transmitted on the data channel 254.

[0043] The input of the differential strobe receiver 212 is configured to receive a differential strobe signal transmitted through the data strobe channel 252. The output of the differential strobe receiver 212 is a single-ended strobe signal 220 representing the data strobe signal and is provided to the read capture window circuit (RCW 210). In one example, the RCW 210 is configured to provide a qualified signal 222 by aligning an edge (transition) in the single-ended strobe signal 220 with a transition in a received data signal 226 output by a pseudo differential receiver 214, which receives a data signal from a data channel 254 at one input and receives a reference voltage level (Vref 232) at a second input. As used herein, the term pseudo differential receiver can refer to a differential receiver having one of its pair of inputs coupled to a reference voltage source. In the example shown, the calibration delay circuit (CDC 208) receives the qualified signal 222 and can be configured to generate a read clock signal 224, wherein the edge occurs after the transition between bits in the received data signal 226. The illustrated example also includes a duty cycle correction circuit (DCC 216) that can be configured to maximize the time available to sample each bit in a received data signal 226. In this example, an output 228 of the DCC 216 can be sampled by a data capture circuit 206 clocked by a read clock signal 224 to provide a data output 230. The data capture circuit 206 can include latches, flip-flops, shift registers, and combinational logic, among other circuits.

[0044] Figure 3 Certain aspects of an example of a memory interface 300 that can be modified according to certain aspects of the present disclosure are illustrated. The memory interface 300 includes a memory PHY circuit 302 (e.g., an LPDDR PHY) and a memory device 350 (e.g., an LPDDR SDRAM). The memory PHY circuit 302 includes a data read circuit that provides or supports a data read path and its associated read data strobe path. Figure 3 Circuitry that provides a data write path is omitted. The illustrated memory PHY circuit 302 includes a read capture window frame (RCW 310) and a data read frame 312. The RCW 310 receives a read data strobe signal 330 from an RDQS differential receiver 304 coupled to a pair of interconnects that couple the memory PHY circuit 302 to a memory device 350. The memory device 350 transmits the differential strobe signal to the memory PHY circuit 302 as a RDQS_t signal 352a and a RDQS_c signal 352b via the interconnects. The RCW 310 can be configured to provide a pulse in a read clock signal 334 that can be used by the data read frame 312 to sample and capture data from a data signal received by the data read frame 312.

[0045] RCW 310 may be configured to propagate a second signal representing a differential strobe signal into a data read block 312. For purposes of this disclosure, the second signal representing a differential strobe signal may be referred to as a qualifier signal, a qualifying signal, or a qualifying signal. The term "qualifying edge" may be used to indicate the aspect of propagating a qualifier signal into a data read block 312 by gating, de-gating, or otherwise modifying the timing of an edge in a clock signal used for data capture.

[0046] In the example shown, logic circuitry configured as an AND gate 326 is used to control the timing of edges in the read clock signal 334 by strobing the read data strobe signal 330 with a timing control signal 332. The timing control signal 332 is generated using a logic block 322 and a pulse generation circuit 324 that respond to the read data strobe signal 330 and edges in the RDQS_c signal 352b. The pseudo differential receiver (Qual RX 306) provides a qualifier signal 320 by comparing the voltage state of the RDQS_c signal 352b to a reference voltage level (Vref 318). The edge in the qualifier signal 320 clocks the high voltage state through the first flip-flop 328b and the corresponding edge in the read data strobe signal 330 clocks the second flip-flop, thereby propagating the high voltage state to the logic block 322. The logic block 322 includes timing and / or combinational logic that can change the timing or duration of the high voltage state of the output of the second flip-flop 328a. In some examples, the logic block 322 can terminate the pulse by resetting the first flip-flop 328b and / or the second flip-flop 328a after detecting the trailing edge in the read data strobe signal 330. In some examples, the logic block 322 can terminate the pulse at a point in time after detecting the initial edge in the RDQS_c signal 352b, where the termination point can be controlled by configuring a delay circuit.

[0047] For each pulse in the RDQS_c signal 352 b, the start of a pulse in the read clock signal 334 may be delayed by the timing control signal 332. A pulse in the read clock signal 334 may also be terminated by the timing control signal 332 before the termination of a corresponding pulse in the read clock signal 334. The timing control signal 332 may be used to ensure that the read clock signal 334 is configured to enable the data read block 312 to reliably capture data transmitted by the memory device 350.

[0048] In the example shown, the memory device 350 transmits data in a single-ended data signal 354 (DQ). The pseudo differential receiver (DQ RX 308) provides a received data signal (Rx_data 338) by comparing the voltage state of the single-ended data signal 354 with Vref 318. Rx_data 338 is coupled to the data read block 312 through a selection circuit 316, which can be used to select a calibration or test signal to be used as an input signal 340 of the data read block 312 during a training process that can be performed to configure Vref 318. The selection circuit 316 can be implemented using a multiplexer circuit or a combinational logic circuit. In some examples, the training mode is indicated by a mode selection signal 336, which causes the output of the qualifier signal 320 to be fed to the data read block 312 as a data signal.

[0049] Figure 4 The diagram shows Figure 3 An example 400 of generating and using Vref318 in a memory PHY circuit 302 is shown. The pseudo differential receivers 306 and 308 in the memory PHY circuit 302 include differential receivers 406, 408 based on the same type of differential receiver design. Vref318 is generated using a configurable voltage generator 402, which is controlled using one or more control signals. In the example shown, a first control signal (Vref_r0_en 410) can be used to turn the output of the voltage generator 402 on or off, and a second control signal (Vref_r0_sel 412) can be used to select the voltage of Vref318. Vref318 determines a reference voltage that each of the differential receivers 406, 408 uses to compare the voltage of the corresponding input signal 416, 418. In some implementations, a voltage offset cancellation circuit 404 can be used to calibrate the differential receiver 408 in the read data path, and the voltage offset cancellation circuit 404 can accommodate voltage offsets or drifts due to the use of single-ended signaling. In the example shown, the voltage offset cancellation circuit 404 is configured using a 4-bit control signal 414. The read data strobe is transmitted as a differential signal and can be expected to cancel common mode voltage offsets at the differential receiver, thereby limiting or eliminating the need to cancel offsets at the RDQS differential receiver 304. The Qual RX 306 effectively operates as a single-ended receiver and can be affected by offset voltages or voltage drifts in the RDQS_c signal 352b.

[0050] The training process in conventional PHY circuits trains Vref 318 to optimize the operation of the differential receiver 408 in the read data path. In these conventional PHY circuits, it is generally assumed that Vref 318, which is trained to optimize read data capture, also optimizes the operation of RCW 310. However, this assumption may not hold true under all operating conditions or frequencies, especially at the high frequencies specified by the new generation LPDDR standard. In one example, it may be preferred to optimize the timing aspects of the operation of Qual RX 306 and preferably optimize the responsiveness of DQ RX 308 to voltage levels.

[0051] Conventional training processes train Vref 318 in a manner that optimizes DQ RX 308 in the read data path and may compromise the timing characteristics of Qual RX 306 associated with the RCW. Operation of RCW 310 requires tight timing between the RDQS differential receiver 304 and the Qual RX 306, and conventional training processes may result in suboptimal timing relationships between these receivers 304 and 306. Qual RX 306 and DQ RX 308 have different purposes and receive signals from different sources that may introduce different timing offsets or phase shifts. In some cases, DQ RX 308 includes voltage offset cancellation circuitry 404 and the lack of voltage offset cancellation in Qual RX 306 may result in different operating points between Qual RX 306 and DQ RX 308. In some examples, when a timing violation occurs between the qualifier signal 320 and the read data strobe signal 330 due to suboptimal training of Vref 318 for RCW 310, a read clock error may result.

[0052] Certain aspects of the present disclosure provide for additional training or calibration of the operation of the Qual RX 306 and / or the RDQS differential receiver 304 . Figure 5 A portion of a memory PHY circuit 500 is illustrated that includes a DQS differential receiver (DQS RX 506) that receives complementary RDQS_t signals 510a and RDQS_c signals 510b and a pseudo differential receiver (Qual RX 504) that includes a voltage offset cancellation circuit according to certain aspects of the present disclosure. Qual RX 504 and DQS RX 506 drive a read capture window circuit (RCW circuit 508). Figure 66 is a flow chart 600 illustrating a secondary training process of the Qual RX 504. At block 602, the memory PHY circuit 500 may be configured for training. The voltage generator 502 may be enabled using the Vref_r0_en control signal 516 and the output voltage (Vref 514) may be configured using the previously determined value of the Vref_r0_sel 518. In an example, a primary training process for optimizing the data path may produce the previously determined value of the Vref_r0_sel 518. Vref 514 is coupled to a first input of the Qual RX 504. During training, a second input of the Qual RX 504 may also be coupled to Vref 514. In an example, the second input of the Qual RX 504 may be decoupled from the RDQS_c signal 510b by opening the transistor switch 512 and the transmission gate 522 may be enabled to couple the Vref 514 to the second input of the Qual RX 504. The transistor switch 512 and the transmission gate 522 may be controlled by a training enable control signal (training_en524). The memory device coupled to the memory PHY circuit 500 may be disabled prior to starting the secondary training. In one example, the DRAM may be placed in an operating mode in which its data and / or strobe outputs remain in a high impedance state. At block 604, the control signal (dqsb_offset 520) for the offset cancellation circuit in the Qual RX 504 may be set to a minimum setting. In the example shown, the dqsb_offset 520 may be provided as a multi-bit binary value and the dqsb_offset 520 may be initialized to a zero value in block 604.

[0053] At box 606, the state of the training output signal 528 may be sampled for capture in other ways. The training output signal 528 may be derived from the output of the Qual RX 504 providing the qualifier signal 526 under normal or non-training mode operation. At box 608, the dqsb_offset 520 is incremented. At box 610, the state of the training output signal 528 is compared with the state captured in box 606. When no change in state of the training output signal 528 is detected, the training process returns to box 606 for another iteration. When a change in state of the training output signal 528 is detected, the training process continues at box 612. At box 612, the current setting of the dqsb_offset 520 is locked for normal operation mode. The current setting of the dqsb_offset 520 may be recorded or maintained as a binary code. The secondary training process may then end.

[0054] Certain aspects of the present disclosure relate to memory PHY circuits that employ multiple independently configurable voltage references. Figure 7An example 700 of employing multiple voltage generators 702, 722 in a memory PHY circuit is illustrated. In one example, Figure 3 The illustrated memory PHY circuit 302 may be adapted to incorporate voltage generators 702, 722. A pair of pseudo differential receivers 704 and 724, respectively, include differential receivers 706, 726 that may be based on the same or different types of differential receiver designs.

[0055] A first configurable voltage generator (DQ voltage generator 702) provides a reference voltage level (Vref_DQ 716) to a first pseudo differential receiver (DQRX 704). Vref_DQ 716 is configured or controlled using one or more control signals 710, 712. In the illustrated example, the output of the voltage generator 702 may be turned on or off using a first control signal (Vref_r0_en 710), and the voltage level of Vref_DQ 716 may be selected using a second control signal (Vref_r0_sel 712). Vref_DQ 716 determines the reference voltage that the DQRX 704 uses to compare or determine the voltage of the input signal 718. In some implementations, the DQRX 704 is deployed in the read data path of the memory PHY and may be calibrated using a voltage offset cancellation circuit 708 that may accommodate voltage offsets or drifts due to the use of single-ended signaling. In the example shown, the voltage offset cancellation circuit 708 is configured using a 4-bit control signal 714 .

[0056] A second configurable voltage generator, namely the Qual voltage generator 722, provides a reference voltage level (Vref_DQ 736) to a second differential receiver (Qual RX 724). Vref_DQ 736 is configured or controlled using one or more control signals 730, 732. In the illustrated example, the output of the Qual voltage generator 722 can be turned on or off using a first control signal (Vref_r1_en 730), and the voltage level of Vref_Qual 736 can be selected using a second control signal (Vref_r1_sel 732). Vref_Qual 736 determines the reference voltage that the Qual RX 724 uses to compare or determine the voltage of the input signal 728. In some implementations, the Qual RX 724 is deployed in the data strobe path of the memory PHY. In some implementations, the Qual RX 724 can be calibrated using a voltage offset cancellation circuit (not shown) that can accommodate voltage offsets or drifts attributable to the use of single-ended signaling.

[0057] Figure 8Various aspects of a memory interface configured according to certain aspects of the present disclosure are illustrated. The memory interface includes a PHY circuit that enables the SoC 800 to read data from the memory device 860 through a data communication link 850. In the example shown, a data channel 856 and a data strobe channel 854 are illustrated. The data channel 856 can be one of a plurality of data channels that implement a parallel bus that couples the SoC 800 to the memory device 860. Channels 854, 856 can be implemented using a combination of wires, metal traces, pads, pins, and other interconnects or interconnect elements. The data channel 856 provides a signal path between a data pin (DQ) in the data transceiver 804 in the SoC 800 and a corresponding data pin (DQ) in the data transceiver 864 in the memory device 860. The data strobe channel 854 provides a signal path for the components of the differential receive data strobe signal (RDQS_t 852a and RDQS_c 852b) that are transmitted from the data strobe transceiver 862 in the memory device 860 to the data strobe transceiver 802 in the SoC 800. The edges or transitions in the data strobe signal transmitted on the data strobe signal 854 provide timing information that can be used to capture data bits from the data signal transmitted on the data channel 856.

[0058] The input of the differential strobe receiver (DQS RX 812) is configured to receive a differential strobe signal transmitted through a data strobe channel 854. The output of the DQS RX 812 is a single-ended strobe signal 820 representing the data strobe signal and is provided to a read capture window circuit (RCW circuit 810). In one example, the RCW circuit 810 is configured to receive the single-ended strobe signal 820 and a qualifier signal 836 representing RDQS_c 852b, and generate an output signal 822, which includes a pulse that can be used to control the sampling or capture of data carried in the received data signal 826 output by the first pseudo differential receiver (DQ RX 814). The qualifier signal 836 is output by a second pseudo differential receiver (Qual RX 818) that receives RDQS_c 852b and a first reference signal (Vref_Qual 834) as input. DQ RX 814 receives as input the data signal from the data lane 856 and a second reference signal (Vref_DQ 832 ).

[0059] In the example shown, the calibrated delay circuit (CDC 808) can be configured to delay the output signal 822 provided by the RCW circuit 810 to obtain a read clock signal 824 where the edge occurs after the transition between bits in the received data signal 826. In some implementations, the RCW circuit 810 corresponds to Figure 3RCW 310 shown. The example shown also includes a duty cycle correction circuit (DCC 816) that receives a received data signal 826 and can be configured to output a corrected received data signal 828 that maximizes the time available to sample each bit of data. In this example, in a normal operating mode, the corrected received data signal 828 can be sampled by a data capture circuit 806 clocked by a read clock signal 824. The data capture circuit 806 can include latches, flip-flops, shift registers, and combinational logic, among other circuits, and can output a captured data signal 830.

[0060] Certain aspects of the present disclosure relate to a training process targeting Vref_Qual 834 that can be trained independently of Vref_DQ 832. The training process employs a combination of hardware modules and software modules that work together to optimize certain aspects of RCW 310. In one example, Vref_Qual 834 is trained to provide a voltage level that causes QualRX 818 to output a qualifier signal 836 having a 50% duty cycle in response to an input signal having a 50% duty cycle.

[0061] In some implementations, Vref_Qual 834 is trained by incrementally increasing the voltage level of Vref_Qual 834 and by sampling the qualifier signal 836 at different phases of the cycle of the qualifier signal 836. The CDC 808 may be used to select the phase at which the samples are captured. For each voltage level of Vref_Qual 834, a portion of the cycle of the qualifier signal 836 may be scanned by capturing samples of the voltage level at a phase associated with each delay value configured for the CDC 808. In one example, a first portion of the cycle of the qualifier signal 836 (where a rising edge of a pulse may be expected) may be scanned and recorded as a first pattern of voltage states. A second portion of the cycle of the qualifier signal 836 (where a falling edge of a pulse may be expected) may be scanned and recorded as a second pattern of voltage states. The first pattern and the second pattern may be compared to determine the duration of each voltage phase to measure the number of samples of the voltage state recorded. The pattern of voltage states may be captured from one or more shift registers configured to store a sequence of samples captured during the scan.

[0062] Fig. 9An example of a training process is provided in flowchart 900 of . A controller circuit 838 may be used to configure, start, monitor and / or control parts of the training process. The controller circuit 838 may include a microprocessor, a microcontroller, a finite state machine, a sequential logic, or other type of processing device. At box 902, the memory interface may be reconfigured to support the training process. Certain circuits, flags, interrupts, and / or messages may be disabled so that the upper layer protocol processor and the application ignore the activity on the bus used to couple the PHY circuit to the memory device. In some implementations, the memory device may be disabled by a command issued from a controller in the SoC memory PHY. In some examples, shift registers, latches, buffers, and error detection / error handling circuits or modules may be disabled to prevent read hang situations in which read transactions are not completed. In some examples, during training, some other microcontrollers or finite state machines may be put into an idle state.

[0063] In some implementations, the RCW circuit 810 may be enabled to begin the training process. In some cases, some functions of the RCW circuit 810 may be reconfigured to enable the training process to be performed, and a control signal may be provided to cause the RCW circuit 810 to enter a training mode of operation. In some cases, the RCW circuit 810 may be configured to operate normally while the training process is being performed. For training purposes, the qualifier signal 836 is provided to the data capture circuit 806 as a data stream.

[0064] The qualifier signal 836 can be coupled to the data capture circuit 806 through a selection circuit such as a multiplexer 840. The multiplexer 840 is responsive to a mode control signal 842. In a first mode indicated by the mode control signal 842, the multiplexer 840 couples the corrected received data signal 828 to the input of the data capture circuit 806. The first mode can correspond to a normal operating mode. In a second mode indicated by the mode control signal 842, the multiplexer 840 couples the qualifier signal 836 to the input of the data capture circuit 806. The second mode can correspond to a training mode in which a training process can be performed. During training, the SoC memory PHY can be configured to train at a target frequency, which in some cases can exceed 2 GHz.

[0065] At block 904, Vref_Qual 834 is set to a minimum value. In one example, this can be accomplished by configuring Figure 7 Vref_r1_sel 732 of voltage generator 722 is shown to select the voltage level of Vref_Qual 736. At block 906, CDC 808 may initially be configured to introduce minimal delay or no delay.

[0066] Also refer to Fig.10 and Fig.11 , the training process can be monitored using a multiple-input shift register (MISR) configured to capture the state of the qualified signal 822 at multiple sampling points within each clock cycle of the qualified signal 822. Each sampling point can correspond to the phase of the qualified signal 822. In some examples, the pattern or signature in the captured state can indicate the duty cycle of the qualified signal 822. In some implementations, a deterministic or predefined data pattern can be generated and provided to the memory PHY as read traffic. The captured state can be checked based on the known or expected content of the read traffic to calibrate or train the timing elements used to generate the read clock signal 824.

[0067] Fig.10 1 is a timing diagram 1000 illustrating the relative timing of RDQS_t 852a and RDQS_c 852b and the qualifying signal 822 for three different Vref_Qual 736 values ​​1002, 1004, 1006. The Vref_Qual 736 settings result in different duty cycles. The first Vref_Qual 736 value 1002 produces a 70 / 30 duty cycle of the qualifying signal 822, the second Vref_Qual 736 value 1004 produces a 50 / 50 duty cycle of the qualifying signal 822, and the third Vref_Qual 736 value 1006 produces a 30 / 70 duty cycle in the qualifying signal 822. In the first capture mode 1008, the delay provided by the CDC 808 can be configured to scan the time period 1012 during which the rising edge in the qualifying signal 822 can occur. In the second capture mode 1010, the delay provided by the CDC 808 can be configured to scan a time period 1014 during which a falling edge may occur in the defined signal 822. In the second capture mode 1010, the CDC 808 can be configured to scan a time period 1016 associated with the falling edge of the last pulse or beat in the defined signal 822. The pattern of state information captured during the scan can be used to determine the duty cycle of the defined signal 822. Fig.11 Example training results 1100 are illustrated. Fig.11 Provides a pass / fail indicator based on Fig.10 An example of a pattern of three different Vref_Qual 736 values ​​1002, 1004, 1006 is shown.

[0068] At box 908, read traffic can be generated. The read traffic can be configured to include a determined number of read bursts and can include a predefined data pattern or sequence. At box 910, the results stored in the MISR can be read after the read burst has been transmitted. These results can include a pattern of states captured when a rising edge is expected (rising MISR signature) and a pattern of states captured when a falling edge is expected (falling MISR signature). The rising MISR signature and the falling MISR signature can be stored in a register or memory, and the MISR can be reset. The MISR signature can include values ​​for different patterns of qualifier slices corresponding to data captured for the common Vref_Qual 736 value. The elements of the pattern can include all '0' states, all '1' states, groups of all '0' states except the last captured bit, and failure and / or uncertain groups.

[0069] At block 912, it may be determined whether the immediately preceding ascending MISR result indicates a failure and whether the current ascending MISR result includes all '1' states. If not, the process continues at block 916. If the immediately preceding ascending MISR result indicates a failure and the current MISR result includes all '1' states, at block 914, the CDC delay is configured to match the ascending range start delay.

[0070] At block 916, it may be determined whether the current ascending MISR result indicates a failure and the immediately preceding ascending MISR result includes all '1' states. If not, the process continues at block 920. If the current ascending MISR result indicates a failure and the immediately preceding ascending MISR result includes all '1' states, then at block 918, the ascending MISR pass range is set such that:

[0071] Rising MISR through range = Current CDC delay – Rising range start delay.

[0072] The "rising MISR complete" flag may be set.

[0073] At block 920, it may be determined whether the immediately preceding descent MISR result indicates a failure and whether the current descent MISR result includes all '0' states. If not, the process continues at block 924. If the immediately preceding descent MISR result indicates a failure and the current descent MISR result includes all '0' states, then at block 922, the CDC delay is configured to match the descent range start delay.

[0074] At block 924, it may be determined whether the current descent MISR result indicates a failure and the immediately preceding descent MISR result includes all '0' states. If not, the process continues at block 928. If the current descent MISR result indicates a failure and the immediately preceding descent MISR result includes all '0' states, then at block 926, the descent MISR pass range is set such that:

[0075] Fall MISR through range = current CDC delay – fall range start delay.

[0076] The "drop MISR complete" flag may be set.

[0077] At block 924, both the rising MISR completion flag and the falling MISR completion flag are considered. If neither flag is set, the process continues at block 934, where the CDC delay is increased by the step size defined by CDC 808, and then the process restarts at block 908. If it is determined at block 924 that both flags are set, at block 930, the rising MISR pass range is compared to the falling MISR pass range. If the rising MISR pass range is not greater than the falling MISR pass range, training can be completed at block 932, where the training result is provided as the current Vref_Qual voltage. The current Vref_Qual voltage can be recorded as the current value of the Vref_r1_sel signal 732. If it is determined at block 924 that the rising MISR pass range is greater than the falling MISR pass range, the process continues at block 936, where the rising MISR completion and falling MISR completion flags are cleared, and the Vref_qual value is increased by the step size defined by the Qual voltage generator 722, and then the process restarts at block 906.

[0078] Fig.12 is a flow chart illustrating an example of a method 1200 for communicating with a memory device according to certain aspects of the present disclosure. In one example, the method includes Figure 6 and Fig. 9 At least some portions of the method shown. For example, the method 1200 can be implemented in a memory PHY circuit in a SoC.

[0079] At block 1202, a first input of a first differential receiver may be coupled to a first reference voltage source. At block 1204, a second differential receiver may be configured to receive a differential data strobe signal transmitted as a complementary signal pair. At block 1206, a first input of a third differential receiver is coupled to a second reference voltage source. At block 1208, a second input of the third differential receiver is configured to receive one of the complementary signal pairs. At block 1210, a clock generation circuit is configured to generate a read clock signal based on an output of the second differential receiver, and to define one or more edges in the read clock signal using a definition signal output by the third differential receiver. At block 1212, a data capture circuit is configured to capture data from the output of the first differential receiver using one or more edges in the read clock signal.

[0080] In some implementations, the read capture window circuit is configured to provide a qualifying selection signal by gating an output of the second differential receiver with a pulse generated from an edge in the qualifying signal. The clock generation circuit may include a calibration delay circuit configured to provide a read clock signal by applying a delay to the qualifying selection signal.

[0081] In some examples, the second reference voltage source can be trained by monitoring the duty cycle of the qualifying signal for multiple values ​​of the control signal provided to the second reference voltage source. The control signal can be used to configure the voltage level provided to the first input of the third differential receiver. The control signal can include or relay a multi-bit number. Multiple samples of the voltage level of the qualifying signal can be captured. Each of the multiple samples can be captured at a different phase of the qualifying signal. The clock generation circuit can include a calibration delay circuit configured to provide a read clock signal by applying a delay to the qualifying selection signal. For each sample in the multiple samples, the calibration delay circuit can be configured to select the phase of the qualifying signal by delaying the sampling edge in the qualifying signal. The data capture circuit can be used to capture multiple samples.

[0082] The first reference voltage source can be trained independently of the second reference voltage source. In one example, the first reference voltage source is trained before the second reference voltage source is trained. In another example, the first reference voltage source is trained after the second reference voltage source is trained.

[0083] In some examples, the second reference voltage source provides a calibrated voltage level to the first input of the third differential receiver. The calibrated voltage level can be configured to obtain a 50% duty cycle in the defined signal.

[0084] Various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements") may be used to implement the apparatus and methods described herein and illustrated in the accompanying drawings. These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and design constraints on the overall system.

[0085] According to certain aspects of the present disclosure, a device configured to operate as a memory interface circuit includes: a circuit or module configured to receive a data signal, including a first differential receiver having a first input coupled to a first reference voltage source; a circuit or module configured to receive a differential data strobe signal in a complementary signal pair; a circuit or module configured to generate a qualifying signal by comparing one of the complementary signal pair with an output of a second reference voltage source; a circuit or module configured to generate a read clock signal based on an output of the circuit or module configured to receive the differential data strobe signal; and a circuit or module configured to capture data from the output of the first differential receiver using one or more edges in the read clock signal. In some cases, the qualifying signal is used to qualify the edges in the read clock signal.

[0086] In some examples, the read capture window circuit is configured to provide a defined strobe signal through the output of a strobe circuit or module, the circuit or module being configured to receive the differential data strobe signal with a pulse generated from an edge in the defined signal. . The device for generating a read clock signal may include a calibration delay circuit configured to provide a read clock signal by applying a delay to the defined strobe signal. The second reference voltage source may be trained by monitoring the duty cycle of the defined signal of multiple values ​​of a control signal provided to the second reference voltage source. The control signal may configure the voltage level output by the second reference voltage source. The circuit or module configured to capture data may be configured to capture multiple samples of the voltage level of the defined signal, each of the multiple samples being captured at a different phase of the defined signal.

[0087] The first reference voltage source can be trained independently of the second reference voltage source. In one example, the first reference voltage source is trained before the second reference voltage source is trained. In another example, the first reference voltage source is trained after the second reference voltage source is trained.

[0088] In some examples, a circuit or module configured to generate a read clock signal includes a calibration delay circuit configured to provide a read clock signal by applying a delay to a qualifying selection signal provided by a device for generating the read clock signal. The calibration delay circuit can be configured to select a phase of the qualifying signal for each of a plurality of samples by delaying a sampling edge in the qualifying signal. A circuit or module configured to capture data can be used to capture a plurality of samples.

[0089] In some examples, the output of the second reference voltage source has a calibrated voltage level. The calibrated voltage level can be configured to obtain a 50% duty cycle in the defined signal.

[0090] According to at least one example described herein, a memory interface circuit has: a first differential receiver configured to have a first input coupled to a first reference voltage source; a second differential receiver configured to receive a differential data select signal in a complementary signal pair; a third differential receiver having a first input coupled to a second reference voltage source and a second input configured to receive one of the complementary signal pair; a clock generation circuit configured to generate a read clock signal based on an output of the second differential receiver and to define one or more edges in the read clock signal using a definition signal output by the third differential receiver; and a data capture circuit clocked by the read clock signal and configured to capture data from the output of the first differential receiver using one or more edges in the read clock signal.

[0091] In some examples, the clock generation circuit includes a read capture window circuit configured to provide a qualified selection signal by gating the output of the second differential receiver with a pulse generated from an edge in the qualified signal. The clock generation circuit may include a calibration delay circuit configured to provide a read clock signal by applying a delay to the qualified selection signal.

[0092] In some examples, the memory interface circuit includes a controller configured to train the second reference voltage source by monitoring the duty cycle of the qualifying signal for multiple values ​​of the control signal provided to the second reference voltage source. The control signal can configure the voltage level provided to the first input of the third differential receiver. The controller can be further configured to capture multiple samples of the voltage level of the qualifying signal, each of the multiple samples being captured at a different phase of the qualifying signal. The clock generation circuit can include a calibration delay circuit configured to provide a read clock signal by applying a delay to a qualifying selection signal provided by the clock generation circuit. The controller can configure the calibration delay circuit to select the phase of the qualifying signal for each of the multiple samples by delaying the sampling edge in the qualifying signal. The data capture circuit can be used to capture multiple samples.

[0093] In some examples, the second reference voltage source provides a calibrated voltage level to the first input of the third differential receiver. The calibrated voltage level can be configured to obtain a 50% duty cycle in the defined signal.

[0094] In some implementations, some functions or parts of functions may be implemented using software residing in a memory device or other computer-readable medium in a computer-readable form. Computer-readable media may include non-transitory computer-readable media. For example, non-transitory computer-readable media include magnetic memory devices (e.g., hard disks, floppy disks, magnetic strips), optical disks (e.g., compact disks (CDs) or digital versatile disks (DVDs)), smart cards, flash memory devices (e.g., "flash drives", cards, sticks or key drives), RAM, ROM, programmable read-only memory (PROM), erasable PROMs (EPROMs) including EEPROMs, registers, removable disks, and any other suitable media for storing software and / or instructions that can be accessed and read by a computer.

[0095] In some implementations, the computer-readable medium stores instructions and information, wherein the instructions are configured to cause one or more processors or controllers to perform certain functions and processes. In some cases, the instructions and information may involve Figure 6 , Fig. 9 and Fig.12 Methods 600, 900, 1200 are shown.

[0096] In one example, a processor-readable storage medium stores or maintains a circuit for configuring a voltage level provided by a first reference voltage source to a first input of a first differential receiver, configuring a second differential receiver to receive a differential data select signal in a complementary signal pair, configuring a voltage level provided by a second reference voltage source to a first input of a third differential receiver, the third differential receiver receiving one of the complementary signal pairs at a second input, configuring a clock generation circuit to generate a read clock signal based on an output of the second differential receiver and using a qualification signal output by the third differential receiver to qualify one or more edges in the read clock signal and causing a data capture circuit to capture data from the output of the first differential receiver using the one or more edges in the read clock signal.

[0097] In some examples, the read capture window circuit is configured to provide a qualified selection signal by gating the output of the second differential receiver with a pulse generated from an edge in the qualified signal. The clock generation circuit can include a calibration delay circuit configured to provide a read clock signal by applying a delay to the qualified selection signal.

[0098] In some examples, the processor-readable storage medium includes code for training the second reference voltage source by monitoring the duty cycle of the qualifying signal for multiple values ​​of the control signal provided to the second reference voltage source. The control signal can configure the voltage level provided to the first input of the third differential receiver. Multiple samples of the voltage level of the qualifying signal can be captured at different phases of the qualifying signal. The data capture circuit can be used to capture multiple samples. The clock generation circuit may include a calibration delay circuit configured to provide a read clock signal by applying a delay to a qualifying selection signal provided by the clock generation circuit. The processor-readable storage medium may include code for configuring the calibration delay circuit to select the phase of the qualifying signal by delaying a sampling edge in the qualifying signal.

[0099] The processor-readable storage medium may also include code for training the first reference voltage source. The first reference voltage source may be trained independently of the second reference voltage source. In one example, the first reference voltage source is trained before the second reference voltage source is trained. In another example, the first reference voltage source is trained after the second reference voltage source is trained.

[0100] Some implementation examples are described in the following numbered clauses:

[0101] 1. A memory interface circuit, comprising: a first differential receiver having a first input coupled to a first reference voltage source; a second differential receiver configured to receive a differential data selection signal including a complementary signal pair; a third differential receiver having a first input coupled to a second reference voltage source and a second input configured to receive one of the complementary signal pairs; a clock generation circuit configured to generate a read clock signal based on an output of the second differential receiver and using a qualification signal output by the third differential receiver to qualify one or more edges in the read clock signal; and a data capture circuit clocked by the read clock signal and configured to capture data from the output of the first differential receiver using one or more edges in the read clock signal.

[0102] 2. The memory interface circuit of clause 1, wherein the clock generation circuit comprises: a read capture window circuit configured to provide a qualified selection signal by gating an output of the second differential receiver with a pulse generated from an edge in the qualified signal.

[0103] 3. The memory interface circuit of clause 2, wherein the clock generation circuit comprises: a calibration delay circuit configured to provide the read clock signal by applying a delay to the qualified selection signal.

[0104] 4. The memory interface circuit of claim 1 further comprising a controller configured to train a second reference voltage source by monitoring a duty cycle of a limiting signal for multiple values ​​of a control signal provided to the second reference voltage source, wherein the control signal configures a voltage level provided to the first input of the third differential receiver.

[0105] 5. The memory interface circuit of clause 4, wherein the controller is further configured to: train the first reference voltage source, wherein the first reference voltage source and the second reference voltage source are trained independently of each other.

[0106] 6. The memory interface circuit of clause 4, wherein the controller is further configured to capture a plurality of samples of a voltage level of the defining signal, each sample of the plurality of samples being captured at a different phase of the defining signal.

[0107] 7. A memory interface circuit according to claim 6, wherein the clock generation circuit includes: a calibration delay circuit configured to provide a read clock signal by applying a delay to a qualifying selection signal provided by the clock generation circuit, wherein the controller is further configured to: for each sample in a plurality of samples, configure the calibration delay circuit to select a phase of the qualifying signal by delaying a sampling edge in the qualifying signal.

[0108] 8. The memory interface circuit of clause 6, wherein the data capture circuit is used to capture a plurality of samples.

[0109] 9. The memory interface circuit of clause 1, wherein the second reference voltage source provides a calibrated voltage level to the first input of the third differential receiver, and wherein the calibrated voltage level is configured to obtain a 50% duty cycle in the defined signal.

[0110] 10. A method for communicating with a memory device, comprising: coupling a first input of a first differential receiver to a first reference voltage source; configuring a second differential receiver to receive a differential data selection signal including a complementary signal pair; coupling a first input of a third differential receiver to a second reference voltage source; configuring a second input of the third differential receiver to receive one of the complementary signal pairs; configuring a clock generation circuit to generate a read clock signal based on an output of the second differential receiver and using a qualifying signal output by the third differential receiver to qualify one or more edges in the read clock signal; and configuring a data capture circuit to capture data from the output of the first differential receiver using one or more edges in the read clock signal.

[0111] 11. The method of clause 10, further comprising: configuring a read capture window circuit to provide a qualified selection signal by gating an output of a second differential receiver using a pulse generated from an edge in the qualified signal, wherein the clock generation circuit includes a calibration delay circuit configured to provide a read clock signal by applying a delay to the qualified selection signal.

[0112] 12. The method of clause 10, further comprising: training the second reference voltage source by monitoring the duty cycle of the defined signal for multiple values ​​of a control signal provided to the second reference voltage source, wherein the control signal configures the voltage level provided to the first input of the third differential receiver.

[0113] 13. The method of clause 12, further comprising: training the first reference voltage source, wherein the first reference voltage source and the second reference voltage source are trained independently of each other.

[0114] 14. The method of clause 12, further comprising capturing a plurality of samples of a voltage level defining the signal, each sample of the plurality of samples being captured at a different phase of the defining signal.

[0115] 15. A method according to clause 14, wherein the clock generation circuit includes a calibration delay circuit, the calibration delay circuit is configured to provide a read clock signal by applying a delay to a qualifying selection signal provided by the clock generation circuit, and the method further includes: for each sample in a plurality of samples, configuring the calibration delay circuit to select a phase of the qualifying signal by delaying a sampling edge in the qualifying signal.

[0116] 16. The method of clause 14, wherein the data capture circuit is used to capture a plurality of samples.

[0117] 17. The method of clause 10, wherein the second reference voltage source provides a calibrated voltage level to the first input of the third differential receiver, and wherein the calibrated voltage level is configured to achieve a 50% duty cycle in the defined signal.

[0118] 18. An apparatus comprising: a component for receiving a data signal, including a first differential receiver, the first differential receiver having a first input coupled to a first reference voltage source; a component for receiving a differential data selection signal, the differential data selection signal including a complementary signal pair; a component for generating a qualification signal by comparing one signal in the complementary signal pair with an output of a second reference voltage source; a component for generating a read clock signal based on the output of the component for receiving the differential data selection signal, wherein one or more edges in the read clock signal are qualified by using the qualification signal; and a device for capturing data, configured to capture data from the output of the first differential receiver using one or more edges in the read clock signal.

[0119] 19. An apparatus according to clause 18, wherein the read capture window circuit is configured to provide a qualified selection signal by gating an output of an output of a component for receiving a differential data selection signal using a pulse generated from an edge in the qualified signal, and wherein the component for generating the read clock signal includes a calibration delay circuit, which is configured to provide the read clock signal by applying a delay to the qualified selection signal.

[0120] 20. The apparatus of clause 18, wherein the second reference voltage source is trained by monitoring a duty cycle of the defined signal for a plurality of values ​​of a control signal provided to the second reference voltage source, wherein the control signal configures a voltage level output by the second reference voltage source.

[0121] 21. The apparatus of clause 20, wherein the first reference voltage source and the second reference voltage source are trained independently with respect to each other.

[0122] 22. The apparatus of clause 20, wherein the means for capturing data is configured to capture a plurality of samples of a voltage level defining the signal, each sample of the plurality of samples being captured at a different phase of the defining signal.

[0123] 23. An apparatus according to clause 22, wherein the component for generating a read clock signal includes: a calibration delay circuit configured to provide the read clock signal by applying a delay to a qualifying selection signal provided by the component for generating the read clock signal, and wherein for each sample in a plurality of samples, the calibration delay circuit is configured to select a phase of the qualifying signal by delaying a sampling edge in the qualifying signal.

[0124] 24. The apparatus of clause 22, wherein the means for capturing data is for capturing a plurality of samples.

[0125] 25. A processor-readable storage medium comprising code for the following operations: configuring a voltage level provided by a first reference voltage source to a first input of a first differential receiver; configuring a second differential receiver to receive a differential data selection signal including a complementary signal pair; configuring a voltage level provided by a second reference voltage source to a first input of a third differential receiver, wherein a second input of the third differential receiver receives one of the complementary signal pairs; configuring a clock generation circuit to generate a read clock signal based on an output of the second differential receiver and using a limiting signal output by the third differential receiver to limit one or more edges in the read clock signal; and causing a data capture circuit to capture data from the output of the first differential receiver using one or more edges in the read clock signal.

[0126] 26. A processor-readable storage medium as described in claim 25, wherein the read capture window circuit is configured to provide a qualified selection signal by gating the output of the second differential receiver using a pulse generated from an edge in the qualified signal, and wherein the clock generation circuit includes a calibration delay circuit, the calibration delay circuit being configured to provide the read clock signal by applying a delay to the qualified selection signal.

[0127] 27. The processor-readable storage medium of clause 25, further comprising code for: training a second reference voltage source by monitoring a duty cycle of a defined signal for multiple values ​​of a control signal provided to the second reference voltage source, wherein the control signal configures a voltage level provided to a first input of a third differential receiver.

[0128] 28. The processor-readable storage medium of clause 27, further comprising code for: training the first reference voltage source, wherein the first reference voltage source and the second reference voltage source are trained independently of each other.

[0129] 29. The processor-readable storage medium of clause 27, wherein a plurality of samples of a voltage level defining the signal are captured at different phases of the defining signal, wherein the data capture circuit is used to capture the plurality of samples.

[0130] 30. A processor-readable storage medium as described in claim 29, wherein the clock generation circuit includes a calibration delay circuit, the calibration delay circuit is configured to provide a read clock signal by applying a delay to a qualifying selection signal provided by the clock generation circuit, and the processor-readable storage medium further includes code for the following operations: configuring the calibration delay circuit to select the phase of the qualifying signal by delaying a sampling edge in the qualifying signal.

[0131] As used herein, a phrase referring to "at least one" of a series of items refers to any combination of those items, including single members. For example, "at least one of a, b, or c" is intended to cover a, b, c, ab, ac, bc, and abc, as well as any combination with multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other order of a, b, and c).

[0132] The present disclosure is provided to enable any person skilled in the art to make or use the various aspects of the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the examples and designs described herein, but to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory interface circuit, comprising: a first differential receiver having a first input coupled to a first reference voltage source; a second differential receiver configured to receive a differential data strobe signal comprising a complementary signal pair; a third differential receiver having a first input coupled to a second reference voltage source and a second input configured to receive one signal of the complementary signal pair; a clock generation circuit configured to: generate the read clock signal based on the output of the second differential receiver and using a definition signal output by the third differential receiver to define one or more edges in the read clock signal; as well as A data capture circuit is clocked by the read clock signal and is configured to capture data from the output of the first differential receiver using the one or more edges in the read clock signal.

2. The memory interface circuit according to claim 1, wherein the clock generation circuit comprises: A read capture window circuit is configured to provide a qualified strobe signal by gating the output of the second differential receiver with a pulse generated from an edge in the qualified signal.

3. The memory interface circuit according to claim 2, wherein the clock generation circuit comprises: A calibrated delay circuit is configured to provide the read clock signal by applying a delay to the qualified strobe signal.

4. The memory interface circuit according to claim 1 , further comprising a controller, wherein the controller is configured to: The second reference voltage source is trained by monitoring the duty cycle of the defined signal for a plurality of values ​​of a control signal provided to the second reference voltage source, wherein the control signal configures a voltage level provided to the first input of the third differential receiver.

5. The memory interface circuit of claim 4 , wherein the controller is further configured to: The first reference voltage source is trained, wherein the first reference voltage source and the second reference voltage source are trained independently of each other.

6. The memory interface circuit of claim 4 , wherein the controller is further configured to: A plurality of samples of a voltage level of the qualifying signal are captured, each sample of the plurality of samples being captured at a different phase of the qualifying signal.

7. The memory interface circuit according to claim 6, wherein the clock generation circuit comprises: a calibrated delay circuit configured to provide the read clock signal by applying a delay to a defined strobe signal provided by the clock generation circuit, The controller is further configured to: For each sample in the plurality of samples, the calibrated delay circuit is configured to select a phase of the qualifying signal by delaying a sampling edge in the qualifying signal.

8. The memory interface circuit of claim 6, wherein the data capture circuit is used to capture the plurality of samples.

9. The memory interface circuit of claim 1 , wherein the second reference voltage source provides a calibrated voltage level to the first input of the third differential receiver, and wherein the calibrated voltage level is configured to obtain a 50% duty cycle in the qualifying signal.

10. A method for communicating with a memory device, comprising: coupling a first input of the first differential receiver to a first reference voltage source; configuring a second differential receiver to receive a differential data strobe signal comprising a complementary signal pair; coupling a first input of a third differential receiver to a second reference voltage source; configuring a second input of the third differential receiver to receive one signal of the complementary signal pair; configuring a clock generation circuit to generate the read clock signal based on the output of the second differential receiver and using a qualification signal output by the third differential receiver to define one or more edges in the read clock signal; as well as Data capture circuitry is configured to capture data from the output of the first differential receiver using the one or more edges in the read clock signal.

11. The method according to claim 10, further comprising: A read capture window circuit is configured to provide a qualified selection signal by gating the output of the second differential receiver with a pulse generated from an edge in the qualified signal, wherein the clock generation circuit includes a calibration delay circuit configured to provide the read clock signal by applying a delay to the qualified selection signal.

12. The method according to claim 10, further comprising: The second reference voltage source is trained by monitoring a duty cycle of the defined signal for a plurality of values ​​of a control signal provided to the second reference voltage source, wherein the control signal configures the voltage level provided to the first input of the third differential receiver.

13. The method according to claim 12, further comprising: The first reference voltage source is trained, wherein the first reference voltage source and the second reference voltage source are trained independently of each other.

14. The method according to claim 12, further comprising: A plurality of samples of a voltage level of the qualifying signal are captured, each sample of the plurality of samples being captured at a different phase of the qualifying signal.

15. The method of claim 14, wherein the clock generation circuit comprises a calibration delay circuit configured to provide the read clock signal by applying a delay to a defined strobe signal provided by the clock generation circuit, the method further comprising: For each sample in the plurality of samples, the calibrated delay circuit is configured to select a phase of the qualifying signal by delaying a sampling edge in the qualifying signal.

16. The method of claim 14, wherein the data capture circuit is used to capture the plurality of samples.

17. The method of claim 10, wherein the second reference voltage source provides a calibrated voltage level to the first input of the third differential receiver, and wherein the calibrated voltage level is configured to obtain a 50% duty cycle in the qualifying signal.

18. An apparatus comprising: Means for receiving a data signal, comprising a first differential receiver having a first input coupled to a first reference voltage source; means for receiving a differential data strobe signal, the differential data strobe signal comprising a complementary signal pair; means for generating said qualifying signal by comparing one signal of said complementary signal pair with an output of a second reference voltage source; means for generating a read clock signal based on an output of the means for receiving the differential data strobe signal, wherein one or more edges in the read clock signal are defined by using the definition signal; as well as Means for capturing data is configured to capture data from the output of the first differential receiver using the one or more edges in the read clock signal.

19. The apparatus of claim 18, wherein the read capture window circuit is configured to provide a qualified strobe signal by gating the output of the output of the means for receiving the differential data strobe signal with a pulse generated from an edge in the qualified signal, and The means for generating a read clock signal comprises a calibration delay circuit configured to provide the read clock signal by applying a delay to the qualified selection signal.

20. The apparatus of claim 18, wherein the second reference voltage source is trained by: The duty cycle of the defined signal is monitored for a plurality of values ​​of a control signal provided to the second reference voltage source, wherein the control signal configures a voltage level output by the second reference voltage source.

21. The apparatus of claim 20, wherein the first reference voltage source and the second reference voltage source are trained independently with respect to each other.

22. The apparatus of claim 20, wherein the means for capturing data is configured to: A plurality of samples of a voltage level of the qualifying signal are captured, each sample of the plurality of samples being captured at a different phase of the qualifying signal.

23. The apparatus of claim 22, wherein the means for generating a read clock signal comprises: a calibration delay circuit configured to provide the read clock signal by applying a delay to a defined selection signal provided by the means for generating the read clock signal, and Wherein for each sample in the plurality of samples, the calibration delay circuit is configured to select a phase of the qualification signal by delaying a sampling edge in the qualification signal.

24. The apparatus of claim 22, wherein the means for capturing data is used to capture the plurality of samples.

25. A processor-readable storage medium comprising code for: configuring a voltage level provided by a first reference voltage source to a first input of a first differential receiver; configuring a second differential receiver to receive a differential data strobe signal comprising a complementary signal pair; configuring a voltage level provided by a second reference voltage source to a first input of a third differential receiver, wherein a second input of the third differential receiver receives one signal of the complementary signal pair; configuring a clock generation circuit to generate a read clock signal based on the output of the second differential receiver and using a qualification signal output by the third differential receiver to define one or more edges in the read clock signal; as well as A data capture circuit is caused to capture data from the output of the first differential receiver using the one or more edges in the read clock signal.

26. A processor-readable storage medium according to claim 25, wherein the read capture window circuit is configured to provide a qualified selection signal by gating the output of the second differential receiver with a pulse generated from an edge in the qualified signal, and wherein the clock generation circuit includes a calibration delay circuit, which is configured to provide the read clock signal by applying a delay to the qualified selection signal.

27. The processor-readable storage medium of claim 25, further comprising code for: The second reference voltage source is trained by monitoring a duty cycle of the defined signal for a plurality of values ​​of a control signal provided to the second reference voltage source, wherein the control signal configures the voltage level provided to the first input of the third differential receiver.

28. The processor-readable storage medium of claim 27, further comprising code for: The first reference voltage source is trained, wherein the first reference voltage source and the second reference voltage source are trained independently of each other.

29. The processor-readable storage medium of claim 27, wherein a plurality of samples of a voltage level of the defined signal are captured at different phases of the defined signal, wherein the data capture circuit is to capture the plurality of samples.

30. The processor-readable storage medium of claim 29, wherein the clock generation circuit comprises a calibration delay circuit configured to provide the read clock signal by applying a delay to a defined strobe signal provided by the clock generation circuit, the processor-readable storage medium further comprising code for: The calibrated delay circuit is configured to select a phase of the qualifying signal by delaying a sampling edge in the qualifying signal.

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