Driving circuit, display panel, display substrate and display device

Abstract

The invention provides a driving circuit, a display panel, a display substrate and a display device. The driving circuit comprises a first node control circuit (11), a second node control circuit (12) and a first output circuit (13); the second node control circuit (12) is controlled by a low-voltage signal provided by a first low-voltage input end (VL1) to control connection between the first electric node (N1) and the second node (N2); the first node control circuit (11) controls the first node (N1) to be electrically connected with the second low-voltage input end (VL2) under the control of a first clock signal (CK); the first output circuit (13) controls the connection between the driving signal output end (O1) and the third low-voltage input end (VL3) under the control of the potential of the pull-down node (PD); at least two of the first low-voltage input end (VL1), the second low-voltage input end (VL2) and the third low-voltage input end (VL3) are different, and at least two low-voltage signals are adopted.

Description

Driving circuit, display panel, display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving circuit, a display panel, a display substrate, and a display device. Background Art

[0002] Active-matrix organic light-emitting diode (AMOLED) display devices are widely used in various products due to their advantages such as flexibility, high contrast and low power consumption.

[0003] In related art, an AMOLED display device typically includes an AMOLED display panel and a gate drive circuit. The AMOLED display panel includes multiple rows of pixels. The gate drive circuit includes multiple cascaded shift register units. Each shift register unit is coupled to a row of pixels and is used to transmit a gate drive signal to that row of pixels to drive that row of pixels to emit light. The multiple cascaded shift register units can achieve row-by-row scanning and drive of the multiple rows of pixels, allowing the AMOLED display panel to display an image.

[0004] However, the related shift register units use the same voltage input terminal, and the potential of each node cannot be flexibly set.

[0005] Summary of the Invention

[0006] In one aspect, an embodiment of the present disclosure provides a driving circuit, comprising a first node control circuit, a second node control circuit, and a first output circuit;

[0007] The second node control circuit is electrically connected to the first low voltage input terminal, the first node, and the second node, respectively, and is configured to control the connection between the first node and the second node under the control of a low voltage signal provided by the first low voltage input terminal;

[0008] The first node control circuit is electrically connected to the second low voltage input terminal, the first clock signal line and the first node respectively, and is used to control the first node to be electrically connected to the second low voltage input terminal under the control of the first clock signal provided by the first clock signal line;

[0009] The first output circuit is electrically connected to the pull-down node, the drive signal output terminal and the third low voltage input terminal respectively, and is used to control the connection between the drive signal output terminal and the third low voltage input terminal under the control of the potential of the pull-down node;

[0010] At least two of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal are different from each other.

[0011] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a second output circuit and a fourth node control circuit;

[0012] The second output circuit is electrically connected to the pull-up node, the first high voltage input terminal and the drive signal output terminal respectively, and is used to control the connection between the first high voltage input terminal and the drive signal output terminal under the control of the potential of the pull-up node;

[0013] The fourth node control circuit is electrically connected to the first node, the fourth node and the fourth high voltage input terminal respectively, and is used to control the connection between the fourth node and the fourth high voltage input terminal under the control of the potential of the first node;

[0014] The first high voltage input terminal is different from the fourth high voltage input terminal.

[0015] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a third node reset circuit;

[0016] The third node reset circuit is electrically connected to the reset line, the third high voltage input terminal and the third node respectively, and is used to control the connection between the third high voltage input terminal and the third node under the control of the reset signal provided by the reset line;

[0017] The third high voltage input terminal is different from at least one of the first high voltage input terminal and the fourth high voltage input terminal.

[0018] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a pull-up node control circuit;

[0019] The pull-up node control circuit is electrically connected to the third node, the second high voltage input terminal and the pull-up node respectively, and is used to control the connection between the second high voltage input terminal and the pull-up node under the control of the potential of the third node;

[0020] The second high voltage input terminal is different from at least one of the first high voltage input terminal and the fourth high voltage input terminal.

[0021] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a pull-up node control circuit;

[0022] The pull-up node control circuit is electrically connected to the third node, the second high voltage input terminal and the pull-up node respectively, and is used to control the connection between the second high voltage input terminal and the pull-up node under the control of the potential of the third node;

[0023] The second high voltage input terminal is different from the third high voltage input terminal.

[0024] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a pull-down node control circuit;

[0025] The pull-down node control circuit is electrically connected to the fourth low voltage input terminal, the third node and the pull-down node respectively, and is used to control the connection between the third node and the pull-down node under the control of the low voltage signal provided by the fourth low voltage input terminal;

[0026] The fourth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal.

[0027] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a fifth node control circuit and a pull-up node control circuit;

[0028] The fifth node control circuit is electrically connected to the second node, the fifth node, and the second clock signal line, respectively, and is configured to control the connection between the second clock signal line and the fifth node under the control of the potential of the second node, and to control the potential of the fifth node according to the potential of the second node;

[0029] The pull-up node control circuit is also electrically connected to the fifth node, the second clock signal line and the pull-up node, respectively, and is used to control the connection between the fifth node and the pull-up node under the control of the second clock signal provided by the second clock signal line, and to maintain the potential of the pull-up node.

[0030] Optionally, the driving circuit further includes a third node control circuit;

[0031] The third node control circuit is electrically connected to the starting voltage terminal, the first clock signal line and the third node respectively, and is used to control the connection between the starting voltage terminal and the third node under the control of the first clock signal provided by the first clock signal line;

[0032] The first node control circuit is further electrically connected to the third node, the first node and the first clock signal line respectively, and is configured to control the connection between the first node and the first clock signal line under the control of the potential of the third node;

[0033] The fourth node control circuit is also electrically connected to the pull-down node and the second clock signal line respectively, and is used to control the connection between the fourth node and the second clock signal line under the control of the potential of the pull-down node, and control the potential of the fourth node according to the potential of the pull-down node.

[0034] Optionally, the first node control circuit includes a first transistor, and the second node control circuit includes a second transistor;

[0035] The control electrode of the first transistor is electrically connected to the first clock signal line, the first electrode of the first transistor is electrically connected to the second low voltage input terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0036] The control electrode of the second transistor is electrically connected to the first low voltage input terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node;

[0037] The first output circuit includes an output reset transistor, a control electrode of the output reset transistor is electrically connected to the pull-down node, a first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and a second electrode of the output reset transistor is electrically connected to the third low voltage input terminal.

[0038] Optionally, the second output circuit includes an output transistor, and the pull-up node control circuit includes a third transistor and a first capacitor;

[0039] The control electrode of the output transistor is electrically connected to the pull-up node, the first electrode of the output transistor is electrically connected to the first high voltage input terminal, and the second electrode of the output transistor is electrically connected to the drive signal output terminal;

[0040] The control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the second high voltage input terminal, and the second electrode of the third transistor is electrically connected to the pull-up node;

[0041] The first plate of the first capacitor is electrically connected to the pull-up node, and the second plate of the first capacitor is electrically connected to the first high voltage input terminal.

[0042] Optionally, the third node reset circuit includes a fourth transistor;

[0043] The control electrode of the fourth transistor is electrically connected to the reset line, the first electrode of the fourth transistor is electrically connected to the third high voltage input terminal, and the second electrode of the fourth transistor is electrically connected to the third node.

[0044] Optionally, the fourth node control circuit includes a fifth transistor;

[0045] The control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the fourth high voltage input terminal, and the second electrode of the fifth transistor is electrically connected to the fourth node.

[0046] Optionally, the pull-down node control circuit includes a sixth transistor;

[0047] The control electrode of the sixth transistor is electrically connected to the fourth low voltage input terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the pull-down node.

[0048] Optionally, the fifth node control circuit includes a seventh transistor and a second capacitor; the pull-up node control circuit further includes an eighth transistor;

[0049] The control electrode of the seventh transistor is electrically connected to the second node, the first electrode of the seventh transistor is electrically connected to the second clock signal line, and the second electrode of the seventh transistor is electrically connected to the fifth node;

[0050] The first plate of the second capacitor is electrically connected to the second node, and the second plate of the second capacitor is electrically connected to the fifth node;

[0051] The control electrode of the eighth transistor is electrically connected to the second clock signal line, the first electrode of the eighth transistor is electrically connected to the fifth node, and the second electrode of the eighth transistor is electrically connected to the pull-up node.

[0052] Optionally, the first node control circuit further includes a ninth transistor;

[0053] The control electrode of the ninth transistor is electrically connected to the third node, the first electrode of the ninth transistor is electrically connected to the first clock signal line, and the second electrode of the ninth transistor is electrically connected to the first node;

[0054] The fourth node control circuit further includes a tenth transistor and a third capacitor;

[0055] The control electrode of the tenth transistor is electrically connected to the pull-down node, the first electrode of the tenth transistor is electrically connected to the second clock signal line, and the second electrode of the tenth transistor is electrically connected to the fourth node;

[0056] A first plate of a third capacitor is electrically connected to the pull-down node, and a second plate of the third capacitor is electrically connected to the fourth node;

[0057] The third node control circuit includes an eleventh transistor;

[0058] The control electrode of the eleventh transistor is electrically connected to the first clock signal line, the first electrode of the eleventh transistor is electrically connected to the starting voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the third node.

[0059] In a second aspect, an embodiment of the present disclosure provides a driving circuit including a first transistor, a second transistor, an output reset transistor, and a sixth transistor;

[0060] The control electrode of the first transistor is electrically connected to the first clock signal line, the first electrode of the first transistor is electrically connected to the second low voltage input terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0061] The control electrode of the second transistor is electrically connected to the first low voltage input terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node;

[0062] The first output circuit includes an output reset transistor, a control electrode of the output reset transistor is electrically connected to the pull-down node, a first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and a second electrode of the output reset transistor is electrically connected to the third low voltage input terminal;

[0063] The control electrode of the sixth transistor is electrically connected to the fourth low voltage input terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the pull-down node;

[0064] The first low voltage input terminal, the second low voltage input terminal, the third low voltage input terminal and the low voltage input terminal are not completely the same.

[0065] In a third aspect, an embodiment of the present disclosure provides a driving circuit including an output transistor, a third transistor, a fourth transistor, and a fifth transistor;

[0066] The control electrode of the output transistor is electrically connected to the pull-up node, the first electrode of the output transistor is electrically connected to the first high voltage input terminal, and the second electrode of the output transistor is electrically connected to the drive signal output terminal;

[0067] The control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the second high voltage input terminal, and the second electrode of the third transistor is electrically connected to the pull-up node;

[0068] The control electrode of the fourth transistor is electrically connected to the reset line, the first electrode of the fourth transistor is electrically connected to the third high voltage input terminal, and the second electrode of the fourth transistor is electrically connected to the third node;

[0069] The control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the fourth high voltage input terminal, and the second electrode of the fifth transistor is electrically connected to the fourth node;

[0070] The first high voltage input terminal, the second high voltage input terminal, the third high voltage input terminal and the fourth high voltage input terminal are not completely the same.

[0071] In a fourth aspect, an embodiment of the present disclosure provides a display panel, comprising the aforementioned driving circuit; the display panel further comprises a display driving chip;

[0072] The first low voltage input terminal is electrically connected to the first low voltage line, the second low voltage input terminal is electrically connected to the second low voltage line, and the third low voltage input terminal is electrically connected to the third low voltage line. The first low voltage line, the second low voltage line, and the third low voltage line are electrically connected to different pins of the display driver chip, respectively. The display driver chip is used to provide a first low voltage signal for the first low voltage line, a second low voltage signal for the second low voltage line, and a third low voltage signal for the third low voltage line; or

[0073] The first low voltage input terminal is electrically connected to the first low voltage line, the second low voltage input terminal and the third low voltage input terminal are both electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal to the first low voltage line and provide a second low voltage signal to the second low voltage line; or

[0074] The first low voltage input terminal and the second low voltage input terminal are both electrically connected to the first low voltage line, the third low voltage input terminal is electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal to the first low voltage line and provide a second low voltage signal to the second low voltage line; or

[0075] The first low voltage input terminal and the third low voltage input terminal are both electrically connected to the first low voltage line, the second low voltage input terminal is electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are respectively electrically connected to different pins of the display driver chip, and the display driver chip is used to provide a first low voltage signal for the first low voltage line and provide a second low voltage signal for the second low voltage line.

[0076] In a sixth aspect, an embodiment of the present disclosure provides a display panel, comprising the aforementioned driving circuit; the display panel further comprises a display driving chip;

[0077] The first high voltage input terminal is electrically connected to the first high voltage line, and the second high voltage input terminal is electrically connected to the second high voltage line; the first high voltage line and the second high voltage line are respectively electrically connected to different pins of the display driver chip, and the display driver chip is used to provide a first high voltage signal for the first high voltage line, and the display driver chip is used to provide a second high voltage signal for the second high voltage line.

[0078] In a seventh aspect, an embodiment of the present disclosure provides a display substrate, comprising a base substrate and a driving circuit disposed on the base substrate.

[0079] Optionally, the driving circuit includes a first low voltage line, a second low voltage line, a first high voltage line, a second high voltage line, a first node control circuit, a second node control circuit, a first output circuit, a second output circuit, a pull-up node control circuit, a fourth node control circuit, a pull-down node control circuit, a fifth node control circuit, and a third node control circuit;

[0080] The second low-voltage line is arranged on a side of the driving circuit away from the display area, and the first low-voltage line is arranged on a side of the driving circuit close to the display area;

[0081] The first high voltage line and the second high voltage line are provided between a first circuit portion included in the driving circuit and a second circuit portion included in the driving circuit;

[0082] The first circuit portion includes a first node control circuit, a second node control circuit, a pull-up node control circuit, a fourth node control circuit, a pull-down node control circuit, a fifth node control circuit, and a third node control circuit, and the second circuit portion includes a first output circuit and a second output circuit;

[0083] The first circuit portion is disposed between the second low voltage line and the second high voltage line, and the second circuit portion is disposed between the first high voltage line and the first low voltage line.

[0084] Optionally, the driving circuit further includes a third node reset circuit, and the first circuit portion includes the third node reset circuit.

[0085] In the eighth disclosure, an embodiment of the present disclosure provides a display device including the above-mentioned driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0086] FIG1 is a structural diagram of a driving circuit according to an embodiment of the present disclosure;

[0087] FIG2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0088] FIG3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0089] FIG4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0090] FIG5 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0091] FIG6 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0092] FIG7 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0093] FIG8A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0094] FIG8B is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG8A of the present disclosure;

[0095] FIG9 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0096] FIG10 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0097] FIG11 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0098] FIG12 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0099] FIG13 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0100] FIG14 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0101] FIG15 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0102] FIG16 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0103] FIG17 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0104] FIG18 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0105] FIG19A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0106] FIG19B is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0107] FIG20 is a circuit diagram of a related pixel circuit;

[0108] FIG21 is a layout diagram of at least one embodiment of the driving circuit shown in FIG15 of the present disclosure;

[0109] FIG22 is a layout diagram of the active layer in FIG21;

[0110] FIG23 is a layout diagram of the first gate metal layer in FIG21;

[0111] FIG24 is a layout diagram of the second gate metal layer in FIG21;

[0112] FIG25 is a layout diagram of the source / drain metal layer in FIG21 ;

[0113] FIG26 is a layout diagram of at least one embodiment of the driving circuit shown in FIG19 of the present disclosure;

[0114] FIG27 is a layout diagram of the active layer in FIG26;

[0115] FIG28 is a layout diagram of the first gate metal layer in FIG26;

[0116] FIG29 is a layout diagram of the second gate metal layer in FIG26;

[0117] FIG30 is a layout diagram of the source / drain metal layer in FIG26 ;

[0118] FIG31 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0119] FIG32 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0120] FIG33 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0121] FIG34 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0122] FIG35 is a structural diagram of a display panel according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0123] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0124] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0125] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0126] As shown in FIG1 , the driving circuit according to the embodiment of the present disclosure includes a first node control circuit 11 , a second node control circuit 12 and a first output circuit 13 ;

[0127] The second node control circuit 12 is electrically connected to the first low voltage input terminal VL1, the first node N1 and the second node N2, respectively, and is used to control the connection between the first node N1 and the second node N2 under the control of the low voltage signal provided by the first low voltage input terminal VL1;

[0128] The first node control circuit 11 is electrically connected to the second low voltage input terminal VL2, the first clock signal line CK and the first node N1 respectively, and is used to control the first node N1 to be electrically connected to the second low voltage input terminal VL2 under the control of the first clock signal provided by the first clock signal line CK;

[0129] The first output circuit 13 is electrically connected to the pull-down node PD, the drive signal output terminal O1, and the third low voltage input terminal VL3, respectively, and is used to control the connection between the drive signal output terminal O1 and the third low voltage input terminal VL3 under the control of the potential of the pull-down node PD;

[0130] At least two of the first low voltage input terminal VL1 , the second low voltage input terminal VL2 , and the third low voltage input terminal VL3 are different from each other.

[0131] In at least one embodiment of the present disclosure, the two low-voltage input terminals being different may mean that the two low-voltage input terminals respectively provide different low-voltage signals.

[0132] In the embodiment of the driving circuit shown in FIG1 , the low voltage signal provided by the first low voltage input terminal VL1 may be different from the low voltage signal provided by the second low voltage input terminal VL2 .

[0133] In at least one embodiment of the present disclosure, the voltage value of the low voltage signal may be a negative voltage.

[0134] For example, when the transistor included in the first node control circuit 11 and the transistor included in the second node control circuit 12 are p-type transistors, the absolute value of the low voltage signal provided by the second low voltage input terminal VL2 is greater than the absolute value of the low voltage signal provided by the first low voltage input terminal VL1, so that the potential of N1 and the potential of N2 are lower.

[0135] In at least one embodiment of the present disclosure, the first low voltage input terminal may provide a first low voltage signal, and the second low voltage input terminal may provide a second low voltage signal, but the present invention is not limited thereto.

[0136] In at least one embodiment of the present disclosure, a first low voltage line VGL may provide a first low voltage signal, and a second low voltage line VGL2 may provide a second low voltage signal.

[0137] In the embodiment of the driving circuit shown in FIG1 , the first low voltage input terminal VL1 may provide a first low voltage signal, the second low voltage input terminal VL2 may provide a second low voltage signal, and the third low voltage input terminal VL3 may provide a first low voltage signal; or

[0138] The first low voltage input terminal VL1 may provide a second low voltage signal, the second low voltage input terminal VL2 may provide a second low voltage signal, and the third low voltage input terminal VL3 may provide a first low voltage signal; or

[0139] The first low voltage input terminal VL1 may provide a first low voltage signal, the second low voltage input terminal VL2 may provide a first low voltage signal, and the third low voltage input terminal VL3 may provide a second low voltage signal; or

[0140] The first low voltage input terminal VL1 can provide a first low voltage signal, the second low voltage input terminal VL2 can provide a second low voltage signal, and the third low voltage input terminal VL3 can provide a second low voltage signal;

[0141] But it is not limited to this.

[0142] As shown in FIG2 , based on the embodiment of the driving circuit shown in FIG1 , the driving circuit according to at least one embodiment of the present disclosure further includes a second output circuit 21 and a fourth node control circuit 41 ;

[0143] The second output circuit 21 is electrically connected to the pull-up node PU, the first high voltage input terminal VH1 and the drive signal output terminal O1, respectively, and is used to control the connection between the first high voltage input terminal VH1 and the drive signal output terminal O1 under the control of the potential of the pull-up node PU;

[0144] The fourth node control circuit 41 is electrically connected to the first node N1, the fourth node N4 and the fourth high voltage input terminal VH4, respectively, and is used to control the connection between the fourth node N4 and the fourth high voltage input terminal VH4 under the control of the potential of the first node N1; the first high voltage input terminal VH1 is different from the fourth high voltage input terminal VH4.

[0145] In at least one embodiment of the present disclosure, the two high voltage input terminals being different may mean that the two high voltage input terminals respectively provide different high voltage signals.

[0146] In at least one embodiment of the present disclosure, the first high voltage input terminal VH1 may provide a first high voltage signal, and the second high voltage input terminal VH2 may provide a second high voltage signal.

[0147] In at least one embodiment of the present disclosure, a first high voltage line VGH may provide a first high voltage signal, and a second high voltage line VGH2 may provide a second high voltage signal.

[0148] In a specific implementation, when the transistor included in the second output circuit 21 is a p-type transistor, the voltage value of the high voltage signal provided by the first high voltage input terminal can be set to be lower than the voltage value of the high voltage signal provided by the second high voltage input terminal, so that when the transistor included in the pull-up node control circuit 22 is turned on, the transistor included in the second output circuit 21 can be better turned off;

[0149] When the transistor included in the second output circuit 21 is an n-type transistor, the voltage value of the high voltage signal provided by the first high voltage input terminal can be set to be greater than the voltage value of the high voltage signal provided by the second high voltage input terminal, so that when the transistor included in the pull-up node control circuit 22 is turned on, the transistor included in the second output circuit 21 can be turned off better;

[0150] But it is not limited to this.

[0151] In at least one embodiment of the present disclosure, the driving circuit further includes a third node reset circuit;

[0152] The third node reset circuit is electrically connected to the reset line, the third high voltage input terminal and the third node respectively, and is used to control the connection between the third high voltage input terminal and the third node under the control of the reset signal provided by the reset line;

[0153] The third high voltage input terminal is different from at least one of the first high voltage input terminal and the second high voltage input terminal.

[0154] As shown in FIG3 , based on at least one embodiment of the driving circuit shown in FIG2 , the driving circuit according to at least one embodiment of the present disclosure may further include a third node reset circuit 31 ;

[0155] The third node reset circuit 31 is electrically connected to the reset line VEL, the third high voltage input terminal VH3 and the third node N3 respectively, and is used to control the connection between the third high voltage input terminal VH3 and the third node N3 under the control of the reset signal provided by the reset line VEL.

[0156] In at least one embodiment shown in FIG. 3 , the third high voltage input terminal VH3 may be used to provide a second high voltage signal, or the third high voltage input terminal VH3 may be used to provide a first high voltage signal, but the present invention is not limited thereto.

[0157] In at least one embodiment of the present disclosure, the voltage value of the first low voltage signal may be greater than the voltage value of the second low voltage signal; or, the voltage value of the first low voltage signal may be less than the voltage value of the second low voltage signal;

[0158] The voltage value of the first high voltage signal may be greater than the voltage value of the second high voltage signal; or, the voltage value of the first high voltage signal may be less than the voltage value of the second high voltage signal.

[0159] The driving circuit according to at least one embodiment of the present disclosure further includes a pull-up node control circuit;

[0160] The pull-up node control circuit is electrically connected to the third node, the second high voltage input terminal and the pull-up node respectively, and is used to control the connection between the second high voltage input terminal and the pull-up node under the control of the potential of the third node;

[0161] The second high voltage input terminal is different from at least one of the first high voltage input terminal and the fourth high voltage input terminal.

[0162] The driving circuit according to at least one embodiment of the present disclosure further includes a pull-up node control circuit;

[0163] The pull-up node control circuit is electrically connected to the third node, the second high voltage input terminal and the pull-up node respectively, and is used to control the connection between the second high voltage input terminal and the pull-up node under the control of the potential of the third node;

[0164] The second high voltage input terminal is different from the third high voltage input terminal.

[0165] As shown in FIG4 , based on at least one embodiment of the driving circuit shown in FIG3 , the driving circuit according to at least one embodiment of the present disclosure further includes a pull-up node control circuit 22 ;

[0166] The pull-up node control circuit 22 is electrically connected to the third node N3, the second high voltage input terminal VH2 and the pull-up node PU respectively, and is used to control the connection between the second high voltage input terminal VH2 and the pull-up node PU under the control of the potential of the third node N3;

[0167] The second high voltage input terminal VH2 is different from at least one of the first high voltage input terminal VH1 , the fourth high voltage input terminal VH4 , and the third high voltage input terminal VH3 .

[0168] In a specific implementation, the fourth high voltage input terminal VH4 can provide a first high voltage signal or a second high voltage signal, but is not limited thereto.

[0169] In at least one embodiment of the present disclosure, the driving circuit further includes a pull-down node control circuit;

[0170] The pull-down node control circuit is electrically connected to the fourth low voltage input terminal, the third node and the pull-down node respectively, and is used to control the connection between the third node and the pull-down node under the control of a fourth low voltage signal provided by the fourth low voltage input terminal;

[0171] The fourth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal.

[0172] As shown in FIG5 , based on at least one embodiment of the driving circuit shown in FIG4 , the driving circuit according to at least one embodiment of the present disclosure further includes a pull-down node control circuit 51 ;

[0173] The pull-down node control circuit 51 is electrically connected to the fourth low voltage input terminal VL4, the third node N3 and the pull-down node PD, respectively, and is used to control the connection between the third node N3 and the pull-down node PD under the control of the fourth low voltage signal provided by the fourth low voltage input terminal VL4;

[0174] The fourth low voltage input terminal VL4 is different from at least one of the first low voltage input terminal VL1 , the second low voltage input terminal VL2 , and the third low voltage input terminal VL3 .

[0175] In at least one embodiment of the present disclosure, the fourth low voltage input terminal VL4 can provide a first low voltage signal or a second low voltage signal, but is not limited thereto.

[0176] In at least one embodiment of the present disclosure, the driving circuit further includes a fifth node control circuit and a pull-up node control circuit;

[0177] The fifth node control circuit is electrically connected to the second node, the fifth node, and the second clock signal line, respectively, and is configured to control the connection between the second clock signal line and the fifth node under the control of the potential of the second node, and to control the potential of the fifth node according to the potential of the second node;

[0178] The pull-up node control circuit is also electrically connected to the fifth node, the second clock signal line and the pull-up node, respectively, and is used to control the connection between the fifth node and the pull-up node under the control of the second clock signal provided by the second clock signal line, and to maintain the potential of the pull-up node.

[0179] In a specific implementation, the driving circuit further includes a fifth node control circuit, the fifth node control circuit is used to control the potential of the fifth node, and the pull-up node control circuit is used to control the potential of the pull-up node.

[0180] In at least one embodiment of the present disclosure, the driving circuit further includes a third node control circuit;

[0181] The third node control circuit is electrically connected to the starting voltage terminal, the first clock signal line and the third node respectively, and is used to control the connection between the starting voltage terminal and the third node under the control of the first clock signal provided by the first clock signal line;

[0182] The first node control circuit is further electrically connected to the third node, the first node and the first clock signal line respectively, and is configured to control the connection between the first node and the first clock signal line under the control of the potential of the third node;

[0183] The fourth node control circuit is also electrically connected to the pull-down node and the second clock signal line respectively, and is used to control the connection between the fourth node and the second clock signal line under the control of the potential of the pull-down node, and control the potential of the fourth node according to the potential of the pull-down node.

[0184] In a specific implementation, the driving circuit further includes a third node control circuit, which controls the potential of the third node, the first node control circuit controls the potential of the first node, and the fourth node control circuit controls the potential of the fourth node.

[0185] As shown in FIG6 , based on at least one embodiment of the driving circuit shown in FIG5 , the driving circuit further includes a fifth node control circuit 71 and a third node control circuit 72 ;

[0186] The fifth node control circuit 71 is electrically connected to the second node N2, the fifth node N5, and the second clock signal line CB, respectively, and is configured to control the connection between the second clock signal line CB and the fifth node N5 under the control of the potential of the second node N2, and to control the potential of the fifth node N5 according to the potential of the second node N2;

[0187] The pull-up node control circuit 22 is further electrically connected to the fifth node N5, the second clock signal line CB, and the pull-up node PU, respectively, and is configured to control the communication between the fifth node N5 and the pull-up node PU under the control of the second clock signal provided by the second clock signal line CB, and to maintain the potential of the pull-up node PU;

[0188] The third node control circuit 72 is electrically connected to the start voltage terminal STV, the first clock signal line CK, and the third node N3, respectively, and is used to control the connection between the start voltage terminal STV and the third node N3 under the control of the first clock signal provided by the first clock signal line CK;

[0189] The first node control circuit 11 is further electrically connected to the third node N3, the first node N1 and the first clock signal line CK, and is configured to control the connection between the first node N1 and the first clock signal line CK under the control of the potential of the third node N3;

[0190] The fourth node control circuit 41 is also electrically connected to the pull-down node PD and the second clock signal line CB, respectively, and is used to control the connection between the fourth node N4 and the second clock signal line CB under the control of the potential of the pull-down node PD, and control the potential of the fourth node N4 according to the potential of the pull-down node PD.

[0191] Optionally, the first node control circuit includes a first transistor, and the second node control circuit includes a second transistor;

[0192] The control electrode of the first transistor is electrically connected to the first clock signal line, the first electrode of the first transistor is electrically connected to the second low voltage input terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0193] The control electrode of the second transistor is electrically connected to the first low voltage input terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node;

[0194] The first output circuit includes an output reset transistor;

[0195] The control electrode of the output reset transistor is electrically connected to the pull-down node, the first electrode of the output reset transistor is electrically connected to the driving signal output terminal, and the second electrode of the output reset transistor is electrically connected to the third low voltage input terminal.

[0196] Optionally, the second output circuit includes an output transistor, and the pull-up node control circuit includes a third transistor and a first capacitor;

[0197] The control electrode of the output transistor is electrically connected to the pull-up node, the first electrode of the output transistor is electrically connected to the first high voltage input terminal, and the second electrode of the output transistor is electrically connected to the drive signal output terminal;

[0198] The control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the second high voltage input terminal, and the second electrode of the third transistor is electrically connected to the pull-up node;

[0199] The first plate of the first capacitor is electrically connected to the pull-up node, and the second plate of the first capacitor is electrically connected to the first high voltage input terminal.

[0200] Optionally, the third node reset circuit includes a fourth transistor;

[0201] The control electrode of the fourth transistor is electrically connected to the reset line, the first electrode of the fourth transistor is electrically connected to the third high voltage input terminal, and the second electrode of the fourth transistor is electrically connected to the third node.

[0202] Optionally, the fourth node control circuit includes a fifth transistor;

[0203] The control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the fourth high voltage input terminal, and the second electrode of the fifth transistor is electrically connected to the fourth node.

[0204] Optionally, the pull-down node control circuit includes a sixth transistor;

[0205] The control electrode of the sixth transistor is electrically connected to the fourth low voltage input terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the pull-down node.

[0206] Optionally, the fifth node control circuit includes a seventh transistor and a second capacitor; the pull-up node control circuit further includes an eighth transistor;

[0207] The control electrode of the seventh transistor is electrically connected to the second node, the first electrode of the seventh transistor is electrically connected to the second clock signal line, and the second electrode of the seventh transistor is electrically connected to the fifth node;

[0208] The first plate of the second capacitor is electrically connected to the second node, and the second plate of the second capacitor is electrically connected to the fifth node;

[0209] The control electrode of the eighth transistor is electrically connected to the second clock signal line, the first electrode of the eighth transistor is electrically connected to the fifth node, and the second electrode of the eighth transistor is electrically connected to the pull-up node.

[0210] Optionally, the first node control circuit further includes a ninth transistor;

[0211] The control electrode of the ninth transistor is electrically connected to the third node, the first electrode of the ninth transistor is electrically connected to the first clock signal line, and the second electrode of the ninth transistor is electrically connected to the first node;

[0212] The fourth node control circuit further includes a tenth transistor and a third capacitor;

[0213] The control electrode of the tenth transistor is electrically connected to the pull-down node, the first electrode of the tenth transistor is electrically connected to the second clock signal line, and the second electrode of the tenth transistor is electrically connected to the fourth node;

[0214] A first plate of a third capacitor is electrically connected to the pull-down node, and a second plate of the third capacitor is electrically connected to the fourth node;

[0215] The third node control circuit includes an eleventh transistor;

[0216] The control electrode of the eleventh transistor is electrically connected to the first clock signal line, the first electrode of the eleventh transistor is electrically connected to the starting voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the third node.

[0217] As shown in FIG7 , based on at least one embodiment of the driving circuit shown in FIG6 , the first node control circuit includes a first transistor T1 , and the second node control circuit includes a second transistor T2 ;

[0218] The gate of the first transistor T1 is electrically connected to the first clock signal line CK, the source of the first transistor T1 is electrically connected to the second low voltage input terminal VL2, and the drain of the first transistor T1 is electrically connected to the first node N1;

[0219] The gate of the second transistor T2 is electrically connected to the first low voltage input terminal VL1, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the second node N2;

[0220] The first output circuit includes an output reset transistor Tf;

[0221] The gate of the output reset transistor Tf is electrically connected to the pull-down node PD, the source of the output reset transistor Tf is electrically connected to the drive signal output terminal O1, and the drain of the output reset transistor Tf is electrically connected to the third low voltage input terminal VL3;

[0222] The second output circuit includes an output transistor To, and the pull-up node control circuit includes a third transistor T3 and a first capacitor C1;

[0223] The gate of the output transistor To is electrically connected to the pull-up node PU, the source of the output transistor To is electrically connected to the first high voltage input terminal VH1, and the drain of the output transistor To is electrically connected to the drive signal output terminal O1;

[0224] The gate of the third transistor T3 is electrically connected to the third node N3, the source of the third transistor T3 is electrically connected to the second high voltage input terminal VH2, and the drain of the third transistor T3 is electrically connected to the pull-up node PU;

[0225] The first plate of the first capacitor C1 is electrically connected to the pull-up node PU, and the second plate of the first capacitor C1 is electrically connected to the first high voltage input terminal VH1;

[0226] The third node reset circuit includes a fourth transistor T4;

[0227] The gate of the fourth transistor T4 is electrically connected to the reset line VEL, the source of the fourth transistor T4 is electrically connected to the third high voltage input terminal VH3, and the drain of the fourth transistor T4 is electrically connected to the third node N3;

[0228] The fourth node control circuit includes a fifth transistor T5;

[0229] The gate of the fifth transistor T5 is electrically connected to the first node N1, the source of the fifth transistor T5 is electrically connected to the fourth high voltage input terminal VH4, and the drain of the fifth transistor T5 is electrically connected to the fourth node N4;

[0230] The pull-down node control circuit includes a sixth transistor T6;

[0231] The gate of the sixth transistor T6 is electrically connected to the fourth low voltage input terminal VL4, the source of the sixth transistor T6 is electrically connected to the third node N3, and the drain of the sixth transistor T6 is electrically connected to the pull-down node PD;

[0232] The fifth node control circuit includes a seventh transistor T7 and a second capacitor C2; the pull-up node control circuit also includes an eighth transistor T8;

[0233] The gate of the seventh transistor T7 is electrically connected to the second node N2, the source of the seventh transistor T7 is electrically connected to the second clock signal line CB, and the drain of the seventh transistor T7 is electrically connected to the fifth node N5;

[0234] The first plate of the second capacitor C2 is electrically connected to the second node N2, and the second plate of the second capacitor C2 is electrically connected to the fifth node N5;

[0235] The gate of the eighth transistor T8 is electrically connected to the second clock signal line CB, the source of the eighth transistor T8 is electrically connected to the fifth node N5, and the drain of the eighth transistor T8 is electrically connected to the pull-up node PU;

[0236] The first node control circuit further includes a ninth transistor T9;

[0237] The gate of the ninth transistor T9 is electrically connected to the third node N3, the source of the ninth transistor T9 is electrically connected to the first clock signal line CK, and the drain of the ninth transistor T9 is electrically connected to the first node N1;

[0238] The fourth node control circuit further includes a tenth transistor T10 and a third capacitor C3;

[0239] The gate of the tenth transistor T10 is electrically connected to the pull-down node PD, the source of the tenth transistor T10 is electrically connected to the second clock signal line CB, and the drain of the tenth transistor T10 is electrically connected to the fourth node N4;

[0240] A first plate of the third capacitor C3 is electrically connected to the pull-down node PD, and a second plate of the third capacitor C3 is electrically connected to the fourth node N4;

[0241] The third node control circuit includes an eleventh transistor T11;

[0242] A gate of the eleventh transistor T11 is electrically connected to the first clock signal line CK, a source of the eleventh transistor T11 is electrically connected to the starting voltage terminal STV, and a drain of the eleventh transistor T11 is electrically connected to the third node N3.

[0243] In at least one embodiment of the driving circuit shown in FIG7 , all transistors are p-type transistors, but the present invention is not limited thereto. In actual operation, the transistors in FIG7 may also be n-type transistors.

[0244] In at least one embodiment of the driving circuit shown in FIG7 , the first low voltage input terminal VL1 may provide a first low voltage signal, the second low voltage input terminal VL2 may provide a second low voltage signal, the third low voltage input terminal VL3 may provide a first low voltage signal, and the fourth low voltage input terminal VL4 may provide a first low voltage signal; or

[0245] The first low voltage input terminal VL1 can provide a second low voltage signal, the second low voltage input terminal VL2 can provide a second low voltage signal, the third low voltage input terminal VL3 can provide a first low voltage signal, and the fourth low voltage input terminal VL4 can provide a second low voltage signal; or,

[0246] The first low voltage input terminal VL1 can provide a first low voltage signal, the second low voltage input terminal VL2 can provide a first low voltage signal, the third low voltage input terminal VL3 can provide a first low voltage signal, and the fourth low voltage input terminal VL4 can provide a second low voltage signal; or,

[0247] The first low voltage input terminal VL1 can provide a second low voltage signal, the second low voltage input terminal VL2 can provide a first low voltage signal, the third low voltage input terminal VL3 can provide a first low voltage signal, and the fourth low voltage input terminal VL4 can provide a first low voltage signal; or,

[0248] The first low voltage input terminal VL1 can provide a second low voltage signal, the second low voltage input terminal VL2 can provide a first low voltage signal, the third low voltage input terminal VL3 can provide a first low voltage signal, and the fourth low voltage input terminal VL4 can provide a second low voltage signal; or,

[0249] The first low voltage input terminal VL1 can provide a second low voltage signal, the second low voltage input terminal VL2 can provide a second low voltage signal, the third low voltage input terminal VL3 can provide a second low voltage signal, and the fourth low voltage input terminal VL4 can provide a first low voltage signal; or,

[0250] The first low voltage input terminal VL1 can provide a first low voltage signal, the second low voltage input terminal VL2 can provide a second low voltage signal, the third low voltage input terminal VL3 can provide a second low voltage signal, and the fourth low voltage input terminal VL4 can provide a first low voltage signal; or,

[0251] The first low voltage input terminal VL1 can provide a first low voltage signal, the second low voltage input terminal VL2 can provide a first low voltage signal, the third low voltage input terminal VL3 can provide a second low voltage signal, and the fourth low voltage input terminal VL4 can provide a first low voltage signal;

[0252] But it is not limited to this.

[0253] In at least one embodiment of the driving circuit shown in FIG7 ,

[0254] The first high voltage input terminal VH1 can provide a first high voltage signal, the second high voltage input terminal VH2 can provide a second high voltage signal, the third high voltage input terminal VH3 can provide a second high voltage signal, and the fourth high voltage input terminal VH4 can provide a first high voltage signal; or,

[0255] The first high voltage input terminal VH1 can provide a first high voltage signal, the second high voltage input terminal VH2 can provide a second high voltage signal, the third high voltage input terminal VH3 can provide a first high voltage signal, and the fourth high voltage input terminal VH4 can provide a first high voltage signal; or,

[0256] The first high voltage input terminal VH1 can provide a first high voltage signal, the second high voltage input terminal VH2 can provide a second high voltage signal, the third high voltage input terminal VH3 can provide a first high voltage signal, and the fourth high voltage input terminal VH4 can provide a second high voltage signal; or,

[0257] The first high voltage input terminal VH1 can provide a second high voltage signal, the second high voltage input terminal VH2 can provide a first high voltage signal, the third high voltage input terminal VH3 can provide a second high voltage signal, and the fourth high voltage input terminal VH4 can provide a first high voltage signal; or,

[0258] The first high voltage input terminal VH1 can provide a second high voltage signal, the second high voltage input terminal VH2 can provide a first high voltage signal, the third high voltage input terminal VH3 can provide a first high voltage signal, and the fourth high voltage input terminal VH4 can provide a first high voltage signal; or,

[0259] The first high voltage input terminal VH1 can provide a second high voltage signal, the second high voltage input terminal VH2 can provide a first high voltage signal, the third high voltage input terminal VH3 can provide a first high voltage signal, and the fourth high voltage input terminal VH4 can provide a second high voltage signal;

[0260] But it is not limited to this.

[0261] As shown in FIG8A , based on at least one embodiment of the driving circuit shown in FIG7 , the first low voltage input terminal VL1 provides a first low voltage signal, the second low voltage input terminal VL2 provides a second low voltage signal, the third low voltage input terminal VL3 provides a first low voltage signal, and the fourth low voltage input terminal VL4 provides a first low voltage signal; the first low voltage signal is provided by a first low voltage line VGL, and the second low voltage signal is provided by a second low voltage line VGL2;

[0262] The first high voltage input terminal VH1 provides a first high voltage signal, the second high voltage input terminal VH2 provides a second high voltage signal, the third high voltage input terminal VH3 provides a second high voltage signal, and the fourth high voltage input terminal VH4 provides a first high voltage signal; the first high voltage signal is provided by the first high voltage line VGH, and the second high voltage signal is provided by the second high voltage line VGH2.

[0263] When at least one embodiment of the driving circuit shown in Figure 8A of the present disclosure is in operation, the voltage value of the second low voltage signal provided by VGL2 can be lower than the voltage value of the first low voltage signal provided by VGL. For example, when the voltage value of the first low voltage signal provided by VGL is -6V, the voltage value of the second low voltage signal provided by VGL2 can be -6.5V. Since there is a threshold voltage loss when the p-type transistor transmits a low level, the voltage value of can be set to a voltage value lower than that of, so that when T1 and T2 are turned on, the potential of N1 and the potential of N2 can be lower, so that the pull-up node PU is turned on faster and the Delay of the driving signal output by O1 is smaller.

[0264] In at least one embodiment of the present disclosure, a difference between the voltage value of the second low voltage signal and the voltage value of the first low voltage signal may be slightly greater than or equal to a threshold voltage of the p-type transistor.

[0265] At least one embodiment of the driving circuit shown in FIG8A of the present disclosure employs two high voltage input terminals and two low voltage input terminals;

[0266] When performing low-frequency display, the voltage value of the high-voltage signal provided by a high-voltage input terminal and the absolute value of the voltage value of the low-voltage signal provided by a low-voltage input terminal can be appropriately reduced to reduce power consumption;

[0267] For example, when performing low-frequency display, the voltage value of the first high voltage signal and the voltage value of the first low voltage signal can be controlled to remain unchanged, but the voltage value of the second high voltage signal can be reduced from 7V to 6V, and the voltage value of the second low voltage signal can be adjusted from -7V to -6V to reduce power consumption.

[0268] When working, at least one embodiment of the driving circuit shown in Figure 8A of the present disclosure can adjust the voltage value of the second high voltage signal from 7V to 10V and the voltage value of the second low voltage signal from -7V to -10V to improve the switching capabilities of To and Tf.

[0269] As shown in FIG9 , based on at least one embodiment of the driving circuit shown in FIG7 , the first low voltage input terminal VL1 provides a second low voltage signal, the second low voltage input terminal VL2 provides a second low voltage signal, the third low voltage input terminal VL3 provides a first low voltage signal, and the fourth low voltage input terminal VL4 provides a second low voltage signal; the first low voltage signal is provided by a first low voltage line VGL, and the second low voltage signal is provided by a second low voltage line VGL2;

[0270] The first high voltage input terminal VH1 provides a first high voltage signal, the second high voltage input terminal VH2 provides a second high voltage signal, the third high voltage input terminal VH3 provides a second high voltage signal, and the fourth high voltage input terminal VH4 provides a first high voltage signal; the first high voltage signal is provided by the first high voltage line VGH, and the second high voltage signal is provided by the second high voltage line VGH2.

[0271] In at least one embodiment of the present disclosure, the voltage value of VGH2 may be greater than the voltage value of VGH1 to compensate for leakage effects caused by threshold voltage drift, but the present invention is not limited thereto.

[0272] In at least one embodiment of the driving circuit shown in FIG. 9 , the gates of T2 and T6 are both electrically connected to the second low voltage line VGL2 providing the second low voltage signal, which facilitates layout and improves space utilization.

[0273] The difference between at least one embodiment of the driving circuit shown in FIG. 10 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 8A of the present disclosure is that T4 is not provided.

[0274] The difference between at least one embodiment of the driving circuit shown in FIG. 11 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 9 of the present disclosure is that T4 is not provided.

[0275] The difference between at least one embodiment of the driving circuit shown in FIG. 12 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 8A of the present disclosure is that the source of To is electrically connected to the second high voltage line VGH2 , and the source of T3 is electrically connected to the first high voltage line VGH.

[0276] The difference between at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 12 of the present disclosure is that the source of T4 is electrically connected to the first high voltage line VGH.

[0277] The difference between at least one embodiment of the driving circuit shown in FIG. 14 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure is that the source of T5 is electrically connected to the second high voltage line VGH2 .

[0278] The difference between at least one embodiment of the driving circuit shown in FIG. 15 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 14 of the present disclosure is that the source of T4 is electrically connected to the second high voltage line VGH2 .

[0279] The difference between at least one embodiment of the driving circuit shown in FIG. 16 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 12 of the present disclosure is that the gates of T2 and T6 are both electrically connected to the second low voltage line VGL2 .

[0280] The difference between at least one embodiment of the driving circuit shown in FIG. 17 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 16 of the present disclosure is that the gate of T2 is electrically connected to the first low voltage line VGL.

[0281] The difference between at least one embodiment of the driving circuit shown in FIG. 18 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 16 of the present disclosure is that the gate of T6 is electrically connected to the first low voltage line VGL.

[0282] The difference between at least one embodiment of the driving circuit shown in FIG. 19A of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 15 of the present disclosure is that T4 is not included.

[0283] The driving circuit according to at least one embodiment of the present disclosure includes a second output circuit and a pull-up node control circuit;

[0284] The second output circuit is electrically connected to the pull-up node, the first high voltage input terminal and the drive signal output terminal respectively, and is used to control the connection between the first high voltage input terminal and the drive signal output terminal under the control of the potential of the pull-up node;

[0285] The pull-up node control circuit is electrically connected to the third node, the second high voltage input terminal and the pull-up node respectively, and is used to control the connection between the second high voltage input terminal and the pull-up node under the control of the potential of the third node;

[0286] The first high voltage input terminal is different from the second high voltage input terminal.

[0287] In at least one embodiment of the present disclosure, the driving circuit further includes a third node reset circuit;

[0288] The third node reset circuit is electrically connected to the reset line, the third high voltage input terminal and the third node respectively, and is used to control the connection between the third high voltage input terminal and the third node under the control of the reset signal provided by the reset line;

[0289] The third high voltage input terminal is different from at least one of the first high voltage input terminal and the second high voltage input terminal.

[0290] In at least one embodiment of the present disclosure, the driving circuit further includes a fourth node control circuit;

[0291] The fourth node control circuit is electrically connected to the first node, the fourth node and the fourth high voltage input terminal respectively, and is used to control the connection between the fourth node and the fourth high voltage input terminal under the control of the potential of the first node;

[0292] The fourth high voltage input terminal is different from at least one of the first high voltage input terminal and the second high voltage input terminal.

[0293] In at least one embodiment of the present disclosure, the driving circuit further includes a fourth node control circuit;

[0294] The fourth node control circuit is electrically connected to the first node, the fourth node and the fourth high voltage input terminal respectively, and is used to control the connection between the fourth node and the fourth high voltage input terminal under the control of the potential of the first node;

[0295] The fourth high voltage input terminal is different from the third high voltage input terminal.

[0296] The embodiment of the present disclosure further provides a display panel, comprising the above-mentioned driving circuit; the display panel further comprises a display driving chip;

[0297] The first high voltage input terminal is electrically connected to the first high voltage line, and the second high voltage input terminal is electrically connected to the second high voltage line; the first high voltage line and the second high voltage line are respectively electrically connected to different pins of the display driver chip, and the display driver chip is used to provide a first high voltage signal for the first high voltage line, and the display driver chip is used to provide a second high voltage signal for the second high voltage line.

[0298] In the display panel described in the embodiment of the present disclosure, the first high voltage input terminal is electrically connected to the first high voltage line, the second high voltage input terminal is electrically connected to the second high voltage line, the first high voltage line is electrically connected to the first pin of the display driver chip, and the second high voltage line is electrically connected to the second pin of the display driver chip. The display driver chip provides a first high voltage signal to the first high voltage line through the first pin, and the display driver chip provides a second high voltage signal to the second high voltage line through the second pin.

[0299] As shown in FIG19B , the display panel includes a display driver chip 320 ;

[0300] The first high voltage input terminal VH1 is electrically connected to the first high voltage line LH1, and the second high voltage input terminal VH2 is electrically connected to the second high voltage line LH2;

[0301] The first high voltage line LH1 is electrically connected to the first pin P1 of the display driver chip 320 , and the second high voltage line LH2 is electrically connected to the second pin P2 of the display driver chip 320 ;

[0302] The display driver chip 320 is used to provide a first high voltage signal to the first high voltage line LH1 , and the display driver chip 320 is used to provide a second high voltage signal to the second high voltage line LH2 .

[0303] As shown in FIG20 , the relevant pixel circuit includes a first display control transistor M1, a second display control transistor M2, a third display control transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, an eighth display control transistor M8, a storage capacitor C0, and an organic light emitting diode E1;

[0304] In Figure 20, the line labeled EM is the light-emitting control line, the line labeled R1 is the first reset control line, the line labeled R2 is the second reset control line, the line labeled NG is the first scanning line, the line labeled PG is the second scanning line, the line labeled Vi1 is the first initial voltage, the line labeled Vi2 is the second initial voltage, the line labeled Vi3 is the third initial voltage, the line labeled VDD is the high level end, and the line labeled VSS is the low level end.

[0305] The driving circuit described in at least one embodiment of the present disclosure can be used to provide a first scan signal for the first scan line NG, a light control signal for the light control line EM, a first reset control signal for the first reset control line R1, and a second reset control signal for the second reset control line R2.

[0306] The driving circuit according to at least one embodiment of the present disclosure includes a first transistor, a second transistor, an output reset transistor and a sixth transistor;

[0307] The control electrode of the first transistor is electrically connected to the first clock signal line, the first electrode of the first transistor is electrically connected to the second low voltage input terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0308] The control electrode of the second transistor is electrically connected to the first low voltage input terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node;

[0309] The first output circuit includes an output reset transistor, a control electrode of the output reset transistor is electrically connected to the pull-down node, a first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and a second electrode of the output reset transistor is electrically connected to the third low voltage input terminal;

[0310] The control electrode of the sixth transistor is electrically connected to the fourth low voltage input terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the pull-down node;

[0311] The first low voltage input terminal, the second low voltage input terminal, the third low voltage input terminal and the fourth low voltage input terminal are not completely the same.

[0312] In at least one embodiment of the present disclosure, the first low voltage input terminal VL1, the second low voltage input terminal VL2, the third low voltage input terminal VL3 and the fourth low voltage input terminal VL4 are not completely the same, as follows:

[0313] VL1 and VL2 are not the same; or,

[0314] VL1 and VL3 are not the same; or,

[0315] VL1 and VL4 are not the same; or,

[0316] VL2 and VL3 are not the same; or,

[0317] VL2 is not the same as VL4; or,

[0318] VL3 and VL4 are not the same; or,

[0319] VL1, VL2 and VL3 are different from each other; or,

[0320] VL1, VL2 and VL4 are different from each other; or,

[0321] VL1, VL3 and VL4 are different from each other; or,

[0322] VL2, VL3 and VL4 are different from each other; or,

[0323] VL1, VL2, VL3 and VL4 are different from each other.

[0324] The driving circuit according to at least one embodiment of the present disclosure includes an output transistor, a third transistor, a fourth transistor, and a fifth transistor;

[0325] The control electrode of the output transistor is electrically connected to the pull-up node, the first electrode of the output transistor is electrically connected to the first high voltage input terminal, and the second electrode of the output transistor is electrically connected to the drive signal output terminal;

[0326] The control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the second high voltage input terminal, and the second electrode of the third transistor is electrically connected to the pull-up node;

[0327] The control electrode of the fourth transistor is electrically connected to the reset line, the first electrode of the fourth transistor is electrically connected to the third high voltage input terminal, and the second electrode of the fourth transistor is electrically connected to the third node;

[0328] The control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the fourth high voltage input terminal, and the second electrode of the fifth transistor is electrically connected to the fourth node;

[0329] The first high voltage input terminal, the second high voltage input terminal, the third high voltage input terminal and the fourth high voltage input terminal are not completely the same.

[0330] In at least one embodiment of the present disclosure, the first high voltage input terminal VH1, the second high voltage input terminal VH2, the third high voltage input terminal VH3, and the fourth high voltage input terminal VH4 are not completely the same, specifically as follows:

[0331] VH1 and VH2 are not identical; or,

[0332] VH1 and VH3 are not identical; or,

[0333] VH1 and VH4 are not identical; or,

[0334] VH2 and VH3 are not identical; or,

[0335] VH2 and VH4 are not identical; or,

[0336] VH3 and VH4 are not identical; or,

[0337] VH1, VH2 and VH3 are different from each other; or,

[0338] VH1, VH2 and VH4 are different from each other; or,

[0339] VH1, VH3 and VH4 are different from each other; or,

[0340] VH2, VH3 and VH4 are different from each other; or,

[0341] VH1, VH2, VH3 and VH4 are different from each other.

[0342] The display substrate described in the embodiment of the present disclosure includes a base substrate and the above-mentioned driving circuit disposed on the base substrate.

[0343] Optionally, the driving circuit includes a first low voltage line, a second low voltage line, a first high voltage line, a second high voltage line, a first node control circuit, a second node control circuit, a first output circuit, a second output circuit, a pull-up node control circuit, a fourth node control circuit, a pull-down node control circuit, a fifth node control circuit, and a third node control circuit;

[0344] The second low-voltage line is arranged on a side of the driving circuit away from the display area, and the first low-voltage line is arranged on a side of the driving circuit close to the display area;

[0345] The first high voltage line and the second high voltage line are provided between a first circuit portion included in the driving circuit and a second circuit portion included in the driving circuit;

[0346] The first circuit portion includes a first node control circuit, a second node control circuit, a pull-up node control circuit, a fourth node control circuit, a pull-down node control circuit, a fifth node control circuit, and a third node control circuit, and the second circuit portion includes a first output circuit and a second output circuit;

[0347] The first circuit portion is arranged between the second low voltage line and the second high voltage line, and the second circuit portion is arranged between the first high voltage line and the first low voltage line, so that the electrodes of each transistor in the driving circuit are electrically connected to the corresponding voltage line.

[0348] In at least one embodiment of the present disclosure, the driving circuit further includes a third node reset circuit, and the first circuit portion includes the third node reset circuit. FIG21 is a layout diagram of at least one embodiment of the driving circuit shown in FIG15 of the present disclosure.

[0349] Figure 22 is a layout diagram of the active layer in Figure 21, Figure 23 is a layout diagram of the first gate metal layer in Figure 21, Figure 24 is a layout diagram of the second gate metal layer in Figure 21, and Figure 25 is a layout diagram of the source and drain metal layers in Figure 21.

[0350] In Figures 21 and 25, the line labeled ESTV is the start signal line, the line labeled CB is the second clock signal line, the line labeled CK is the first clock signal line, the line labeled VEL is the reset line, the line labeled VGL2 is the first low voltage line, the line labeled VGH2 is the second high voltage line, the line labeled VGH is the first high voltage line, and the line labeled VGL is the first low voltage line.

[0351] As shown in FIG21 , the start signal line ESTV, the second clock signal line CB, the first clock signal line CK, the reset line VEL, the second low voltage line VGL2, the second high voltage line VGH2, the first high voltage line VGH and the first low voltage line VGL all extend in the vertical direction;

[0352] The start signal line ESTV, the second clock signal line CB, the first clock signal line CK, the reset line VEL and the second low voltage line VGL2 are arranged on a side of the driving circuit away from the display area;

[0353] The start signal line ESTV, the second clock signal line CB, the first clock signal line CK, the reset line VEL and the second low voltage line VGL2 are arranged in a direction close to the display area.

[0354] The first low voltage line VGL is arranged on a side of the driving circuit close to the display area;

[0355] As shown in FIG25 , the first high voltage line VGH is connected to the first electrode So of To, and the second high voltage line VGH2 is arranged on a side of the first high voltage line VGH away from To;

[0356] The first low voltage line VGL is connected to the second electrode Df of Tf.

[0357] In at least one embodiment corresponding to FIG21 , the driving circuit includes a first circuit portion and a second circuit portion; the first circuit portion includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11; and the second circuit portion includes an output transistor To and an output reset transistor Tf;

[0358] The first circuit portion is disposed between the second low voltage line VGL2 and the second high voltage line VGH2 , and the second circuit portion is disposed between the second high voltage line VGH2 and the first low voltage line VGL.

[0359] As shown in FIG21 to FIG25 , T2 and T6 are adjacent to VGL2 , so that the gate G2 of T2 and the gate G6 of T6 are electrically connected to VGL;

[0360] T1 is adjacent to VGL2 so that a first electrode of T1 is electrically connected to VGL2.

[0361] In FIG23 , G1 is the gate of T1, G2 is the gate of T2, G3 is the gate of T3, G4 is the gate of T4, G5 is the gate of T5, G6 is the gate of T6, G7 is the gate of T7, G8 is the gate of T8, G9 is the gate of T9, G10 is the gate of T10, G11 is the gate of T11, Go is the gate of To, and Gf is the gate of Tf.

[0362] In FIG23 , the first electrode plate of C2 is labeled C2a, and in FIG24 , the second electrode plate of C2 is labeled C2b;

[0363] In FIG23 , the first electrode plate of C3 is labeled C3a, and in FIG24 , the second electrode plate of C3 is labeled C3b;

[0364] In FIG23 , the first electrode plate of C1 is labeled C1a, and in FIG24 , the second electrode plate of C2 is labeled C1b.

[0365] As shown in FIG. 21 to FIG. 25 , the gate G4 of T4 is electrically connected to VEL, the first electrode of T4 is electrically connected to VGH2 through a via hole, and the first electrode of T5 is electrically connected to VGH2 through a via hole.

[0366] In FIG22 , A1 is the active layer pattern of T1, A2 is the active layer pattern of T2, A3 is the active layer pattern of T3, A4 is the active layer pattern of T4, A5 is the active layer pattern of T5, A6 is the active layer pattern of T6, A7 is the active layer pattern of T7, A8 is the active layer pattern of T8, A9 is the active layer pattern of T9, A10 is the active layer pattern of T10, A11 is the active layer pattern of T11, and A0 is the first active layer pattern;

[0367] The first active layer pattern A0 includes an active layer pattern of To and an active layer pattern of Tf.

[0368] FIG. 26 is a layout diagram of at least one embodiment of the driving circuit shown in FIG. 19 of the present disclosure.

[0369] The difference between the layout diagram shown in FIG26 and at least one embodiment of the driving circuit shown in FIG21 is that T4 is not included.

[0370] Figure 27 is a layout diagram of the active layer in Figure 26, Figure 28 is a layout diagram of the first gate metal layer in Figure 26, Figure 29 is a layout diagram of the second gate metal layer in Figure 26, and Figure 30 is a layout diagram of the source and drain metal layers in Figure 26.

[0371] The display panel according to the embodiment of the present disclosure includes the above-mentioned driving circuit; the display panel also includes a display driving chip;

[0372] The first low voltage input terminal is electrically connected to the first low voltage line, the second low voltage input terminal is electrically connected to the second low voltage line, and the third low voltage input terminal is electrically connected to the third low voltage line. The first low voltage line, the second low voltage line, and the third low voltage line are electrically connected to different pins of the display driver chip, respectively. The display driver chip is used to provide a first low voltage signal for the first low voltage line, a second low voltage signal for the second low voltage line, and a third low voltage signal for the third low voltage line; or

[0373] The first low voltage input terminal is electrically connected to the first low voltage line, the second low voltage input terminal and the third low voltage input terminal are both electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal to the first low voltage line and provide a second low voltage signal to the second low voltage line; or

[0374] The first low voltage input terminal and the second low voltage input terminal are both electrically connected to the first low voltage line, the third low voltage input terminal is electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal to the first low voltage line and provide a second low voltage signal to the second low voltage line; or

[0375] The first low voltage input terminal and the third low voltage input terminal are both electrically connected to the first low voltage line, the second low voltage input terminal is electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are respectively electrically connected to different pins of the display driver chip, and the display driver chip is used to provide a first low voltage signal for the first low voltage line and provide a second low voltage signal for the second low voltage line.

[0376] As shown in FIG31 , the display panel includes a display driver chip 320 ;

[0377] The first low voltage input terminal VL1 is electrically connected to the first low voltage line Ld1, the second low voltage input terminal VL2 is electrically connected to the second low voltage line Ld2, and the third low voltage input terminal VL3 is electrically connected to the third low voltage line Ld3. The first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320, the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320, and the third low voltage line Ld3 is electrically connected to the third pin P3 of the display driver chip 320.

[0378] The display driver chip 320 is configured to provide a first low voltage signal to the first low voltage line Ld1 , a second low voltage signal to the second low voltage line Ld2 , and a third low voltage signal to the third low voltage line Ld3 .

[0379] As shown in FIG32 , the display panel includes a display driver chip 320 ;

[0380] The first low voltage input terminal VL1 is electrically connected to the first low voltage line Ld1, and the second low voltage input terminal VL2 and the third low voltage input terminal VL3 are both electrically connected to the second low voltage line Ld2;

[0381] The first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320 , and the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320 ;

[0382] The display driver chip 320 is configured to provide a first low voltage signal to the first low voltage line Ld1 and a second low voltage signal to the second low voltage line Ld2 .

[0383] As shown in FIG33 , the display panel includes a display driver chip 320 ;

[0384] The first low voltage input terminal VL1 and the second low voltage input terminal VL2 are both electrically connected to the first low voltage line Ld1, and the third low voltage input terminal VL3 is electrically connected to the second low voltage line Ld2;

[0385] The first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320 , and the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320 ;

[0386] The display driver chip 320 is configured to provide a first low voltage signal to the first low voltage line Ld1 and a second low voltage signal to the second low voltage line Ld2 .

[0387] As shown in FIG34 , the display panel includes a display driver chip 320 ;

[0388] The first low voltage input terminal VL1 and the third low voltage input terminal VL3 are both electrically connected to the first low voltage line Ld1, and the second low voltage input terminal VL2 is electrically connected to the second low voltage line Ld2;

[0389] The first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320 , and the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320 ;

[0390] The display driver chip 320 is configured to provide a first low voltage signal to the first low voltage line Ld1 and a second low voltage signal to the second low voltage line Ld2 .

[0391] The display panel described in the embodiment of the present disclosure includes the above-mentioned driving circuit; the display panel also includes a display driving chip;

[0392] The first high voltage input terminal is electrically connected to the first high voltage line, and the second high voltage input terminal is electrically connected to the second high voltage line; the first high voltage line and the second high voltage line are respectively electrically connected to different pins of the display driver chip, and the display driver chip is used to provide a first high voltage signal for the first high voltage line, and the display driver chip is used to provide a second high voltage signal for the second high voltage line.

[0393] As shown in FIG35 , the display panel includes a display driver chip 320 ;

[0394] The first low voltage input terminal VL1 and the third low voltage input terminal VL3 are both electrically connected to the first low voltage line Ld1, and the second low voltage input terminal VL2 is electrically connected to the second low voltage line Ld2;

[0395] The first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320 , and the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320 ;

[0396] The display driver chip 320 is configured to provide a first low voltage signal to the first low voltage line Ld1 and a second low voltage signal to the second low voltage line Ld2 .

[0397] The display device described in the embodiment of the present disclosure includes the above-mentioned driving circuit.

[0398] The display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0399] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A driving circuit comprising a first node control circuit, a second node control circuit, and a first output circuit; The second node control circuit is electrically connected to the first low voltage input terminal, the first node, and the second node, respectively, and is configured to control the connection between the first node and the second node under the control of a low voltage signal provided by the first low voltage input terminal; The first node control circuit is electrically connected to the second low voltage input terminal, the first clock signal line and the first node respectively, and is used to control the first node to be electrically connected to the second low voltage input terminal under the control of the first clock signal provided by the first clock signal line; The first output circuit is electrically connected to the pull-down node, the drive signal output terminal and the third low voltage input terminal respectively, and is used to control the connection between the drive signal output terminal and the third low voltage input terminal under the control of the potential of the pull-down node; At least two of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal are different from each other.

2. The driving circuit according to claim 1, wherein: Also comprising a second output circuit and a fourth node control circuit; The second output circuit is electrically connected to the pull-up node, the first high voltage input terminal and the drive signal output terminal respectively, and is used to control the connection between the first high voltage input terminal and the drive signal output terminal under the control of the potential of the pull-up node; The fourth node control circuit is electrically connected to the first node, the fourth node and the fourth high voltage input terminal respectively, and is used to control the connection between the fourth node and the fourth high voltage input terminal under the control of the potential of the first node; The first high voltage input terminal is different from the fourth high voltage input terminal.

3. The driving circuit according to claim 2, wherein: Also included is a third node reset circuit; The third node reset circuit is electrically connected to the reset line, the third high voltage input terminal and the third node respectively, and is used to control the connection between the third high voltage input terminal and the third node under the control of the reset signal provided by the reset line; The third high voltage input terminal is different from at least one of the first high voltage input terminal and the fourth high voltage input terminal.

4. The driving circuit according to claim 2, wherein: Also included is a pull-up node control circuit; The pull-up node control circuit is electrically connected to the third node, the second high voltage input terminal and the pull-up node respectively, and is used to control the connection between the second high voltage input terminal and the pull-up node under the control of the potential of the third node; The second high voltage input terminal is different from at least one of the first high voltage input terminal and the fourth high voltage input terminal.

5. The driving circuit according to claim 3, wherein: Also included is a pull-up node control circuit; The pull-up node control circuit is electrically connected to the third node, the second high voltage input terminal and the pull-up node respectively, and is used to control the connection between the second high voltage input terminal and the pull-up node under the control of the potential of the third node; The second high voltage input terminal is different from the third high voltage input terminal.

6. The driving circuit according to any one of claims 1 to 5, wherein: Also included is a pull-down node control circuit; The pull-down node control circuit is electrically connected to the fourth low voltage input terminal, the third node and the pull-down node respectively, and is used to control the connection between the third node and the pull-down node under the control of the low voltage signal provided by the fourth low voltage input terminal; The fourth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal.

7. The driving circuit according to any one of claims 2 to 5, wherein: Also included is a fifth node control circuit and a pull-up node control circuit; The fifth node control circuit is electrically connected to the second node, the fifth node, and the second clock signal line, respectively, and is configured to control the connection between the second clock signal line and the fifth node under the control of the potential of the second node, and to control the potential of the fifth node according to the potential of the second node; The pull-up node control circuit is also electrically connected to the fifth node, the second clock signal line and the pull-up node, respectively, and is used to control the connection between the fifth node and the pull-up node under the control of the second clock signal provided by the second clock signal line, and to maintain the potential of the pull-up node.

8. The driving circuit according to claim 4, wherein: The driving circuit further includes a third node control circuit; The third node control circuit is electrically connected to the starting voltage terminal, the first clock signal line and the third node respectively, and is used to control the connection between the starting voltage terminal and the third node under the control of the first clock signal provided by the first clock signal line; The first node control circuit is further electrically connected to the third node, the first node and the first clock signal line respectively, and is configured to control the connection between the first node and the first clock signal line under the control of the potential of the third node; The fourth node control circuit is also electrically connected to the pull-down node and the second clock signal line respectively, and is used to control the connection between the fourth node and the second clock signal line under the control of the potential of the pull-down node, and control the potential of the fourth node according to the potential of the pull-down node.

9. The driving circuit according to claim 1, wherein: The first node control circuit includes a first transistor, and the second node control circuit includes a second transistor; The control electrode of the first transistor is electrically connected to the first clock signal line, the first electrode of the first transistor is electrically connected to the second low voltage input terminal, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the first low voltage input terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node; The first output circuit includes an output reset transistor, a control electrode of the output reset transistor is electrically connected to the pull-down node, a first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and a second electrode of the output reset transistor is electrically connected to the third low voltage input terminal.

10. The driving circuit according to claim 4 or 5, wherein: The second output circuit includes an output transistor, and the pull-up node control circuit includes a third transistor and a first capacitor; The control electrode of the output transistor is electrically connected to the pull-up node, the first electrode of the output transistor is electrically connected to the first high voltage input terminal, and the second electrode of the output transistor is electrically connected to the drive signal output terminal; The control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the second high voltage input terminal, and the second electrode of the third transistor is electrically connected to the pull-up node; The first plate of the first capacitor is electrically connected to the pull-up node, and the second plate of the first capacitor is electrically connected to the first high voltage input terminal.

11. The driving circuit according to claim 3, wherein: The third node reset circuit includes a fourth transistor; The control electrode of the fourth transistor is electrically connected to the reset line, the first electrode of the fourth transistor is electrically connected to the third high voltage input terminal, and the second electrode of the fourth transistor is electrically connected to the third node.

12. The driving circuit according to claim 2, wherein: The fourth node control circuit includes a fifth transistor; The control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the fourth high voltage input terminal, and the second electrode of the fifth transistor is electrically connected to the fourth node.

13. The driving circuit according to claim 6, wherein: The pull-down node control circuit includes a sixth transistor; The control electrode of the sixth transistor is electrically connected to the fourth low voltage input terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the pull-down node.

14. The driving circuit according to claim 7, wherein: The fifth node control circuit includes a seventh transistor and a second capacitor; the pull-up node control circuit also includes an eighth transistor; The control electrode of the seventh transistor is electrically connected to the second node, the first electrode of the seventh transistor is electrically connected to the second clock signal line, and the second electrode of the seventh transistor is electrically connected to the fifth node; The first plate of the second capacitor is electrically connected to the second node, and the second plate of the second capacitor is electrically connected to the fifth node; The control electrode of the eighth transistor is electrically connected to the second clock signal line, the first electrode of the eighth transistor is electrically connected to the fifth node, and the second electrode of the eighth transistor is electrically connected to the pull-up node.

15. The driving circuit according to claim 8, wherein: The first node control circuit further includes a ninth transistor; The control electrode of the ninth transistor is electrically connected to the third node, the first electrode of the ninth transistor is electrically connected to the first clock signal line, and the second electrode of the ninth transistor is electrically connected to the first node; The fourth node control circuit further includes a tenth transistor and a third capacitor; The control electrode of the tenth transistor is electrically connected to the pull-down node, the first electrode of the tenth transistor is electrically connected to the second clock signal line, and the second electrode of the tenth transistor is electrically connected to the fourth node; A first plate of a third capacitor is electrically connected to the pull-down node, and a second plate of the third capacitor is electrically connected to the fourth node; The third node control circuit includes an eleventh transistor; The control electrode of the eleventh transistor is electrically connected to the first clock signal line, the first electrode of the eleventh transistor is electrically connected to the starting voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the third node.

16. A driving circuit comprising a first transistor, a second transistor, an output reset transistor and a sixth transistor; The control electrode of the first transistor is electrically connected to the first clock signal line, the first electrode of the first transistor is electrically connected to the second low voltage input terminal, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the first low voltage input terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node; The first output circuit includes an output reset transistor, a control electrode of the output reset transistor is electrically connected to the pull-down node, a first electrode of the output reset transistor is electrically connected to the drive signal output terminal, and a second electrode of the output reset transistor is electrically connected to the third low voltage input terminal; The control electrode of the sixth transistor is electrically connected to the fourth low voltage input terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the pull-down node; The first low voltage input terminal, the second low voltage input terminal, the third low voltage input terminal and the low voltage input terminal are not completely the same.

17. A driving circuit comprising an output transistor, a third transistor, a fourth transistor, and a fifth transistor; The control electrode of the output transistor is electrically connected to the pull-up node, the first electrode of the output transistor is electrically connected to the first high voltage input terminal, and the second electrode of the output transistor is electrically connected to the drive signal output terminal; The control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the second high voltage input terminal, and the second electrode of the third transistor is electrically connected to the pull-up node; The control electrode of the fourth transistor is electrically connected to the reset line, the first electrode of the fourth transistor is electrically connected to the third high voltage input terminal, and the second electrode of the fourth transistor is electrically connected to the third node; The control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the fourth high voltage input terminal, and the second electrode of the fifth transistor is electrically connected to the fourth node; The first high voltage input terminal, the second high voltage input terminal, the third high voltage input terminal and the fourth high voltage input terminal are not completely the same.

18. A display panel comprising the driving circuit according to any one of claims 1 to 15; the display panel further comprising a display driver chip; The first low voltage input terminal is electrically connected to the first low voltage line, the second low voltage input terminal is electrically connected to the second low voltage line, and the third low voltage input terminal is electrically connected to the third low voltage line. The first low voltage line, the second low voltage line, and the third low voltage line are electrically connected to different pins of the display driver chip, respectively. The display driver chip is used to provide a first low voltage signal for the first low voltage line, a second low voltage signal for the second low voltage line, and a third low voltage signal for the third low voltage line. or, The first low voltage input terminal is electrically connected to the first low voltage line, the second low voltage input terminal and the third low voltage input terminal are both electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal to the first low voltage line and provide a second low voltage signal to the second low voltage line; or The first low voltage input terminal and the second low voltage input terminal are both electrically connected to the first low voltage line, the third low voltage input terminal is electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal to the first low voltage line and provide a second low voltage signal to the second low voltage line; or The first low voltage input terminal and the third low voltage input terminal are both electrically connected to the first low voltage line, the second low voltage input terminal is electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are respectively electrically connected to different pins of the display driver chip, and the display driver chip is used to provide a first low voltage signal for the first low voltage line and provide a second low voltage signal for the second low voltage line.

19. A display panel comprising the driving circuit according to any one of claims 4 to 15; the display panel further comprising a display driver chip; The first high voltage input terminal is electrically connected to the first high voltage line, and the second high voltage input terminal is electrically connected to the second high voltage line; the first high voltage line and the second high voltage line are respectively electrically connected to different pins of the display driver chip, and the display driver chip is used to provide a first high voltage signal for the first high voltage line, and the display driver chip is used to provide a second high voltage signal for the second high voltage line.

20. A display substrate comprising a base substrate and the driving circuit according to any one of claims 1 to 17 disposed on the base substrate.

21. The display substrate according to claim 20, wherein: The driving circuit includes a first low voltage line, a second low voltage line, a first high voltage line, a second high voltage line, a first node control circuit, a second node control circuit, a first output circuit, a second output circuit, a pull-up node control circuit, a fourth node control circuit, a pull-down node control circuit, a fifth node control circuit and a third node control circuit; The second low-voltage line is arranged on a side of the driving circuit away from the display area, and the first low-voltage line is arranged on a side of the driving circuit close to the display area; The first high voltage line and the second high voltage line are provided between a first circuit portion included in the driving circuit and a second circuit portion included in the driving circuit; The first circuit portion includes a first node control circuit, a second node control circuit, a pull-up node control circuit, a fourth node control circuit, a pull-down node control circuit, a fifth node control circuit, and a third node control circuit, and the second circuit portion includes a first output circuit and a second output circuit; The first circuit portion is disposed between the second low voltage line and the second high voltage line, and the second circuit portion is disposed between the first high voltage line and the first low voltage line.

22. The display substrate according to claim 21, wherein The driving circuit further includes a third node reset circuit, and the first circuit portion includes the third node reset circuit.

23. A display device comprising the driving circuit according to any one of claims 1 to 17.

Images