Calculation apparatus, imaging apparatus, and calculation method

Abstract

The present disclosure provides a computing device equipped with a first signal line, a first capacitor connected to the first signal line, one or more sub-arrays connected to the first signal line, and a readout circuit for generating a digital signal corresponding to a charge of the first signal line, the subarray has a second signal line connected to the first signal line via a first switching element, a second capacitor connected to the second signal line, and one or more memory cells connected to the second signal line and capable of applying to the second signal line a charge corresponding to a signal value to be stored.

Description

Technical Field

[0001] The present disclosure relates to a computing device, an imaging device, and a computing method. Background Art

[0002] In recent years, processors that implement deep neural networks (DNNs) in hardware to perform calculations have been put into practical use in order to achieve advanced tasks such as image recognition and object position detection. However, since neural networks (DNNs) require a large amount of memory access, the power efficiency of von Neumann-type arithmetic units (e.g., DSPs) is poor. For this reason, as a calculation method for DNNs, computation in memory (CIM), which is a non-von Neumann-type arithmetic unit that performs operations on a memory array, has attracted much attention.

[0003] Reference List

[0004] Patent Literature

[0005] Patent document 1: Japanese patent application No. 2021-510774.

[0006] Patent document 2: JP 2020-113809A. Summary of the invention

[0007] Technical issues

[0008] Therefore, the present disclosure provides a computing device, an imaging device, and a computing method that are capable of performing calculations on a storage array at a higher speed.

[0009] Solution to the problem

[0010] In order to solve the above problems, the present disclosure provides a computing device, including: a first signal line; a first capacitor connected to the first signal line; at least one sub-array connected to the first signal line; and a readout circuit, generating a digital signal according to the charge of the first signal line, wherein the sub-array includes: a second signal line connected to the first signal line via a first switching element; a second capacitor connected to the second signal line; and at least one storage unit connected to the second signal line and capable of providing a charge corresponding to a signal value to be stored to the second signal line.

[0011] The first capacitor and the second capacitor may be parasitic capacitors formed in a metal layer of the semiconductor element.

[0012] A plurality of sub-arrays may be connected to the first signal line, and the second capacitance may be different for each sub-array.

[0013] The plurality of sub-arrays may be connected to the first signal line, and the second capacitor may be a variable capacitor.

[0014] The memory unit may be connected to the second signal line via the second switching element to provide the second signal line with charges corresponding to the signal value.

[0015] The second switching element can be composed of a single switching element, or by connecting a plurality of switching elements in series. One end of the second switching element can be connected to the second signal line. The second switching element can be turned on or off according to the stored data. A potential pulse signal can be provided from the other end of the second switching element, and a charge corresponding to the potential and pulse width of the potential pulse signal can be stored in the second capacitor.

[0016] The sub-array may have a plurality of memory cells, and the memory cell may be a static random access memory (SRAM) having a second switching element.

[0017] The computing device may have a mode in which the second signal line and the plurality of storage units are sequentially turned on at different timings, a mode in which the second signal line and the plurality of storage units are simultaneously turned on, and a mode in which the second signal line and the storage units are repeatedly turned on at different timings.

[0018] When the multiple sub-arrays are used as memories, the variable capacitors of each of the multiple sub-arrays may have the same capacitance, and when the multiple sub-arrays are used as arithmetic units, the variable capacitors of each of the multiple sub-arrays may be variable according to a rate of data addition.

[0019] Among the plurality of sub-arrays, a sub-array to be used as an arithmetic unit and a sub-array to be used as a memory can be switched.

[0020] The computing device may further include: a first control unit that controls the first switching element and the second switching element; and a second control unit that controls a potential of the second signal line when writing data to the storage unit.

[0021] The sub-array may have a plurality of memory cells, and the memory cell may be composed of a second switching element and a flip-flop.

[0022] The second signal line may be connected to the first signal line via the first switching element and the first resistor.

[0023] The memory cell may be connected to the second signal line via a second switching element and a second resistor.

[0024] The first switching element or the second switching element may have a predetermined resistance value.

[0025] The computing device may further include: a first control unit that controls the first switching element and the second switching element; a second control unit that controls the potential of the second signal line when data is written to the storage unit; an array unit, wherein the array unit may have a plurality of sub-array units arranged in a matrix, the sub-array unit may have a plurality of sub-arrays connected to the first signal line in columns, the first control unit may be arranged at both ends of one place in the array unit, and the second control unit may be arranged at both ends of another place in the array unit.

[0026] Sub-array cells can share readout circuitry.

[0027] The operation device may include a plurality of readout circuits, and at least one of the plurality of readout circuits may be arranged at one end of the array unit, and at least one of the plurality of readout circuits may be arranged at the other end of the array unit.

[0028] In order to solve the above problems, the present disclosure provides a computing device and a pixel array unit, in which pixels that generate pixel signals obtained by photoelectrically converting incident light are two-dimensionally arranged, wherein image data obtained by converting the pixel signals into digital data is stored in a storage unit of the computing device.

[0029] In order to solve the above problems, the present disclosure provides a computing method for a computing device, which computing device includes: multiple second signal lines, connected to a first signal line connected to a first capacitor; a second capacitor, connected to each of the multiple second signal lines; and a storage unit, connected to each of the multiple second signal lines, the method including: providing each second signal line with a charge corresponding to a signal value to be stored in the storage unit; storing the charge corresponding to the signal value to be stored in the storage unit in each second capacitor; performing capacitance division on the charge stored between the first capacitor and the multiple second capacitors; and obtaining a digital signal corresponding to the charge of the first signal line.

[0030] Aspects of the present disclosure are not limited to the aforementioned embodiments, and include various modifications that can be implemented by those skilled in the art, and the effects of the present disclosure are not limited to the above details. In other words, various additions, modifications and partial deletions can be made without departing from the conceptual concept and gist of the present disclosure, and the conceptual concept and gist of the present disclosure can be derived from the details defined in the claims and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a diagram illustrating a configuration of an imaging device according to a first embodiment of the present technology.

[0032] Figure 2 is a diagram showing an example of the configuration of a memory array unit.

[0033] Figure 3 is a diagram showing an example of a configuration of sub-arrays connected between local bit lines.

[0034] Figure 4 It is shown Figure 3 A diagram of an example of an equivalent circuit.

[0035] Figure 5 is a diagram showing an example of a memory cell configured with a 6-transistor SRAM.

[0036] Figure 6 is a diagram showing an example of the configuration of a readout circuit.

[0037] Figure 7 is a diagram showing an example of a pulse signal supplied from a vertical driver.

[0038] Figure 8 is a diagram schematically showing potential fluctuation of a local bit line.

[0039] Fig. 9 is a diagram showing potential fluctuation of the global line of mode 1.

[0040] Fig.10 is a diagram showing potential fluctuation of the global line of mode 2.

[0041] Fig.11 is a diagram showing an example of a pulse signal supplied from a vertical driver to a word line.

[0042] Fig.12 is a diagram schematically showing potential fluctuation of a local bit line.

[0043] Fig.13 3 is a diagram showing potential fluctuation of the global bit line in mode 3.

[0044] Fig.14 is a diagram illustrating an imaging device according to Modification 1 of the first embodiment.

[0045] Fig.15 is a diagram illustrating an imaging device according to Modification 2 of the first embodiment.

[0046] Fig.16 is a diagram illustrating an imaging device according to Modification 3 of the first embodiment.

[0047] Fig.17 is a diagram illustrating an imaging device according to Modification 4 of the first embodiment.

[0048] Fig.18A is a diagram illustrating an imaging device according to Modification 5 of the first embodiment.

[0049] Fig.18B is a diagram showing an example of arrangement of sub-arrays according to Modification 5 of the first embodiment.

[0050] Fig.19A is a diagram showing an example of the configuration of a storage unit according to Modification 6 of the first embodiment.

[0051] Fig.19B is a diagram showing an example of the configuration of a storage unit according to Modification 7 of the first embodiment.

[0052] Fig.19C is a diagram showing an example of the configuration of a storage unit according to Modification 8 of the first embodiment.

[0053] Fig.19D is a diagram showing an example of the configuration of a storage unit according to Modification 9 of the first embodiment.

[0054] Fig. 20 : is a diagram showing an example of the configuration of a memory array unit according to the second embodiment.

[0055] Fig.21 is a diagram showing a more detailed example of the configuration of the memory array unit.

[0056] Fig. 22 is a block diagram showing an imaging device according to Modification 1 of the second embodiment.

[0057] Fig.23 is a block diagram showing an example of the configuration of a memory array unit according to the third embodiment.

[0058] Fig.24 is shown with Fig.23 The configuration is the same as the block diagram of the word line configuration.

[0059] Fig.25 is a diagram showing an example of a pulse signal supplied from a vertical driver to a word line.

[0060] Fig.26 is a diagram showing the amount of potential fluctuation of a pulse signal applied to a local bit line.

[0061] Fig. 27 is a diagram showing potential fluctuation of a global line.

[0062] Fig.28 is a diagram showing an example in which different pulse signals are simultaneously applied to each sub-array of each column.

[0063] Fig.29 is a diagram showing pixel values ​​of a captured image and calculation values ​​of a convolution operation.

[0064] Fig.30 It shows that when executing Fig.29 A diagram showing an example of a configuration of a memory array cell during operation.

[0065] Fig.31 is a block diagram showing a sub-array according to Modification 1 of the third embodiment.

[0066] Fig.32 is a block diagram showing a sub-array according to Modification 2 of the third embodiment.

[0067] Fig.33 is a block diagram showing a sub-array according to Modification 3 of the third embodiment.

[0068] Fig.34 is a diagram showing a memory array unit 21 according to Modification 4 of the third embodiment.

[0069] Fig.35 is a diagram showing an example of the configuration of a storage unit according to Modification 5 of the third embodiment.

[0070] Fig.36 : is a diagram showing an example of the configuration of a memory array unit according to the fourth embodiment.

[0071] Fig.37 : is a diagram showing an example of the configuration of a memory array unit according to Modification 1 of the fourth embodiment.

[0072] Fig.38 : is a diagram showing an example of the configuration of a memory array unit according to Modification 2 of the fourth embodiment.

[0073] Fig.39 is a diagram showing an example of the configuration of a storage unit according to Modification 3 of the fourth embodiment.

[0074] Fig.40 : is a diagram showing an example of the configuration of a memory array unit according to the fifth embodiment.

[0075] Fig.41 : is a diagram showing an example of the configuration of a memory array unit according to the sixth embodiment.

[0076] Fig.42 is a diagram showing an example of a configuration of memory array cells grouped also in the row direction.

[0077] Fig.43 is a diagram showing an example of a configuration in which only one end side can be connected to a global bit line.

[0078] Fig.44is a diagram showing an example of a configuration in which a readout circuit is arranged at both ends of a memory array cell.

[0079] Fig.45 is a diagram showing an example of an arrangement together with a vertical driver, a horizontal driver, and a control unit. DETAILED DESCRIPTION

[0080] Hereinafter, embodiments of the computing device, the imaging device, and the computing method will be described with reference to the accompanying drawings. The main components of the computing device, the imaging device, and the computing method are mainly described below, but the computing device, the imaging device, and the computing method may have components and functions that are not shown or described. The following description does not exclude components or functions that are not shown or described.

[0081] (First Embodiment)

[0082] Figure 1 is a block diagram showing the configuration of an imaging device according to the first embodiment. Figure 1 The imaging device 1 shown includes a pixel array unit 11, a pixel control circuit 12, a pixel signal processing circuit 13, a horizontal drive circuit 14, a logic circuit 15, a memory array unit 21, a CIM input control circuit 22, a CIM readout circuit 23, a signal processing circuit 31, a memory 32, and an input / output unit 33. Note that the memory array unit 21, the CIM input control circuit 22, and the CIM readout circuit 23 constitute the arithmetic device 100 according to the present embodiment.

[0083] A plurality of pixels are two-dimensionally arranged in the pixel array unit 11. Each pixel generates a pixel signal S12 by photoelectrically converting incident light based on a plurality of types of pixel control signals S11 from the pixel control circuit 12. In addition, each pixel is configured to output the pixel signal S12 toward the pixel signal processing circuit 13 in one direction.

[0084] The pixel control circuit 12 is composed of, for example, a shift register and is connected via a pixel drive wiring ( Figure 1 (not shown) the pixel control signal S11 is input to each pixel of the pixel array unit 11. By using the pixel control signal S11, the pixel control circuit 12 sequentially selects and scans each pixel of the pixel array unit 11, and outputs the pixel signal S12 of each pixel to the pixel signal processing circuit 13.

[0085] The pixel signal processing circuit 13 performs a correlated double sampling (CDS) process for removing pixel-specific fixed pattern noise and an analog-to-digital (AD) conversion process on the pixel signal S12 read from the pixel array unit 11. The image signal S13 processed by the pixel signal processing circuit 13 is input to the CIM input control circuit 22. The horizontal drive circuit 14 is composed of, for example, a shift register, and sequentially outputs horizontal scanning pulses to the pixel signal processing circuit 13. As a result, for example, the image signal S13 held in the pixel signal processing circuit 13 is sequentially output to the CIM readout circuit 23.

[0086] The logic circuit 15 receives a clock signal and data indicating an operation mode, etc. input from the outside, and controls the operation of the entire imaging device 1. For example, the logic circuit 15 generates a vertical synchronization signal, a horizontal synchronization signal, etc. based on the input clock signal, and supplies these signals to the pixel control circuit 12, the pixel signal processing circuit 13, the horizontal drive circuit 14, the CIM input control circuit 22, the CIM readout circuit 23, etc. The memory array unit 21 outputs a signal S15 indicating the result of the product-sum operation in an analog manner using a plurality of memory cells toward the CIM readout circuit 23 in one direction.

[0087] The CIM input control circuit 22 is composed of, for example, a shift register, and drives the CIM input control circuit 22 via a storage cell drive wiring ( Figure 1 The CIM input control circuit 22 (not shown) inputs a storage unit control signal S14 associated with the image signal S13 to each storage unit of the memory array unit 21. That is, the CIM input control circuit 22 sequentially or collectively selects and scans each storage unit of the memory array unit 21 according to the storage unit control signal S14, and stores data associated with the pixel signal S12 of each pixel in each storage unit of the memory array unit 21.

[0088] The CIM readout circuit 23 performs AD conversion processing and the like on the signal S15 read from the memory array unit 21. The signal S16 processed by the CIM readout circuit 23 is input to the signal processing circuit 31. The signal S16 may be intermediate data at an intermediate stage of image recognition. The signal processing circuit 31 performs conversion processing using an activation function, pooling processing, and the like on the signal S16 input from the CIM readout circuit 23, and outputs the processing result to the input / output unit 33. Note that some of these processes may be performed in the memory array unit 21 or in the CIM readout circuit 23. In addition, when multiple signal processing is performed, the CIM readout circuit 23 may perform the signal processing several times, and then the signal processing circuit 31 may perform the remaining signal processing. In this way, by sharing the signal processing between the CIM readout circuit 23 and the signal processing circuit 31, the concentration of the processing load may be avoided. In addition, the signal processing circuit 31 may store parameters and the like input from an external image processing device via the input / output unit 33 in the memory 32, and may appropriately select and perform the signal processing based on the instruction from the external image processing device. The memory 32 stores data of parameters and the like necessary for the signal processing performed by the signal processing circuit 31. The memory 32 may also have a frame memory for storing image signals in processing such as demosaic processing.

[0089] The input / output unit 33 outputs the signals sequentially input from the signal processing circuit 31 to an external image processing device such as a downstream image signal processor (ISP). The input / output unit 33 also provides the signals and parameters input from the external image processing device to the signal processing circuit 31 and the logic circuit 15. The input / output unit 33 also writes the data value indicating the learning result provided from the outside into the storage unit of the memory array unit 21, and the learning result can also be updated through the input / output unit 33 to reflect the result calculated by the signal processing circuit 31.

[0090] Figure 2 2 is a block diagram showing an example of the configuration of the memory array unit 21. Figure 2 As shown, the memory array unit 21 has a plurality of sub-array units 30, a vertical driver 304, a horizontal driver 306, and a control unit 308. The memory array unit 21 is also constituted by, for example, a semiconductor element.

[0091] The memory array unit 21 includes a sub-array unit 30 in which a plurality of sub-arrays 302 are connected in columns, and the plurality of sub-array units 30 are arranged in columns. The plurality of memory array units 21 may also be arranged in a matrix. The memory array units 21 arranged in a matrix may be referred to as a tile structure.

[0092] In addition, at least one memory cell is arranged in the sub-array 302. In the sub-array according to this embodiment, for example, a plurality of memory cells 310 (see Figure 3 ). Therefore, the memory array unit 21 has the memory cells 310 arranged two-dimensionally (see Figure 3 ).

[0093] The CIM input control circuit 22 includes a plurality of write circuits 220 . In addition, the CIM read circuit 23 includes a plurality of read circuits 230 .

[0094] The vertical driver 304 can control the switching elements in the sub-array unit 30 via the word line WL as a horizontal signal line according to the control of the control unit 308. As a result, the vertical driver 304 can select the memory cells in the sub-array unit 30 in units of horizontal rows.

[0095] The horizontal driver 306 may control the plurality of write circuits 220 and the plurality of read circuits 230 of each column under the control of the control unit 308. For example, the write circuit 220 may control the potential of the global bit lines GBL0 and GBL1 between a predetermined high potential and a predetermined low potential. The read circuit 230 may perform analog-to-digital conversion of the potential read from the global bit lines GBL0 and GBL1. For example, the control unit 308 includes a CPU, and controls the entire computing device 100 (see Figure 1 ).

[0096] Figure 3 3 is a block diagram showing an example of a configuration of a sub-array 302 connected between local bit lines LBL0 and LBL1. The sub-array 302 has a plurality of memory cells 310. In the present embodiment, for simplicity, the number of sub-arrays 302 and the number of memory cells 310 will be described as several, but the present invention is not limited thereto.

[0097] The memory cell 310 is a memory cell in which data (signal value) can be written and read. The memory cell 310 is, for example, a SARM. The ends of the memory cell 310 are connected between the local bit lines LBL0 and LBL1 via, for example, a switching element.

[0098] This allows data to be written and read for each memory cell 310. The memory cell 310 is also configured to be able to apply a potential corresponding to the stored data to the local bit lines LBL0 and LBL1.

[0099] The local bit lines LBL0 and LBL1 of each sub-array 302 are formed with parasitic capacitances ca to cd. The global bit lines GBL0 and GBL1 are also formed with parasitic capacitances call. These parasitic capacitances are formed, for example, by metal wiring within the semiconductor element. This allows the capacitance ratio of the parasitic capacitances ca to cd and call required for each sub-array unit 30 constituting the memory array unit 21 to be constant. The local bit lines LBL0 and LBL1 of each sub-array 302 are connected to the global bit lines GBL0 and GBL1 via transistors tr1 and tr4.

[0100] In this embodiment, in the case of computing in memory (CIM) driving, for example, data read from global bit line GBL0 is added, and data read from global bit line GBL1 is subtracted. Note that data read from global bit line GBL0 may be subtracted, and data read from global bit line GBL1 may be added.

[0101] (CIM product sum operation)

[0102] In the case of CIM driving, for example, the memory cells 310 of each sub-array 302 are electrically connected to the global bit lines GBL0 and GBL1 in sequence. Figure 3 An example of reading the second memory cell 310 is shown. Here, an example in which the global bit lines GBL0 and GBL1 and the local bit lines LBL0 and LBL1 are set to the ground potential as an example of precharging before the product-sum operation will be described.

[0103] The storage data (signal values) of the second memory cell 310 in each sub-array 302 are (0, 1), (0, 1), (1, 0), and (0, 1), respectively. For example, 0 in (0, 1) corresponds to the ground potential, and 1 corresponds to the VDD potential. Note that as precharge before the product-sum operation, the global bit lines GBL0 and GBL1 and the local bit lines LBL0 and LBL1 may be set to a predetermined potential to read the charge. In this case, the potential drop from the predetermined potential corresponds to the data of the memory cell 310.

[0104] like Figure 3 As shown, when the second memory cell 310 is read, the parasitic capacitor ca of the local bit line LBL0 stores a charge k1×Qa proportional to ca×0, the parasitic capacitor cb stores a charge k1×Qb proportional to cb×0, the parasitic capacitor cc stores a charge k1×Qc proportional to cc×1, and the parasitic capacitor cd stores a charge k1×Qd proportional to cd×0.

[0105] When the transistor tr1 of each sub-array 302 is turned on, the parasitic capacitances ca to cd are connected in parallel, and the charge capacitance Qall1 is Qall1=k1×(Qa+Qb+Qc+Qd). At this time, the parasitic capacitance call is connected in series with the parasitic capacitances ca to cd connected in parallel, so its charge capacitance Qall2 is Qall2=Qall1×(ca+cb+cc+cd) / call=k1×(ca×0+cb×0+cc×1+cd×0) / call. In the readout circuit 230, the potential proportional to Qall2 is converted into a digital value D.

[0106] Similarly, parasitic capacitance ca of local bit line LBL1 stores charge k1×Qax proportional to ca×1, parasitic capacitance cb stores charge k1×Qbx proportional to cb×1, parasitic capacitance cc stores charge k1×Qcx proportional to cc×0, and parasitic capacitance cd stores charge k1×Qdx proportional to cd×1.

[0107] Next, when the transistor tr4 of each sub-array 302 is turned on, the original capacitances ca to cd are connected in parallel, and the charge capacitance Qallx1 is Qallx1=k1×(Qax+Qbx+Qcx+Qdx). At this time, call is connected in series with the parallel-connected ca to cd, so the charge capacitance Qallx2=Qallx1×(ca+cb+cc+cd) / cal=k1×(ca×1+cb×1+cc×0+cd×1) / call. The readout circuit 230 converts the potential proportional to Qallx2 into a digital value Dx.

[0108] Then, the readout circuit 230 subtracts the digital value Dx from the digital value D. This results in D-Dx=k1×(ca×0+cb×0+cc×1+cd×0) / call-k1×(ca×1+cb×1+cc×0+cd×1) / call=k1×(ca×(-1)+cb×(-1)+cc×(+1)+cd×(-1)). In this case, if k1×ca / call is coefficient a, k1×cb / call is coefficient b, k1×cb / call is coefficient c, and k1×cd / call is coefficient b, this is equivalent to the operation a×(-1)+b×(-1)+c×(+1)+d×(-1). In this way, in the memory array unit 21 according to the present embodiment, charges are stored in the parasitic capacitances ca to cd at a potential corresponding to the data, a digital value proportional to the stored charges is generated, and a product-sum operation can be performed.

[0109] Figure 4 It is shown Figure 3The storage unit 310 is composed of a static random access memory (SRAM). Figure 5 3 is a diagram showing an example in which the memory cell 310 is composed of a six-transistor SRAM. Figure 4 and Figure 5 As shown, from the vertical driver 304 (see Figure 2 ) is connected to the gates of transistors tr1 to tr4. Figure 4 and Figure 5 As shown, when (0, 1) is set in the memory cell 310, the transistors tr1 to tr4 are turned on, and the write circuit 220 (see Figure 2 ) sets the global bit line GBL0 to the ground (GND) potential and sets the global bit line GBL1 to the VDD potential. Note that the transistors tr1 and tr2 in this embodiment correspond to the first switch element, the transistors tr3 and tr4 in this embodiment correspond to the second switch element, the global bit lines GBL0 and GBL1 correspond to the first signal line, and the local bit lines LBL0 and LBL1 correspond to the second signal line.

[0110] On the other hand, when (1, 0) is set in the memory cell 310, the transistors tr1 to tr4 are turned on, and the write circuit 220 (see Figure 2 ) sets the global bit line GBL0 to the VDD potential and sets the global bit line GBL1 to the ground potential. Although the memory cell 310 according to the present embodiment is composed of a complementary output SRAM, the present invention is not limited thereto. For example, if a potential corresponding to the data stored in the memory cell 310 can be applied to the parasitic capacitances ca to cd, a product-sum operation corresponding to the data stored in the memory cell 310 can be performed. The first signal line for reading can be composed of one instead of two.

[0111] Figure 6 2 is a block diagram showing an example of the configuration of the readout circuit 230. In the readout circuit 230, an ADC 221 and a latch circuit 224 are arranged for each of the global bit lines GBL0 and GBL1.

[0112] The ADC 221 converts the analog output signal Aout from the corresponding column into a digital signal Dout. This AD conversion is also called “reading” of the analog signal. For example, the ADC 221 is a single slope ADC and includes a comparator 222 and a counter 223.

[0113] The comparator 222 compares the reference signal RMP from the DAC (not shown) with the output signal Aout. The comparator 222 provides the comparison result CMP to the counter 223. The counter 223 counts the count value until the comparison result CMP is inverted. The counter 223 outputs the digital signal Dout indicating the count value to the latch circuit 224. The counter 223 can also perform up-counting or down-counting, and can switch from one of up-counting and down-counting to the other under the control of the timing control circuit 212.

[0114] The latch circuit 224 on the global bit line GBL0 side holds the digital signal D, and the latch circuit 224 on the global bit line GBL1 side holds the digital signal Dx. These latch circuits 224 are controlled by the control circuit 308 (see Figure 2 The differential circuit 226 calculates the difference between the digital signals Dx and D, and outputs the result to the signal processing circuit 31 (see Figure 1 ).

[0115] Note that in this embodiment, ADC 221 is arranged for each of the global bit lines GBL0 and GBL1, but the present invention is not limited thereto. For example, a system in which one ADC 221 corresponds to all columns may be adopted. In addition, ADC 221 may be, for example, a single slope ADC, a successive approximation register analog-to-digital converter (SAR ADC), an incremental sigma ADC, a pipeline ADC, a dual integral type ADC, or a flash ADC. In addition, AutoZero may be performed based on a reset signal, and CDS may be performed. When there is one VSL, a single-input ADC is preferred. On the other hand, when two lines are used to represent positive and negative, two single-input ADCs may be prepared, and the difference of the ADC results may be taken in the digital domain, or a dual-input ADC may be used to perform ADC on the difference. For example, in the case of a dual-input ADC, a SAR-ADC may be used. In addition, in the case of a dual-input ADC, an operation such as ReLU may be performed. The ReLU is a function that outputs zero when a negative signal is obtained when a positive signal and a negative signal are added. Note that if it is clear that the output will become negative during the ADC operation, the ADC operation may be stopped midway to confirm the zero output.

[0116] (Read Driver)

[0117] For example, the first read driver according to the present embodiment has three read modes. Mode 1 is a mode in which a product-sum operation is performed whenever a memory cell 310 of each row of each sub-array 302 is read. Mode 2 is a mode in which a product-sum operation is performed after all memory cells 310 of each row of each sub-array 302 are read. Mode 3 is a mode in which a product-sum operation is performed whenever a memory cell 310 of each row of each sub-array 302 is read multiple times. Here, an example in which each read is started after writing to the memory cell 310 has been completed is described. Note that although the operation on the local bit line LBL1 side is described, the operation on the local bit line LBL0 side is also similar.

[0118] For example, precharging according to the present embodiment means setting the global bit line GBL1 and the local bit line LBL1 to a predetermined potential before reading data to the parasitic capacitances ca to cd and the parasitic capacitance call.

[0119] Here, we will refer to Figures 7 to 9 An example of read driving in mode 1 is described. Figure 7 3 is a diagram showing an example of a pulse signal of a word line WL supplied from a vertical driver 304 to each memory cell 310. The horizontal axis represents time. Signals a to d show pulse signals applied to the gates of transistors tr3 and tr4 (see Figure 4 and Figure 5 ). a to d correspond to Figure 3 The order of the top of each sub-array 302 (opposite to the readout circuit 230) in FIG.

[0120] When a high level signal is applied to transistors tr3 and tr4, transistors tr3 and tr4 are turned on. For example, signal a shows Figure 3 The top sub-array 302 in FIG. 1 is a top sub-array 302 in FIG. 1. The global conduction (GBLON) indicates the conduction state of transistors tr1 and tr2 (see Figure 4 and Figure 5 ).

[0121] Figure 8 is a schematic diagram showing that when executing Figure 7 FIG. 1 is a diagram showing the potential fluctuation of the local bit line LBL0 during driving. The horizontal axis represents time and corresponds to Figure 7 . The vertical axis represents the potential. The potential fluctuation corresponds to the potential corresponding to the data of the storage cell 310. In this specification, the precharge is set to a predetermined potential, so the potential corresponding to the data is represented as a drop in potential. On the other hand, there is no potential fluctuation in the potential corresponding to the signal value 0. When the precharge is set to ground, the line of the reference potential corresponds to the ground potential, and the absolute value of the potential fluctuation is proportional to the amount of stored charge.

[0122] Fig. 9 It is shown that the execution in mode 1 Figure 7 Graph showing the potential fluctuation of the global line GBL1 during driving. The horizontal axis represents time and corresponds to Figure 7 The vertical axis corresponds to the potential Vswing of the global line GBL1.

[0123] like Figures 7 to 9 As shown, the vertical driver 304 turns on or off the transistors tr3 and tr4 of the first row of each sub-array 302 at time t1 after the precharging of the local bit line LBL1 is completed according to the stored data. For example, if the data is 1, the transistor is turned on, and if the data is 0, the transistor is turned off.

[0124] As a result, charges corresponding to the signal values ​​of the memory cells 310 of the first row of each sub-array 302 are stored in the parasitic capacitors ca to cd. For example, if the stored data is 1, the potential of VDD is applied to the local bit line LBL1. Next, the transistors tr1 and tr2 (see Figure 4 and Figure 5 ) is turned on, and at the timing of global conduction, the data capacitance of the first row of each sub-array 302 is divided into the parasitic capacitance call. As described above, the processing on the global bit line GLB0 side is also performed in the same manner. Then, the signal corresponding to the potential of the global bit line GLB0 and the signal corresponding to the potential of the global bit line GLB1 are subjected to a product-sum operation in the readout circuit 230.

[0125] Next, at time t2 after precharging of the local bit line LBL1 has been completed, the vertical driver 304 turns on or off the transistors tr3 and tr4 of the second row of each sub-array 302 according to the stored data. As a result, charges corresponding to the signal values ​​of the memory cells 310 of the second row of each sub-array 302 are stored in the parasitic capacitors ca to cd. Next, the transistors tr1 and tr2 of each sub-array 302 (see Figure 4 and Figure 5 ) is turned on, and at the timing of global conduction, the data capacitance of the second row of each sub-array 302 is divided into the parasitic capacitance call. Then, the signal corresponding to the potential of the global bit line GLB0 and the signal corresponding to the potential of the global bit line GLB1 are multiplied and calculated in the readout circuit 230.

[0126] Next, at time t3 after the precharge of the local bit line LBL1 is completed, the vertical driver 304 turns on or off the transistors tr3 and tr4 of the second row of each sub-array 302 according to the stored data. As a result, the charge corresponding to the signal value of the memory cell 310 of the third row of each sub-array 302 is stored in the parasitic capacitors ca to cd. Next, the transistors tr1 and tr2 (see Figure 4 and Figure 5 ) is turned on, and at the timing of global conduction, the data capacitance of the third row of each sub-array 302 is divided into the parasitic capacitance call. Then, the signal corresponding to the potential of the global bit line GLB0 and the signal corresponding to the potential of the global bit line GLB1 are multiplied and calculated in the readout circuit 230.

[0127] Next, at time t4 after the precharge of the local bit line LBL0 is completed, the vertical driver 304 turns on or off the transistors tr3 and tr4 of the fourth row of each sub-array 302 according to the stored data. As a result, the charge corresponding to the signal value of the memory cell 310 of the fourth row of each sub-array 302 is stored in the parasitic capacitors ca to cd. Next, the transistors tr1 and tr2 (see Figure 4 and Figure 5 ) is turned on, and at the timing of global conduction, the data capacitance of the third row of each sub-array 302 is divided into the parasitic capacitance call. Then, the signal corresponding to the potential of the global bit line GLB0 and the signal corresponding to the potential of the global bit line GLB1 are multiplied and calculated in the readout circuit 230.

[0128] In Modes 2 and 3, the global bit line GBL1 is precharged only once before reading. On the other hand, the local bit line LBL1 is precharged each time data is read. Therefore, in Modes 2 and 3, since the global bit line GBL1 is not precharged again, precharging is performed using, for example, a dedicated line (not shown) for precharging the local bit line LBL1.

[0129] Fig.10 It is shown that the execution in mode 2 Figure 7 Graph showing the potential fluctuation of the global line GBL1 during driving. The horizontal axis represents time and corresponds to Figure 7 The vertical axis corresponds to the potential Vswing of the global line GBL. Fig.10 As shown, in mode 2, charge sharing is performed multiple times on the global bit line GBL1 before the product-sum operation is performed in the readout circuit 230. As described above, the processing on the global bit line GLB0 side is performed in the same manner. Then, a signal corresponding to the potential of the global bit line GLB0 and a signal corresponding to the potential of the global bit line GLB1 are subjected to a product-sum operation in the readout circuit 230.

[0130] In this manner, in mode 1, each time the memory cells 310 of each row of each sub-array 302 are read, the product-sum operation is performed, so that the result of the product-sum operation of the memory cells 310 of each row of each sub-array 302 can be obtained. On the other hand, in mode 2, the product-sum operation is performed after all the memory cells 310 of each row of each sub-array 302 are read, so that the product-sum operation of all the memory cells 310 can be performed at the same time, and the number of calculation processes can be reduced.

[0131] Here, we will refer to Figures 11 to 13 An example of control of repeated reading in Mode 3 is described. Mode 3 is different from Mode 1 in that memory cells 310 of each row of each sub-array 302 are repeatedly read. Here, an example of repeatedly reading memory cells 310 of the first row of each sub-array 302 four times will be described.

[0132] Fig.11 3 is a diagram showing an example of a pulse signal of a word line WL supplied from a vertical driver 304 to each memory cell 310. The horizontal axis represents time. Signals a to d represent pulse signals applied to the gates of transistors tr3 and tr4 (see Figure 4 and Figure 5 ). When a high level signal is applied to transistors tr3 and tr4, transistors tr3 and tr4 are turned on. Signals a to d correspond to Figure 3 For example, signal a indicates Figure 3 The top sub-array 302 in FIG. 1 is globally turned on (GBLON) indicating that transistors tr1 and tr2 (see Figure 4 and Figure 5 That is, this shows an example of repeatedly reading the memory cells 310 of the first row of each sub-array 302 at times t1 to t4.

[0133] Fig.12 is a schematic diagram showing that when executing Fig.11 FIG. 1 is a diagram showing the potential fluctuation of the local bit line LBL1 during driving. The horizontal axis represents time and corresponds to Fig.11 The vertical axis represents the electric potential.

[0134] Fig.13 It is shown that the execution in mode 3 Figure 7 Graph showing the potential fluctuation of the global bit line GBL1 during driving. The horizontal axis represents time and corresponds to Fig.11 The vertical axis corresponds to the potential Vswing of the global bit line GBL1.

[0135] like Figures 11 to 13As shown, at time t1 after completing precharging of the global bit line GBL01 and the local bit line LBL1, the vertical driver 304 turns on or off the transistors tr3 and tr4 of the first row of each sub-array 302. As a result, the charge corresponding to the signal value of the memory cell 310 of the first row of each sub-array 302 is stored in the parasitic capacitors ca to cd. Next, the transistors tr1 and tr2 (see Figure 4 and Figure 5 ) is turned on, and at the timing of global conduction, the data capacitance of the first row of each sub-array 302 is divided into the parasitic capacitance call.

[0136] Next, at time t2 after the precharge of the local bit line LBL0 is completed, the vertical driver 304 turns on or off the transistors tr3 and tr4 of the first row of each sub-array 302. As a result, the charge corresponding to the signal value of the memory cell 310 of the first row of each sub-array 302 is stored in the parasitic capacitors ca to cd again. Next, the transistors tr1 and tr2 (see Figure 4 and Figure 5 ) is turned on, and at the timing of the global turn-on, the data capacitance of the second row of each sub-array 302 is divided into the parasitic capacitance call.

[0137] Next, at time t3 after the precharge of the local bit line LBL0 is completed, the vertical driver 304 turns on or off the transistors tr3 and tr4 of the first row of each sub-array 302. As a result, the charge corresponding to the signal value of the memory cell 310 of the first row of each sub-array 302 is stored again in the parasitic capacitors ca to cd. Next, the transistors tr1 and tr2 (see Figure 4 and Figure 5 ) is turned on, and at the timing of the global turn-on, the data capacitance of the second row of each sub-array 302 is divided into the parasitic capacitance call.

[0138] Next, at time t4 after the precharge of the local bit line LBL0 is completed, the vertical driver 304 turns on or off the transistors tr3 and tr4 of the fourth row of each sub-array 302. As a result, the charge corresponding to the signal value of the memory cell 310 of the fourth row of each sub-array 302 is stored in the parasitic capacitors ca to cd again. Next, the transistors tr1 and tr2 (see Figure 4 and Figure 5) is turned on, and at the timing of global conduction, the data of the third row of each sub-array 302 is divided by the parasitic capacitance call. As described above, the processing on the global bit line GLB0 side is performed in the same manner. Then, a signal corresponding to the potential of the global bit line GLB0 and a signal corresponding to the potential of the global bit line GLB1 are subjected to a product-sum operation in the readout circuit 230. By performing such processing, a calculation process whose coefficient is an integer multiple (for example, 4 times) corresponding to repeated reading can be performed, such as 4{a×(-1)+b×(-1)+c×(+1)+d×(-1)}.

[0139] Note that in this embodiment, precharge is described as being set to a predetermined high potential, but the present invention is not limited thereto. For example, as described above, the global bit line GBL0 and the local bit line LBL0 may be precharged to the ground potential. In this case, precharge is shown as setting the global bit line GBL0 and the local bit line LBL0 to the ground level, and the potential fluctuation appears to rise in the direction from the ground level (see Figure 8 , Fig. 9 , Fig.10 , Fig.12 and Fig.13 ). In this way, the precharge can be set to ground potential.

[0140] As described above, according to the present embodiment, the local bit lines LBL0 and LBL1 of each sub-array 302 are formed with parasitic capacitances ca to cd in a predetermined ratio with the parasitic capacitances call of the global bit lines GLB0 and GBL1, and a potential corresponding to the signal value of the memory cell 310 of each sub-array 302 is applied to the global bit lines GLB0 and GLB1 of each sub-array 302. As a result, a charge corresponding to the signal value of the memory cell 310 can be stored and added to the parasitic capacitances ca to cd, and then the charge can be read by the global bit lines GLB0 and GLB1. A product-sum operation (e.g., a×(+1)+b×(+1)+c×(-1)) in which the signal value of the memory cell 310 is multiplied by coefficients a to d proportional to the parasitic capacitances ca to cd can be performed on the memory array.

[0141] (Modification 1 of First Embodiment)

[0142] Fig.14 1 is a block diagram showing an imaging device 1 according to a modification 1 of the first embodiment. Figure 3 The configuration example of the sub-array 302 shown is different in that the parasitic capacitance ca of the first sub-array 302 and the parasitic capacitance ca of the second sub-array 302 have the same value. This allows calculation processing using a doubling factor, such as 2a×(+1)+b×(+1)+c×(-1).

[0143] (Modification 2 of the first embodiment)

[0144] Fig.15 2 is a block diagram showing an imaging device 1 according to a modification 2 of the first embodiment. Fig.14 The configuration example of the sub-array 302 shown is different in that the first sub-array 302 and the second sub-array 302 are integrated. This allows, for example, 2a×(+1) calculation processing to be performed in one read.

[0145] (Modification 3 of the first embodiment)

[0146] Fig.16 is a block diagram showing an imaging device 1 according to Modification 3 of the first embodiment. Figure 3 The configuration example of the sub-array 302 shown is different in that each of the global bit lines GBL0 and GBL1 of each column can be divided by a plurality of capacitors c10 and c20.

[0147] Dividing the voltage through the plurality of capacitors c10 and c20 is equivalent to multiplying the left global bit lines GBL0 and GBL1 by coefficients Xa, Xb, Xc, and Xd and adding them to the right global bit lines GBL0 and GBL1. For example, when the same data is stored in the sub-array 302 of the first and second columns, it is equivalent to multiplying and adding the coefficients Xa, Xb, Xc, and Xd, such as Xa×a×(+1)+Xb×b×(+1)+Xc×c×(-1)+Xd×c×(+1). Note that although in Fig.16 , but the present invention is not limited thereto. For example, a configuration in which more capacitors are connected in parallel may be adopted. In addition, a configuration in which a plurality of capacitors are connected in series to each of the global bit lines GBL0 and GBL1 of each column may be adopted.

[0148] (Modification 4 of the first embodiment)

[0149] Fig.17 1 is a block diagram showing an imaging device 1 according to Modification 4 of the first embodiment. Fig.17 The configuration example of the sub-array 302 shown is different in that the parasitic capacitance of the local bit lines LBL0 and LBL1 is configured with variable capacitances vca to vcd. As a result, for example, by setting vca to vcd to the same value, the operation device 100 can be used as a normal memory. The variable capacitance can be configured using elements such as MΩ resistors (MOR) (see JP 2020-113809A), ferroelectric tunnel junctions (FTJs), and magnetic tunnel junctions (MTJs).

[0150] On the other hand, in the case of a computation-in-memory (CIM) mode in which calculations are performed on a memory array by, for example, setting vca to vcd to capacitances corresponding to coefficients a to d of a×(+1)+b×(+1)+c×(-1), it becomes possible to perform a product-sum operation on a target memory array.

[0151] (Modification 5 of the first embodiment)

[0152] Fig.18A is a block diagram showing an imaging device 1 according to Modification 5 of the first embodiment. Fig.18A The illustrated configuration example of the sub-array 302 is different from the modification 4 of the imaging device 1 according to the first embodiment in that the parasitic capacitance of the local bit lines LBL0 and LBL1 is constituted by a variable capacitance unit (RMX) 400 .

[0153] like Fig.18A As shown, the variable capacitance unit 400 has a plurality of transistors tr5 and tr6 and a plurality of capacitors c30 and c40. One set of ends of the plurality of transistors tr5 and tr6 is connected to the local bit line LBL0, and the plurality of capacitors c30 and c40 are connected to the other set of ends of each transistor. The local bit line LBL1 side has the same configuration. The vertical driver 304 has a plurality of triggers 320 that control the variable capacitance unit 400 of each sub-array 302. The output signal of the trigger 320 is input to the gate that is the control electrode of the plurality of transistors tr5 and tr6.

[0154] The trigger 320 is in the control unit 308 (see Figure 2 ) to turn on one of the plurality of transistors tr5 and tr6 and turn off the remaining transistors. This makes it possible to change the parasitic capacitance of the local bit lines LBL0 and LBL1.

[0155] Fig.18B : is a diagram showing an example of the arrangement of the sub-array 302 according to the modification 5 of the first embodiment. Fig.18B As shown, the write circuit 220 according to the modification 5 of the first embodiment (see Figure 2 ) has a word line amplifier (WSA: Wr-amp) 220a and a word line amplifier control unit (WDV: global Wt-driver) 220b. The CIM readout circuit 23 has a global line amplifier (RSA: global Rd-amp) 230a.

[0156] The word line amplifier 220a is provided between a pair of sub-arrays 302. The variable capacitance unit 400 is formed at the ends of the pair of sub-arrays 302. That is, the word line amplifier 220a and the variable capacitance unit 400 are alternately provided between the sub-arrays 302. The word line amplifier control unit (WDV: global Wt-driver) 220b controls the word line amplifier 220a according to the control unit 308 (see Figure 2 ) to control the word line amplifier 220a. The global line amplifier 230a amplifies the voltage of the global lines GBL0 and GBL1 and outputs it to the readout circuit 230. In this way, by forming the parasitic capacitance of the local bit lines LBL0 and LBL1 using the variable capacitance unit (RMX) 400, it becomes possible to use the operation device 100 as a normal memory and perform calculations on the memory array.

[0157] (Modification 6 of the first embodiment)

[0158] Fig.19A 6 is a diagram showing an example of the configuration of the storage unit 310 according to the modification 6 of the first embodiment. Fig.15 The illustrated configuration example of the memory cell 310 is different in that the memory cell 310 has a resistor r3 .

[0159] like Fig.19A As shown, transistors tr3 and tr4 are connected to local bit lines LBL0 and LBL1 via resistor r3. This allows the charge to be supplied to the parasitic capacitor call at a faster rate than Fig.15 The configuration example of the memory cell 310 shown is delayed, and by turning off the transistors tr3 and tr4 before the charge is completely supplied, the amount of charge supplied from the memory cell 310 can be adjusted. In other words, by making the timing of turning off the transistors tr3 and tr4 different for each memory cell 310, the coefficient value of each memory cell 310 can be further adjusted.

[0160] (Modification 7 of First Embodiment)

[0161] Fig.19B 7 is a diagram showing an example of the configuration of the storage unit 310 according to the modification 7 of the first embodiment. Fig.19A The configuration example of the memory cell 310 shown is different in that the transistors tr3 and tr4 are NMOS transistors, while the transistors tr3b and tr4b are PMOS transistors. As a result, by reversing the high level and low level of the gate signal of the transistor tr3b, the same function as that of the memory cell 310 according to the modification 6 of the first embodiment can be realized.

[0162] (Modification 8 of First Embodiment)

[0163] Fig.19C is a diagram showing an example of the configuration of the storage unit 310 according to Modification 8 of the first embodiment. Fig.19A The configuration example of the memory cell 310 shown is different in that the transistor tr3 and the resistor r3 are configured with a transistor tr3c, and the transistor tr4 and the resistor r3 are configured with a transistor tr4c. The resistance of the transistor tr3c in the on state is equal to the resistance of the resistor r3 in the on state and the resistance of the transistor tr3 connected in series. The same is true for the transistor tr4c. Therefore, the resistor r3 is not required.

[0164] (Modification 9 of the first embodiment)

[0165] Fig.19D is a diagram showing an example of the configuration of the storage unit 310 according to Modification 9 of the first embodiment. Fig.19B The configuration example of the memory cell 310 shown is different in that the transistor tr3b and the resistor r3 are configured with the transistor tr3d, and the transistor tr4b and the resistor r3 are configured with the transistor tr4d. The resistance of the transistor tr3d in the on state is equal to the resistance of the resistance of the transistor tr3b in the on state and the resistance of the resistor r3 connected in series. The same is true for the transistor tr4d. Therefore, the resistor r3 is not required.

[0166] (Second Embodiment)

[0167] The imaging device 1 according to the second embodiment is different from the imaging device 1 according to the first embodiment in that the sub-array unit 30 constituting the memory array unit 21 is configured for each of the global bit lines GBL0 and GBL1. The difference from the imaging device 1 according to the first embodiment will be described below.

[0168] Fig. 20 2 is a block diagram showing an example of the configuration of the memory array unit 21 according to the second embodiment. Fig. 20 As shown, in the memory array unit 21, a sub-array unit 30 is configured for each of the global bit lines GBL0 and GBL1. This allows independent addition and subtraction operations to be performed on each of the global bit lines GBL0 and GBL1.

[0169] Fig.21 2 is a block diagram showing a more detailed example of the configuration of the memory array unit 21 according to the second embodiment. Fig.21As shown, the memory array unit 21 has a plurality of sub-arrays 302 connected only to the global bit line GBL0 side, and a plurality of sub-arrays 302 connected only to the global bit line GBL1 side. As can be seen from this, data stored in the plurality of sub-arrays 302 connected only to the global bit line GBL0 side and data stored in the plurality of sub-arrays 302 connected only to the global bit line GBL1 side can be independently set. This allows the addition process on the global bit line GBL0 side and the subtraction process on the global bit line GBL1 side to be independently performed.

[0170] As described above, according to the present embodiment, the memory array unit 21 has the sub-array unit 30 configured for each of the global bit lines GBL0 and GBL1. This allows independent addition and subtraction calculations to be performed on each of the global bit lines GBL0 and GBL1.

[0171] (Modification 1 of Second Embodiment)

[0172] Fig. 22 1 is a block diagram showing an imaging device 1 according to a modification 1 of the second embodiment. Fig.21 The configuration example of the sub-array 302 shown is different in that the parasitic capacitance of the local bit lines LBL0 and LBL1 is configured with variable capacitance vca to vcd. For example, this allows the operation device 100 to be used as a normal memory by setting vca to vcd to the same value. The variable capacitance can be configured using elements such as MΩ resistors (MOR) (see JP 2020-113809A), ferroelectric tunnel junctions (FTJs), and magnetic tunnel junctions (MTJs).

[0173] On the other hand, in the case of a computation-in-memory (CIM) mode in which computation is performed on a memory array, a product-sum operation may be performed on a target memory array by setting capacitances according to coefficients a to d such as a×(+1)+b×(+1)+c×(-1).

[0174] (Third Embodiment)

[0175] The imaging device 1 according to the third embodiment is different from the imaging device 1 according to the first embodiment in that the memory unit 310 constituting the memory array unit 21 can change its coefficient according to the potential and pulse width of the pulse signal. The difference from the imaging device 1 according to the first embodiment will be described below.

[0176] Fig.23 2 is a block diagram showing an example of the configuration of the memory array unit 21 according to the third embodiment. Fig.23 As shown, the memory array unit 21 has a plurality of sub-arrays 302 arranged between the global bit lines GBL0 and GBL1. The sub-arrays 302 have a plurality of memory cells 310.

[0177] Parasitic capacitance c50 is arranged in the local bit lines LBL0x and LBL1x of each sub-array 302. In addition, parasitic capacitance call is arranged in the global bit lines GBL0 and GBL1. These parasitic capacitances are formed of metal wiring, for example.

[0178] like Fig.23 As shown, the memory cell 310 according to the third embodiment is composed of an SRAM, a plurality of transistors tr7 and tr8, and a plurality of resistors r. The SRAM has Figure 5 Therefore, the memory cell 310 has local bit lines LBL0 and LBL1 (not shown) for setting data in the SRAM. As a result, data can be set in the same manner as the SRAM according to the first embodiment.

[0179] A plurality of transistors tr7 and tr8 and a resistor r are connected in series. One end of the transistor tr7 is connected to the local bit line LBL0x, and one end of the resistor r is connected to the vertical driver 304 via the word line act (see Figure 2 ). The local bit line LBL1x side has the same structure. The gate of the transistor tr7 is connected to the vertical driver 304, and the gate of the transistor tr8 is connected to one end of the SRAM. Note that the plurality of transistors tr7 and tr8 according to the present embodiment correspond to the second switching element. Unlike this configuration, the number of switching elements does not have to be 1.

[0180] (Read Driver)

[0181] An example of read driving when performing a product-sum operation on the CIM of the memory array unit 21 according to the third embodiment will be described. Fig.24 is shown with Fig.23 Block diagram of the word line for the same configuration. Fig.24 WLa to WLp in FIG. 3 correspond to word lines connected to each memory cell 310. In addition, circles 1 to 4 indicate rows in the subarray 302.

[0182] Here, we will refer to Fig.24 Use at the same time Figure 25 to Figure 27 An example of read driving of the memory array unit 21 according to the third embodiment is described. Fig.25 is a diagram showing an example of pulse signals Pa to Po supplied from the vertical driver 304 to the word lines WLa to WLo of each memory cell 310. The horizontal axis represents time. The pulse signals Pa to Po indicate pulse signals applied to one end of the resistor r via the word lines WLa to WLo. In addition, circles 1 to 4 indicate rows in the subarray 302. The height of the pulse signals Pa to Po corresponds to the applied potential, and the pulse width corresponds to time.

[0183] Fig.26 It is shown that when applied Figure 5 1 is a diagram showing the potential fluctuation amount of the local bit line LBL0x of each sub-array 302 when the pulse signals Pa to Po are applied. The horizontal axis represents time. The vertical axis represents the potential fluctuation amount. The potential fluctuation amounts LBL0xa to LBL0xo correspond to the potential fluctuation amounts when the pulse signals Pa to Po are applied.

[0184] Fig. 27 It shows that when executing Fig.26 Graph showing the potential fluctuation of the global line GBL0 during driving. The horizontal axis represents time and corresponds to Fig.26 The vertical axis corresponds to the potential Vswing of the global line GBL0.

[0185] like Figure 25 to Figure 27 As shown, after completing the precharge of the local bit line LBLx1, the vertical driver 304 applies a high level signal to the gate of each transistor tr7, thereby turning on each transistor tr7. In this case, when (1, 0) is stored in the memory cell 310, the transistor tr8 is turned on, and when (0, 1) is stored in the memory cell 310, the transistor tr8 is turned off.

[0186] Next, the pulse signals Pa to Po are applied to one end of each resistor r via the word lines WLa to WLo. As a result, when (1, 0) is stored in the memory cell 310, a current corresponding to the potential and pulse width of the pulse signals Pa to Po flows through the local bit line LBLx1. This current is stored as charge in the parasitic capacitor c50. The fluctuation of the potential at this time depends on the potential of the pulse signals Pa to Po, such as Fig.26 As shown, and the fluctuation time of the potential depends on the pulse width. In this way, the charge corresponding to the potential and pulse width of the pulse signal Pa to Po is stored in the parasitic capacitor c50. It can be seen that the potential and pulse width of the pulse signal Pa to Po correspond to the coefficient of the product-sum operation. On the other hand, when (0, 1) is stored in the storage unit 310, the transistor tr8 is in the off state, so it does not contribute to the charge storage of the parasitic capacitor c50.

[0187] Next, if Fig. 27 As shown, each sub-array 302 has transistors tr1 and tr2 (see Fig.23) is turned on, and the charge of the parasitic capacitance c50 of each sub-array 302 is divided into the parasitic capacitance call by the capacitance. The same process is also performed on the global bit line GLB1 side. At this time, the potential and pulse width of the pulse signals Pa to Po on the global bit line GLB1 side can be made different from the potential and pulse width of the pulse signals Pa to Po on the global bit line GLB0 side. Then, the signal corresponding to the potential of the global bit line GLB0 and the signal corresponding to the potential of the global bit line GLB1 are subjected to a product-sum operation in the readout circuit 230. In this way, a product-sum operation can be performed on the data of all the memory cells 310 of each sub-array 302 according to the potential and pulse width of the pulse signals Pa to Po.

[0188] Fig.28 3 is a diagram showing an example of applying pulse signals Pa to Po having different potentials and pulse widths to each sub-array 302 of each column at the same time. In this case, the potential and pulse width of the pulse signals Pa to Po can be made different for each sub-array unit 30. This makes it possible to perform the operation described later at high speed. Fig.29 and Fig.30 Operations shown.

[0189] Fig.29 It is a diagram showing the pixel values ​​of the captured image and the calculated values ​​of the convolution operation in a cube. There are C captured images with pixels of vertical H and horizontal W as input values ​​(Input). The filter size used for the convolution operation is vertical R and horizontal S. One calculated value of the output value (fmap) is the convolution operation for the C captured images in the range of R×S. The coefficients of the convolution operation are the potential and pulse width of the pulse signals Pa to Po. Each coefficient is sometimes referred to as a weighting coefficient. M corresponds to the number obtained by converting the coefficients within the range of R×S of the C captured image, and the vertical H' and horizontal W' correspond to the numbers calculated by moving the filter within the vertical H and horizontal W.

[0190] Fig.30 It shows that when executing Fig.29 The diagram is a diagram showing an example of the configuration of the memory array unit 21 during the operation of Fig.30 As shown in FIG. 1 , by setting the number of memory cells in a column to R×S×C, a calculated value can be obtained. Fig.29 As shown, when M calculated values ​​are obtained at the same time, the number of columns may be M. The weighting coefficient at this time corresponds to the potential and pulse width of the pulse signals Pa to Po supplied to each column.

[0191] As described above, according to this embodiment, transistors tr7 and tr8 (one set of ends of which are connected to local bit lines LBL0x and LBL1x) and resistor r (the other end of which is connected to word line WL) are connected in series, and transistor tr8 is turned on according to the signal value stored in memory cell 310, and pulse signals Pa to Po are provided to word line WL. This allows capacitor c50 to store charges corresponding to the signal value of the memory cell and the potential and pulse width of pulse signals Pa to Po, and allows data of all memory cells 310 of subarray 302 to be multiplied and summed according to the potential and pulse width of pulse signals Pa to Po.

[0192] (Modification 1 of the third embodiment)

[0193] Fig.31 3 is a block diagram showing a subarray 302 according to modification 1 of the third embodiment. Fig.24 The configuration example of the sub-array 302 shown is different in that the first sub-array 302 and the second sub-array 302 are integrated. This allows the number of transistors to be reduced.

[0194] (Modification 2 of the third embodiment)

[0195] Fig.32 3 is a block diagram showing a sub-array 302 according to a modification 2 of the third embodiment. Each of the global bit lines GBL0 and GBL1 of each column may be divided by a plurality of capacitors c10 and c20. Dividing the voltage by the plurality of capacitors c10 and c20 is equivalent to multiplying the left global bit lines GBL0 and GBL1 by coefficients Xa, Xb, Xc, and Xd and adding them to the right global bit lines GBL0 and GBL1.

[0196] (Modification 3 of the third embodiment)

[0197] Fig.33 is a block diagram showing a sub-array 302 according to Modification 3 of the third embodiment. In the sub-array 302 according to Modification 3 of the third embodiment, the parasitic capacitance c50 can also be configured with a variable capacitance vc50. This makes it possible to further change the coefficient of each sub-array 302 in an integrated manner.

[0198] (Modification 4 of the third embodiment)

[0199] Fig.34 is a block diagram showing an example of the configuration of the memory array unit 21 according to Modification 4 of the third embodiment. Fig.23 The illustrated configuration example of the memory array cell 21 is different in that the memory array cell has a resistor R.

[0200] like Fig.34As shown, transistors tr1 and tr2 are connected to global bit lines GBL0 and GBL1 through resistors R. This allows the charge to be supplied to the parasitic capacitor call faster than Fig.33 The configuration example of the memory array unit 21 shown is delayed, and by turning off the transistors tr1 and tr2 before the charge is completely supplied, the amount of charge supplied from each sub-array 302 can be adjusted. In other words, by making the timing of turning off the transistors tr1 and tr2 different for each sub-array 302, the coefficient value of each sub-array 302 can be further adjusted.

[0201] (Modification 5 of the third embodiment)

[0202] Fig.35 : is a diagram showing a configuration example of a storage unit 310 according to Modification 5 of the third embodiment. Fig.35 The memory cell 310 shown has a transistor tr7a instead of Fig.33 The transistor Tr7 and the resistor R are shown. The resistance of the transistor Tr7a in the on state is equal to the resistance of the transistor Tr7 in the on state and the resistance of the resistor R connected in series. As a result, the resistor R is not required.

[0203] (Fourth Embodiment)

[0204] The imaging device 1 according to the fourth embodiment is different from the imaging device 1 according to the third embodiment in that the sub-array unit 30 constituting the memory array unit 21 is configured for each of the global bit lines GBL0 and GBL1. The difference from the imaging device 1 according to the third embodiment will be described below.

[0205] Fig.36 2 is a block diagram showing an example of the configuration of the memory array unit 21 according to the fourth embodiment. Fig.36 As shown, the memory array unit 21 has a sub-array unit 30 configured for each of the global bit lines GBL0 and GBL1. This makes it possible to perform independent addition and subtraction operations on each of the global bit lines GBL0 and GBL1 in addition to the same effects as the imaging device 1 according to the third embodiment.

[0206] (Modification 1 of Fourth Embodiment)

[0207] Fig.37 1 is a block diagram showing an example of the configuration of the memory array unit 21 according to the modification 1 of the fourth embodiment. In the memory array unit 21 according to the modification 1 of the fourth embodiment, the parasitic capacitance c50 is configured with the variable capacitance vc50. This provides the same effect as the imaging device 1 according to the fourth embodiment, and further allows the coefficient of each sub-array 302 to be changed in an integrated manner.

[0208] (Modification 2 of Fourth Embodiment)

[0209] Fig.38 2 is a block diagram showing an example of the configuration of the memory array unit 21 according to the modification 2 of the fourth embodiment. Fig.37 The illustrated configuration example of the memory array cell 21 is different in that the memory array cell has a resistor R.

[0210] like Fig.38 As shown, transistors tr1 and tr2 are connected to global bit lines GBL0 and GBL1 via resistors R. This allows the charge to be supplied to the parasitic capacitor call at a speed faster than Fig.37 The configuration example of the memory array unit 21 shown is delayed, and by turning off the transistors tr1 and tr2 before the charge is completely supplied, the amount of charge supplied from each sub-array 302 can be adjusted. In other words, by making the timing of turning off the transistors tr1 and tr2 different for each sub-array 302, the coefficient value of each sub-array 302 can be further adjusted.

[0211] (Modification 3 of Fourth Embodiment)

[0212] Fig.39 is a diagram showing a configuration example of a storage unit 310 according to Modification 3 of the fourth embodiment. Fig.39 The memory cell 310 shown has a transistor tr7a instead of Fig.36 The transistor Tr7 and the resistor R are shown. The resistance of the transistor Tr7a in the on state is equivalent to the resistance of the transistor Tr7 in the on state and the resistance of the resistor R connected in series. As a result, the resistor R is not required. The potentials provided to the SRAM can also be made different for the word lines WBL and WBLB. This makes it possible to further adjust the values ​​of the coefficients used in the product-sum operation.

[0213] (Fifth Embodiment)

[0214] The imaging device 1 according to the fifth embodiment is different from the imaging device 1 according to the first to fourth embodiments in that the imaging device 1 according to the fifth embodiment is configured so that the subarray 302 can be connected to the local bit lines LBL0 and LBL1 via the connection transistor tr10. The difference from the imaging device 1 according to the first to fourth embodiments will be described below.

[0215] Fig.40 1 is a block diagram showing an example of the configuration of the memory array unit 21 according to the fifth embodiment. Fig.40As shown, the sub-array 302 is configured so that the local bit lines LBL0 and LBL1 can be connected to the transistor tr10. A second capacitor c60 (not shown) is connected to the local bit lines LBL0 and LBL1 of each sub-array 302.

[0216] As a result, for example, when transistor tr10 is connected to read memory cell 310, the parasitic capacitance is twice the second capacitance c60. In addition, transistors tr10 and tr20 are transistors controlled to have opposite polarities, and the capacitance c20 of transistor tr20 is configured to be half the capacitance c10 of transistor tr10. It can be seen that, for example, when transistor tr10 is connected to read memory cell 310, the transistor has a capacitance of 2×c60+c20, and when the transistor is disconnected, the transistor has a capacitance of c60+c20 / 2. In this way, the parasitic capacitance can be adjusted by taking into account the capacitance of transistor tr10.

[0217] As described above, in the imaging device 1 according to the embodiment, the plurality of sub-arrays 302 are configured so that the local bit lines LBL0 and LBL1 can be connected through the transistor tr10. Therefore, when the memory cell 310 is read, by turning on or off the transistor tr10, the amount of stored charge can be changed by a multiple of 2. As a result, the coefficient associated with the memory cell 310 during the product-sum operation can be changed by a multiple of 2.

[0218] (Sixth Embodiment)

[0219] The imaging device 1 according to the sixth embodiment is different from the imaging devices 1 according to the first to fifth embodiments in that a plurality of sub-array units 30 are two-dimensionally arranged. The differences from the imaging devices 1 according to the first to fifth embodiments will be described below.

[0220] Fig.41 1 is a block diagram showing an example of the configuration of the memory array unit 21 according to the sixth embodiment. Fig.42 As shown, in the memory array unit 21 according to the sixth embodiment, a plurality of sub-array units 30 are arranged two-dimensionally. In addition, a plurality of sub-array units 30 in the same column are configured to be able to share a readout circuit 230 by switching a switch element. In addition, a sub-array unit 30 used as an arithmetic unit and a sub-array unit 30 used as a memory are configured to be able to be switched by switching a switch element. That is, in the memory array unit 21 according to the sixth embodiment, a sub-array unit 302 (see Figure 3 and Fig.33 etc.) and a sub-array 302 used as a memory is configured to be switchable by switching a switching element.

[0221] Fig.422 is a block diagram showing an example of the configuration of the memory array unit 21 which is also grouped in the row direction. Fig.42 As shown, a plurality of sub-array units 30 are also grouped in the row direction, and the plurality of sub-array units 30 grouped in the row direction are also configured to be able to share a readout circuit 230 by switching a switch element.

[0222] Fig.43 1 is a diagram showing an example in which only one end side of the sub-array unit 30 is configured to be connectable to the global bit line GBL. Fig.43 As shown, only the local bit line LBL on one end side of the sub-array unit 30 is configured to be connectable to the global bit line GBL. In addition, the plurality of sub-array units 30 are also grouped in the row direction, and the plurality of sub-array units 30 grouped in the row direction are also configured to be able to share the readout circuit 230 by switching the switch element.

[0223] Fig.44 2 is a block diagram showing an example of a configuration in which the readout circuit 230 is arranged at both ends of the memory array unit 21 . Fig.45 It is shown Fig.44 The configuration of FIG. 300 is a block diagram of an example in which the vertical driver 304, the horizontal driver 306 and the control unit 308 are arranged together. Fig.44 and Fig.45 As shown, by enabling the sub-array element 30 to be read from two directions, the sum-of-products operation can be performed at a higher speed.

[0224] The present technology can also adopt the following configurations. (1)

[0226] A computing device, comprising:

[0227] The first signal line;

[0228] A first capacitor connected to a first signal line;

[0229] at least one sub-array connected to the first signal line; and

[0230] The readout circuit generates a digital signal according to the charge of the first signal line, wherein:

[0231] The subarrays include:

[0232] a second signal line connected to the first signal line via the first switch element;

[0233] a second capacitor connected to the second signal line; and

[0234] At least one storage unit is connected to the second signal line and is capable of providing the second signal line with a charge corresponding to a signal value to be stored. (2)

[0236] The computing device according to (1), wherein:

[0237] The first capacitor and the second capacitor are parasitic capacitors formed in a metal layer of the semiconductor element. (3)

[0239] The computing device according to (1), wherein:

[0240] A plurality of sub-arrays are connected to a first signal line, and

[0241] The second capacitance is different for each sub-array. (4)

[0243] The computing device according to (1), wherein:

[0244] A plurality of sub-arrays are connected to a first signal line, and

[0245] The second capacitor is a variable capacitor. (5)

[0247] The computing device according to (4), wherein:

[0248] The memory unit is connected to the second signal line via the second switch element to supply the second signal line with charges corresponding to the signal value. (6)

[0250] The computing device according to (5), wherein:

[0251] The second switching element is composed of a single switching element or a plurality of switching elements connected in series,

[0252] One end of the second switch element is connected to the second signal line,

[0253] The second switch element is turned on or off according to the stored data,

[0254] A potential pulse signal is supplied from the other end of the second switching element, and

[0255] Charge corresponding to the potential and pulse width of the potential pulse signal is stored in the second capacitor. (7)

[0257] The computing device according to (5), wherein:

[0258] The subarray has multiple memory cells, and

[0259] The memory cell is a static random access memory (SRAM) having a second switching element. (8)

[0261] The computing device according to (7), wherein:

[0262] The computing device has:

[0263] A mode in which the second signal line and the plurality of storage cells are turned on sequentially at different timings,

[0264] A mode in which the second signal line and the plurality of memory cells are turned on simultaneously; and

[0265] The second signal line and the memory cell repeat a pattern of being turned on at different timings. (9)

[0267] The computing device according to (8), wherein:

[0268] When the plurality of sub-arrays are used as a memory, the variable capacitor of each of the plurality of sub-arrays has the same capacitance, and

[0269] When the plurality of sub-arrays are used as an arithmetic unit, the variable capacitance of each of the plurality of sub-arrays is variable according to a rate at which data is added. (10)

[0271] The computing device according to (9), wherein:

[0272] Among the plurality of sub-arrays, a sub-array to be used as an arithmetic unit and a sub-array to be used as a memory are configured to be switchable. (11)

[0274] The computing device according to (9), further comprising:

[0275] a first control unit that controls the first switching element and the second switching element; and

[0276] The second control unit controls the potential of the second signal line when writing data into the memory cell. (12)

[0278] The computing device according to (5), wherein:

[0279] The subarray has multiple memory cells, and

[0280] The storage unit is composed of a second switching element and a trigger. (13)

[0282] The computing device according to (1), wherein:

[0283] The second signal line is connected to the first signal line via the first switch element and the first resistor. (14)

[0285] The computing device according to (5), wherein:

[0286] The memory cell is connected to the second signal line via a second switching element and a second resistor. (15)

[0288] The computing device according to (5), wherein:

[0289] The first switching element or the second switching element has a predetermined resistance value. (16)

[0291] The computing device according to (5), further comprising:

[0292] a first control unit that controls the first switching element and the second switching element; and

[0293] a second control unit that controls the potential of the second signal line when writing data into the memory cell,

[0294] Array unit, where

[0295] The array unit has a plurality of sub-array units arranged in a matrix,

[0296] The sub-array unit has a plurality of sub-arrays connected to the first signal line in columns,

[0297] The first control unit is arranged at both ends of one of the array units, and

[0298] The second control unit is arranged at both ends of another location in the array unit. (17)

[0300] The computing device according to (16), wherein:

[0301] Multiple sub-array cells share readout circuitry. (18)

[0303] The computing device according to (16), comprising:

[0304] A plurality of readout circuits, wherein

[0305] At least one of the plurality of readout circuits is arranged at one end of the array unit, and

[0306] At least one of the plurality of readout circuits is disposed at the other end of the array unit. (19)

[0308] An imaging device, comprising:

[0309] The computing device according to (1); and

[0310] A pixel array unit in which pixels that generate pixel signals obtained by photoelectrically converting incident light are two-dimensionally arranged, wherein

[0311] Image data obtained by converting the pixel signal into digital data is stored in a storage unit of the arithmetic device. (20)

[0313] A computing method for a computing device, the computing device comprising:

[0314] a plurality of second signal lines connected to the first signal line connected to the first capacitor;

[0315] a second capacitor connected to each of the plurality of second signal lines; and

[0316] A storage unit is connected to each second signal line of a plurality of second signal lines, and the method comprises:

[0317] supplying each second signal line with a charge corresponding to a signal value to be stored in the memory cell;

[0318] storing in each second capacitor a charge corresponding to a signal value to be stored in the memory cell;

[0319] Capacitively dividing the charge stored between the first capacitor and the plurality of second capacitors; and

[0320] A digital signal corresponding to the charge of the first signal line is obtained.

[0321] The various aspects of the present disclosure are not limited to the above-mentioned embodiments, but also include various modifications that can be thought of by those skilled in the art, and the effects of the present disclosure are not limited to the above-mentioned contents. In other words, various additions, modifications and partial deletions are possible within the scope of the conceptual concept and intent of the present disclosure derived from the contents defined in the claims and their equivalents.

Claims

1. A computing device, comprising: The first signal line; A first capacitor connected to the first signal line; at least one sub-array connected to the first signal line; as well as A readout circuit generates a digital signal according to the charge of the first signal line, wherein: The sub-array includes: a second signal line connected to the first signal line via a first switch element; a second capacitor connected to the second signal line; and At least one storage unit is connected to the second signal line and is capable of providing the second signal line with a charge corresponding to a signal value to be stored.

2. The computing device according to claim 1, wherein: The first capacitor and the second capacitor are parasitic capacitors formed in a metal layer of a semiconductor element.

3. The computing device according to claim 1, wherein: A plurality of said sub-arrays are connected to said first signal line, and The second capacitance is different for each sub-array.

4. The computing device according to claim 1, wherein: A plurality of said sub-arrays are connected to said first signal line, and The second capacitor is a variable capacitor.

5. The computing device according to claim 4, wherein: The storage unit is connected to the second signal line via a second switching element to supply the charge corresponding to the signal value to the second signal line.

6. The computing device according to claim 5, wherein: The second switching element is composed of a single switching element or a plurality of switching elements connected in series, One end of the second switch element is connected to the second signal line, The second switch element is turned on or off according to the stored data, A potential pulse signal is provided from the other end of the second switching element, and Charge corresponding to the potential and pulse width of the potential pulse signal is stored in the second capacitor.

7. The computing device according to claim 5, wherein: The sub-array has a plurality of the memory cells, and The memory cell is a static random access memory (SRAM) having the second switching element.

8. The computing device according to claim 7, wherein: The computing device comprises: A mode in which the second signal line and the plurality of storage units are turned on sequentially at different timings, A mode in which the second signal line and the plurality of storage units are turned on simultaneously; and The second signal line and the memory cell repeat a pattern of being turned on at different timings.

9. The computing device according to claim 8, wherein: When the plurality of sub-arrays are used as memories, the variable capacitors in the plurality of sub-arrays have the same capacitance, and When the plurality of sub-arrays are used as an arithmetic unit, the variable capacitance of each of the plurality of sub-arrays is variable according to a rate at which data is added.

10. The computing device according to claim 9, wherein: Among the plurality of sub-arrays, a sub-array to be used as an arithmetic unit and a sub-array to be used as a memory are configured to be switchable.

11. The computing device according to claim 9, further comprising: a first control unit, controlling the first switch element and the second switch element; as well as The second control unit controls the potential of the second signal line when writing data into the memory cell.

12. The computing device according to claim 5, wherein: The sub-array has a plurality of the memory cells, and The storage unit is composed of the second switch element and a trigger.

13. The computing device according to claim 1, wherein: The second signal line is connected to the first signal line via the first switch element and a first resistor.

14. The computing device according to claim 5, wherein: The memory cell is connected to the second signal line via the second switch element and a second resistor.

15. The computing device according to claim 5, wherein: The first switching element or the second switching element has a predetermined resistance value.

16. The computing device according to claim 5, further comprising: a first control unit, controlling the first switch element and the second switch element; a second control unit that controls a potential of the second signal line when writing data into the storage unit; as well as Array unit, where The array unit has a plurality of sub-array units arranged in a matrix, The sub-array unit has a plurality of sub-arrays connected to the first signal line in columns, the first control unit is arranged at both ends of one location in the array unit, and the second control unit is arranged at both ends of another location in the array unit.

17. The computing device according to claim 16, wherein: A plurality of the sub-array units share the readout circuit.

18. The computing device according to claim 16, comprising: A plurality of said readout circuits, wherein: At least one of the plurality of readout circuits is arranged at one end of the array unit, and At least one of the plurality of readout circuits is arranged at the other end of the array unit.

19. An imaging device comprising: The computing device according to claim 1; as well as A pixel array unit in which pixels generating pixel signals obtained by photoelectrically converting incident light are two-dimensionally arranged, wherein Image data obtained by converting the pixel signal into digital data is stored in the storage unit of the arithmetic device.

20. A computing method for a computing device, the computing device comprising: a plurality of second signal lines connected to the first signal line connected to the first capacitor; a second capacitor connected to each of the second signal lines; as well as A storage unit is connected to each of the second signal lines of the plurality of second signal lines, and the method comprises: providing each of the second signal lines with a charge corresponding to a signal value to be stored in the storage unit; storing the charge corresponding to the signal value to be stored in the storage unit in each of the second capacitors; performing capacitance division on the charge stored between the first capacitor and the plurality of the second capacitors; and A digital signal corresponding to the charge of the first signal line is obtained.

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