Systems and methods for bidirectional message architecture for inverter for electric vehicle

Abstract

A system includes an inverter configured to convert DC power from a battery to AC power to drive a motor, where the inverter includes: an electrical interface configured to separate a high voltage region from a low voltage region; a low voltage message manager, the low voltage message manager being in the low voltage region; a high voltage message manager in the high voltage region and configured to communicate with the low voltage message manager; and a point of use message manager in the high voltage region and configured to communicate with the high voltage message manager.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 377,486 filed on September 28, 2022, U.S. Provisional Patent Application No. 63 / 377,501 filed on September 28, 2022, U.S. Provisional Patent Application No. 63 / 377,512 filed on September 28, 2022, U.S. Provisional Patent Application No. 63 / 378,601 filed on October 6, 2022, and U.S. Non-Provisional Patent Application No. 18 / 057,890 filed on November 22, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of the present disclosure relate generally to circuit communication architectures, and more particularly to bidirectional communication architectures for withstanding coupling currents. Background Art

[0004] Inverters, such as those used to drive motors in electric vehicles, are responsible for converting high voltage direct current (HVDC) to alternating current (AC) to drive the motor, for example. Common mode transients occur during power device switching and when one side of a floating high voltage battery terminal is shorted to ground or subjected to electrostatic discharge. These voltage transients cause fast edges that form common mode current bursts through electrical isolation and affect the operation of the gate driver.

[0005] The present disclosure is directed to overcoming one or more of these aforementioned challenges. Summary of the invention

[0006] In some aspects, the technology described herein relates to a system comprising: an inverter configured to convert DC power from a battery into AC power to drive a motor, wherein the inverter comprises: an electrical interface configured to separate a high voltage area from a low voltage area; a low voltage message manager in the low voltage area; a high voltage message manager in the high voltage area and configured to communicate with the low voltage message manager; and a point-of-use message manager in the high voltage area and configured to communicate with the high voltage message manager.

[0007] In some aspects, the technology described herein relates to a system that further includes a battery configured to supply DC power to an inverter and a motor configured to receive AC power from the inverter to drive the motor.

[0008] In some aspects, the technology described herein relates to a system wherein a point-of-use message manager is in a power module that includes one or more power device switches for an inverter, and wherein the inverter further includes: a single-wire data bus that connects a high voltage message manager to the point-of-use message manager, wherein the point-of-use message manager is configured to communicate with the high voltage message manager using the single-wire data bus, and a timer that is configured to measure a time period that the single-wire data bus is in a dominant phase or a recessive phase, wherein the low voltage message manager, the high voltage message manager, and the point-of-use message manager are configured to communicate using a logic 0 bit and a logic 1 bit, wherein a logic 0 bit is defined as a dominant phase measured by the timer for a first time period followed by a recessive phase measured for a second time period, and a logic 1 bit is defined as a dominant phase measured by the timer for a first time period followed by a recessive phase measured for a third time period that is longer than the second time period for the logic 0 bit.

[0009] In some aspects, the technology described herein relates to a system comprising: an electrical interface configured to separate a high voltage region from a low voltage region; a low voltage message manager in the low voltage region; a high voltage message manager in the high voltage region and configured to communicate with the low voltage message manager; and a point-of-use message manager in the high voltage region and configured to communicate with the high voltage message manager.

[0010] In some aspects, the technology described herein relates to a system further comprising: a single wire data bus connecting the high voltage message manager to the point of use message manager, wherein the point of use message manager is configured to communicate with the high voltage message manager using the single wire data bus.

[0011] In some aspects, the technology described herein relates to a system further comprising: a first switched current source, the first switched current source configured to operate with the high voltage message manager to drive the single wire data bus to a power rail; a second switched current source, the second switched current source configured to operate with the point-of-use message manager to drive the single wire data bus to the power rail; a third switched current sink, the third switched current sink configured to operate with the high voltage message manager to drive the single wire data bus to a ground rail; and a fourth switched current sink, the fourth switched current sink configured to operate with the point-of-use message manager to drive the single wire data bus to the ground rail.

[0012] In some aspects, the technology described herein relates to a system wherein one or more of a first switched current source or a second switched current source is configured to overdrive a state of a single-wire data bus as driven by operation of a third switched current sink or a fourth switched current sink, or wherein one or more of a third switched current sink or a fourth switched current sink is configured to overdrive a state of a single-wire data bus as driven by operation of the first switched current source or the second switched current source.

[0013] In some aspects, the techniques described herein relate to a system in which a first switched current source, a second switched current source, a third switched current sink, and a fourth switched current sink have a higher current capability than an expected worst case external coupling current.

[0014] In some aspects, the technology described herein relates to a system further comprising: a first comparator configured to operate with the high voltage message manager to distinguish between a high state or a low state of a single wire data bus; and a second comparator configured to operate with the point of use message manager to distinguish between a high state or a low state of the single wire data bus.

[0015] In some aspects, the techniques described herein relate to a system in which a point-of-use message manager is in a power module that includes one or more power device switches for an inverter.

[0016] In some aspects, the technology described herein relates to a system wherein one or more of a low voltage message manager, a high voltage message manager, or a point of use message manager includes a timer configured to measure a time period that a single wire data bus is in a dominant phase or a recessive phase.

[0017] In some aspects, the technology described herein relates to a system in which a low voltage message manager, a high voltage message manager, and a point of use message manager are configured to communicate using a logic 0 bit and a logic 1 bit, wherein a logic 0 bit is defined as a dominant phase measured by a timer for a first time period followed by a recessive phase measured for a second time period, and a logic 1 bit is defined as a dominant phase measured by a timer for a first time period followed by a recessive phase measured for a third time period longer than the second time period for the logic 0 bit.

[0018] In some aspects, the technology described herein relates to a system in which an interrupt manager in a low voltage message manager, a high voltage message manager, and a point-of-use message manager is configured to interrupt a transmission manager in the low voltage message manager, the high voltage message manager, and the point-of-use message manager by transmitting a logic 0 bit or a logic 1 bit during a second time period or a third time period, and the transmission manager is configured to yield communication to the interrupt manager within a single bit transmission.

[0019] In some aspects, the techniques described herein relate to a system in which a low voltage message manager, a high voltage message manager, and a point of use message manager are configured to communicate with any other of the low voltage message manager, the high voltage message manager, and the point of use message manager.

[0020] In some aspects, the technology described herein relates to a method for communicating with a power device switch for an inverter, the method comprising: transmitting messages between a high voltage message manager of the inverter and a point of use message manager for the power device switch using a single wire data bus.

[0021] In some aspects, the technology described herein relates to a method further comprising measuring, with a timer of the inverter, a time period during which the single-wire data bus is in a dominant phase or a recessive phase.

[0022] In some aspects, the technology described herein relates to a method in which transmitting a message includes: using a logic-0 bit and a logic-1 bit, wherein the logic-0 bit is defined as a dominant phase measured by a timer for a first time period followed by a recessive phase measured for a second time period, and the logic-1 bit is defined as a dominant phase measured by the timer for the first time period followed by a recessive phase measured for a third time period longer than the second time period for the logic-0 bit.

[0023] In some aspects, the technology described herein relates to a method further comprising transmitting a logic 0 bit or a logic 1 bit during a second time period or a third time period to interrupt the communication of a message within a single bit transmission.

[0024] In some aspects, the technology described herein relates to a method further comprising applying one or more of a current source or a current sink to a single-wire data bus.

[0025] In some aspects, the techniques described herein relate to a method in which the one or more of the current source or the current sink has a higher current capability than an expected worst case external coupling current.

[0026] Other objects and advantages of the disclosed embodiments will be described in part in the following description, and in part will be obvious from the description, or can be understood by practicing the disclosed embodiments. The objects and advantages of the disclosed embodiments will be realized and achieved by means of the elements and combinations particularly pointed out in the appended claims.

[0027] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosed embodiments, as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various exemplary embodiments and, together with the description, serve to explain the principles of the disclosed embodiments.

[0029] Figure 1 An exemplary system infrastructure for a vehicle including a combined inverter and converter is depicted according to one or more embodiments.

[0030] Figure 2 Depicted is a method for providing a point-of-use switching controller according to one or more embodiments. Figure 1 An exemplary system infrastructure of a combined inverter and converter.

[0031] Figure 3 Describes a method for Figure 2 An exemplary system infrastructure for a controller of FIG.

[0032] Figure 4 Describes a method for Figure 2 An exemplary system infrastructure for a point-of-use switching controller.

[0033] Figure 5 Describes a method for Figure 4 An exemplary system infrastructure of an upper power module.

[0034] Figure 6 Depicted is an exemplary electrical schematic diagram for a bidirectional communication architecture in accordance with one or more embodiments.

[0035] Figure 7 Depicted is an exemplary messaging protocol between logic managers in a circuit in accordance with one or more embodiments.

[0036] Figure 8 Depicted is an exemplary messaging protocol between logic managers in a circuit in accordance with one or more embodiments.

[0037] Fig. 9Depicted is an exemplary electrical schematic diagram for a bidirectional communication architecture in accordance with one or more embodiments.

[0038] Fig.10 Depicted are exemplary methods for message communications in accordance with one or more embodiments. DETAILED DESCRIPTION

[0039] Both the foregoing general description and the following detailed description are exemplary and explanatory only and do not constrain the claimed features. As used herein, the terms "comprises," "comprising," "has," "having," "includes," "including," or other variations thereof are intended to encompass non-exclusive inclusions such that a process, method, article, or device that includes a series of elements includes not only those elements, but may also include other elements that are not explicitly listed or inherent to such process, method, article, or device. In the present disclosure, unless otherwise stated, relative terms (such as, for example, "about," "substantially," and "approximately") are used to indicate possible ±10% variations in the stated values. In the present disclosure, unless otherwise stated, any numerical value may include possible ±10% variations in the stated values.

[0040] The terms used below may be interpreted in their broadest reasonable manner, although they are being used in conjunction with a detailed description of certain specific examples of the present disclosure. Indeed, certain terms may even be emphasized below; however, any term intended to be interpreted in any constrained manner will be explicitly and specifically defined as such in this detailed description. For example, in the context of the present disclosure, a switching device may be described as a switching element or device, but may refer to any device for controlling power flow in a circuit. For example, a switching element may be, for example, a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT) or a relay, or any combination thereof, but is not limited thereto.

[0041] Various embodiments of the present disclosure relate generally to circuit communication architectures, and more particularly to bidirectional communication architectures for withstanding coupling currents.

[0042] Inverters (such as those used to drive motors in electric vehicles) are responsible for converting high voltage direct current (HVDC) into alternating current (AC) to drive the motor. A three-phase inverter may include a bridge having six power device switches (e.g., power transistors such as IGBTs or MOSFETs) that are controlled by pulse width modulation (PWM) signals generated by a controller. The inverter may include three half-H-bridge switches to control phase voltages, upper and lower gate drivers to control the switches, a PWM controller, and glue logic between the PWM controller and the gate driver. The PWM controller may generate signals to define the expected state of the system. The gate driver may send signals from the PWM controller to the half-H-bridge switches. The half-H-bridge switches may drive the phase voltages. The inverter may include an isolation barrier between a low voltage plane and a high voltage plane. The signal may be passed from the PWM controller to the half-H-bridge switch by passing through the isolation barrier, which may employ optical, converter-based, or capacitor-based isolation. The PWM signal may be distorted when passing through the glue logic, which may include resistive, capacitive, or other types of filtering. Due to the electrical isolation barrier and other delays within the gate driver, the PWM signal may be distorted when passing through the gate driver. The PWM signal may be distorted when the signal is processed by the half-H switching element via the gate driver output.

[0043] Gate drivers withstand common-mode transients that occur during field effect transistor (FET) switching and when one side of a floating high voltage terminal is shorted to ground or subjected to electrostatic discharge. These voltage transients can cause fast edges that can form common-mode current bursts through electrical isolation. Gate drivers may need to demonstrate common-mode transient immunity (CMTI) in order to be effective and safe.

[0044] The gate driver may have a high voltage domain in common with the voltage plane of the associated FET. Further, the high voltage plane may be supplied by a flyback converter, which may be isolated from the low voltage plane by a transformer. The high voltage domain power supply may be used to provide power to such a circuit that sources and sinks gate current to drive the FET and can detect FET faults, thereby acting on the faults and / or transmitting the faults to the low voltage domain. The gate driver may include an electrical channel dedicated to FET commands, and one or more bidirectional or unidirectional electrical channels dedicated to FET communications.

[0045] High current switching transients can form strong electromagnetic (EM) fields that can couple into nearby metal traces. The magnitude and frequency of the coupled current can depend on the layout of the FET packaging solution and the direction and length of the metal traces between the FET and the control integrated circuit (IC). For example, a typical value for the coupled current can be up to 1A at an AC frequency of up to 100MHz. Typically, within the circuit, the gate driver IC can be placed far enough away from the FET so that the high EM field is not directly coupled into the internal metal traces within the gate driver IC. The gate driver is placed at a distance from the EM field so that the induced current within the circuit is below the level that will cause the gate driver to malfunction, or a metal shield is placed between the gate driver and the source of the EM field to protect the gate driver circuit. The output terminals of the gate driver connected to the FET are exposed to the EM field at a point where the output terminals are no longer covered by the shield. The gate driver switches large currents (e.g., such as 5A to 15A) through these exposed terminals. The large currents switched are usually larger in magnitude than the EM induced current. The gate driver can overdrive the induced current to maintain control of the FET. The gate driver and the high side of the FET may share a common ground and gate control signal trace, both of which may be susceptible to coupled currents.

[0046] The gate driver can turn on low resistance switches to source and sink gate current. Sometimes a series resistor can be added to limit the gate current. The switched gate current can be greater than the coupling current in order to maintain control of their respective FETs.

[0047] The gate driver may be able to sense the FET operating voltage or current in order to provide feedback and react to faults. An overcurrent fault may typically be detected by sensing the FET drain to source voltage and comparing the sensed voltage to a reference value. The sensed voltage may be heavily filtered to reject coupled currents. Filtering may slow the response to a fault condition, causing a delay in response. For example, the rate of current increase due to a low resistance short may reach damaging levels before being detected by a heavily filtered drain to source voltage detection strategy. The resulting short may damage the FET or the vehicle before being detected and cut off.

[0048] According to one or more embodiments, a FET driver circuit may provide fast overcurrent detection by shunt current sensing, or by diverting a portion of the load current through a parallel FET that may have a current sensing circuit. Utilizing either strategy may require a "point of use IC" in which the sensing circuit is very close to the FET. Even if the point of use IC and the remote controller are resistant to EM fields, the communication between the point of use IC and the remote controller is still susceptible to induced currents. Point of use ICs have been implemented in low EM field applications, such as smart FETs for automotive applications. However, due to the lack of a high-speed messaging architecture that is robust to coupled currents, point of use ICs have not been used in high EM field applications. High EM fields can be fields that (i) induce a current within the IC that exceeds the operating current of the IC and causes a malfunction, or (ii) induce a differential voltage within the IC that exceeds the operating differential voltage and causes a malfunction. High EM fields can be, for example, fields greater than about 10A or about 100V.

[0049] According to one or more embodiments, a high-speed bidirectional communication architecture can withstand coupling currents to enable point-of-use ICs to be placed in high EM field applications. The point-of-use ICs can reduce detection and response times to allow safe control and management of FETs within inverter systems.

[0050] Some architectures may disclose isolation between a microcontroller in a primary plane and a load in a secondary plane that may be controlled by a switch. The isolation is achieved through a converter that may be inherently susceptible to induced currents generated by EM fields during high current switching of the load. Some architectures cannot compensate for induced currents in the primary or secondary converters. Some communication architectures designed to withstand EM disturbances may include local interconnect network (LIN) and controller area network (CAN) systems.

[0051] The LIN single wire bus architecture uses the required external components that can be connected to the LIN bus. These systems can describe a LIN architecture with a maximum data rate of 20kB / s, where the bus low state is a logic 0 and the bus high state is a logic 1. The bus can be passively pulled up to a higher voltage using a 1kOhm resistor and actively pulled down to a lower voltage using a switch with a maximum specified current limit of 200mA. The LIN driver current may be too low to reject the coupling current, which may range from 100mA to 1A.

[0052] The CAN architecture has a two-wire bus using passive bus load resistors and a message protocol. The CAN architecture may have a maximum data rate of 5MB / S with a differential stage bus driver at logic 0 and a bus passively pulled together at logic 1. The bus may be passively pulled together using 120Ohm termination resistors on either end of the bus and actively pulled down using switches with a maximum specified current limit of 100mA. The CAN bus may use a twisted pair architecture which may have a high common mode rejection of coupled currents unless the current is high enough to resist the maximum voltage of the bus with an electrostatic discharge fixture. A 1A inductive current may be more than sufficient to direct the CAN bus in this manner, and therefore CAN may not be an acceptable architecture for high EM field applications.

[0053] According to one or more embodiments, the gate driver system described below may be utilized to solve the problem of communication through large coupling currents.

[0054] Figure 1 An exemplary system infrastructure for a vehicle including a combined inverter and converter according to one or more embodiments is depicted. In the context of the present disclosure, the combined inverter and converter may be referred to as an inverter. Figure 1 As shown, the electric vehicle 100 may include an inverter 110, a motor 190, and a battery 195. The inverter 110 may include a component for receiving electric power from an external source and outputting electric power to charge the battery 195 of the electric vehicle 100. For example, the inverter 110 may convert DC power from the battery 195 in the electric vehicle 100 into AC power to drive the motor 190 of the electric vehicle 100, but the embodiment is not limited thereto. For example, the inverter 110 may be bidirectional and may convert DC power into AC power, or convert AC power into DC power, such as during regenerative braking. The inverter 110 may be a three-phase inverter, a single-phase inverter, or a multi-phase inverter.

[0055] Figure 2 Depicted is a method for providing a point-of-use switching controller according to one or more embodiments. Figure 1 The electric vehicle 100 may include an inverter 110, a motor 190, and a battery 195. The inverter 110 may include an inverter controller 300 ( Figure 314). The inverter 110 may include a low voltage upper phase controller 120 separated from a high voltage upper phase controller 130 by an electrical isolator 150, and an upper phase power module 140. The upper phase power module 140 may include a point-of-use upper phase controller 142 and an upper phase switch 144. The inverter 110 may include a low voltage lower phase controller 125 separated from a high voltage lower phase controller 135 by an electrical isolator 150, and a lower phase power module 145. The lower phase power module 145 may include a point-of-use lower phase controller 146 and a lower phase switch 148. The upper phase switch 144 and the lower phase switch 148 may be connected to a motor 190 and a battery 195. The electrical isolator 150 may be one or more of optical, converter-based, or capacitor-based isolation. For example, the electrical isolator 150 may be one or more capacitors having a value from about 20 fF to about 100 fF, having a breakdown voltage from about 6 kV to about 12 kV. The electrical isolator 150 may include a pair of capacitors, wherein one capacitor in the pair carries an inverted data signal from the other capacitor in the pair to form a differential signal that is rejected for common mode noise. The electrical isolator 150 may include more than one capacitor in series. The electrical isolator 150 may include one capacitor located on a first IC, or may include a first capacitor located on a first IC and a second capacitor located on a second IC that communicates with the first IC.

[0056] The inverter 110 may include a low voltage region (e.g., where the voltage is typically less than 5V) and a high voltage region (e.g., where the voltage may exceed 500V). The low voltage region may be separated from the high voltage region by an electrical isolator 150. The inverter controller 300 may be in the low voltage region of the inverter 110, and may send a signal to and receive a signal from the low voltage upper phase controller 120. The low voltage upper phase controller 120 may be in the low voltage region of the inverter 110, and may send a signal to and receive a signal from the high voltage upper phase controller 130. The low voltage upper phase controller 120 may send a signal to and receive a signal from the low voltage lower phase controller 125. The high voltage upper phase controller 130 may be in the high voltage region of the inverter 110. Therefore, the signal between the low voltage upper phase controller 120 and the high voltage upper phase controller 130 passes through the electrical isolator 150. The high voltage upper phase controller 130 may send signals to and receive signals from a point-of-use upper phase controller 142 in the upper phase power module 140. The point-of-use upper phase controller 142 may send signals to and receive signals from an upper phase switch 144. The upper phase switch 144 may be connected to a motor 190 and a battery 195. For example, the upper phase switch 144 and the lower phase switch 148 may be used to transfer energy from the motor 190 to the battery 195, from the battery 195 to the motor 190, from an external source to the battery 195, or from the battery 195 to an external source. The lower phase system of the inverter 110 may be similar to the upper phase system described above.

[0057] Figure 3 Describes a method for Figure 2 FIG. 3 is an exemplary system infrastructure of an inverter controller 300 . The inverter controller 300 may include one or more controllers.

[0058] The inverter controller 300 may include a set of instructions that can be executed to cause the inverter controller 300 to perform any one or more of the methods or computer-based functions disclosed herein. The inverter controller 300 may operate as a standalone device, or may be connected to other computer systems or peripheral devices, for example using a network.

[0059] In a networked deployment, the inverter controller 300 can operate in the capacity of a server, or as a client in a server-client user network environment, or as a peer computer system in a peer (or distributed) network environment. The inverter controller 300 can also be implemented as or incorporated into various devices, such as a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile device, a palmtop computer, a laptop computer, a desktop computer, a communication device, a wireless phone, a landline phone, a control system, a camera, a scanner, a fax machine, a printer, a pager, a personal trusted device, a network device, a network router, a switch or bridge, or any other machine capable of executing a set of instructions (sequentially or otherwise) (the set of instructions specifies the actions to be taken by the machine). In a specific implementation, the inverter controller 300 can be implemented using an electronic device that provides voice, video or data communication. Further, although the inverter controller 300 is illustrated as a single system, the term “system” should also be understood to include any collection of systems or subsystems that individually or jointly execute one or more sets of instructions to perform one or more computer functions.

[0060] like Figure 3 As shown, the inverter controller 300 may include a processor 302, such as a central processing unit (CPU), a graphics processing unit (GPU), or both. The processor 302 may be a component in a variety of systems. For example, the processor 302 may be part of a standard inverter. The processor 302 may be one or more general-purpose processors, digital signal processors, application-specific integrated circuits, field programmable gate arrays, servers, networks, digital circuits, analog circuits, combinations thereof, or other devices now known or later developed for analyzing and processing data. The processor 302 may implement a software program, such as a manually generated (i.e., programmed) code.

[0061] The inverter controller 300 may include a memory 304 that can communicate via a bus 308. The memory 304 may be a main memory, a static memory, or a dynamic memory. The memory 304 may include, but is not limited to, computer-readable storage media, such as various types of volatile and non-volatile storage media, including but not limited to random access memory, read-only memory, programmable read-only memory, electrically programmable read-only memory, electrically erasable read-only memory, flash memory, tape or disk, optical media, etc. In one specific implementation, the memory 304 includes a cache or random access memory for the processor 302. In an alternative specific implementation, the memory 304 is separated from the processor 302, such as a cache memory, system memory, or other memory of the processor. The memory 304 may be an external storage device or database for storing data. Examples include a hard drive, a compact disk ("CD"), a digital video disk ("DVD"), a memory card, a memory stick, a floppy disk, a universal serial bus ("USB") storage device, or any other device operable to store data. The memory 304 is operable to store instructions that can be executed by the processor 302. The functions, actions, or tasks illustrated in the figures or described herein may be performed by the processor 302 executing instructions stored in the memory 304. The functions, actions, or tasks are not related to a particular type of instruction set, storage medium, processor, or processing strategy, and may be performed by software, hardware, integrated circuits, firmware, microcode, etc. operating alone or in combination. Likewise, processing strategies may include multi-processing, multi-tasking, parallel processing, etc.

[0062] As shown, the inverter controller 300 may further include a display 310, such as a liquid crystal display (LCD), an organic light emitting diode (OLED), a flat panel display, a solid state display, a cathode ray tube (CRT), a projector, a printer, or other display devices known now or later developed for outputting the determined information. The display 310 may serve as an interface for a user to view the operation of the processor 302, or specifically serve as an interface with the software stored in the memory 304 or in the drive unit 306.

[0063] Additionally or alternatively, the inverter controller 300 may include an input device 312 configured to allow a user to interact with any of the components of the inverter controller 300. The input device 312 may be a numeric keypad, a keyboard or a cursor control device (such as a mouse or a joystick), a touch screen display, a remote control, or any other device operable to interact with the inverter controller 300.

[0064] The inverter controller 300 may also or alternatively include a drive unit 306 implemented as a disk or optical drive. The drive unit 306 may include a computer-readable medium 322 in which one or more sets of instructions 324 (e.g., software) may be embedded. Further, the instructions 324 may embody one or more of the methods or logics described herein. The instructions 324 may reside completely or partially within the memory 304 and / or within the processor 302 during execution by the inverter controller 300. The memory 304 and the processor 302 may also include computer-readable media as described above.

[0065] In some systems, the computer-readable medium 322 includes instructions 324 or receives and executes instructions 324 in response to a propagated signal, so that a device connected to the network 370 can transmit voice, video, audio, images, or any other data through the network 370. Further, the instructions 324 can be transmitted or received through the network 370 and / or using the bus 308 via the communication port or interface 320. The communication port or interface 320 can be part of the processor 302 or can be an independent component. The communication port or interface 320 can be formed in software or can be a physical connector in hardware. The communication port or interface 320 can be configured to connect to the network 370, external media, display 310, or any other component in the inverter controller 300, or a combination thereof. The connection to the network 370 can be a physical connection (such as a wired Ethernet connection) or can be established wirelessly, as described below. Similarly, additional connections to other components of the inverter controller 300 can be physical connections or can be established wirelessly. The network 370 can alternatively be directly connected to the bus 308.

[0066] Although the computer-readable medium 322 is shown as a single medium, the term "computer-readable medium" may include a single medium or multiple media (such as a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" may also include any medium capable of storing, encoding, or carrying a set of instructions for execution by a processor or causing a computer system to perform any one or more of the methods or operations disclosed herein. The computer-readable medium 322 may be non-transitory and may be tangible.

[0067] Computer readable medium 322 may include solid-state memory, such as a memory card or other package that accommodates one or more non-volatile read-only memories. Computer readable medium 322 may be random access memory or other volatile rewritable memory. Additionally or alternatively, computer readable medium 322 may include magneto-optical or optical media, such as a disk or tape or other storage device for capturing carrier signals (such as signals transmitted through a transmission medium). Digital file attachments to emails or other self-contained information archives or archive sets may be considered distribution media as tangible storage media. Therefore, the present disclosure is considered to include any one or more of computer-readable media or distribution media and other equivalents and successor media in which data or instructions may be stored.

[0068] In alternative implementations, dedicated hardware implementations (such as application specific integrated circuits, programmable logic arrays, and other hardware devices) may be constructed to implement one or more of the methods described herein. Applications that may include the apparatus and systems of various implementations may broadly include a variety of electronic and computer systems. One or more implementations described herein may use two or more specific interconnected hardware modules or devices with associated control and data signals that may be transmitted between and through the modules or as part of an application specific integrated circuit to implement functionality. Thus, the present system encompasses software, firmware, and hardware implementations.

[0069] The inverter controller 300 may be connected to a network 370. The network 370 may define one or more networks, including wired or wireless networks. The wireless network may be a cellular telephone network, an 802.11, 802.16, 802.20, or WiMAX network. Further, such networks may include public networks (such as the Internet), private networks (such as intranets), or combinations thereof and may utilize a variety of networking protocols that are now available or later developed, including but not limited to TCP / IP-based networking protocols. The network 370 may include a wide area network (WAN) (such as the Internet), a local area network (LAN), a campus area network, a metropolitan area network, a direct connection (such as through a universal serial bus (USB) port), or any other network that allows data communication. The network 370 may be configured to couple one computing device to another computing device to enable data communication between devices. The network 370 may generally be enabled to use any form of machine-readable media to transmit information from one device to another. The network 370 may include a communication method by which information can travel between computing devices. The network 370 may be divided into subnetworks. A subnetwork may allow access to all other components connected to it, or a subnetwork may restrict access between components. Network 370 may be considered a public or private network connection and may include, for example, a virtual private network or encryption or other security mechanisms employed over the public Internet.

[0070] According to various implementations of the present disclosure, the methods described herein may be implemented by a software program that can be executed by a computer system. Further, in an exemplary non-limiting implementation, the implementation may include distributed processing, component or object distributed processing, and parallel processing. Alternatively, a virtual computer system process may be constructed to implement one or more of the methods or functionalities described herein.

[0071] Although this specification describes components and functions that can be implemented in a specific implementation with reference to specific standards and protocols, the present disclosure is not limited to such standards and protocols. For example, standards for Internet and other packet-switched network transmissions (e.g., TCP / IP, UDP / IP, HTML, HTTP) represent examples of the prior art. Such standards are periodically replaced by faster or more efficient equivalents having substantially the same functionality. Therefore, alternative standards and protocols having the same or similar functionality as those disclosed herein are considered equivalents thereof.

[0072] It will be appreciated that, in one embodiment, the operations of the methods discussed are performed by an appropriate processor (or processors) of a processing (i.e., computer) system executing instructions (computer readable code) stored in a storage device. It will also be appreciated that the present disclosure is not limited to any particular implementation or programming technique, and that the present disclosure may be implemented using any suitable technique for implementing the functionality described herein. The present disclosure is not limited to any particular programming language or operating system.

[0073] Figure 4 Describes a method for Figure 2 An exemplary system infrastructure of a point-of-use switching controller. For a three-phase inverter, each of the upper phase and the lower phase may include three phases related to phases A, B, and C. For example, the upper phase power module 140 may include an upper phase power module 140A for upper phase A, an upper phase power module 140B for upper phase B, and an upper phase power module 140C for upper phase C. The upper phase power module 140A may include a point-of-use upper phase A controller 142A and an upper phase A switching element 144A. The upper phase power module 140B may include a point-of-use upper phase B controller 142B and an upper phase B switching element 144B. The upper phase power module 140C may include a point-of-use upper phase C controller 142C and an upper phase C switching element 144C. Each of the upper phase A switching member 144A, the upper phase B switching member 144B, and the upper phase C switching member 144C may be connected to the motor 190 and the battery 195 . Figure 4 Details of the upper phase power module 140 are depicted. Although not shown, the lower phase power module 145 may include a similar structure as the upper phase power module 140 for the lower phases A, B, and C.

[0074] Figure 5 Describes a method for Figure 4 Example system infrastructure for the upper power module. For example, Figure 5 Additional details of upper phase power module 140A are provided. Although not shown, upper phase power module 140B, upper phase power module 140C, and respective lower phase power modules of lower phase power module 145 may include components related to Figure 5 The upper phase power module 140A shown in FIG. 1 is similar in structure to the upper phase power module 140A shown in FIG. 1. In addition, the terms "upper", "lower", "northern", and "southern" as used in this disclosure are used for reference only, do not limit the elements to a particular orientation, and are generally interchangeable throughout the text. For example, the upper phase power module 140 may be referred to as a lower phase power module, a northern phase power module, a southern phase power module, a first phase power module, or a second phase power module.

[0075] The upper phase power module 140A may include a point-of-use upper phase A controller 142A and an upper phase A switch 144A. The upper phase A switch 144A may include one or more sets of switches. Figure 5 As shown, the upper phase A switch 144A may include an upper phase A north switch 144A-N and an upper phase A south switch 144A-S. The point-of-use upper phase A controller 142A may include one or more memories, controllers, or sensors. For example, the point-of-use upper phase A controller 142A may include a communication manager 405, a functional safety controller 410, a test interface and controller 415, a north thermal sensor 420A, a south thermal sensor 420B, a self-test controller 425, a command manager 430, a waveform adjuster 435, a memory 440, a north switch control and diagnostic controller 450N, and a south switch control and diagnostic controller 450S. The point-of-use upper phase A controller 142A may include a controller 405, a functional safety controller 410, a test interface and controller 415, a north thermal sensor 420A, a south thermal sensor 420B, a self-test controller 425, a command manager 430, a waveform adjuster 435, a memory 440, a north switch control and diagnostic controller 450N, and a south switch control and diagnostic controller 450S. Figure 5 More or fewer components than those shown. For example, the point-of-use upper phase A controller 142A may include more or less than two switch controls and diagnostic controllers, and may include more than two thermal sensors.

[0076] The communication manager 405 may control inter-controller communications to and from the point-of-use upper phase A controller 142A and / or may control intra-controller communications between components of the point-of-use upper phase A controller 142A. The functional safety controller 410 may control safety functions of the point-of-use upper phase A controller 142A. For example, the test interface and controller 415 may control test functions of the point-of-use upper phase A controller 142A, such as end-of-line testing in manufacturing. The north thermal sensor 420A may sense the temperature at a first location in the point-of-use upper phase A controller 142A, and the south thermal sensor 420B may sense the temperature at a second location in the point-of-use upper phase A controller 142A. For example, the self-test controller 425 may control self-test functions of the point-of-use upper phase A controller 142A, such as during initialization of the point-of-use upper phase A controller 142A after an inverter 110 power-on event. The command manager 430 may control commands received from the communication manager 405 and issued to the north switch control and diagnostic controller 450N and the south switch control and diagnostic controller 450S. The waveform adjuster 435 may control the waveform timing and shape of the commands received from the communication manager 405 and issued to the north switch control and diagnostic controller 450N and the south switch control and diagnostic controller 450S. The memory 440 may include one or more volatile and non-volatile storage media for the operation of the point-of-use upper phase A controller 142A. The north switch control and diagnostic controller 450N may send one or more signals to the north switch 144A-N to control the operation of the north switch 144A-N, and may receive one or more signals from the north switch 144A-N that provide information about the north switch 144A-N. The south switch control and diagnostic controller 450S may send one or more signals to the south switches 144A-S to control the operation of the south switches 144A-S, and may receive one or more signals from the south switches 144A-S providing information about the south switches 144A-S. As described above, the terms "north" and "south" are used for reference only, and the north switch control and diagnostic controller 450N may send one or more signals to the south switches 144A-S, and the south switch control and diagnostic controller 450S may send one or more signals to the south switches 144A-N.

[0077] Figure 6 An exemplary electrical schematic diagram for a bidirectional communication architecture according to one or more embodiments is depicted. The bidirectional communication architecture may include one or more integrated circuits or other electronic circuits. Figure 6As shown, the gate driver 600 of the inverter 110 may include two ground (GND) planes, represented as GND1 608 and GND2 610, which may be separated by an electrical interface 604. GND1 608 may be a low voltage plane of the inverter 110, and GND2 610 may be a high voltage plane of the inverter 110, and the electrical interface 604 may be a specific implementation of the electrical isolator 150. GND1 608 and GND2 610 may communicate by modulating a stream of pulses in either direction across the electrical interface 604 using electrical transceivers that may be controlled by logic managers (referred to as MGR1 612 and MGR2 614, respectively). MGR1 612 and MGR2 614 may include additional components as shown by MGR1 module 602 and MGR2 module 606, and may be specific implementations of the low voltage upper phase controller 120 and the high voltage upper phase controller 130. This communication may be performed at the upper and lower phases of the inverter 110. Figure 7 , as further discussed below. Within the message encoding scheme for the electrical interface, a period with a transmission pulse may be defined as a dominant phase, and a period without a transmission pulse may be defined as a recessive phase. MGR1 612 and MGR2 614 may further include a timer (T) 613 and a timer (T) 615, respectively, which may measure the time during which the communication on the electrical interface 604 is measured as dominant or recessive. The measured time may be used to depict the data bit. For example, the pulse stream may be an approximately 50% duty cycle square wave having a period from about 10nS to about 100nS. For example, the pulse may be continuously provided to be turned on or off to send data to command the FET to turn on or off, respectively. For example, the pulse may be modulated into a logic 0 bit and a logic 1 bit, wherein the range of the logic 0 bit is from about 250nS to about 2μS, and the range of the logic 1 bit is from about 500nS to about 4μS.

[0078] The gate driver 600 may include a message encoding scheme for an electrical interface, wherein a logic 0 bit is defined as a dominant phase for a first time period, followed by a recessive phase for a second time period, and a logic 1 bit is defined as a dominant phase for a first time period, followed by a recessive phase for a third time period that is longer than the second time period for the recessive phase for the logic 0 bit. For example, for a logic 0 bit, the dominant phase may include a dominant phase of approximately 500 nS, followed by a recessive phase of approximately 1 μS. For example, for a logic 1 bit, the dominant phase may include a dominant phase of approximately 500 nS, followed by a recessive phase of approximately 2 μS. In this example, the recessive phase of approximately 2 μS for a logic 1 bit is longer than the recessive phase of approximately 1 μS for a logic 0 bit.

[0079] MGR1 612 and MGR2 614 may include logic rules whereby the electrical transmitter may be placed in a tri-state during a recessive phase, between dominant phases, and when communications over the electrical interface 604 are not being used, such that pulses traveling in the opposite direction may be detected by MGR1 612 and MGR2 614. Further, MGR1 612 and MGR2 614 may include logic rules such that detection of a pulse during a recessive phase of a data bit is interpreted as an interrupt from the opposite MGR, causing the interruptee to yield communications over the electrical interface 604 to the interrupter (e.g., the corresponding MGR, MGR1 612 or MGR2 614). Tri-state refers to a transmitter that no longer drives two signal lines to the electrical interface 604. Both transmitters (e.g., MGR1 612 or MGR2 614) may be in a tri-state on both sides of the electrical interface 604.

[0080] In tri-state, either transmitter can start sending data while the other side can be used to listen. Both transmitters can be in tri-state at the same time and then start sending data at the same time. Here, neither receiver will see the data because both are sending data and the transceiver cannot send and receive data at the same time. One or more embodiments may describe a message protocol that is used to ensure that the conflict does not continue. One of the transmitters (e.g., MGR1 612 or MGR2 614) can use a break bit with a very long dominant phase (e.g., such as about 3μS) to start communication. The other transmitter can start the message with a normal logic 0 bit or logic 1 bit with a shorter dominant phase (e.g., such as about 500nS). Either of the transmitters (e.g., MGR1 612 or MGR2 614) can be configured to start the message with a break, and either can be configured to start the message without a break. However, both transmitters should not be configured to start a message with an interruption, and both transmitters should not be configured to start a message without an interruption. One of the transmitters (e.g., MGR1 612 or MGR2 614) is configured to start a message with an interruption, and the other is configured to start a message without an interruption. This configuration solves the conflict problem described above, because the transmitter that starts a message without an interruption will turn off the pulse, for example, for about 500nS, and will enter a recessive phase where no pulse is sent as the first logic 0 bit or the ending phase of the logic 1 bit. At this point, the non-interrupting transmitter will see that the other (interrupting) transmitter is sending a pulse and will give up the communication bus to the interrupting transmitter.

[0081] The gate driver 600 may include a single wire data bus 630. The single wire data bus 630 may be bidirectional and may operate in the GND2 610 plane connecting the MGR2 614 to a point of use IC that may be placed in, on, or near the FET driver 632 and have a logic manager MGR3 616. For example, the MGR3 616 and FET driver 632 may include additional components as shown by the MGR3 module 634 and may be a specific implementation of the communication manager 405 and the north switch control and diagnostic controller 450N for the point of use upper phase controller 142 of the upper phase switch 144. The gate driver 600 may include switched current sources and current sinks (Ia 618, Ib 620, Ic 622, and Id 624) on both sides of the single-wire data bus 630, which may drive the single-wire data bus 630 to a high power rail (SUP) or a low power rail (GND2 610). The gate driver 600 may further include a first comparator CMP2 628 on a first side of the single-wire data bus 630 and a second comparator CMP3 626 on a second side of the single-wire data bus 630. CMP2 628 and CMP3 626 may distinguish between a high or low state of the single-wire data bus 630, where a low (or high) state is defined as dominant and an opposite state is defined as recessive.

[0082] Further, timer (T) 615 and timer (T) 617 within MGR2 614 and MGR3 616, respectively, may measure the time during which the single wire data bus 630 is measured as dominant or recessive and wherein the measured time is used to depict the data bit. Between MGR2 614 and MGR3 616 may be a message encoding scheme for the single wire data bus 630, wherein a logic 0 bit is defined as a dominant phase for a first period of time, followed by a recessive phase for a second period of time, and a logic 1 bit is defined as a dominant phase for a first period of time, followed by a recessive phase for a third period of time that is longer than the second period of time for the recessive phase for the logic 0 bit.

[0083] The current sources and current sinks (i.e., Ia 618, Ib 620, Ic 622, and Id 624) can provide currents greater than the highest possible EM field inductive coupling current that can be received by the single wire data bus 630 in order to maintain driving a dominant or recessive state. The dimensions of Ia 618, Ib 620, Ic 622, and Id 624 can be such that assertion of a dominant state will always overdrive assertion of a recessive state, such that a transmitter on either side of the single wire data bus 630 can interrupt the recessive phase of a data bit by pulling the single wire data bus 630 to a dominant state. For example, the operation of Ia 618 or Ic 622 can overdrive the state of the single wire data bus 630 over the operation of Ib 620 or Id 624, or the operation of Ib 620 or Id 624 can overdrive the state of the single wire data bus 630 over the operation of Ia 618 or Ic 622. Further, MGR2 614 and MGR3 616 may include logic rules such that an interruption on the single-wire data bus 630 causes the interruptee to yield the single-wire data bus 630 to the interrupter (eg, the corresponding MGR).

[0084] Fig. 9 Depicted is an exemplary electrical schematic diagram for a bidirectional communication architecture in accordance with one or more embodiments. Fig. 9 Sections of the gate driver 600 are depicted, specifically including MGR2 614 , a single-wire data bus 630 , and MGR3 616 . Fig. 9 The gate driver 600 is depicted with a coupling current (Iac 902) on a single wire data bus 630. As described herein, the current sources and sinks Ia 618, Ib 620, Ic 622, and Id 624 may have higher current capabilities than the worst case external coupling current (Iac 902) so that the recessive or dominant state of the single wire data bus 630 may be maintained in a desired state in the presence of Iac.

[0085] like Figure 6 As shown, the gate driver 600 may include a bidirectional electrical interface between two voltage planes. The gate driver 600 may include: (1) MGR1 612 and MGR2 614 that can manage sending and receiving electrical pulses; (2) MGR2 614 and MGR3 616 that can manage sending and receiving data on a single wire data bus 630; (3) current sources and current sinks (Ia 618, Ib 620, Ic 622, and Id 624); and (4) a message architecture for communication between MGR1 612 and MGR2 614 and between MGR2 614 and MGR3 616.

[0086] Figure 7An exemplary message protocol between logic managers in a circuit according to one or more embodiments is depicted. For example, Figure 7 An example communication between MGR1 612 and MGR2 614 with interruptions is illustrated.

[0087] like Figure 7 As shown, the transmission of pulse 702 may occur during a dominant phase of a bit transmission. In the example transmission at 708, MGR1 612 is transmitting a logic 0 and MGR2 614 is receiving a logic 0. Following the dominant phase of the transmission of the logic 0, the transmission of the logic 0 may include a recessive phase in which no pulses are transmitted by MGR1 612 or MGR2 614. Figure 7 As shown, a logic 0 at 708 may be transmitted with a short dominant phase followed by a short recessive phase, and a logic 1 at 710 may be transmitted with a short dominant phase followed by a long recessive phase. MGR1 612 or MGR2 614 may interrupt a transmitter by transmitting a pulse during the recessive phase of the transmitter, as shown by the interruption at 712, where MGR2 614 transmits pulse 704 to interrupt the transmission of pulse 702 by MGR1 612. Here, MGR1 612 interprets the detection of pulse 704 from MGR2 614 during the recessive phase as an interruption, and yields communication over the electrical interface 604 to interrupter MGR2 614. After the interruption at 712, MGR2 614 transmits a logic 0 followed by a logic 1 to MGR1 612. As shown in FIG. Figure 7 As shown, in the recessive phase of each bit transmission, both MGR1 612 and MGR2 614 are listening for an interrupt signal from the other MGR. Thus, a high priority message can interrupt a lower priority message in a very short amount of time. Here, the interrupt occurs within a single bit transmission.

[0088] Figure 8 An exemplary message protocol between logic managers in a circuit according to one or more embodiments is depicted. For example, Figure 8 An example communication between MGR2 614 and MGR3 616 with interruptions is illustrated.

[0089] Within the communication, a low state (e.g., 802) may indicate that the dominant phase implemented by the current sink of the transmitter (Ib 620 for MGR2 614, or Id 624 for MGR3 616) is active. A high state may indicate that the recessive phase implemented by the current source of the transmitter (Ia 618 for MGR2 614, or Ic 622 for MGR3 616) is active. Figure 7Similar to the communication of , the transmission of a logic 0 at 808 may correspond to a short dominant phase followed by a short recessive phase, and the transmission of a logic 1 at 810 may correspond to a short dominant phase followed by a long recessive phase. When the transmitter is pulling up the single wire data bus 630 to SUP with the corresponding current source (Ia 618 for MGR2 614, or Ic 622 for MGR3 616) during the recessive phase, both MGR2 614 and MGR3 616 may interrupt the transmitter by activating the pull-down of the single wire data bus 630 to GND2 610 with the corresponding current sink (Ib 620 for MGR2 614, or Id 624 for MGR3 616). The current sink (Ib 620 or Id 624) may have a higher current than the current source (Ia 618 or Ic 622) and may therefore overdrive the state of the single wire data bus 630 as driven by the current source (Ia 618 or Ic 622). The transmitter may interpret the detection of the dominant phase during the recessive phase as an interrupt and yield the single wire data bus 630 to the interrupter. MGR2 614 or MGR3 616 may interrupt the transmitter by activating the pull-down of the single wire data bus 630 to GND2 610 with the corresponding current sink during the recessive phase of the transmitter, as shown by the interrupt at 812, where MGR3 616 activates the pull-down of the single wire data bus 630 at 804 to interrupt the transmission 802 by MGR2 614. Here, MGR2 614 interprets the pull-down from MGR3 616 during the recessive phase as an interrupt and yields the single wire data bus 630 to interrupter MGR3 616. After the interrupt at 812, MGR3 616 transmits a logic 0 followed by a logic 1 to MGR2 614. Figure 8 As shown, in the recessive phase of each bit transmission, both MGR2 614 and MGR3 613 are listening for an interrupt signal from the other MGR. Thus, a high priority message can interrupt a lower priority message in a very short amount of time. Here, the interrupt occurs within a single bit transmission.

[0090] For example, the message architecture may include fields such as SOF, ID, ADD, R, PAY, CRC, and EOF. SOF may refer to a start of frame field indicating that a new message is starting. If a new message is interrupting an existing message, SOF may also be an interruption phase. ID may refer to an identification field. The ID field may define which MGR sends the message. For example, MGR1 612 may use a two-bit ID field to send a message to MGR2 614 or MGR3 616. Further, MGR2 614 and MGR3 616 may send a message to any other MGR. ADD may refer to an address field indicating which register address is being written to or being read from. R may refer to a read (write) field and may define whether a message is being written to the ADD field or a request is being made to read from the field. PAY may refer to a message payload field and may be data to be written to the ADD. When the message is a read request, the PAY field may be equal to zero. CRC may refer to a cyclic redundancy check field and may be used by a receiver to verify that a message has arrived intact. EOF may refer to the End of Frame field and may indicate that a message has ended. Both the SOF and EOF fields may be formed using different bit structures of logic 0 or logic 1 by changing the dominant or recessive time.

[0091] The gate driver 600 may have a Figure 7 and Figure 8 The message architecture shown. However, the present disclosure is not limited thereto. The gate driver 600 may use an electrical interface 604 in series with a single wire data bus 630 to communicate between the point of use IC and the reference GND1 plane. The communication protocol may use the same bit structure and the same interrupt structure so that MGR1 612, MGR2 614, and MGR3 616 may communicate seamlessly with each other and interrupt each other using the same format.

[0092] MGR1 612 may formulate messages originating from the inverter controller 300 or from the internal logic of MGR1 612. MGR1 612 may send messages to MGR2 614 via electrical pulses. MGR2 614 may convert "pulse" to a low state and "no pulse" to a high state, or vice versa. These states may then be sent to MGR3 616 on the single wire data bus 630. MGR2 614 may also read the message, as the message may be intended for MGR2 614 rather than MGR3 616. MGR2 614 may not receive advance information indicating the intended recipient, and may send all messages received via the electrical interface 604 to MGR3 616 and read all received messages.

[0093] MGR3 616 can similarly send a message to MGR2 614 via a single wire data bus 630. MGR2 614 can send a message to MGR1 613 via an electrical interface 604 and also read the message. MGR2 614 can convert a single wire data bus 630 low state to a "pulse" and convert a single wire data bus 630 high state to a "no pulse", or vice versa. MGR2 614 has information indicating the direction in which the message is received (e.g., received from MGR1 613 via an electrical interface 604 or received from MGR3 616 via a single wire data bus 630) to prevent MGR2 614 from sending a message back to the message sender. MGR2 614 also has information indicating that MGR2 614 is sending a message, and checks the corresponding data bus to ensure that the data bus is driven correctly, without having to read the outgoing message on the corresponding data bus as in the incoming message.

[0094] Fig.10 A method for message communication according to one or more embodiments is depicted. The method 1000 for communicating with a power device switch for an inverter 110 may include various operations. The method 1000 may include: using a single-wire data bus 630 to transmit messages between a high voltage message manager MGR1 612 of the inverter 110 and a point-of-use message manager MGR3 616 for a power device switch (e.g., an upper phase switch 144) (operation 1010). The method 1000 may include: using a timer 615 of the inverter 110 to measure a time period during which the single-wire data bus 630 is in a dominant phase (e.g., with a pulse 702) or a recessive phase (e.g., without a pulse 702) (operation 1020). Method 1000 may include transmitting a message using a logic 0 bit 808 and a logic 1 bit 810, wherein the logic 0 bit is defined as a dominant phase measured by timer 615 for a first time period, followed by a recessive phase measured for a second time period, and a logic 1 bit is defined as a dominant phase measured by timer 615 for a first time period, followed by a recessive phase measured for a third time period longer than the second time period for the logic 0 bit (operation 1030). Method 1000 may include transmitting a logic 0 bit or a logic 1 bit during the second time period or the third time period to interrupt (e.g., 812) the communication of the message within a single bit transmission (operation 1040). Method 1000 may include applying one or more of a current source (e.g., 618, 622) or a current sink (e.g., 620, 624) to the single wire data bus 630 (operation 1050). The one or more of the current source or the current sink may have a current capability higher than the expected worst case external coupling current. For example, the expected worst case external coupling current may be from about 100 mA to about 5A.

[0095] The system described herein can solve the communication problem between the electrically isolated plane and the point-of-use IC by using a single wire data bus 630 that is robust to worst case induced currents. The system described herein can allow the point-of-use IC to be used within the high EM field environment around the FET. The point-of-use IC can implement point-of-use control and feedback on the FET operating conditions and fault responses. The point-of-use control and response signals can be faster than the control and response signals, which can be greatly filtered to reject coupling currents before traveling between the FET and the electrically isolated controller.

[0096] The signals transmitted from the point-of-use IC to the remotely located gate driver must be filtered to reject coupled currents and voltages. As described above, the gate driver itself sends very high current signals to the FET to turn the FET on and off. For example, these very high currents overdrive the coupled current, and therefore the gate driver can turn the FET on or off in less than about 100nS. However, the signals from the FET are not driven by a low impedance source with many amperes of current. These signals are typically sensed voltages or currents at low levels, and therefore must be greatly filtered to reject high-frequency coupled currents. This filtering slows down the feedback from the FET to the gate driver and allows dangerous conditions to persist beyond the point where the gate driver can react to stop them. For example, overcurrent sensing for all SiC FETs is typically performed by sensing the FET V drain to V source differential voltage (Vds). After the gate driver has commanded the FET to turn on, the gate driver determines that the sensed Vds is greater than an acceptable threshold. When the sensed Vds is too high, the gate driver will cut off the FET. The sensed Vds must be filtered for about 2μS to reject the coupled current. However, 2μS is too long to allow the SiC FET to remain in an overcurrent condition, which causes the SiC FET to be damaged during an overcurrent event. The system described herein can provide a point-of-use IC that senses an overcurrent event in much less than 2μS because the point-of-use IC is co-located with the FET and does not need to filter the data before reacting. The point-of-use IC will automatically shut off the FET and will then report to the remote controller IC that a shutdown has occurred.

[0097] The system described herein may provide a common messaging architecture that works seamlessly across the electrical interface 604 and the single wire data bus 630. Messages sent from MGR1 612 to MGR2 614 across the electrical interface 604 may be simultaneously read by MGR2 614 and passed to MGR3 616 across the single wire data bus 630. The same data flow may be described for messages sent by MGR3 616 to MGR1 612 through MGR2 614. MGR2 614 may send messages to MGR1 612 and MGR3 616 simultaneously. MGR1 612, MGR2 614, or MGR3 616 may interrupt incoming messages to gain control of the electrical interface 604, the single wire data bus 630, or both in order to send a high priority message that may interrupt a lower priority message.

[0098] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the invention being indicated by the following claims.

Claims

1. A system comprising: An inverter configured to convert DC power from a battery into AC power to drive a motor, wherein the inverter comprises: an electrical interface configured to separate a high voltage region from a low voltage region; a low voltage message manager, the low voltage message manager being in the low voltage area; a high voltage message manager in the high voltage region and configured to communicate with the low voltage message manager; and A point-of-use message manager is in the high voltage area and is configured to communicate with the high voltage message manager.

2. The system according to claim 1, further comprising: the battery, the battery being configured to supply the DC power to the inverter; as well as The motor is configured to receive the AC power from the inverter to drive the motor.

3. The system of claim 1, wherein the point-of-use message manager is in a power module that includes one or more power device switches for the inverter, and The inverter further comprises: a single wire data bus connecting the high voltage message manager to the point of use message manager, wherein the point of use message manager is configured to communicate with the high voltage message manager using the single wire data bus, and a timer configured to measure a time period during which the single-wire data bus is in a dominant phase or a recessive phase, wherein the low voltage message manager, the high voltage message manager, and the point of use message manager are configured to communicate using logic 0 bits and logic 1 bits, wherein The logic 0 bit is defined as a dominant phase measured by the timer for a first period of time followed by a recessive phase measured for a second period of time, and The logic 1 bit is defined as a dominant phase measured by the timer for the first time period followed by a recessive phase measured for a third time period longer than the second time period for the logic 0 bit.

4. A system comprising: an electrical interface configured to separate a high voltage region from a low voltage region; a low voltage message manager, the low voltage message manager being in the low voltage area; a high voltage message manager in the high voltage region and configured to communicate with the low voltage message manager; as well as A point-of-use message manager is in the high voltage area and is configured to communicate with the high voltage message manager.

5. The system according to claim 4, further comprising: A single wire data bus connects the high voltage message manager to the point of use message manager, wherein the point of use message manager is configured to communicate with the high voltage message manager using the single wire data bus.

6. The system according to claim 5, further comprising: a first switched current source configured to operate with the high voltage message manager to drive the single wire data bus to a power rail; a second switched current source configured to operate with the point-of-use message manager to drive the single-wire data bus to the power rail; a third switched current sink configured to operate with the high voltage message manager to drive the single wire data bus to a ground rail; as well as A fourth switched current sink is configured to operate with the point-of-use message manager to drive the single-wire data bus to the ground rail.

7. The system of claim 6, wherein one or more of the first switched current source or the second switched current source is configured to overdrive a state of the single-wire data bus as driven by operation of the third switched current sink or the fourth switched current sink, or Wherein one or more of the third switched current sink or the fourth switched current sink is configured to overdrive a state of the single-wire data bus as driven by operation of the first switched current source or the second switched current source.

8. The system of claim 6, wherein the first switched current source, the second switched current source, the third switched current sink, and the fourth switched current sink have a current capability that is higher than an expected worst case external coupling current.

9. The system of claim 6, further comprising: a first comparator configured to operate with the high voltage message manager to distinguish between a high state or a low state of the single wire data bus; as well as A second comparator is configured to operate with the point-of-use message manager to distinguish between a high state and a low state of the single-wire data bus.

10. The system of claim 4, wherein the point-of-use message manager is in a power module that includes one or more power device switches for an inverter.

11. The system of claim 5, wherein one or more of the low voltage message manager, the high voltage message manager, or the point of use message manager comprises a timer configured to measure a time period that the single wire data bus is in a dominant phase or a recessive phase.

12. The system of claim 11, wherein the low voltage message manager, the high voltage message manager, and the point of use message manager are configured to communicate using logic 0 bits and logic 1 bits, wherein The logic 0 bit is defined as a dominant phase measured by the timer for a first period of time followed by a recessive phase measured for a second period of time, and The logic 1 bit is defined as a dominant phase measured by the timer for the first time period followed by a recessive phase measured for a third time period longer than the second time period for the logic 0 bit.

13. The system of claim 12, wherein the interruption managers in the low voltage message manager, the high voltage message manager, and the point-of-use message manager are configured to interrupt the transmission managers in the low voltage message manager, the high voltage message manager, and the point-of-use message manager by transmitting a logic 0 bit or a logic 1 bit during the second time period or the third time period, and the transmission manager is configured to yield communication to the interruption manager within a single bit transmission.

14. The system of claim 4, wherein the low voltage message manager, the high voltage message manager, and the point of use message manager are configured to communicate with any other of the low voltage message manager, the high voltage message manager, and the point of use message manager.

15. A method for communicating with a power device switch for an inverter, the method comprising: Messages are communicated between a high voltage message manager of the inverter and a point of use message manager for the power device switches using a single wire data bus.

16. The method according to claim 15, further comprising: A timer of the inverter is used to measure the time period during which the single-wire data bus is in the dominant phase or the recessive phase.

17. The method of claim 16, wherein transmitting the message comprises: Use logic 0 and logic 1 bits, where The logic 0 bit is defined as a dominant phase measured by the timer for a first period of time followed by a recessive phase measured for a second period of time, and The logic 1 bit is defined as a dominant phase measured by the timer for the first time period followed by a recessive phase measured for a third time period longer than the second time period for the logic 0 bit.

18. The method according to claim 17, further comprising: A logic 0 bit or a logic 1 bit is transmitted during the second time period or the third time period to interrupt the communication of the message within the single bit transmission.

19. The method of claim 15, further comprising: One or more of a current source or a current sink is applied to the single wire data bus.

20. The method of claim 19, wherein the one or more of the current source or the current sink has a current capability that is higher than an expected worst case external coupling current.

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