Vertical structure management in three-dimensional semiconductor devices

Abstract

Systems, devices, and methods for managing vertical structures in three-dimensional (3D) semiconductor devices are provided. In one aspect, a method includes providing a semiconductor substrate; and forming isolation regions between the plurality of adjacent vertical transistors in the semiconductor substrate. Each vertical transistor of the plurality of adjacent vertical transistors extends in a vertical direction. Two adjacent vertical transistors and a corresponding isolation region between the two adjacent vertical transistors are arranged along a horizontal direction perpendicular to the vertical direction. The corresponding isolation region includes a conductive material, and in a vertical direction, a length of the conductive material in the corresponding isolation region is greater than a length of a vertical gate of each of the two adjacent vertical transistors.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and fabrication processes for semiconductor devices. Background Art

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive because they can increase array density by stacking more layers within a similar footprint. 3D memory devices generally include a memory array of memory cells and peripheral circuits for facilitating the operation of the memory array. The memory cells can include vertical structures, such as vertical transistors. Summary of the invention

[0003] The present disclosure describes methods, devices, systems, and techniques for managing vertical structures in three-dimensional (3D) semiconductor devices.

[0004] One aspect of the present disclosure is characterized by a method, comprising: providing a semiconductor substrate; and forming an isolation region between a plurality of adjacent vertical transistors in the semiconductor substrate. Each of the plurality of adjacent vertical transistors extends in a vertical direction, and two adjacent vertical transistors and a corresponding isolation region between the two adjacent vertical transistors are arranged in a horizontal direction perpendicular to the vertical direction. The corresponding isolation region includes a conductive material, and along the vertical direction, a length of the conductive material in the corresponding isolation region is greater than a length of a vertical gate of each of the two adjacent vertical transistors.

[0005] In some embodiments, forming an isolation region between multiple adjacent vertical transistors in a semiconductor substrate includes: forming a plurality of trenches in the semiconductor substrate, the plurality of trenches being arranged along the horizontal direction, each of the plurality of trenches extending along the vertical direction; and forming a corresponding isolation region by depositing a conductive material in an intermediate trench between two adjacent trenches used to form the two adjacent vertical transistors.

[0006] In some embodiments, the method further includes: forming the two adjacent vertical transistors by depositing an isolation material in the two adjacent trenches and then depositing at least one conductive layer on the isolation material deposited in the two adjacent trenches to form vertical gates of the two adjacent vertical transistors. In the vertical direction, the length of the at least one conductive layer deposited in each of the two adjacent trenches is less than the length of the conductive material filled in the middle trench.

[0007] In some embodiments, the semiconductor substrate includes a first side and a second side opposite to the first side. Forming an isolation region between adjacent vertical transistors in the semiconductor substrate includes forming an isolation region between adjacent vertical transistors in the semiconductor substrate from the first side of the semiconductor substrate. In some embodiments, the method further includes: etching the semiconductor substrate from the second side of the semiconductor substrate to expose the conductive material in the corresponding isolation region without exposing the vertical gates of the two adjacent vertical transistors.

[0008] In some embodiments, etching the semiconductor substrate from the second side of the semiconductor substrate includes: etching the semiconductor substrate in an etching region along a vertical direction from the surface of the semiconductor substrate. The etching region has a bottom edge and an etching depth from the surface of the semiconductor substrate to the bottom edge. In the vertical direction, the etching depth is greater than a first distance between the surface of the semiconductor substrate and an end of the conductive material filled in the middle trench, and is less than a second distance between the surface of the semiconductor substrate and an end of at least one conductive layer deposited in each of the two adjacent trenches. In some embodiments, the etching region has two opposite edges located in two adjacent trenches along a horizontal direction.

[0009] In some embodiments, the method further includes: forming a corresponding conductive interconnect in the second side of the semiconductor substrate in contact with the exposed conductive material in the corresponding isolation region. In some embodiments, the method further includes: forming a plurality of bit lines from the second side of the semiconductor substrate.

[0010] In some embodiments, the method includes: depositing an isolation material to fill a portion of each of the multiple trenches in a vertical direction; patterning a photoresist to cover the two adjacent trenches and expose the middle trench; etching the isolation material deposited in the middle trench; depositing a conductive material in the middle trench to form a corresponding isolation region; and removing the photoresist and depositing the at least one conductive layer on the isolation material deposited in the two adjacent trenches to form vertical gates of the two adjacent vertical transistors.

[0011] In some embodiments, the method includes, for each of the two adjacent trenches, cutting at least one conductive layer deposited in the trench to form two separate vertical gates of a pair of independent vertical transistors in the trench.

[0012] In some embodiments, the method further comprises: forming an array structure in the first region, the array structure comprising a plurality of memory cell strings, each memory cell of the plurality of memory cell strings comprising a corresponding vertical transistor. The plurality of adjacent vertical transistors and the isolation region in the semiconductor substrate are formed in a second region adjacent to the first region.

[0013] In some embodiments, forming the array structure includes: forming corresponding vertical transistors of the plurality of memory cell strings by depositing at least one conductive layer in corresponding trenches. Along the vertical direction, the length of the at least one conductive layer deposited in the corresponding trench in the first region is greater than the length of the vertical gate of each of the two adjacent vertical transistors in the second region.

[0014] In some embodiments, the method includes: depositing an isolation material to fill a portion of each of two adjacent trenches for the two adjacent vertical transistors in the second region and a corresponding trench for the memory cell in the first region along a vertical direction; patterning a photoresist to cover the two adjacent trenches and expose the corresponding trench; etching the isolation material deposited in the corresponding trenches; removing the photoresist to expose the two adjacent trenches; and depositing at least one conductive layer on the isolation material deposited in the two adjacent trenches to form vertical gates of the two adjacent vertical transistors, and depositing the at least one conductive layer in the corresponding trench to form a vertical transistor for the memory cell.

[0015] Another aspect of the present disclosure features a semiconductor device, the semiconductor device comprising: a semiconductor substrate; a plurality of vertical transistors located in the semiconductor substrate along a horizontal direction, each of the plurality of vertical transistors extending along a vertical direction perpendicular to the horizontal direction; and a plurality of isolation regions located in the semiconductor substrate, each of the plurality of isolation regions being located between two adjacent vertical transistors in the plurality of vertical transistors along the horizontal direction. The isolation regions include a conductive material, and along the vertical direction, a length of the conductive material in the isolation regions is greater than a length of a vertical gate of each of the two adjacent vertical transistors.

[0016] In some embodiments, the isolation region includes a conductive material filled in a middle trench between two adjacent trenches corresponding to the two adjacent vertical transistors. The vertical gate of each of the two adjacent vertical transistors includes at least one conductive layer on the isolation material filled in a portion of a corresponding trench of the two adjacent trenches. In the vertical direction, the length of the at least one conductive layer in each of the two adjacent trenches is less than the length of the conductive material filled in the middle trench.

[0017] In some embodiments, the semiconductor substrate includes a first side and a second side opposite each other. The plurality of isolation regions and the plurality of vertical transistors are located in the first side of the semiconductor substrate. The semiconductor device further includes a conductive interconnect formed in the second side of the semiconductor substrate. Each of the conductive interconnects contacts the conductive material in a corresponding isolation region of the plurality of isolation regions, and in a vertical direction, from the second side of the semiconductor substrate, each of the conductive interconnects has an end that is higher than an end of the at least one conductive layer in each of the two adjacent trenches.

[0018] In some embodiments, the semiconductor device further includes a plurality of bit lines located in the second side of the semiconductor substrate, each of the plurality of bit lines being coupled to a corresponding vertical transistor. In some embodiments, in each of the two adjacent trenches, two vertical gates of a pair of independent vertical transistors are separated by an isolation material filled in the trench.

[0019] In some embodiments, the semiconductor device further includes: an array structure located in the first region, the array structure including a plurality of memory cell strings, each memory cell of the plurality of memory cell strings including a vertical transistor having a vertical gate. The plurality of isolation regions and the plurality of vertical transistors are formed in a second region of the semiconductor substrate adjacent to the first region along a third direction perpendicular to the vertical direction and the horizontal direction.

[0020] In some embodiments, along the vertical direction, the length of the vertical gate of the vertical transistor of the memory cell in the first region is greater than the length of the vertical gate of each of the two adjacent vertical transistors in the second region. In some embodiments, the length of the vertical transistor of the memory cell in the first region is greater than the length of the conductive material in the isolation region in the second region.

[0021] In some embodiments, along the third direction, the vertical gate of the vertical transistor of the memory cell in the first region is in direct contact with the first isolation layer, while the vertical gate of each of the two adjacent vertical transistors in the second region is separated from the second isolation layer by the passivation layer.

[0022] Another aspect of the present disclosure features a system comprising: a memory device; and a controller coupled to the memory device and configured to control the memory device. The memory device comprises: a semiconductor substrate; a plurality of vertical transistors located in the semiconductor substrate along a horizontal direction, each of the plurality of vertical transistors extending along a vertical direction perpendicular to the horizontal direction; and a plurality of isolation regions located in the semiconductor substrate. Each of the plurality of isolation regions is located between two adjacent vertical transistors along a horizontal direction. The isolation region comprises a conductive material, and along a vertical direction, a length of the conductive material in the isolation region is greater than a length of a vertical gate of each of the two adjacent vertical transistors.

[0023] In some embodiments, the isolation region includes a conductive material filled in a middle trench between two adjacent trenches corresponding to the two adjacent vertical transistors. The vertical gate of each of the two adjacent vertical transistors includes at least one conductive layer located on the isolation material filled in a portion of a corresponding trench of the two adjacent trenches, and along the vertical direction, the length of the at least one conductive layer in each of the two adjacent trenches is less than the length of the conductive material filled in the middle trench.

[0024] Embodiments of the present disclosure may provide one or more of the following technical advantages and / or benefits. For example, a plurality of trenches may be formed in a semiconductor substrate. An isolation material (e.g., oxide) may be filled in the bottom portion of the trench in the connection region, and a vertical gate may be formed on the isolation material filled in the trench, which may control the depth of the vertical gate or the cutting depth of the vertical gate, and accordingly better control the process window of the gate cutting process. In addition, the isolation region in the middle trench between adjacent trenches for forming the vertical gate may include a conductive material (e.g., metal) filled in the middle trench, while there is no isolation material in the bottom portion of the middle trench. Thus, the semiconductor substrate can be etched from the back to expose the conductive material in the isolation region without exposing the vertical gate in the adjacent trench, during which the isolation material deposited in the adjacent trench acts as a stop layer. Similarly, each conductive layer (e.g., metal) for forming the vertical gate of the memory cell may also be exposed from the back of the semiconductor substrate and each conductive layer may be cut into two separate blocks to serve as the vertical gate of the memory cell. By etching the conductive material in the isolation region together with the conductive layer for forming the vertical gate of the memory cell in the array region, the technology can reduce the manufacturing cost and difficulty, eliminate the problems or risks caused by metal punching from the front side of the semiconductor substrate (e.g., difficult to control due to line wiggling), and optimize the manufacturing process (e.g., omitting one or more processing operations, such as high-cost oxide recessing operations). The technology can also control the area used for coupling outward from the back side of the 3D semiconductor structure, which can expand the processing window, simplify or optimize the manufacturing process of the 3D semiconductor device and reduce the manufacturing cost.

[0025] The technology can be applied to various types of semiconductor devices, volatile memory devices such as DRAM memory devices, or non-volatile memory (NVM) devices, such as NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change memory (PCM) such as phase change random access memory (PCRAM), spin transfer torque (STT)-magnetoresistive random access memory (MRAM) and others. The technology can also be applied to charge trapping-based memory devices (e.g., silicon-oxide-nitride-oxide-silicon (SONOS) memory devices) and floating gate-based memory devices. The technology can also be applied to three-dimensional (3D) memory devices. The technology can also be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices (such as 2-level cell devices), TLC (three-level cell) devices, QLC (quadruple-level cell) devices, or PLC (five-level cell) devices. Additionally or alternatively, the technology may be applied to various types of devices and systems, such as a secure digital (SD) card, an embedded multimedia card (eMMC) or a solid-state drive (SSD), embedded systems, and others.

[0026] The details of one or more implementations of the subject matter of the present disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which are incorporated herein and form a part of the present disclosure, illustrate various aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable one of ordinary skill in the relevant art to make and use the present disclosure.

[0028] Figure 1 A cross-sectional view of an exemplary 3D semiconductor device is shown.

[0029] Figure 2A A perspective view of an exemplary 3D semiconductor device is shown.

[0030] Figure 2B Shows Figure 2A Top view of an exemplary 3D semiconductor device.

[0031] Figures 3A-3C Cross-sectional views of an exemplary 3D semiconductor structure at different locations along a first lateral direction are shown.

[0032] Figure 3D-3E Shows Figures 3A-3C Cross-sectional views of an exemplary 3D semiconductor structure at different positions along the second lateral direction.

[0033] Figures 4A-4E Structural cross-sectional views of 3D semiconductor structures at various stages of the fabrication process are shown.

[0034] Figure 5 is a flow chart of an exemplary process for forming a 3D semiconductor device.

[0035] Figure 6 A block diagram of an exemplary system having one or more semiconductor devices is shown.

[0036] Like reference numbers and designations in the various drawings represent like elements.It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative representations and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0037] Figure 1 1 shows a side view of a cross section of an exemplary 3D semiconductor device 100. The 3D semiconductor device 100 may be a 3D dynamic random access memory (DRAM). It should be understood that Figure 1 It is only used for illustrative purposes and may not necessarily reflect the actual device structure (e.g., interconnection) in practice. In some embodiments, the 3D semiconductor device 100 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on the first semiconductor structure 102. The first semiconductor structure 102 and the second semiconductor structure 104 can be connected at a bonding interface 106 therebetween.

[0038] like Figure 1 As shown, the first semiconductor structure 102 may include a substrate 110, which may include silicon (e.g., single crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material. The first semiconductor structure 102 may include a peripheral circuit 112 located on and / or within the substrate 110. In some embodiments, the peripheral circuit 112 includes a plurality of transistors 114 (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of the transistor 114) may also be formed on or within the substrate 110. In some examples, the peripheral circuit 112 is formed using complementary metal oxide semiconductor (CMOS) technology, and the first semiconductor structure 102 may also be formed on a semiconductor die, which may be referred to as a control die or a CMOS die 102.

[0039] In some embodiments, the first semiconductor structure 102 further includes an interconnect layer 116 located above the peripheral circuit 112 to transmit electrical signals to and from the peripheral circuit 112. The interconnect layer 116 may include a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnects and VIA contacts. The interconnect layer 116 may further include one or more interlayer dielectric (ILD) layers, in which the interconnects and via contacts may be formed. That is, the interconnect layer 116 may include interconnects and via contacts located in a plurality of ILD layers. In some embodiments, the peripheral circuits 112 are coupled to each other through the interconnects in the interconnect layer 116. The interconnects in the interconnect layer 116 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layer may be formed using a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0040] like Figure 1 As shown in , the first semiconductor structure 102 has a front side and a back side, and the first semiconductor structure 102 may further include a bonding layer 118 located at the bonding interface 106 on the back side and located above the interconnect layer 116 and the peripheral circuit 112. The bonding layer 118 may include a plurality of bonding contacts 119 and a dielectric that electrically isolates the bonding contacts 119. The bonding contacts 119 may include a conductive material, such as Cu. The remaining area of ​​the bonding layer 118 may be formed using a dielectric material (e.g., silicon oxide). The bonding contacts 119 and the surrounding dielectric in the bonding layer 118 may be used for hybrid bonding. Similarly, as Figure 1 As shown in , the second semiconductor structure 104 may also include a bonding layer 120 at the bonding interface 106 and located above the bonding layer 118 of the first semiconductor structure 102. The bonding layer 120 may include a plurality of bonding contacts 121 and a dielectric that electrically isolates the bonding contacts 121. The bonding contacts 121 may include a conductive material, such as Cu. The remaining area of ​​the bonding layer 120 may be formed using a dielectric material (e.g., silicon oxide). The bonding contacts 121 and the surrounding dielectric in the bonding layer 120 may be used for hybrid bonding. The bonding contact 121 may be in contact with the bonding contact 119 at the bonding interface 106. In some embodiments, the bonding layer 120 includes a dielectric layer opposite to a memory cell (e.g., a DRAM cell) 124, wherein a bit line 123 is located between the dielectric layer and the memory cell 124, as shown in FIG. Figure 1 The dielectric layer may include a bonding interface 106 having a bonding contact 121 .

[0041] The second semiconductor structure 104 can be bonded on top of the first semiconductor structure 102 in a face-to-face manner at a bonding interface 106. In some embodiments, the bonding interface 106 is provided between the bonding layer 120 and the bonding layer 118 as a result of hybrid bonding (also referred to as "metal / dielectric hybrid bonding"), which is a direct bonding technology (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) and can simultaneously obtain metal-metal bonding and dielectric-dielectric bonding. In some embodiments, the bonding interface 106 is where the bonding layer 120 and the bonding layer 118 meet and bond. In some examples, the bonding interface 106 can be a layer having a certain thickness including the top surface of the bonding layer 118 of the first semiconductor structure 102 and the bottom surface of the bonding layer 120 of the second semiconductor structure 104.

[0042] In some embodiments, the second semiconductor structure 104 further includes an interconnect layer 122 including a bit line 123 located above the bonding layer 120 to transmit electrical signals. The interconnect layer 122 may include a plurality of interconnects, for example, a middle-end-of-line (MEOL) interconnect and a back-end-of-line (BEOL) interconnect. In some embodiments, the interconnects in the interconnect layer 122 also include local interconnects such as a bit line 123 and a word line contact (not shown). The interconnect layer 122 may further include one or more ILD layers, in which interconnect lines and via contacts may be formed. The interconnects in the interconnect layer 122 may include a conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layer may be formed using a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0043] In some embodiments, peripheral circuit 112 includes a word line driver / row decoder coupled to a word line contact in interconnect layer 122 through bonding contacts 121 and 119 in bonding layers 120 and 118 and interconnect layer 116. In some embodiments, peripheral circuit 112 includes a bit line driver / column decoder coupled to a bit line 123 and a bit line contact in interconnect layer 122 through bonding contacts 121 and 119 in bonding layers 120 and 118 and interconnect layer 116. In some embodiments, bit line 123 is a metal bit line, which is in contrast to a semiconductor bit line (e.g., a doped silicon bit line). For example, bit line 123 can include W, Co, Cu, Al, or any other suitable metal having a higher conductivity than doped silicon. In some embodiments, the bit line contact is an ohmic contact, which is in contrast to a Schottky contact.

[0044] In some embodiments, the bit line 123 is made of a composite conductive material, which may be based on a metal material (e.g., W, Co, Cu, Al) and a semiconductor material (e.g., Si). For example, the composite conductive material may include a metal silicide such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon.

[0045] In some embodiments, the second semiconductor structure 104 includes a DRAM device, wherein memory cells are provided in the form of an array of DRAM cells 124 over the interconnect layer 122 and the bonding layer 120. That is, the interconnect layer 122 including the bit lines 123 may be disposed between the bonding layer 120 and the array of DRAM cells 124. The bit lines 123 in the interconnect layer 122 may be coupled to strings of DRAM cells 124. In some embodiments, the second semiconductor structure 104 is formed on a semiconductor die and may be referred to as an array die 104.

[0046] In some embodiments, the semiconductor device may include a plurality of array dies (e.g., array die 104) and a CMOS die (e.g., CMOS die 102). A plurality of array dies and the CMOS die may be stacked and bonded together. The CMOS die may be coupled to each of the plurality of array dies, respectively, and may be capable of driving each of the plurality of array dies, respectively, so that it operates in a manner similar to that of a semiconductor device. The semiconductor device may be any suitable device. In some examples, the semiconductor device includes at least a first wafer and a second wafer bonded face to face. The array die may be disposed on a first wafer together with other array dies, and the CMOS die may be disposed on a second wafer together with other CMOS dies. The first wafer and the second wafer may be bonded together so that the array die on the first wafer can be bonded to the corresponding CMOS die on the second wafer. In some examples, the semiconductor device is a chip having at least an array die and a CMOS die bonded together. In an example, the chip is obtained by dicing the bonded wafers. In another example, the semiconductor device is a semiconductor package including one or more semiconductor chips assembled on a package substrate.

[0047] Each DRAM cell 124 may include a vertical transistor 126 and a capacitor 128 coupled to the vertical transistor 126. The DRAM cell 124 may be a 1T1C cell consisting of one transistor and one capacitor. It should be understood that the DRAM cell 124 may have any appropriate configuration, such as a 2T1C cell, a 3T1C cell, etc. The vertical transistor 126 may be a MOSFET for switching the corresponding DRAM cell 124. In some embodiments, the vertical transistor 126 includes a semiconductor body 130 (an active region in which a channel can be formed) extending vertically (along the z-direction) and a gate structure 136 contacting one side of the semiconductor body 130. In a single-gate vertical transistor, the semiconductor body 130 may have a rectangular parallelepiped shape or a cylindrical shape, and in a plan view, the gate structure 136 may be adjacent to a single side of the semiconductor body 130, for example, as shown in FIG. Figure 1 . In some embodiments, the vertical transistor 126 has a structure including two or more gates, for example, a two-gate structure, a three-gate structure, or a gate all around (GAA) structure. In some embodiments, the gate structure 136 includes a gate electrode 134 and a gate dielectric 132 laterally located between the gate electrode 134 and the semiconductor body 130 in a bit line direction (for example, in the Y direction). In some embodiments, the gate dielectric 132 is adjacent to one side of the semiconductor body 130, and the gate electrode 134 is adjacent to the gate dielectric 132.

[0048] like Figure 1 As shown in FIG. 1 , in some embodiments, the semiconductor body 130 has two ends ( Figure 1In some embodiments, the semiconductor body 130 has an upper end and a lower end in the vertical direction (z direction), and at least one end extends beyond the gate dielectric 132 into the ILD layer in the vertical direction (z direction). In some embodiments, one end (e.g., the upper end) of the semiconductor body 130 is flush with the corresponding end (e.g., the upper end) of the gate dielectric 132. In some embodiments, both ends (the upper end and the lower end) of the semiconductor body 130 extend into the ILD layer in the vertical direction (z direction) beyond the gate electrode 134, respectively. That is, the semiconductor body 130 may have a vertical dimension (e.g., depth) larger than the vertical dimension (e.g., depth) of the gate electrode 134 (e.g., in the z direction), and neither the upper end nor the lower end of the semiconductor body 130 is flush with the corresponding end of the gate electrode 134. Thus, a short circuit between the bit line 123 and the word line / gate electrode 134 or between the word line / gate electrode 134 and the capacitor 128 may be avoided. The vertical transistor 126 may further include a source and a drain (both referred to as 138, because their positions may be interchangeable) disposed at two ends (upper end and lower end) of the semiconductor body 130 in the vertical direction (z direction), respectively. In some embodiments, one of the source and the drain 138 (e.g., at Figure 1 ) is coupled to capacitor 128, and the other of source and drain 138 (e.g., at Figure 1 That is, the vertical transistor 126 may have a first end facing the positive z-direction and a second end facing the negative z-direction opposite to the first end, such as Figure 1 as shown in .

[0049] In some embodiments, the semiconductor body 130 includes a semiconductor material such as single crystal silicon, polycrystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 130 may include single crystal silicon. The source and drain 138 may be doped at a desired doping level using an N+ type dopant (e.g., phosphorus (P) or arsenic (As)) or a P type dopant (e.g., boron (B) or gallium (Ga)). In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the source / drain 138 of the vertical transistor 126 and the bit line 123 to serve as a bit line contact, or between the source / drain 138 of the vertical transistor 126 and the first electrode of the capacitor 128 to serve as a capacitor contact 142 to reduce contact resistance. In some embodiments, the gate dielectric 132 includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the gate electrode 134 includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the gate electrode 134 includes multiple conductive layers, for example, a W layer located above a TiN layer. In one example, the gate structure 136 can be a "gate oxide / gate polysilicon" gate, wherein the gate dielectric 132 includes silicon oxide and the gate electrode 134 includes doped polysilicon. In another example, the gate structure 136 can be HKMG, wherein the gate dielectric 132 includes a high-k dielectric and the gate electrode 134 includes a metal.

[0050] As described above, since the gate electrode 134 can be a word line portion or extend as a word line in a word line direction (e.g., the X direction), the second semiconductor structure 104 of the 3D memory device 100 can also include a plurality of word lines, each of which extends along the word line direction. Each word line 134 can be coupled to a row of DRAM cells 124. That is, the bit lines 123 and the word lines 134 can extend along two perpendicular lateral directions, and the semiconductor body 130 of the vertical transistor 126 can extend in a vertical direction perpendicular to the two lateral directions followed by the bit lines 123 and the word lines 134. The word line 134 is in contact with a word line contact (not shown). In some embodiments, the word line 134 includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the word line 134 includes a plurality of conductive layers, for example, a W layer located above a TiN layer, such as Figure 1 as shown in .

[0051] In some embodiments, Figure 1As shown in , the vertical transistor 126 extends vertically through the word line 134 and contacts therewith, and the source or drain 138 of the vertical transistor 126 located at the lower end thereof contacts the bit line 123 (or the bit line contact (if any)). Accordingly, due to the vertical arrangement of the vertical transistor 126, the word line 134 and the bit line 123 can be arranged in different planes in the vertical direction, which simplifies the wiring of the word line 134 and the bit line 123. In some embodiments, the bit line 123 is arranged between the bonding layer 120 and the word line 134 in the vertical direction, and the word line 134 is arranged between the bit line 123 and the capacitor 128 in the vertical direction. The word line 134 can be coupled to the peripheral circuit 112 in the first semiconductor structure 102 through the word line contact (not shown) in the interconnection layer 122, the bonding contacts 121 and 119 in the bonding layers 120 and 118, and the interconnection in the interconnection layer 116. Similarly, the bit lines 123 in the interconnect layer 122 may be coupled to the peripheral circuits 112 in the first semiconductor structure 102 through the bonding contacts 121 and 119 in the bonding layers 120 and 118 , and the interconnects in the interconnect layer 116 .

[0052] In some embodiments, vertical transistors 126 may be arranged in a mirror-symmetrical manner to increase the density of DRAM cells 124 in the bit line direction (eg, the Y direction). Figure 1As shown in , two adjacent vertical transistors 126 in the bit line direction are mirror-symmetric with respect to the trench isolation 160. That is, the second semiconductor structure 104 may include a plurality of trench isolations 160, each of which extends parallel to the word line 134 in the word line direction (X direction) and is disposed between the semiconductor bodies 130 of the vertical transistors 126 of two adjacent rows. In some embodiments, the vertical transistors 126 of each row separated by the trench isolation 160 are mirror-symmetric with respect to the trench isolation 160. The trench isolation 160 may be formed using a dielectric material, the dielectric material including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics or any combination thereof. It should be understood that the trench isolation 160 may include an air gap, each of which is disposed between adjacent semiconductor bodies 130 in the lateral direction. The air gap may be formed due to the relatively small spacing of the vertical transistors 126 in the bit line direction (e.g., Y direction). On the other hand, the relatively large dielectric constant of air in the air gap (e.g., about 4 times the dielectric constant of silicon oxide) compared to some dielectrics (e.g., silicon oxide) can improve the insulation effect between the vertical transistors 126 (and the rows of DRAM cells 124). Similarly, in some embodiments, air gaps are also formed laterally between the word lines / gate electrodes 134 in the bit line direction, depending on the spacing of the word lines / gate electrodes 134 in the bit line direction. In some embodiments, instead of having an air gap in the trench isolation 160, a conductive material (e.g., a metal such as W) is filled into the trench isolation 160 and surrounded by a dielectric material. As described in more detail below, the conductive material in the trench isolation 160 can be coupled outward from the back side of the second semiconductor structure 104.

[0053] like Figure 1As shown in , in some embodiments, the capacitor 128 includes a first electrode 144 located above the source or drain 138 of the vertical transistor 126 (e.g., the upper end of the semiconductor body 130) and coupled to the source or drain 138 via a capacitor contact 142. In some embodiments, the capacitor contact 142 is an ohmic contact, for example, a metal silicide contact, which is in contrast to a Schottky contact. For example, the capacitor contact 142 can include a metal silicide such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon. The capacitor 128 can also include a capacitor dielectric located above and in contact with the first electrode 144 and a second electrode located above and in contact with the capacitor dielectric. That is, the capacitor 128 can be a vertical capacitor in which the electrodes and the capacitor dielectric are stacked vertically (in the Z direction) and the capacitor dielectric can be sandwiched between the electrodes. In some embodiments, each first electrode is coupled to a source or drain 138 of a corresponding vertical transistor 126 in the same DRAM cell, and all second electrodes are coupled to a common plate 146 coupled to ground (e.g., a common ground). Capacitor 128 can have a first end facing the negative z-direction and a second end opposite the first end facing the positive z-direction, such as Figure 1 In some embodiments, the first end of capacitor 128 is coupled to the first terminal of vertical transistor 126 via an ohmic contact (eg, capacitor contact 142 made of a metal silicide material). Figure 1 As shown in , the second semiconductor structure 104 may further include a capacitor contact 147 (e.g., a conductor) in contact with the common plate 146, thereby coupling the capacitor 128 to the peripheral circuit 112 or directly to the ground. In some embodiments, the capacitor contact 147 (e.g., a conductor) extends from the dielectric layer of the bonding layer 120 in the z direction, thereby coupling to the second end of the capacitor 128 via the common plate 146, as shown in FIG. Figure 1 In some embodiments, the ILD layer in which capacitor 128 is formed has the same dielectric material as the two ILD layers to which semiconductor body 130 extends, for example, silicon oxide.

[0054] It should be understood that the structure and configuration of capacitor 128 is not limited to Figure 1, and may include any suitable structure and configuration, such as a planar capacitor, a stacked capacitor, a multi-fins capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-plate capacitor. In some embodiments, the capacitor dielectric includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, the high-k dielectric including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. It should be understood that in some examples, capacitor 128 can be a ferroelectric capacitor used in a FRAM cell, and the capacitor dielectric can be replaced by a ferroelectric layer having a ferroelectric material (such as PZT or SBT). In some embodiments, the electrode includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof.

[0055] like Figure 1 As shown in , the vertical transistor 126 extends vertically through the word line 134 and contacts therewith, the source or drain 138 of the vertical transistor 126 at the lower end thereof contacts the bit line 123, and the source or drain 138 of the vertical transistor 126 at the upper end thereof is coupled to the capacitor 128. That is, due to the vertical arrangement of the vertical transistor 126, the bit line 123 and the capacitor 128 can be arranged in different planes in the vertical direction and coupled to the opposite ends of the vertical transistor 126 of the DRAM cell 124 in the vertical direction. In some embodiments, the bit line 123 and the capacitor 128 are arranged on opposite sides of the vertical transistor 126 in the vertical direction, which simplifies the wiring of the bit line 123 and reduces the coupling capacitance between the bit line 123 and the capacitor 128 compared to a DRAM cell in which the bit line and the capacitor are arranged on the same side of the planar transistor.

[0056] like Figure 1 As shown in , in some embodiments, the vertical transistor 126 is disposed between the capacitor 128 and the bonding interface 106 in the vertical direction. That is, the vertical transistor 126 can be disposed closer to the peripheral circuit 112 of the first semiconductor structure 102 and the bonding interface 106 than the capacitor 128. Since the bit line 123 and the capacitor 128 are coupled to opposite ends of the vertical transistor 126, the bit line 123 (as part of the interconnect layer 122) is disposed in the vertical direction between the vertical transistor 126 and the bonding interface 106. Therefore, the interconnect layer 122 including the bit line 123 can be disposed close to the bonding interface 106 to reduce the interconnect routing distance and complexity.

[0057] In some embodiments, the second semiconductor structure 104 further includes a substrate 148 disposed above the DRAM cell 124. The substrate 148 may be part of a carrier wafer. It should be understood that in some examples, the substrate 148 may not be included in the second semiconductor structure 104.

[0058] like Figure 1 As shown in , the second semiconductor structure 104 may further include a pad extraction interconnect layer 150 located above the substrate 148 and the DRAM cell 124. The pad extraction interconnect layer 150 may include interconnects located within one or more ILD layers, such as contact pads 154. The pad extraction interconnect layer 150 and the interconnect layer 122 may be formed on opposite sides of the DRAM cell 124. The capacitor 128 may be disposed in a vertical direction between the vertical transistor 126 and the pad extraction interconnect layer 150. In some embodiments, the interconnects in the pad extraction interconnect layer 150 are capable of transmitting electrical signals between the 3D semiconductor device 100 and an external circuit, for example, to achieve pad extraction purposes.

[0059] In some embodiments, the second semiconductor structure 104 further includes one or more contacts 152 extending through the substrate 148 and a portion of the pad lead interconnect layer 150, thereby coupling the pad lead interconnect layer 150 to the DRAM cell 124 and the interconnect layer 122. Therefore, the peripheral circuit 112 can be coupled to the DRAM cell 124 through the interconnect layers 116 and 122 and the bonding layers 120 and 118, and the peripheral circuit 112 and the DRAM cell 124 can be coupled to an external circuit through the contact 152 and the pad lead interconnect layer 150. The contact pad 154 and the contact 152 may include a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. In one example, the contact pad 154 may include Al, and the contact 152 may include W. In some embodiments, the contact 152 includes a via surrounded by a dielectric spacer (e.g., having silicon oxide), thereby electrically isolating the via from the substrate 148. Depending on the thickness of substrate 148 , contact 152 may be an ILV having a depth in the sub-micron order (eg, between 10 nm and 1 μm) or may be a TSV having a depth in the micron or tens of microns order (eg, between 1 μm and 100 μm).

[0060] Although not shown, it should be understood that the pad extraction of the 3D memory device is not limited to the following. Figure 1The second semiconductor structure 104 with the DRAM cell 124 is shown to be led out and can be led out from the first semiconductor structure 102 with the peripheral circuit 112. Although not shown, it should also be understood that the air gaps between the word lines 134 and / or between the semiconductor bodies 130 can be partially or completely filled with a dielectric. Although not shown, it should also be understood that more than one array of DRAM cells 124 can be stacked one on top of the other, thereby expanding the number of DRAM cells 124 vertically upward.

[0061] In some embodiments, instead of Figure 1 14 is shown with the substrate 148 positioned above the DRAM cell 124, the second semiconductor structure 104 includes a substrate disposed below the DRAM cell 124. The substrate may be part of a carrier wafer. The DRAM cell 124 may be formed in the front side of the substrate, and the bit line 123 may be formed in the back side of the substrate. The bit line 123 may be conductively coupled to the DRAM cell 124 (e.g., the terminal 138 of the vertical transistor 126) through the substrate. As described in more detail below, the conductive material filled in the trench isolation 160 may be exposed from the back side of the substrate and coupled to, for example, a conductive interconnect.

[0062] Figure 2A 2 shows a perspective view of an exemplary 3D semiconductor device 200. The 3D semiconductor device 200 may be Figure 1 The 3D semiconductor device 100 is similar to or the same as Figure 1 A portion of the 3D semiconductor device 100 (eg, Figure 1 The second semiconductor structure 104 is similar to or the same as Figure 1 The structure of the 3D semiconductor device 100 during the intermediate manufacturing process is similar or identical.

[0063] like Figure 2A As shown in FIG. 1 , the 3D semiconductor device 200 has a front side 201 and a back side 203 along a vertical direction (Z direction). The 3D semiconductor device 200 includes a plurality of bit lines 202 separated by an isolation material 204 (eg, oxide) at the back side 203. The bit lines 202 may be connected to Figure 1 The bit lines 202 may be similar or identical to the bit lines 123. The bit lines 202 may be separated along the X direction and extend along the Y direction.

[0064] The 3D semiconductor device 200 may include a memory cell string on the front side 201. Each memory cell string may be coupled to a corresponding bit line 202. The memory cells may be connected to the Figure 1 The memory cell may include a vertical transistor (e.g., Figure 1 A vertical transistor 126) and a capacitor coupled to the vertical transistor (eg, Figure 1In some embodiments, the gate structures of the two vertical transistors 212, 214 (e.g., Figure 1 The gate structures 136 of the trench structures 210 can be formed in the trench structures 210 and separated by isolation materials 216 (e.g., oxide) in the trench structures 210. Along the X direction, adjacent trench structures 210 (or adjacent vertical transistors in adjacent trench structures 210) can be separated by isolation regions 220 (e.g., Figure 1 As discussed in more detail below, the isolation region 220 may include a conductive material located between adjacent trench structures 210 and surrounded by a dielectric material in the trench.

[0065] Figure 2B The XY plane shows Figure 2A The 3D semiconductor device 200 may include a first region 200a (eg, an array region) and one or more second regions 200b (eg, connection regions) adjacent to the first region 200a along the X direction. Figure 2B As shown in FIG. 1 , the first region 200a is located between the left second region 200b and the right second region 200b (eg, along the X direction). The left and right second regions 200b may be symmetrical with respect to the first region 200a. Figure 2B 2 shows a boundary line 205 between a first region 200a and a corresponding second region 200b.

[0066] The plurality of bit lines 202 extend in the Y direction and are arranged in the X direction. As described above, since the gate electrodes of the vertical transistors 212 and 214 (eg, Figure 1 The gate electrode 134 of the first region 200a may be a word line portion or extend as a word line in a word line direction (e.g., X direction), and thus the 3D memory device 200 may also include a plurality of word lines each extending along the word line direction. Each word line may be coupled to a row of vertical transistors. The vertical transistors 212, 214 may be coupled to two different word lines. In some embodiments, the first region 200a includes memory cells (e.g., Figure 1 The memory cell 124 is an array of memory cells 124, and the one or more second regions 200b include one or more conductive contacts configured to be respectively coupled to each of the plurality of word lines.

[0067] In some embodiments, Figure 2B As shown in FIG. 1 , the trench structure 210 includes two word lines 230 a and 230 b (eg, Figure 1In some embodiments, the word lines 230a, 230b are connected to the inner surface of the word lines 230a, 230b. In some embodiments, the gate electrodes of the corresponding vertical transistors are connected together to form the word lines 230a, 230b.

[0068] Each word line 230a, 230b may include one or more layers, for example, a high-k dielectric layer, an intermediate layer (e.g., TiN), and a metal layer (e.g., W). The word lines 230a, 230b may be formed by cutting one or more layers formed in the trench structure 210. In some embodiments, the one or more layers may be cut at the ends of the trench structure 210. In some embodiments, for example, Figure 2B As shown in FIG, the one or more layers are cut at a position away from both ends 210a, 210b of the trench structure 210. Each word line 230a, 230b may have a U-shape surrounding the corresponding end of the trench structure 210. Each word line 230a, 230b may be coupled outwardly through a corresponding conductive pad 232a, 232b adjacent to the corresponding end 210a, 210b of the trench structure 210, so that the corresponding conductive pad 232a, 232b has a large area.

[0069] In some embodiments, for example, Figure 2B As shown in , the word line 230a extends around the first end 210a of the trench structure 210 located in the right second region 200b, and the conductive pad 232a is adjacent to the first end 210a in the right second region 200b and conductively coupled to the word line 230a. Similarly, the word line 230b extends around the second end 210b of the trench structure 210 located in the left second region 200b, and the conductive pad 232b is adjacent to the second end in the left second region 200b and conductively coupled to the word line 230b. In some embodiments, in order to expand the area of ​​the conductive pads and avoid overlap between the conductive pads, the adjacent conductive pads 232a in the right second region 200b may have different distances from the first end 210a of the trench structure 210a, and the adjacent conductive pads 232b in the left second region 200b may have different distances from the second end 210b of the trench structure 210a.

[0070] As described above, the isolation region 220 is located between adjacent trench structures 210 and may include a conductive material (e.g., metal) surrounded by an isolation material. Moreover, as described in more detail below, the conductive material in the isolation region 220 may be exposed / etched, for example, by etching from the back side 203 without exposing the word lines 230a, 230b in the trench structure 210. The conductive material of the isolation region 220 may be coupled to the conductive interconnect 240. The conductive interconnect 240 may be coupled outwardly through the conductive pad 242. Adjacent conductive pads 242 may be arranged adjacent to opposite ends of the isolation region 220 (e.g., one end located in the left second region 200b and one end located in the right second region 200b). In some embodiments, the conductive pads 232a, 232b for coupling the word lines 230a, 230b outward are located on the front side 201 of the 3D semiconductor device 200, and the conductive pad 242 for coupling the conductive interconnect 240 outward is located on the back side 203 of the 3D semiconductor device 200. In some embodiments, the conductive pads 232a, 232b and the conductive pad 242 are located on the same side, for example, on the front side 201 of the 3D semiconductor device 200, for example, as shown in FIG. Figure 2B as shown in .

[0071] For the purpose of illustration, Figures 3A-3E as well as Figures 4A-4E As depicted in more detail in FIG. 1 , cross-sectional views at positions A, B, and C along the X direction are shown, and cross-sectional views at positions A, D, and E along the Y direction are shown. Figures 3A-3E as well as Figures 4A-4E The structure shown in the figure may be formed before forming the conductive pads 232a, 232b and / or the conductive pad 242. Note that positions A, B, and C are all located in the trench structure 210, wherein positions A and B are located in the second region 200b, and C is located in the first region 200a; positions A and E are located at adjacent trench structures 210, and D is located at the isolation region 220. Positions A, D, and E may have the same position in the X direction. In some examples, such as Figure 2B As shown in , position A spans both sides of word line 230b, and position B spans only one side of word line 230b and the space between word lines 230a and 230b. For comparison and / or convenience, hereinafter, the cross-sectional views at positions A, B, and C are introduced together, and the cross-sectional views at positions A, D, and E are introduced together. Due to the periodicity of the trench structure 210, the cross-sectional views at positions A and E may be the same.

[0072] Figures 3A-3C Cross-sectional views of the exemplary 3D semiconductor structure 300 at different positions A, D, and E along a first lateral direction (eg, Y direction) are shown. Figure 3D-3E Shows Figures 3A-3C 3D semiconductor structure 300 at different positions A, B, and C along a second lateral direction (eg, X direction). 3D semiconductor structure 300 may be Figure 2A-2B The 3D semiconductor device 200 or the structure of the 3D semiconductor device 200 in the middle of the manufacturing process is similar or identical. For example, the 3D semiconductor structure 300 can be a structure before the conductive material in the isolation region between adjacent trench structures is coupled outwardly and / or before at least one conductive layer in the trench structure is cut to form two separated vertical gates. Note that the positions A, B, C, D, and E are defined as Figure 2B The positions are the same as those shown in .

[0073] like Figure 3A As shown in FIG. 1 , the 3D semiconductor structure 300 includes a plurality of trench structures 310 located in a semiconductor substrate 301. For example, the trench structures 310 are formed from the front side of the semiconductor substrate 301. Adjacent trench structures 310 are separated by corresponding isolation regions 320 that may be formed in intermediate trenches between the adjacent trench structures 310. The trench structures 310 may be connected to Figure 2A-2B The isolation region 320 may be similar to or identical to the trench structure 210. Figure 1 The trench isolation 160 or Figure 2A-2B The isolation regions 220 are similar or identical.

[0074] In some embodiments, for example, Figure 3B As shown in FIG. 1 , the trench structure 310 and the isolation region 320 are formed based on corresponding trenches 313 and 323. The trenches 313 and 323 may have the same depth along the vertical direction (e.g., the Z direction). An isolation layer 302 (e.g., including oxide) may be first formed on the inner surface of the trenches 313 and 323. Thereafter, a dielectric layer 304 (e.g., including SiN) may be formed on the isolation layer 302 in the trenches 313 and 323. Figure 4B-4E As discussed in more detail in , trench structure 310 includes isolation material 306 deposited from the bottom of trench 313 into a portion of trench 313. At least one conductive layer 312 may be deposited on top of the isolation material 306 deposited in the portion of trench 313. The at least one conductive layer 312 may be cut to form a plurality of conductive layers for use in vertical transistors (e.g., Figure 1 The vertical transistor 126 or Figure 2A The vertical transistors 212, 214) have two independent vertical gates (eg, Figure 1 In some embodiments, a dielectric layer 303 is formed in the isolation layer 302 between adjacent trenches. The dielectric layer 303 may include a dielectric material, such as SiN.

[0075] In some examples, at least one conductive layer 312 includes an intermediate layer 312a (e.g., including TiN) and a metal layer 312b (e.g., including W). The trench structure 310 may include a high-K dielectric layer between the at least one conductive layer 312 (e.g., intermediate layer 312a) and the dielectric layer 304. As discussed above, the at least one conductive layer 312 may be used as a gate electrode of a vertical transistor (e.g., Figure 1 gate electrode 134) and / or word line (eg, Figure 2B The gate electrode, dielectric layer 304 and isolation layer 302 may form a gate structure of a vertical transistor (eg, Figure 1 gate structure 136).

[0076] In the vertical direction, the isolation material 306 deposited in the portion of the trench 313 has a length (or thickness) from, for example, the bottom surface of the trench 313 to the bottom surface of the at least one conductive layer 312 (or vertical gate electrode) in the trench 313. This length may be about tens of nm, for example, in the range of 10 nm to 100 nm. Thus, the length of the at least one conductive layer 312 or the length of the vertical gate electrode to be formed is less than the depth of the trench 313 by the length of the deposited isolation material 306. In contrast, the isolation region 320 includes a conductive material (e.g., a metal such as W) 322 that may be deposited in the trench 323 from the bottom of the trench 323. As shown in FIG. Figure 4D-4E As discussed in more detail in , there is no isolation material 306 in the trench 323, and the deposited conductive material 322 may have a length (or thickness or depth) from the bottom surface of the trench 323 to the top surface of the trench 323, which may be equal to the depth of the trench 323. Since the trenches 313 and 323 may have the same depth, the length of the conductive material 322 deposited in the entire trench 323 along the vertical direction is greater than the length of the isolation material 306 deposited in the portion of the trench 313, and is also greater than the length of the at least one conductive layer 312 or the length of the vertical gate electrode.

[0077] The at least one conductive layer 312 may also be formed on top of the isolation region 320, for example, on top of the conductive material 322 deposited in the trench 323. The isolation layer 308 may be deposited on the at least one conductive layer 312. The isolation layer 308 may include an isolation material, for example, an oxide. Figure 3B As shown in , the isolation layer 308 may be formed in the trench 313 of the trench structure 310 and on the top of the isolation region 320 .

[0078] The 3D semiconductor structure 300 may be flipped so that the back side of the semiconductor substrate 301 faces upward, for example, to facilitate further processing. Figure 3C As shown in , the semiconductor substrate 301 can be etched from the back side to expose the conductive material 322 in the isolation region 320 or in the trench 323. Since the length of the conductive material 322 filled in the trench 323 is greater than the length of the at least one conductive layer 312 formed in the trench 313, the end of the conductive material 322 is closer to the surface (e.g., the top surface) of the semiconductor substrate 301 at the back side than the end of the at least one conductive layer 312 in the trench 313.

[0079] like Figure 3C As shown in , the semiconductor substrate 301 can be etched in the etching region 330. The etching region 330 can have a top edge z1 (e.g., the surface of the semiconductor substrate 301) and a bottom edge z2 and an etching depth d from the surface or the top edge z1 of the semiconductor substrate to the bottom edge z2. In the vertical direction, the etching depth d is greater than a first distance between the surface or the top edge z1 of the semiconductor substrate 301 and the end 322z of the conductive material 322 filled in the trench 323, and is less than a second distance between the surface or the top edge z1 of the semiconductor substrate 301 and the end 312z of the at least one conductive layer 312 deposited in the trench 313. In some embodiments, the etching region 330 has two opposite edges Y1 and Y2 located in two adjacent trenches 313 in the horizontal direction (e.g., the Y direction). Since the etching region can extend to the adjacent trenches 313 without etching the vertical gate electrode, the etching window becomes larger compared to the structure without the isolation material 306 deposited in the trench 313. In some embodiments, the semiconductor substrate 301 is etched in an even larger etch region / window that spans across the plurality of trench structures 310 and the isolation region 320 along the Y direction.

[0080] In some embodiments, Figure 3A As shown in FIG. , the 3D semiconductor structure 300 includes a first region 300a (eg, Figure 2B The first region 200a and the second region 300b (eg, Figure 2B The second region 200b) has a boundary line 305 along the X direction (e.g., Figure 2B boundary line 205).

[0081] Figure 3D-3E FIG. 4 shows cross-sectional views of an exemplary 3D semiconductor structure 300 at different positions A, B, and C along the X direction. Figure 3DAs shown in FIG. 1 , positions A and B are located in the second region 300 b (e.g., the connection region), while position C is located in the first region 300 a (e.g., the array region). The trench structure 350 at position C is configured as a vertical gate of a vertical transistor for a memory cell in the second region 300 b. Figure 4C-4E As described in more detail in FIG. 3 , similar to the isolation region 320, no isolation material 306 is deposited in the trench 353 of the trench structure 350. In addition, there may be no dielectric layer 304 formed in the trench 353. At least one conductive layer 312 is conformally formed on the isolation layer 302 in the trench 353. Thus, the length of the at least one conductive layer 312 in the trench 353 (or the vertical gate formed in the trench structure 350) is greater than the length of the at least one conductive layer 312 in the trench 313 (or the vertical gate formed in the trench structure 310).

[0082] The trench structure 340 at position B may be similar to or the same as the trench structure 310 at position A. The trench structure 340 includes an isolation material 306 filled in the bottom of the trench 343, at least one conductive layer 312 located on the top of the isolation material 306 filled in the trench 343, and an isolation layer 308 located on the at least one conductive layer 312 in the trench 343. Since there is a dielectric layer 304 in the trench 343 and there is no dielectric layer 304 in the trench 353, the surface of the at least one conductive layer 312 adjacent to the trench 353 may be lower than the surface of the at least one conductive layer 312 adjacent to the trench 343, for example, Figure 3E as shown in .

[0083] In some embodiments, the semiconductor substrate 301 is etched from the back side of the semiconductor substrate 301 in an etched region / window located in the second region 300b but not in the first region 300a (e.g., not exceeding the boundary line 305 along the X direction). In some embodiments, the semiconductor substrate 301 is etched from the back side of the semiconductor substrate 301 in an etched region / window located in both the second region 300b and the first region 300a, thereby exposing and / or etching the conductive material 322 in the isolation region 320 in the second region 300b for external coupling, and enabling etching or cutting of at least one conductive layer 312 in the bottom of the trench 353 in the first region 300a, thereby forming a vertical gate of a vertical transistor of a memory cell. By etching the conductive material 322 in the isolation region 320 together with at least one conductive layer 312 for forming a vertical gate of a memory cell in the first region, the techniques implemented in the present disclosure can reduce manufacturing costs and difficulties, eliminate problems or risks caused by metal stamping from the front side of the semiconductor substrate (e.g., difficult to control due to wire twisting), and optimize the manufacturing process (e.g., omitting one or more processing operations, such as a high-cost oxide recessing operation).

[0084] Figures 4A-4E 2 shows a cross-sectional view of an exemplary 3D semiconductor structure at various stages of the fabrication process. Figure 3A-3B 3D semiconductor structure 300 is similar or identical to that of FIG. Figures 4A-4E Each of the above includes a cross-sectional view of the corresponding structure in Figures (a) and (b), respectively. Figure (a) shows a cross-sectional view of the corresponding structure at positions A, D, and E in the YZ plane, while Figure (b) shows a cross-sectional view of the corresponding structure at positions A, B, and C in the XZ plane. The definitions of positions A, B, C, D, and E are the same as Figure 2B and Figures 3A-3E The same definition as in .

[0085] Figure 5 is a flow chart of an exemplary process 500 for forming a 3D semiconductor device. The 3D semiconductor device may be Figure 1 3D semiconductor device 100, or a portion of 3D semiconductor device 100 (eg, Figure 1 The second semiconductor structure 104 is similar to or the same as Figure 1 The structure of the 3D semiconductor device 100 in the intermediate process of manufacturing is similar to or the same as that of Figure 2A-2B The 3D semiconductor device 200 is similar to or the same as Figures 3A-3E The 3D semiconductor device 300 is similar to or the same as, or Figure 4EThe 3D semiconductor structure 400e is similar or identical to that of Figures 4A-4E The process 500 may include forming Figures 4A-4E The process 500 includes operations (or steps) that can be performed in any suitable order and / or in any combination. The words "operation" and "step" can be used interchangeably to describe the process in the present disclosure.

[0086] In operation 510, a semiconductor substrate 401 is provided. The semiconductor substrate 401 may be Figures 3A-3E The semiconductor substrate 401 may be similar or identical to the semiconductor substrate 301 of the embodiment of the present invention. The semiconductor substrate 401 may include silicon (eg, single crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material.

[0087] In operation 520, an isolation region 420 is formed between a plurality of adjacent vertical transistors in a semiconductor substrate. The isolation region 420 may be, for example, Figure 1 Trench isolation 160, Figure 2A-2B The isolation area 220 or Figures 3A-3E The vertical transistor may be, for example, Figure 1 The vertical transistor 126 or Figure 2A Each of the plurality of adjacent vertical transistors extends along a vertical direction (e.g., a Z direction), and two adjacent vertical transistors and a corresponding isolation region between the two adjacent vertical transistors are arranged along a first lateral direction (e.g., a Y direction) perpendicular to the vertical direction. The corresponding isolation region includes a conductive material (e.g., Figures 3A-3E The conductive material 322 of the isolation region is formed in a vertical direction, and the length of the conductive material in the isolation region is greater than the length of the vertical gate of each of the two adjacent vertical transistors, for example, Figures 3A-3E as shown in .

[0088] In some embodiments, operation 520 includes sub-operations 522, 524, and 526. In sub-operation 522, a plurality of trenches (e.g., 413, 423, 443, and 453 at positions A, B, C, D, and E) are formed in semiconductor substrate 401, e.g., Figure 4A As shown in FIG. 4 , the grooves 413, 423, 443, and 453 can be respectively Figures 3A-3EThe grooves 313, 323, 343, 353 are similar or identical. These grooves extend in a vertical direction. These grooves may have the same depth in a vertical direction (e.g., Z direction) and / or have the same width in a first lateral direction (e.g., Y direction) and / or have the same width in a second lateral direction (e.g., X direction). The semiconductor substrate 401 may have a front side and a back side, and the plurality of grooves may be formed from the front side of the semiconductor substrate 401. In some embodiments, one or more layers (e.g., an isolation layer 402a and a dielectric layer 403) are deposited on the surface of the front side of the semiconductor substrate 401 and the deposited one or more layers are patterned and etched through to the semiconductor substrate 401, thereby forming grooves.

[0089] In some embodiments, for example, Figure 4A As shown in FIG. , the isolation layer 402 (eg, Figures 3A-3E The isolation layer 302 of the dielectric layer 404 (e.g., Figures 3A-3E The dielectric layer 304 of the semiconductor substrate 401 is formed on the isolation layer 402 inside and outside the trenches 413, 423, 443, 453. The dielectric layer 404 may include a dielectric material, for example, SiN. Figures (a) and (b) show the trench structure 400a after the isolation layer 402 and the dielectric layer 404 are formed in the trenches 413, 423, 443, 453. The semiconductor substrate 401 may include a first region (for example, Figure 2B The first region 200a or Figures 3A-3E The first region 300a) and the second region forming the connection region (eg, Figure 2B The second area 200b or Figures 3A-3E The first region and the second region have a boundary line 405 (eg, Figure 2B The borderline 205 or Figures 3A-3E boundary line 305).

[0090] In some embodiments, process 500 further includes depositing isolation material 406 (e.g., oxide) to fill a portion of each of trenches 413, 423, 443, 453 in a vertical direction. The formed structure 400b includes isolation material 406 deposited in portions of trenches 413, 423, 443, 453, respectively, such as Figure 4B As shown in . The deposited isolation material 406 may have a length (or thickness) in the vertical direction from the bottom of the trenches 413, 423, 443, 453. The length may be about tens of nm, for example, in the range of 10 nm to 100 nm.

[0091] In some embodiments, the process 500 further includes: patterning the photoresist 430 to cover the two adjacent grooves 413 at positions A and E and expose the middle groove 423 at position D along the Y direction, and expose the groove 453 at position C in the first region, and cover the grooves 413 and 443 at positions A and B in the second region along the X direction. Figure 4C As shown in the figures (a) and (b), in the formed structure 400c, the photoresist 430 is inserted into the grooves 413, 443 to fill the grooves 413, 443 and cover the surfaces adjacent to the grooves 413, 443, while there is no photoresist 430 in the middle groove 423 in the second region and in the groove 453 in the first region.

[0092] In some embodiments, the process 500 further includes etching the isolation material 406 deposited in the middle trench 423 in the second region and in the trench 453 in the first region, for example, by wet etching. For example, by wet etching, the process 500 can further etch the dielectric layer 404 deposited in the middle trench 423 in the second region and in the trench 453 in the first region. Note that the isolation layer 402 in the trenches 423, 453 remains unetched. Figure 4D Shows the etching Figure 4C The structure 400d is formed after the structure 400c is formed. It shows that the isolation material 406 and the deposited dielectric layer 404 deposited in the trenches 423 and 453 are etched away, while the isolation material 406 and the deposited dielectric layer 404 deposited in the trenches 413 and 443 are still protected by the photoresist 430.

[0093] In operation 524, a corresponding isolation region 420 is formed by depositing a conductive material 462 in the middle trench 423 between two adjacent trenches 413. Figure 4E As shown in the diagram (a) of , a conductive material 462 may be filled in the middle trench 423. In some embodiments, a dielectric layer 464 is deposited on the isolation layer 402 in the middle trench 423 before the conductive material 462 is filled in the middle trench 423. In some embodiments, during the deposition of the dielectric layer 464 and the conductive material 462 in the middle trench 423, the trench 453 in the first region is protected from deposition, for example, by forming another photoresist in the first region. After the isolation region 420 is formed, the photoresist 430 is removed.

[0094] In operation 526, at least one conductive layer 412 is deposited on the formed structure, wherein the at least one conductive layer 412 may be conformally deposited on the dielectric layer 404 and on top of the isolation material 406 deposited in the trenches 413, 443, the at least one conductive layer 412 may also be deposited on the isolation region 420, and the at least one conductive layer 412 may be conformally deposited on the isolation layer 402 in the trenches 453 in the first region. The at least one conductive layer 412 may be conformally deposited on the dielectric layer 404 and on top of the isolation material 406 deposited in the trenches 413, 443. Figures 3A-3E In some embodiments, at least one conductive layer 412 includes an intermediate layer 412a (e.g., Figures 3A-3E The intermediate layer 312a) and the metal layer 412b (eg, Figures 3A-3E In some embodiments, before depositing the at least one conductive layer 412, a high-K dielectric layer may be deposited on the isolation layer 402 in the trench 453 and on the dielectric layer 404 in the trenches 413 and 443.

[0095] In some embodiments, process 500 further includes depositing isolation layer 408 on at least one conductive layer 412 . Figure 4E The resulting structure 400e is shown after deposition of the isolation layer 408. The structure 400e may be Figures 3A-3E The 3D semiconductor structure 300 is the same as that of FIG. Figure 4E The diagram (a) can be compared with Figure 3A is the same as diagram (b), and Figure 4E The diagram (b) can be compared with Figure 3E The structure 400e may include trench structures 410 at positions A and E (eg, Figures 3A-3E The trench structure 310 of FIG. 1 ), the isolation region 420 at the position D (eg, Figures 3A-3E Isolation region 320), trench structure 440 at position B (eg, Figures 3A-3E ) and trench structures 450 (eg, Figures 3A-3E The trench structure 350).

[0096] As noted above, along the vertical direction, the length of at least one conductive layer 412 deposited in the adjacent trenches 413 is smaller than the length of the conductive material 462 filled in the middle trench 423, for example, Figure 4E The length of at least one conductive layer 412 deposited in the grooves 413, 443 in the second region is also smaller than the length of the at least one conductive layer 412 in the grooves 453 in the first region, as shown in FIG. Figure 4E As shown in diagram (b).

[0097] In some embodiments, as noted above, along the vertical direction, due to the presence of dielectric layer 404 in trench 443 and the absence of dielectric layer 404 in trench 453, the surface of the at least one conductive layer 412 adjacent to trench 453 can be lower than the surface of the at least one conductive layer 412 adjacent to trench 443, for example, Figure 4E As shown in figure (b) in .

[0098] In some embodiments, the process 500 further includes: for each of the trench structures 410, 440, 450, cutting the at least one conductive layer 412 deposited in the trenches 413, 443, 453 to form two separated vertical gates (e.g., Figure 1 The gate electrode 134), for example, Figure 2B The vertical gate may be coupled to a word line or may serve as a word line (eg, Figure 2B Accordingly, each of the vertical gates in the trenches 413, 443 in the second region has a length that is less than the length of the conductive material 462 in the isolation region 420, and less than the length of the vertical gate in the trench 453 in the first region.

[0099] In some embodiments, the process 500 further includes: etching the semiconductor substrate 401 from the back side of the semiconductor substrate 401 to expose the conductive material 462 in the corresponding isolation region 420 without exposing the vertical gates (or the deposited at least one conductive layer 412) of the two adjacent vertical transistors in the adjacent trench structure 410, for example, Figure 3C In some embodiments, along the vertical direction, from the surface of the semiconductor substrate 401 (eg, Figure 3C z1 in the etched area (e.g. Figure 3C The semiconductor substrate is etched in an etched region 330. The etched region has a bottom edge (eg, Figure 3C z2 in ) and the etching depth from the surface of the semiconductor substrate to the bottom edge (e.g., Figure 3C In the vertical direction, the depth is greater than the distance between the surface of the semiconductor substrate 401 and the end of the conductive material filled in the middle trench 423 (for example, Figure 3C 322z in the trenches 413) and is smaller than a distance between the surface of the semiconductor substrate and an end of at least one conductive layer deposited in each of two adjacent trenches 413 (eg, Figure 3C In some embodiments, the etched region has two opposite edges (eg, Figure 3CY1, Y2 in (a).

[0100] In some embodiments, process 500 further includes forming a corresponding conductive interconnect (eg, Figure 2B In some embodiments, the process 500 further includes: forming a plurality of bit lines (eg, Figure 1 The bit line 123 or Figure 2A-2B bit line 202).

[0101] In some embodiments, process 500 includes forming an array structure in a first region. The array structure may include a plurality of memory cells (e.g., Figure 1 Each memory cell includes a corresponding vertical transistor (eg, Figure 1 The vertical transistor 126 or Figure 2A The isolation region 420 and the trench structures 410, 440 are formed in a second region adjacent to the first region.

[0102] Figure 6 A block diagram of a system 600 having one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of the present disclosure is shown. The system 600 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other electronic device having a storage component located therein. Figure 6 As shown in , system 600 may include a host device 608 and a memory system 602, the memory system 602 having one or more 3D memory devices 604 and a memory controller 606. The host device 608 may include a processor of an electronic device, such as a central processing unit (CPU), or may include a system on a chip (SoC), such as an application processor (AP). The host device 608 may be configured to send data to or receive data from the one or more 3D memory devices 604.

[0103] The 3D memory device 604 may be any 3D memory device disclosed herein, for example, Figure 1 , Figure 2A-2B The 3D memory device depicted in or based on Figure 3A-3B3D memory device of the 3D semiconductor structure 300. In some embodiments, the 3D memory device 604 includes a NAND flash memory. A memory controller 606 (also known as a controller circuit) is coupled to the 3D memory device 604 and a host device 608. Consistent with embodiments of the present disclosure, the 3D memory device 604 may include a plurality of conductive interconnects that contact a conductive pad in a conductive pad layer through a cover layer, and the memory controller 606 may be coupled to the 3D memory device 604 through at least one of the plurality of conductive interconnects. The memory controller 606 is configured to control the 3D memory device 604. For example, the memory controller 606 may be configured to operate a plurality of channel structures via word lines. The memory controller 606 may manage data stored in the 3D memory device 604 and communicate with the host device 608.

[0104] In some embodiments, the memory controller 606 is designed / configured to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 606 is designed / configured to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage component of mobile devices such as smart phones, tablets, laptops, etc., and enterprise storage arrays. The memory controller 606 can be configured to control the operation of the 3D memory device 604, such as read, erase, and program (or write) operations. The memory controller 606 can also be configured to manage various functions related to data stored or to be stored in the 3D memory device 604, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 606 is further configured to process error correction codes (ECC) related to data read from or written to the 3D memory device 604. Any other suitable functions may also be performed by the memory controller 606 , such as formatting the 3D memory device 604 .

[0105] The memory controller 606 may communicate with an external device (e.g., the host device 608) according to a specific communication protocol. For example, the memory controller 606 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0106] The memory controller 606 and the one or more 3D memory devices 604 can be integrated into various types of storage devices, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 602 can be implemented and packaged into different types of final electronic products. Figure 6 In one example shown, a memory controller 606 and a single 3D memory device 604 may be integrated into a memory card 602. The memory card 602 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc.

[0107] The embodiments and actions and operations of the subject matter described in the present disclosure may be implemented in a computer software or firmware, computer hardware (including the structures disclosed in the present disclosure and their structural equivalents), or a combination of one or more thereof, embodied in a tangible manner in a digital electronic circuit. The embodiments of the subject matter described in the present disclosure may be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier, for execution by a data processing device or for controlling the operation of a data processing device. The carrier may be a tangible, non-transitory computer storage medium. Alternatively, or additionally, the carrier may be an artificially generated propagation signal, for example, a machine-generated electrical signal, optical signal, or electromagnetic signal, which is generated to encode information for transmission to an appropriate receiving device, thereby being executed by a data processing device. A computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them, or a portion thereof. A computer storage medium is not a propagation signal.

[0108] It should be noted that references to "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment may include the specific features, structures, or characteristics. In addition, such wording does not necessarily refer to the same embodiment. In addition, when specific features, structures, or characteristics are described in conjunction with an embodiment, it is within the knowledge of a person skilled in the relevant art to implement such features, structures, or characteristics in conjunction with other embodiments that are explicitly or not explicitly described.

[0109] In general, terms should be understood at least in part by the context of use. For example, the words "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, at least in part depending on the context. Similarly, words such as "one," "an," or "the" may also be understood to express singular use or plural use, depending at least in part on the context. In addition, the word "based on" may be understood to not necessarily be intended to express an exclusive set of factors, but rather may allow for the presence of other factors that may not be explicitly stated, depending at least in part on the context.

[0110] It should be readily understood that the meanings of "on", "over", and "over" in this disclosure should be interpreted in the broadest manner, and thus "on" not only means being directly on something, but also includes being on something with intervening features or layers. In addition, "over" or "over" not only means being above or on something, but also includes being above or on something without any intervening features or layers (i.e., directly on something).

[0111] In addition, for ease of description, spatially relative terms such as "below", "beneath", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature to one or more other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or process steps in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly in a similar manner.

[0112] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore semiconductor devices are formed on the top side of the substrate, unless otherwise specified. The bottom surface is opposite to the top surface, and therefore the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself can be patterned. The material added to the top of the substrate can be patterned, or it can remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0113] As used herein, the term "layer" refers to a material portion including an area with a certain thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. The layer can extend within the overall range of the lower structure or the upper structure, or can have a range smaller than the range of the lower structure or the upper structure. In addition, the layer can be a region of a homogeneous or heterogeneous continuous structure, which has a thickness less than the thickness of the continuous structure. For example, the layer can be located between any set of horizontal planes between the top surface and the bottom surface of the continuous structure, or at the top surface and the bottom surface. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, can contain one or more layers therein, and / or can have one or more layers located thereon, above it and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductive layers and a contact layer (in which contacts, interconnects and / or vertical interconnect channels (VIAs) are formed) and one or more dielectric layers.

[0114] As used herein, the term "nominal / nominally" refers to an expected value or target value of a characteristic or parameter of a component or process step set during the design phase of a product or process, together with a range of values ​​above and / or below the expected value. As used herein, the range of values ​​may be due to slight variations in the manufacturing process or tolerances. As used herein, the term "approximately" means that the value of a given quantity may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "approximately" may mean that the value of a given quantity varies within, for example, 10-30% of the value (e.g., +-10%, +-20%, or +-30% of the value).

[0115] In this disclosure, the words “horizontal / horizontally / lateral / laterally” refer to being nominally parallel to a lateral surface of a substrate, and the words “vertical” or “vertically” refer to being nominally perpendicular to a lateral surface of a substrate.

[0116] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having a vertically oriented string of memory cell transistors (referred to herein as a "memory string", e.g., a NAND string) located on a laterally oriented substrate such that the memory string extends in a vertical direction relative to the substrate.

[0117] The present disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, forming a first feature on or above a second feature appearing in the description below may include an embodiment in which the first feature and the second feature may be directly in contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. The purpose of this repetition is to simplify and clarify, and it does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0118] The above description of the specific embodiments can be easily modified and / or adjusted for various applications. Therefore, based on the teaching and guidance provided herein, it is intended that such adjustments and modifications fall within the meaning and equivalents of the disclosed embodiments.

[0119] Although the present disclosure contains many specific implementation details, these should not be understood as limiting the scope of the protection claimed, which is defined by the claims themselves, but should only be understood as a description of features unique to a particular embodiment. Certain features described in the present disclosure in the context of multiple separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any appropriate sub-combination. In addition, although certain features may be described above as functioning in a particular combination and even initially claimed as such, one or more features from the claimed combination may be removed from the combination in some cases, and the claims may relate to sub-combinations or variations of sub-combinations.

[0120] Similarly, although operations are depicted in a specific order in the drawings and operations are described in a specific order in the claims, this should not be understood as having to perform such operations in the specific order shown or in a sequential order in order to obtain the desired result, or having to perform all the operations shown. In some cases, multitasking and parallel processing may be advantageous. In addition, the division of various system modules and components in the embodiments described above should not be understood as requiring such division in all embodiments, and it should be understood that the described program components and systems can generally be integrated together into a single software product or packaged into multiple software products.

[0121] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the appended claims. For example, the actions set forth in the claims can be performed in a different order and still achieve the desired results. As an example, the processes shown in the accompanying drawings do not necessarily require the specific order shown or sequential ordering to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

[0122] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A method comprising: providing a semiconductor substrate; as well as forming an isolation region between a plurality of adjacent vertical transistors in the semiconductor substrate, wherein each of the plurality of adjacent vertical transistors extends along a vertical direction, and wherein two adjacent vertical transistors and a corresponding isolation region between the two adjacent vertical transistors are arranged along a horizontal direction perpendicular to the vertical direction, and The corresponding isolation region comprises a conductive material, and wherein, along the vertical direction, a length of the conductive material in the corresponding isolation region is greater than a length of a vertical gate of each of the two adjacent vertical transistors.

2. The method according to claim 1, wherein: Forming the isolation region between the plurality of adjacent vertical transistors in the semiconductor substrate comprises: forming a plurality of trenches in the semiconductor substrate, the plurality of trenches being arranged along the horizontal direction, and each of the plurality of trenches extending along the vertical direction; and The corresponding isolation region is formed by depositing the conductive material in a middle trench between two adjacent trenches used to form the two adjacent vertical transistors.

3. The method according to claim 2, further comprising: forming the two adjacent vertical transistors by depositing an isolation material in the two adjacent trenches and then depositing at least one conductive layer on the isolation material deposited in the two adjacent trenches to form the vertical gates of the two adjacent vertical transistors, Wherein, along the vertical direction, the length of at least one conductive layer deposited in each of the two adjacent trenches is smaller than the length of the conductive material filled in the middle trench.

4. The method according to claim 3, wherein: The semiconductor substrate comprises a first side and a second side opposite to the first side, wherein forming the isolation region between the adjacent vertical transistors in the semiconductor substrate comprises forming the isolation region between the adjacent vertical transistors in the semiconductor substrate from a first side of the semiconductor substrate, and Wherein, the method further comprises: The semiconductor substrate is etched from the second side of the semiconductor substrate to expose the conductive material in the corresponding isolation region without exposing the vertical gates of the two adjacent vertical transistors.

5. The method according to claim 4, wherein: Etching the semiconductor substrate from the second side of the semiconductor substrate includes: etching the semiconductor substrate in an etching region along the vertical direction from a surface of the semiconductor substrate, wherein the etching region has a bottom edge and an etching depth from the surface of the semiconductor substrate to the bottom edge, and Wherein, along the vertical direction, the etching depth is greater than a first distance between the surface of the semiconductor substrate and the end of the conductive material filled in the middle trench, and is less than a second distance between the surface of the semiconductor substrate and the end of at least one conductive layer deposited in each of the two adjacent trenches.

6. The method according to claim 4 or 5, further comprising: A corresponding conductive interconnect is formed in the second side of the semiconductor substrate in contact with the exposed conductive material in the corresponding isolation region.

7. The method according to any one of claims 4 to 6, further comprising: A plurality of bit lines are formed from the second side of the semiconductor substrate.

8. The method according to any one of claims 3 to 7, wherein: The method comprises: depositing the isolation material to fill a portion of each of the plurality of trenches along the vertical direction; patterning a photoresist to cover the two adjacent trenches and expose the middle trench; etching the isolation material deposited in the middle trench; depositing the conductive material in the middle trench to form the corresponding isolation region; and The photoresist is removed, and the at least one conductive layer is deposited on the isolation material deposited in the two adjacent trenches to form the vertical gates of the two adjacent vertical transistors.

9. The method according to any one of claims 3 to 8, wherein: The method comprises: For each of the two adjacent trenches, at least one conductive layer deposited in the trench is cut to form two separate vertical gates of a pair of independent vertical transistors in the trench.

10. The method according to any one of claims 3 to 9, further comprising: forming an array structure in a first region, the array structure comprising a plurality of memory cell strings, each memory cell in the plurality of memory cell strings comprising a corresponding vertical transistor, The plurality of adjacent vertical transistors and the isolation region in the semiconductor substrate are formed in a second region adjacent to the first region.

11. The method according to claim 10, wherein: Forming the array structure comprises: forming the respective vertical transistors of the plurality of memory cell strings by depositing the at least one conductive layer in corresponding trenches, Wherein, along the vertical direction, a length of at least one conductive layer deposited in the corresponding trench in the first region is greater than a length of the vertical gate of each of the two adjacent vertical transistors in the second region.

12. The method according to claim 11, wherein: The method comprises: depositing the isolation material so as to fill, along the vertical direction, a portion of each of the two adjacent trenches for the two adjacent vertical transistors in the second region and the corresponding trench for the memory cell in the first region; patterning a photoresist to cover the two adjacent trenches and expose the corresponding trench; etching the isolation material deposited in the corresponding trench; removing the photoresist to expose the two adjacent trenches; and The at least one conductive layer is deposited on the isolation material deposited in the two adjacent trenches to form the vertical gates of the two adjacent vertical transistors, and the at least one conductive layer is deposited in the corresponding trench to form the vertical transistor for the memory cell.

13. A semiconductor device comprising: Semiconductor substrate; a plurality of vertical transistors located in the semiconductor substrate along a horizontal direction, each of the plurality of vertical transistors extending along a vertical direction perpendicular to the horizontal direction; as well as a plurality of isolation regions located in the semiconductor substrate, each of the plurality of isolation regions being located between two adjacent vertical transistors in the plurality of vertical transistors along the horizontal direction, The isolation region includes a conductive material, and the length of the conductive material in the isolation region along the vertical direction is greater than the length of a vertical gate of each of the two adjacent vertical transistors.

14. The semiconductor device according to claim 13, wherein: The isolation region includes the conductive material filled in a middle trench between two adjacent trenches corresponding to the two adjacent vertical transistors, wherein the vertical gate of each of the two adjacent vertical transistors comprises at least one conductive layer on the isolation material filled in the portion of the corresponding trench of the two adjacent trenches, and Wherein, along the vertical direction, the length of the at least one conductive layer in each of the two adjacent trenches is smaller than the length of the conductive material filled in the middle trench.

15. The semiconductor device according to claim 14, wherein: The semiconductor substrate comprises a first side and a second side opposite to the first side, wherein the plurality of isolation regions and the plurality of vertical transistors are located in the first side of the semiconductor substrate, and Wherein, the semiconductor device further comprises: A conductive interconnect is formed in the second side of the semiconductor substrate, wherein each of the conductive interconnects contacts the conductive material in a corresponding isolation region of the plurality of isolation regions, and each of the conductive interconnects has an end portion that is higher than an end portion of the at least one conductive layer in each of the two adjacent trenches along the vertical direction from the second side of the semiconductor substrate.

16. The semiconductor device according to claim 14 or 15, further comprising: an array structure located in the first region, the array structure comprising a plurality of memory cell strings, each memory cell in the plurality of memory cell strings comprising a vertical transistor having a vertical gate, The plurality of isolation regions and the plurality of vertical transistors are formed in a second region of the semiconductor substrate adjacent to the first region along a third direction perpendicular to the vertical direction and the horizontal direction.

17. The semiconductor device according to claim 16, wherein: Along the vertical direction, a length of the vertical gate of the vertical transistor of the memory cell in the first region is greater than a length of the vertical gate of each of the two adjacent vertical transistors in the second region.

18. The semiconductor device according to claim 16 or 17, wherein: Along the third direction, the vertical gate of the vertical transistor of the memory cell in the first region is in direct contact with the first isolation layer, while the vertical gate of each of the two adjacent vertical transistors in the second region is separated from the second isolation layer by a passivation layer.

19. A system comprising: Memory devices, including: Semiconductor substrate; a plurality of vertical transistors located in the semiconductor substrate along a horizontal direction, each of the plurality of vertical transistors extending along a vertical direction perpendicular to the horizontal direction; and a plurality of isolation regions in the semiconductor substrate, each of the plurality of isolation regions being located between two adjacent vertical transistors along the horizontal direction, wherein the isolation regions include a conductive material, and wherein, along the vertical direction, a length of the conductive material in the isolation regions is greater than a length of a vertical gate of each of the two adjacent vertical transistors; and A controller is coupled to the memory device and is configured to control the memory device.

20. The system of claim 19, wherein: The isolation region includes the conductive material filled in a middle trench between two adjacent trenches corresponding to the two adjacent vertical transistors, wherein the vertical gate of each of the two adjacent vertical transistors comprises at least one conductive layer on the isolation material filled in the portion of the corresponding trench of the two adjacent trenches, and Wherein, along the vertical direction, the length of the at least one conductive layer in each of the two adjacent trenches is smaller than the length of the conductive material filled in the middle trench.

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