Semiconductor heterojunction composite substrate and preparation method thereof

Abstract

The invention discloses a semiconductor heterojunction composite substrate and a preparation method thereof. The composite substrate comprises an epitaxial layer; the first buffer layer is located on one side of the epitaxial layer, and the material of the first buffer layer comprises a two-dimensional Van der Waals material; the first substrate is located on the side, away from the epitaxial layer, of the first buffer layer, and the first substrate and the epitaxial layer have different crystal forms, so that the problem that the performance of a power device is reduced due to crystal defects of heterojunction epitaxy in the related technology is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor heterojunction composite substrate and a method for preparing the semiconductor heterojunction composite substrate. Background Art

[0002] At present, the homogeneous epitaxy technology of silicon carbide is relatively mature, and it is generally carried out in a step flow growth mode. There are still certain problems with heteroepitaxial technology. For example, the current 3C / 4H heterojunction is usually obtained by epitaxially growing a 3C crystal on a 4H substrate, but this method is difficult to obtain high-quality epitaxial materials at the wafer level. Usually, the epitaxial layer manufactured by this method has a double positioning boundary (DPB) crystal defect. This is because the arrangement order of the surface layer of the 4H substrate can be ABC or ACB, so the 3C crystal formed can be ABC or ACB. When the grains of two different arrangement orders come into contact, DPB will be formed. Since this defect is thermodynamically stable, there is currently no relevant means to eliminate it. The presence of DPB will increase the scattering of carriers and reduce the channel mobility. Therefore, it is still technically difficult to obtain a high-quality epitaxial layer of 3C-SiC at the wafer level by heteroepitaxial growth, and the existing technical solutions cannot achieve this goal. With the advancement of liquid phase growth technology, large-size 3C substrate growth technology will gradually break through. At present, 4-inch N-type 3C-SiC has begun commercialization. Summary of the invention

[0003] The present application provides a semiconductor heterojunction composite substrate and a method for preparing the semiconductor heterojunction composite substrate, so as to solve the problem in the related art that the heterojunction epitaxy reduces the performance of power devices due to crystal defects.

[0004] According to one aspect of the present application, a semiconductor heterojunction composite substrate is provided, comprising: an epitaxial layer; a first buffer layer, located on one side of the epitaxial layer, wherein the material of the first buffer layer comprises a two-dimensional van der Waals material; and a first substrate, located on a side of the first buffer layer away from the epitaxial layer, wherein the first substrate and the epitaxial layer have different crystal types.

[0005] Optionally, the two-dimensional van der Waals material includes graphene and / or transition metal chalcogenides.

[0006] Optionally, the first buffer layer and the first substrate form a composite layer, and the semiconductor heterojunction composite substrate includes a plurality of the composite layers.

[0007] Optionally, the thickness of the first buffer layer is less than or equal to 0.5 µm.

[0008] According to another aspect of the present application, a method for preparing a semiconductor heterojunction composite substrate is provided, which is used to prepare any one of the semiconductor heterojunction composite substrates, and the preparation method includes the following steps: providing an epitaxial layer, and forming a first buffer layer on one side of the epitaxial layer, wherein the material of the first buffer layer is a two-dimensional van der Waals material; providing a wafer, wherein the wafer and the epitaxial layer have different crystal forms, and modifying a partial area on one side of the wafer so that the wafer forms a first film layer and a second film layer in a stacked arrangement, wherein the first film layer is the area of ​​the wafer that has undergone the modification treatment, and the second film layer is the area of ​​the wafer that has not undergone the modification treatment; bonding the first buffer layer on the epitaxial layer to the second film layer on the wafer to obtain a first composite structure; and peeling the first film layer from the first composite structure, wherein the second film layer constitutes a first substrate.

[0009] Optionally, the step of forming the first buffer layer on one side of the epitaxial layer includes: covering the two-dimensional van der Waals material with a high molecular polymer to obtain a first composite layer; covering the first composite layer on the epitaxial layer, wherein the two-dimensional van der Waals material is in contact with the epitaxial layer; after the first composite layer and the epitaxial layer are bonded, the high molecular polymer is peeled off, and the remaining two-dimensional van der Waals material constitutes the first buffer layer.

[0010] Optionally, the modification process includes ion implantation or laser heating modification.

[0011] Optionally, the step of bonding the first buffer layer on the epitaxial layer with the second film layer on the wafer includes: bonding the first buffer layer on the epitaxial layer with the second film layer on the wafer to obtain a preliminary composite structure; applying pressure to the epitaxial layer in the preliminary composite structure along a second direction, wherein the second direction is the direction from the epitaxial layer to the first buffer layer; and performing a first annealing treatment on the preliminary composite structure to obtain the first composite structure.

[0012] Optionally, the step of peeling off the first film layer includes: performing a second annealing treatment on the first composite structure to obtain a second composite structure; peeling off the first film layer from the second composite structure to obtain a third composite structure; performing a third annealing treatment on the third composite structure, wherein the second film layer constitutes a first substrate.

[0013] Optionally, the temperature of the first annealing treatment is less than or equal to the temperature of the second annealing treatment, and the temperature of the second annealing treatment is less than or equal to the temperature of the third annealing treatment.

[0014] By applying the technical solution of the present invention, a semiconductor heterojunction composite substrate is provided. In the composite substrate structure, a first buffer layer is added between the first substrate of different crystal forms and the epitaxial layer. The material of the buffer layer is a two-dimensional van der Waals material. Since the two-dimensional van der Waals material has an adjustable band structure and extremely high carrier mobility, the atomic layers are connected by van der Waals forces without dangling bonds, and an atomically flat interface can be obtained. At the same time, the problems of lattice constant mismatch and thermal expansion coefficient mismatch of the materials on both sides of the heterojunction can be solved by slipping between material layers, and the interface stress release can be significantly improved. Combined with the extremely high carrier mobility between layers, the on-resistance of a vertical structure power device manufactured using the heterojunction can be greatly reduced, thereby improving the performance of the power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 is a schematic cross-sectional structure diagram of a semiconductor heterojunction composite substrate provided according to an embodiment of the present application;

[0017] Figure 2 is a schematic cross-sectional structure diagram of another semiconductor heterojunction composite substrate provided according to an embodiment of the present application;

[0018] Figure 3 is a schematic cross-sectional structure diagram of another semiconductor heterojunction composite substrate provided according to an embodiment of the present application;

[0019] Figure 4 is a schematic cross-sectional structure diagram of another semiconductor heterojunction composite substrate provided according to an embodiment of the present application;

[0020] Figure 5 It is a flow chart of a method for preparing a semiconductor heterojunction composite substrate provided according to an embodiment of the present application;

[0021] Figure 6 It is a flow chart of another method for preparing a semiconductor heterojunction composite substrate provided according to an embodiment of the present application.

[0022] The above drawings include the following reference numerals:

[0023] 10. epitaxial layer; 11. second substrate; 12. second buffer layer; 13. drift layer; 20. first buffer layer; 30. first substrate; 50. composite layer. DETAILED DESCRIPTION

[0024] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0025] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] As described in the background technology, in the prior art, there are still certain problems in the silicon carbide heteroepitaxial technology. 3C / 4H heterojunction is usually obtained by epitaxially growing 3C crystals on a 4H substrate. Since the arrangement order of the surface layer of the 4H substrate can be ABC or ACB, the 3C crystals formed can be ABC or ACB. When the grains of two different arrangement orders come into contact, DPB will be formed. Since this defect is thermodynamically stable, there is currently no relevant means to eliminate it. The presence of DPB will increase the scattering of carriers and reduce channel mobility. In order to solve the above technical problems, the present application provides a semiconductor heterojunction composite substrate and a method for preparing a semiconductor heterojunction composite substrate.

[0028] According to one aspect of the present application, a semiconductor heterojunction composite substrate is provided, such as Figures 1 to 4 As shown, the heterojunction composite substrate includes: an epitaxial layer 10; a first buffer layer 20, located on one side of the epitaxial layer 10, and the material of the first buffer layer 20 includes a two-dimensional van der Waals material; a first substrate 30, located on the side of the first buffer layer 20 away from the epitaxial layer 10, wherein the first substrate 30 and the epitaxial layer 10 have different crystal types.

[0029] In the above-mentioned heterojunction composite substrate structure, a first buffer layer is added between the first substrate of different crystal forms and the epitaxial layer. The material of the first buffer layer includes a two-dimensional van der Waals material. Since the two-dimensional van der Waals material has an adjustable band structure and extremely high carrier mobility, the first substrate and the atomic layers of the epitaxial layer are connected by van der Waals forces without hanging bonds, and an atomically smooth interface can be obtained. At the same time, the matching of the lattice constants and the thermal expansion coefficients of the materials on both sides of the heterojunction of different materials can be improved through the slip between the material layers, and the interface stress release between the first substrate of different crystal forms and the epitaxial layer can be significantly improved. Combined with the extremely high carrier mobility between the layers, the on-resistance of the vertical structure power device manufactured using the heterojunction can be greatly reduced, thereby improving the performance of the power device.

[0030] In some optional embodiments, the material of the epitaxial layer and the first substrate may include silicon carbide material.

[0031] Specifically, power devices are one of the core devices of modern energy systems. Silicon carbide (SiC), a typical representative material of the third-generation semiconductor, is widely used in power devices due to its excellent properties. It can be used in electric vehicles, data centers, smart grids and renewable energy systems. The silicon carbide widely used in industry is 4H-SiC, which has a large band gap (Eg) and high thermal conductivity, and its band gap is 3.2eV. Compared with the band gap of silicon (Si) (the band gap of Si is 1.1eV), devices made of 4H-SiC can reduce the thickness of the drift layer and increase the doping concentration of the drift layer while maintaining the withstand voltage unchanged, thereby reducing the forward on-resistance of the device and reducing the reverse leakage current. Since there are many defects in the commercially available substrates, all device active areas are made in the silicon carbide epitaxial layer, so that the quality of the epitaxial layer plays a decisive role in the characteristics of the device. Among them, the step flow growth technology can obtain an epitaxial layer with good surface quality and low defect density while maintaining a high epitaxial speed.

[0032] In some optional embodiments, the crystal type of the epitaxial layer may include a 4H crystal type, and the crystal type of the first substrate is a 3C crystal type.

[0033] Specifically, in the hexagonal structure of silicon carbide, the C-Si diatomic layer exists in three non-equivalent positions: A, B, and C. Due to the different arrangement orders of the C-Si diatomic layer in the silicon carbide structure, silicon carbide can appear in a variety of polymorphs with different structures. For example, the 3C crystal type is along <111> The order of directions is ABC, and the 4H crystal type is along <0001> The order of arrangement of directions is ABCB. The bandgap width of SiC polytype increases with the increase of the percentage of hexagonal lattice structure. Among them, 3C crystalline silicon carbide is a cubic structure with the smallest bandgap of 2.3eV. Although the small bandgap reduces the critical breakdown electric field, it will reduce the interface attitude of SiC / SiO2 by two orders of magnitude. The gate oxide channel mobility made of 3C-SiC can reach 100~370cm 2 / Vs. At the same time, the barrier height between 3C-SiC and SiO2 is much greater than that between 4H-SiC and SiO2, which significantly reduces the gate-drain tunneling current under large gate drive voltage.

[0034] Furthermore, if Figure 1 As shown, the first substrate 30 is a 3C crystal type, the epitaxial layer 10 is a 4H crystal type, and the crystal orientation of the 3C crystal type is <111> , the crystal orientation of 4H crystal form is <0001> , due to the 3C crystal type <111> The lattice constant of the direction is similar to that of the 4H crystal type. <0001> The lattice constants of the two directions are basically consistent, so that the interface stress on both sides of the first buffer layer 20 is small, and there is basically no lattice mismatch phenomenon. Therefore, an atomically flat plane can be formed at the interface of the epitaxial 3C crystal on the 4H substrate, reducing the scattering of carriers and reducing the channel resistance, so that the device has better stability and reliability. In addition, for 3C crystal silicon carbide (3C-SiC), the close-packed plane is the (111) crystal plane, and the selection <111> The crystal orientation helps in the subsequent peeling of 3C-SiC, reduces the difficulty of peeling, and obtains a complete single crystal film.

[0035] Without considering the spontaneous polarization of SiC, the 3C / 4H heterojunction will form an ideal quantum well structure. Due to the strong electron affinity of 3C, the electrons are distributed on the interface of the 3C / 4H heterojunction close to 3C, and the electrons and charge centers are separated, which makes the Coulomb scattering sharply reduced, forming a two-dimensional electron gas with extremely high mobility. In the case of considering the spontaneous polarization of SiC, 3C-SiC obtains a two-dimensional hole gas when it is epitaxially grown on the contact surface of 4H-SiC and Si, and a two-dimensional electron gas is obtained when it is epitaxially grown on the C surface. Compared with AlGaN / GaN, the 3C / 4H quantum well structure does not have the problems of lattice mismatch and component diffusion. The obtained two-dimensional electron gas or hole gas is less scattered and has extremely high mobility. It can significantly improve the problem of low carrier mobility at the gate oxide interface, reduce the channel resistance and switching loss of power devices, and improve the frequency response characteristics of power devices. At the same time, when the device is reverse blocked, the depletion layer is inside the 4H drift layer, which does not affect the voltage resistance of the device.

[0036] Among them, carrier mobility determines the on-resistance and frequency characteristics of power devices. Power devices with high carrier mobility have large current capacity and frequency response. For planar 4H-SiC MOSFET, due to the high temperature (about 1300°C) during the manufacture of gate oxide, SiC / SiO2 has C residues and dangling bonds, resulting in high-density interface states, which makes the channel carrier mobility low (20~40cm 2 / Vs), the threshold voltage of the device will drift, which will seriously affect the on-resistance, frequency characteristics and reliability of the device. If the channel is annealed in an atmosphere containing N or P to passivate the interface state, this method has limited elimination of the interface state and is incompatible with existing process lines. It requires additional equipment, which increases costs. In addition, increasing the thickness of the gate oxide layer can reduce the electric field strength and tunneling current inside the gate oxide and improve the reliability of the gate oxide, but it will reduce the driving capability of the transistor and damage the switching speed and power characteristics of the device. Another commonly used method is to use a trench gate structure, which reduces the channel interface state by placing the gate oxide interface in the trench inside the epitaxial layer and improves the channel mobility (60~90cm 2 / Vs), but the device manufactured by this method is expensive, has lower uniformity than the planar gate structure, and its mobility is still far lower than its intrinsic mobility.

[0037] In some optional embodiments, such as Figures 1 to 4 As shown, the epitaxial layer 10 may include a second substrate 11, a second buffer layer 12 and a drift layer 13 which are stacked, wherein the drift layer 13 is in contact with the first buffer layer 20. Figure 2As shown, a first buffer layer 20 and a first substrate 30 are sequentially stacked on a side of the drift layer 13 facing away from the second substrate 11 .

[0038] Specifically, at least the second substrate and the drift layer have a 4H crystal type.

[0039] In some optional embodiments, the two-dimensional van der Waals material includes graphene and / or transition metal chalcogenides.

[0040] Specifically, graphene is composed of a single layer of carbon atoms tightly arranged in a two-dimensional honeycomb lattice. Its surface is relatively flat and has no dangling bonds, which helps to form an atomically flat interface, reduce interface roughness, and thus reduce carrier scattering and improve mobility. The graphene layers are connected by van der Waals forces, have good flexibility and slip, and can effectively release the stress generated by the difference in lattice constant and thermal expansion coefficient between 3C-SiC and 4H-SiC, avoiding the formation of cracks or dislocations at the interface, thereby improving the integrity and reliability of the composite structure. In addition, graphene has an extremely high electron mobility (up to 10 4 ~10 6 cm 2 / Vs), which can significantly improve the conductivity of vertical structure power devices made of heterojunction composite substrates, reduce on-state resistance, increase frequency response speed, and reduce switching losses. Introducing graphene between the epitaxial layer of different crystal types and the first substrate can reduce the interface state density at the interface between the epitaxial layer and the first substrate, improve the interface quality of the gate oxide layer, reduce threshold voltage drift and reverse leakage current, and improve the stability and reliability of the device.

[0041] Furthermore, transition metal dichalcogenides (TMDs) materials have good interlayer slip ability and flexibility, can effectively adjust the lattice mismatch between semiconductor materials of different crystal forms, release stress at the interface, and reduce crystal defects such as dislocations, cracks or double positioning boundaries (DPB) at the interface, thereby maintaining the integrity of the composite structure and improving the performance of the device. As the material of the first buffer layer, TMDs can not only reduce the interface state density, reduce the scattering of carriers at the interface, and increase the channel carrier mobility, but also form two-dimensional electron gas or hole gas under specific conditions, thereby significantly reducing the forward on-resistance of the power device and improving the frequency response characteristics, so as to increase the switching speed of the device and reduce the switching loss. TMDs themselves have a high carrier mobility and can provide a high-mobility channel for carriers. Even at the heterogeneous interface, carriers can pass quickly, avoiding the decrease in mobility caused by interface defects. In addition, the thermal expansion coefficient of TMDs is closer to that of 4H-SiC and 3C-SiC, which helps to reduce thermal stress during temperature changes, avoid structural damage caused by thermal mismatch, and improve the stability and reliability of the composite substrate under different temperature conditions. In addition, TMDs can form stable chemical bonds with SiC materials, enhance the bonding strength between the upper and lower materials, improve the uniformity and stability of the bonding interface, and help maintain the integrity of the composite substrate structure and the long-term reliability of the device.

[0042] In some optional embodiments, such as Figure 3 As shown, the first buffer layer 20 and the first substrate 30 form a composite layer 50 , and the semiconductor heterojunction composite substrate includes multiple composite layers 50 .

[0043] Specifically, there is a multilayer composite layer between the epitaxial layer and the first substrate, and the multilayer composite layer includes a first buffer layer composed of a two-dimensional van der Waals material such as graphene and TMDs. Since the two-dimensional van der Waals material has excellent interlayer slip, it means that each layer of material can slide slightly relative to its adjacent layer. This sliding ability allows stress to be released and dispersed between layers instead of being concentrated at a single interface, thereby reducing the accumulation of interface stress and avoiding the formation of cracks and the generation of dislocations. The interlayer distance of the multilayer composite layer can be adjusted by selecting different materials, growth conditions or applied stress. Different interlayer distances mean that the material can have a larger adaptation space when thermally expanding or contracting, which helps to release thermal stress caused by the mismatch of thermal expansion coefficients of different materials during temperature changes. Multilayer composite layers can absorb and transform the stress generated during the bonding process. When stress acts on the composite structure, some layers or interlayer interfaces in the multilayer composite layer can transform the lateral stress into interlayer slip or lattice changes. This transformation process can effectively relieve and absorb stress, prevent it from being transmitted to the interface or active layer, and maintain the electrical and mechanical properties of the material. At the same time, the multilayer composite layer can optimize stress release by adjusting the chemical bond properties between the layers.

[0044] In other optional embodiments, such as Figure 4 As shown, the semiconductor heterojunction composite substrate includes a plurality of first buffer layers 20 .

[0045] Specifically, there is a multi-layer first buffer layer 20 between the epitaxial layer 10 and the first substrate 30, especially the two-dimensional van der Waals material has interlayer slip, which can reduce the accumulation of interface stress, avoid the formation of cracks and the generation of dislocations, and help release the thermal stress caused by the mismatch of thermal expansion coefficients of different materials during temperature changes. When stress acts on the composite structure, some layers or interlayer interfaces in the multi-layer first buffer layer 20 can convert the lateral stress into interlayer slip or lattice changes, prevent it from being transmitted to the interface or active layer, and maintain the electrical and mechanical properties of the material. At the same time, the multi-layer first buffer layer 20 can optimize stress release by adjusting the chemical bond properties between the layers.

[0046] In some optional embodiments, the thickness of the first buffer layer is less than or equal to 0.5 μm.

[0047] Specifically, the epitaxial layer and the first substrate have different crystal forms and different doping concentrations. The greater the difference in doping concentration between the epitaxial layer and the first substrate, the greater the difference in lattice constants, and the greater the thickness of the first buffer layer should be. However, the maximum thickness of the first buffer layer shall not exceed 0.5µm to avoid affecting the electrical properties of the semiconductor heterojunction composite substrate.

[0048] Furthermore, the main function of the first buffer layer is to improve the electrical properties of the interface between the epitaxial layer and the first substrate, reduce the interface state density, and improve the carrier mobility. When the first buffer layer is too thick, it will introduce additional resistance, resulting in an increase in the series resistance of the entire structure, thereby affecting the conduction performance and switching speed of the device, increasing power loss, and reducing efficiency. The thickness of the first buffer layer is specifically thinner, less than 0.5µm, which can more flexibly adapt to the lattice mismatch and thermal expansion coefficient difference between the upper and lower materials while improving the conduction performance and switching speed of the device, thereby effectively releasing stress and reducing the generation of cracks or dislocations. In addition, a thinner first buffer layer will avoid introducing more defects at the interface, such as dangling bonds, impurities or impure phases, thereby reducing the interface state density, improving the purity of the interface, and thus improving the transmission efficiency of carriers near the interface. In terms of preparing the first buffer layer, a thinner buffer layer can ensure good interface bonding at a lower temperature, which can reduce the thermal budget range of the first substrate after the epitaxial layer, reduce the degradation of material properties, and even reduce the probability of damage.

[0049] According to another aspect of the present application, a method for preparing a semiconductor heterojunction composite substrate is provided, which is used to prepare any semiconductor heterojunction composite substrate, such as Figure 5 As shown, the preparation method comprises the following steps:

[0050] Step S401: providing an epitaxial layer, and forming a first buffer layer on one side of the epitaxial layer, wherein the material of the first buffer layer is a two-dimensional van der Waals material;

[0051] Step S402: providing a wafer, wherein the wafer and the epitaxial layer have different crystal forms, and performing modification treatment on a part of one side of the wafer so that the wafer forms a first film layer and a second film layer which are stacked, wherein the first film layer is a region of the wafer which has been modified, and the second film layer is a region of the wafer which has not been modified;

[0052] Step S403: bonding the first buffer layer on the epitaxial layer to the second film layer on the wafer to obtain a first composite structure;

[0053] Step S404: peeling the second film layer from the first composite structure, wherein the first film layer constitutes the first substrate.

[0054] By adopting the above-mentioned preparation method of the embodiment of the present application, a first buffer layer is formed on the epitaxial layer, and the material of the buffer layer is a two-dimensional van der Waals material. Since the two-dimensional van der Waals material has an adjustable band structure and extremely high carrier mobility, the atomic layers are connected by van der Waals forces without hanging bonds, and an atomic-level flat interface can be obtained. At the same time, the lattice constant mismatch and thermal expansion coefficient mismatch of the materials on both sides of the heterojunction can be solved by slipping between the material layers, and the interface stress release can be significantly improved. Combined with the extremely high carrier mobility between the layers, the on-resistance of the vertical structure power device manufactured using the heterojunction can be greatly reduced, and the performance of the power device can be improved. In addition, after the wafer is modified and bonded to the epitaxial layer, the wafer is directly peeled off under low temperature conditions, and the wafer portion is transferred to the epitaxial layer to form the first substrate, which can avoid directly epitaxy on the substrate to produce different crystal substrate film layers and produce various structural defects, overcome the lattice constant mismatch and insufficient processing accuracy in the heterojunction substrate, and obtain a high-quality semiconductor heterojunction composite substrate at the wafer level.

[0055] Among them, the above-mentioned preparation method can avoid various defects formed by directly epitaxially growing 3C crystals on 4H substrates, and at the same time, the thermal budget is small, and a wafer-level 3C / 4H heterojunction composite substrate can be obtained, which is suitable for large-scale industrial production. At the same time, considering the problem of processing accuracy, a first buffer layer is added to the 3C / 4H heterojunction composite substrate. The presence of the first buffer layer can significantly improve the tolerance of process errors, and solve the problems of stress and defects caused by the mismatch of lattice parameters and thermal expansion coefficients of the current heterojunction epitaxy. In addition, the first buffer layer can also increase the number of two-dimensional electron gas conductive channels, further improving the current handling capacity of the device. The composite substrate is compatible with existing process lines, and when using the composite substrate to manufacture devices, the existing process can be fully utilized, and the device development cost is low. In addition, the (3C / buffer layer) n / 4H-SiC heterojunction composite substrate structure is obtained by replacing the existing high-temperature chemical vapor deposition (1400~1650℃) with the peeling bonding low-temperature technology (less than 1000℃), which significantly reduces the thermal budget and improves the quality of the heterojunction. It solves the problems of polycrystallization and small size of heterojunction epitaxial materials encountered in the previous patents related to the high-temperature chemical vapor deposition technology, and can obtain a wafer-level (3C / buffer layer) n / 4H-SiC heterojunction composite structure. For high-temperature chemical vapor deposition, the 3C film in the obtained 3C / 4H heterojunction is usually polycrystalline and has a large number of defects, and it is impossible to obtain a material with uniform wafer-level size. Through the first buffer layer in the heterojunction structure, the problems of high stress and many defects caused by the lack of existing process processing capabilities can be overcome, the error tolerance of processing accuracy can be improved, and the quality and reliability of the heterojunction interface can be significantly improved.

[0056] The following is a more detailed description of exemplary embodiments of the method for preparing a trench power device provided by the present application. However, these exemplary embodiments can be implemented in a variety of different forms and should be interpreted as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0057] In some optional embodiments, the step of forming a first buffer layer on one side of the epitaxial layer includes: step S4011, covering the two-dimensional van der Waals material with a high molecular polymer to obtain a first composite layer; step S4012, covering the first composite layer on the epitaxial layer, wherein the two-dimensional van der Waals material is in contact with the epitaxial layer; step S4013, after the first composite layer and the epitaxial layer are bonded, the high molecular polymer is peeled off, and the remaining two-dimensional van der Waals material constitutes the first buffer layer.

[0058] Specifically, the material transfer technology requires a lower temperature, which can reduce the thermal budget, reduce the generation of thermal stress in the composite structure, and help improve the integrity of the composite substrate. The transfer of two-dimensional van der Waals materials through polymers avoids the difficulty of growing TMDs directly on the epitaxial layer, reduces the limitations of the surface quality of the epitaxial layer and the complexity of the growth conditions, and simplifies the process flow. The two-dimensional van der Waals material transfer technology using polymers can obtain a high-quality first substrate while avoiding the formation of DPB defects directly in the epitaxial process, thereby improving the performance and reliability of the device.

[0059] In some specific implementation methods, during the process of bonding the first composite layer to the epitaxial layer, pressure is applied to the epitaxial layer to reduce the gap between the two, increase the bonding strength between the two-dimensional van der Waals material and the epitaxial layer, and make the two-dimensional van der Waals film and the epitaxial layer more closely contacted, thereby reducing the interface stray and defects between the two and improving the carrier migration efficiency of the composite substrate.

[0060] Specifically, the pressure may be 0.1N~100kN, and the pressure may be maintained for 0.5~10min, which is not specifically limited in the present application.

[0061] Furthermore, by making the diameter of the first composite layer larger than the diameter of the epitaxial layer, a complete first buffer layer is formed on the entire epitaxial layer.

[0062] In some optional implementation methods, the polymer may include polydimethylsiloxane (PDMS for short). The method of transferring the two-dimensional van der Waals material to the epitaxial layer through PDMS specifically includes: first, using a polymer (such as PDMS) to cover the TMDs material for bonding; then, after the bonding is completed, the polymer is lifted up and covered on the treated epitaxial layer, wherein the diameter of the TMDs material is larger than the diameter of the epitaxial layer to ensure complete bonding; then, pressure is applied to increase the bonding strength between the TMDs material and the epitaxial layer, wherein the pressure is 0.1N~100kN, and the pressure is maintained for 0.5~10min; then, after the pressure is maintained, the polymer is peeled off to complete the transfer of the TMDs material to the epitaxial layer.

[0063] In some optional embodiments, the first buffer layer is a two-dimensional van der Waals material, preferably graphene or transition metal chalcogenides (TMDs). Exemplarily, when a transition metal chalcogenide material is used as a buffer layer, the crystal structure of the transition metal chalcogenide material should be a hexagonal symmetric or rhombohedral symmetric structure. The size of the first buffer layer should not be less than the size of the epitaxial layer. Depending on the doping type, doping concentration and peeling thickness of 3C-SiC and 4H-SiC, the first buffer layer can be a single buffer layer formed by a transition metal chalcogenide material or a composite buffer layer formed by two or more types of materials; the greater the difference between the doping concentrations of 4H-SiC and 3C-SiC, the greater the difference in lattice constants, and the greater the thickness of the composite buffer layer should be, but the maximum thickness of the composite buffer layer shall not exceed 0.5µm to avoid affecting the electrical properties of the composite substrate. The manufacture of a single-layer or multi-layer composite buffer layer based on a transition metal chalcogenide material uses a material transfer method or grows using metal organic compound vapor deposition (MPCVD). The material transfer method is preferred because the quality of wafer-scale TMD materials grown directly on 4H-SiC is currently poor.

[0064] In another example, when graphene is used as the first buffer layer, <0001> The epitaxial layer of the crystal orientation is annealed in an argon atmosphere, and a graphene buffer layer is directly formed by evaporating Si atoms on the surface of the epitaxial layer material. The argon pressure during annealing is 0.5~2bar, the annealing temperature is 1300~1600℃, and the annealing time is 1~60min. Since this method will undergo a high temperature process, the graphene buffer layer obtained by this method can only be used for the bottom layer of a single buffer layer or a multi-layer buffer layer, and the buffer layer above the graphene cannot withstand such a high temperature. The same method as steps S4011 to S4013 can be used to transfer the graphene material so that the graphene is formed on the side of the TMDs material away from the epitaxial layer.

[0065] In some optional implementation methods, the modification process includes an ion implantation process or a laser heating modification process.

[0066] Specifically, the wafer may include high quality <111> The crystal orientation of the 3C-SiC wafer, the C-Si diatomic layer of the wafer is arranged in ABC order. The wafer is subjected to ion implantation or laser heating modification treatment to generate microcracks to form a defect layer. At this time, under high vacuum conditions, the 3C-SiC wafer can be bonded with the first buffer layer, and the defect layer is used as a peeling interface to peel the 3C-SiC film layer from the original wafer, providing a microcrack path for subsequent peeling without damaging the wafer, so as to form a high-quality 3C-SiC film layer, which can reduce carrier scattering at the interface, improve carrier mobility, and directly improve the performance of the device.

[0067] In some optional embodiments, the surface of the 3C-SiC wafer is polished before the wafer is subjected to ion implantation or laser heating modification to planarize the processed surface.

[0068] Specifically, the flatness of the wafer surface directly affects the energy loss of the implanted particles and the uniformity of the implantation depth. A flat surface can ensure consistent implantation conditions in all areas, avoid ion beam deviation or divergence caused by surface undulations, and achieve more uniform and controllable implantation dose and depth. Ion implantation or laser heating modification will produce defects on the wafer surface. The density of surface defects is positively correlated with the surface roughness. Reducing the surface roughness by polishing can reduce the generation of these defects, improve the crystal quality of the 3C-SiC film after stripping, and reduce the instability of electrical properties. Moreover, whether it is ion implantation or laser heating, the purpose is to form microcracks inside the wafer to facilitate the subsequent stripping process. The flattened surface helps the microcracks to expand evenly along the expected depth, ensuring the controllability of the stripping process and the integrity of the stripped film, and avoiding the film from breaking or discontinuity during the stripping process.

[0069] Furthermore, ion implantation is the process of accelerating charged particles and injecting them below the surface of the material to change the chemical composition or introduce defects. After the ions are injected into the wafer, the wafer is heated to promote the expansion of microcracks. This process is usually carried out in an inert gas atmosphere, and the heating temperature and time need to be carefully designed to ensure that the microcracks can effectively extend while avoiding excessive damage to the wafer. Among them, the ion implantation depth is 50~3000nm, and the ion implantation depth is less than the thickness of the wafer, so that the wafer forms a modified first film layer and an unmodified second film layer. Through the precisely controlled ion implantation and stripping process, the DPB defects commonly seen in high-temperature growth of 3C-SiC are avoided, other types of defects caused by lattice mismatch, such as dislocations and stacking faults, are reduced, and the crystal quality of the thin film layer is significantly improved.

[0070] In addition, the wafer is subjected to laser heating modification treatment, and a high-energy laser is used to locally heat the 3C-SiC wafer. Through the energy and focus of the laser, the heat is concentrated at a predetermined depth of the wafer, usually between 50 and 3000 nm, to induce modification of the lattice structure without damaging the deeper parts of the wafer. During the laser heating process, the temperature of the wafer will increase significantly, resulting in enhanced atomic activity in the lattice and the formation of a defect layer. The laser heating modification stripping technology avoids thermal stress in the high-temperature chemical vapor deposition process through heat input, reduces the formation of defects such as DPB, significantly reduces the defect density of the stripped film, and improves the electrical properties of the material. The laser heating modification stripping technology can achieve wafer-level film preparation, ensuring the thickness uniformity and lattice consistency of the film material over a large size range.

[0071] In some optional embodiments, the step of bonding the first buffer layer on the epitaxial layer to the second film layer on the wafer includes: first, bonding the first buffer layer on the epitaxial layer to the second film layer on the wafer to obtain a preliminary composite structure; then, applying pressure to the epitaxial layer in the preliminary composite structure along a second direction, wherein the second direction is the direction from the epitaxial layer to the first buffer layer; then, performing a first annealing treatment on the preliminary composite structure to obtain a first composite structure.

[0072] Specifically, in the prior art, high-temperature chemical vapor deposition (preparation temperature is 1400~1650℃) is used to form the buffer layer and the first substrate. During the growth process, high-temperature chemical vapor deposition will produce crystal defects such as double positioning boundary (DPB) defects, dislocations and stacking faults due to excessive temperature, so that the buffer layer and the first substrate will have lattice mismatch and other problems due to thermodynamic instability during the growth process. The above-mentioned preparation method adopts a low-temperature (preparation temperature is less than 1000℃) bonding process to form a heterojunction composite substrate. Since the bonding process is carried out at low temperature, the effect of high temperature on thermal stress can be reduced, thereby reducing the generation of defects. Through the bonding process, an atomically flat interface can be achieved, the dangling bonds and stress at the interface are reduced, and the electrical properties of the interface are improved. This is in sharp contrast to the interface defects that are difficult to avoid in the direct epitaxial growth process. The bonding process is more conducive to the formation of high-quality heterojunctions. The bonding technology can prepare 3C-SiC films of wafer-level size, which is difficult to achieve in high-temperature epitaxial growth, especially when solving the lattice mismatch problem. The preparation of wafer-level materials is conducive to large-scale industrial production, reduces manufacturing costs, and improves the uniformity and consistency of devices. The bonding process is carried out at a lower temperature, which significantly reduces the thermal budget and avoids potential damage to materials and structures caused by high temperatures, which is crucial to maintaining the performance stability of materials and extending the life of devices. Since the bonding process can use thinner 3C-SiC wafers, the consumption of expensive silicon carbide materials is reduced, reducing manufacturing costs. At the same time, due to the simplification of the process flow and the reduction of the thermal budget, energy consumption and equipment investment are also reduced.

[0073] In some optional embodiments, before bonding the first buffer layer on the epitaxial layer and the second film layer on the wafer, chemical mechanical polishing is performed on the surfaces of the first buffer layer and the second film layer to be bonded.

[0074] Specifically, the surface roughness of the bonding surface may be less than 0.2 nm. As the roughness of the bonding surface decreases, the vacuum bonding strength increases. Setting the surface roughness to less than 0.2 nm is beneficial to improving the structural strength of the prepared composite substrate.

[0075] In some optional embodiments, the step of peeling off the second film layer includes: first, performing a second annealing treatment on the first composite structure to obtain a second composite structure; then, peeling off the second film layer from the second composite structure to obtain a third composite structure; then, performing a third annealing treatment on the third composite structure, wherein the second annealing treatment can accelerate the expansion of microcracks generated by the ion implantation layer or the laser heating layer, which is beneficial to peeling off the second film layer so that the second film layer constitutes the first substrate.

[0076] Specifically, the first composite structure is subjected to a second annealing treatment to accelerate the expansion of microcracks generated by the ion implantation layer or the laser heating layer. In the second annealing, the composite structure is heated to a higher temperature, which increases the thermal energy of the atoms inside the material. The increase in the thermal energy of the atoms increases their mobility and vibration amplitude, which makes it easier for the atoms at the edge of the microcracks to overcome the energy barrier, thereby promoting the forward expansion of the cracks. At high temperatures, the diffusion rate of atoms is accelerated, and they can move faster from the crack tip to form an extension of the crack. While ion implantation or laser heating forms microcracks in the wafer, local stress fields are also generated inside the material. And as the temperature increases, the elastic modulus and hardness of the material decrease, which helps to release the stress caused by lattice damage and lattice mismatch. The release of stress provides a freer environment for the expansion of microcracks, which can promote the uniform expansion of cracks from the damaged layer until the 3C-SiC film is completely penetrated, which helps to achieve the peeling of the film. During the second annealing process, the defects in the damaged layer (ion implantation damaged layer or laser heating modified layer) will further aggregate and degenerate, forming a crack path that is easier to expand. The degradation of the damaged layer reduces the local strength of the material, making it easier for microcracks to propagate along the damage path until they completely penetrate the film.

[0077] Further, the third composite structure is subjected to a third annealing treatment to repair the lattice damage of the film, wherein the heating provides sufficient energy so that the atoms in the damaged area can be rearranged and the lattice defects introduced by the stripping process can be repaired. This heat-activated repair mechanism allows defects such as dislocations, vacancies or dangling bonds to be eliminated or minimized by diffusion, recombination or other microscopic mechanisms during the annealing process. The stripping process generates stresses in the second film layer, which can cause lattice damage. During the annealing process at the third temperature, due to the thermal expansion of the material and the enhancement of atomic thermal motion, the stress is released, which helps to repair the lattice damage caused by stress. Stress release helps to restore the lattice structure and reduce the density of cracks and dislocations. Annealing allows defects inside the material to gather and eliminate, and the repair of lattice damage directly improves the electrical properties of the material. The resistance to carrier migration in a material with a complete lattice and no high-density defects is small, and the mobility is higher, which helps to reduce the on-state resistance of the device, reduce switching losses, and improve the frequency response characteristics of the power device.

[0078] In some specific embodiments, the third annealing process is performed in a hydrogen atmosphere.

[0079] Specifically, hydrogen molecules can diffuse into damaged areas of the material and react chemically with dangling bonds or defects. Hydrogen combines with carbon or silicon atoms in silicon carbide materials to form hydrides, which are unstable at high temperatures and will decompose or rearrange, helping to repair lattice damage and reduce dangling bonds, thereby reducing interface state density and improving carrier mobility. At the same time, annealing is carried out in a hydrogen atmosphere, which not only promotes the repair of lattice damage, but also prevents oxidation of the material at high temperatures. The protective atmosphere ensures the chemical stability of the material during the repair process and avoids additional damage caused by high-temperature oxidation.

[0080] In some optional embodiments, the temperature of the first annealing treatment is less than or equal to the temperature of the second annealing treatment, and the temperature of the second annealing treatment is less than or equal to the temperature of the third annealing treatment.

[0081] Specifically, the temperature of the first annealing treatment can be 300-600°C, the temperature of the second annealing treatment can be 600-800°C, and the temperature of the third annealing treatment can be 800-1000°C. The temperature of the first annealing treatment is less than or equal to the temperature of the second annealing treatment, wherein the lower first annealing temperature helps to reduce the thermal damage introduced during the bonding process. Although high temperature annealing can effectively release stress, it will also accelerate atomic diffusion and phase change, resulting in an increase in interface damage at the lattice mismatch. By performing the first annealing at a lower temperature, the initial damage can be minimized and the structural stability and electrical properties of the material can be maintained. Due to the low temperature of the first annealing, while optimizing the interfacial bonding between the 3C-SiC film and the buffer layer, it will not cause significant changes in the internal structure of the material. This ensures that the chemical bonding of the interface is carried out under mild conditions, reduces the interfacial reaction or phase change caused by high temperature, and maintains the purity and stability of the interface. The lower first annealing temperature provides the material with an appropriate pretreatment state, enabling it to expand microcracks more effectively and controllably in the subsequent second annealing. This is equivalent to providing a more stable and prestress-releasing starting point for the subsequent stripping process, which helps to ensure the uniformity and controllability of the stripping process. By setting the first annealing temperature in a lower range, the physical and chemical properties of the material can be protected from the effects of the high-temperature annealing process. For example, buffer layer materials such as graphene are sensitive to high temperatures, and a lower first annealing temperature can avoid adverse effects on the properties of these materials and maintain their high carrier mobility and low defect density.

[0082] Further, the temperature of the second annealing treatment can be less than or equal to the temperature of the third annealing treatment. The second annealing is performed at a relatively low temperature, mainly to accelerate and control the extension of microcracks generated in the ion implantation layer or the laser heating layer. The temperature range of 600~800°C provides sufficient thermal energy to promote the extension of microcracks from the damaged layer to the surface, but avoids excessively high temperatures that cause uncontrollable crack extension or cause unnecessary phase changes in the material. Annealing in this temperature range helps to ensure that the 3C~SiC film is uniformly and completely peeled off from the original substrate. During the second annealing process, the thermal motion inside the material increases, which helps to preliminarily repair the lattice damage generated during the peeling process, such as microcracks, dislocations, etc. Although more thorough repair is performed in the third annealing, the preliminary repair at the second annealing temperature helps to improve the initial state of the material and reduce the degree of damage that needs to be treated in the subsequent high-temperature annealing. The high-temperature treatment of the second annealing before peeling helps to release the interfacial stress accumulated during the bonding process and reduce the additional damage caused by uneven stress during the peeling process. By annealing at the second temperature, the stress distribution inside the material can be managed to ensure that the peeling process is smoother and more controllable. In the third annealing treatment, the material is placed in a hydrogen atmosphere and heated to 800-1000°C. This higher temperature range, combined with the hydrogen chemical reaction, deeply repairs the lattice damage inside the 3C-SiC film after peeling. The presence of hydrogen can react with the dangling bonds in the damaged area to form stable hydrides, which helps to eliminate these dangling bonds, further reduce the interface state density, and increase carrier mobility. By keeping the second annealing temperature lower than the third annealing temperature, it can ensure that the material is in a purer and more stable state during the third annealing, which is conducive to further optimizing the electrical properties of the material, improving carrier mobility, reducing the on-state resistance and switching loss of the device, and enhancing the stability of the composite substrate structure.

[0083] Among them, the first annealing treatment time, the second annealing treatment time and the third annealing treatment time are all 1 to 120 minutes, and the specific annealing time is not specifically limited in this application.

[0084] This embodiment relates to a specific method for preparing a semiconductor heterojunction composite substrate. Figure 6 As shown, the following steps are included:

[0085] Step S1: Provide N-type or P-type doped <111> Oriented 3C-SiC wafers and <0001> 4H-SiC epitaxial material with a crystal orientation or off-axis angle less than or equal to 4°;

[0086] Step S2: injecting hydrogen ions and / or helium ions into the 3C-SiC wafer to a preset depth, or using a laser to heat the material at a predetermined depth to form a defect layer;

[0087] Step S3: chemically mechanically polishing, cleaning and plasma treating the 4H-SiC epitaxial layer obtained in step S1, transferring a single layer or a composite buffer layer composed of a two-dimensional van der Waals material onto the 4H-SiC conventional epitaxial material in step S1 by using a material transfer technique, or directly growing a TMDs material on the 4H-SiC epitaxial layer by using an MOCVD method;

[0088] Step S4: chemically mechanically polishing, cleaning and plasma treating the unbonded side of the 3C-SiC wafer, applying pressure under vacuum conditions and performing a first annealing treatment to bond with the upper surface of the first buffer layer to form a 3C-SiC / buffer layer / 4H-SiC epitaxial layer bonded wafer;

[0089] Step S5: After performing a second annealing treatment on the 3C-SiC / buffer layer / 4H-SiC epitaxial layer bonded wafer, the 3C-SiC film is peeled off to obtain a composite substrate.

[0090] In step S1 of the above embodiment, the <111> Orient the 3C-SiC wafer and transfer it to <0001> The axial 4H-SiC epitaxial layer can avoid various structural defects caused by direct epitaxy on the substrate. Among them, due to the limitations of the silicon carbide cutting process, the orientation of the 3C-SiC wafer is <111> There will be a certain deviation in direction, but the deviation cannot exceed 1°.

[0091] In step S2 of the above embodiment, atoms will generate microcrack defects after being heated, and the defects will expand during the heating process, wherein the depth of the defect layer is less than the depth of the wafer, and the defect layer is used as a peeling interface to peel the 3C-SiC thin film layer from the original wafer, thereby providing a microcrack path for subsequent peeling without damaging the wafer, so as to form a high-quality 3C-SiC film layer, which can reduce carrier scattering at the interface, improve carrier mobility, and directly improve device performance.

[0092] In addition, before injecting hydrogen ions and / or helium ions into the 3C-SiC wafer or laser heating modification, the implanted surface of the 3C-SiC wafer is polished for flattening, and then hydrogen ions and / or helium ions are injected into the 3C-SiC wafer to form an implanted defect layer and generate microcracks. The ion implantation depth is 50 to 3000 nm, and the ion implantation depth is set to be less than the thickness of the 3C-SiC wafer, or the laser is used to heat the material at a specific depth to generate microcracks to form a defect layer, and the laser heating depth is less than the thickness of the 3C-SiC wafer.

[0093] In step S3 of the above embodiment, the plasma includes one or more of nitrogen, oxygen, and helium, and the vacuum degree of the vacuum treatment is 1×10-7 ~1×10 -8 mbar, the specific plasma and vacuum degree are not limited in this application. Common wafer-level high-quality TMDs materials are grown on substrate materials such as Cu, Ni, Pt, Au, Si, SiO2, etc., wherein the specific steps of transferring the TMDs material to the 4H-SiC epitaxial layer may include:

[0094] First, a high molecular weight polymer such as PDMS is used to cover the TMDs material;

[0095] Then, after the bonding is completed, the polymer is lifted up and covered on the treated 4H-SiC substrate, wherein the diameter of the TMDs material is larger than the diameter of the 4H-SiC substrate to ensure complete bonding;

[0096] Then, pressure is applied to increase the bonding strength between the TMDs material and the 4H-SiC substrate, the pressure is 0.1N~100kN, and the holding time is 0.5~10min;

[0097] Finally, after the pressure holding is completed, the high molecular polymer is peeled off, and the TMDs material is transferred to the 4H-SiC epitaxial layer.

[0098] If graphene is used as the material of the first buffer layer, <0001> The 4H-SiC off-axis epitaxial material with different crystal orientations is annealed in an argon atmosphere to directly form a graphene buffer layer by evaporating Si atoms on the SiC surface. The argon pressure during annealing is 0.5~2 bar and the annealing temperature is 1300~1600℃. The transition layer process manufactured by this method is simpler than the material transfer technology.

[0099] In step S4 of the above embodiment, applying pressure during the bonding process can reduce the distance between the interfaces of the bonding materials, increase the temperature to increase the energy of the atoms, promote the formation of chemical bonds at the interface of the first buffer layer, and ensure the bonding strength of the bonding surface, wherein no dangling bonds are formed between the chemical bonds at the interface of the first buffer layer and the TMDs material. In the first buffer layer structure, the upper and lower surfaces of the transition layer need to form chemical bonds with 3C-SiC and 4H-SiC respectively, and there are no chemical bonds between the TMDs layers inside the first buffer layer that can be used to release stress.

[0100] In step S5 of the above embodiment, the second annealing is to promote the expansion of microcracks obtained by ion implantation or laser heating to facilitate subsequent stripping. After stripping, a third annealing is performed in a hydrogen atmosphere.

[0101] In some specific embodiments, steps S3 to S5 may be repeated multiple times to obtain a (3C / buffer layer)n / 4H structure (n=1, 2, 3...). The thickness and period n of the buffer layer sublayers may be determined according to the process processing accuracy and the design parameters such as the doping concentration and thickness of the material. The thickness of the buffer layer sublayers may be made uniform, or may be increased or decreased to obtain a gradient buffer layer.

[0102] Specifically, each bonding surface of the heterojunction is subjected to chemical mechanical polishing through steps S3 and S4, and vacuum bonding is performed after plasma treatment to form a bonded wafer. Through step S5, the composite wafer is placed in an atmosphere of an inert gas such as nitrogen, and a certain pressure is applied. The bonded wafer is annealed at a first temperature to improve the interface bonding strength of the buffer layer. After the annealing is completed, the pressure is unloaded, and a second annealing is performed at a second temperature. This annealing is to accelerate the expansion of microcracks generated by the ion implantation layer or the laser heating layer, so as to peel off the remaining 3C substrate to obtain a 3C-SiC film, and the surface of the composite substrate is ground and polished to remove the surface lattice damage layer. Thereafter, annealing is performed again in a hydrogen atmosphere at a third temperature to repair the lattice damage of the film. The temperature of the third annealing is 600~900°C. Thus, the following is obtained: Figure 1 The semiconductor heterojunction composite substrate structure shown.

[0103] Specifically, the first annealing temperature may be 300-600°C, and the pressure applied during annealing may be 0.1-100 kN. The second annealing temperature may be 600-800°C, and the third annealing temperature may be 800-1000°C. No pressure is applied during the second and third annealings, and the three annealing treatment times are all 1-120 min.

[0104] In addition, after the chemical mechanical polishing treatment in steps S3 and S4 in the above embodiment, the surface roughness of the bonding surface can be less than 0.2 nm. As the surface roughness decreases, the vacuum bonding strength increases. Setting the surface roughness to less than 0.2 nm is conducive to improving the structural strength of the prepared composite substrate.

[0105] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0106] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A semiconductor heterojunction composite substrate, characterized in that: include: Epitaxial layer; A first buffer layer, located on one side of the epitaxial layer, wherein the material of the first buffer layer comprises a two-dimensional van der Waals material; The first substrate is located on a side of the first buffer layer away from the epitaxial layer, wherein the first substrate and the epitaxial layer have different crystal types.

2. The semiconductor heterojunction composite substrate according to claim 1, characterized in that: The two-dimensional van der Waals material includes graphene and / or transition metal chalcogenides.

3. The semiconductor heterojunction composite substrate according to claim 1, characterized in that: The first buffer layer and the first substrate form a composite layer, and the semiconductor heterojunction composite substrate includes a plurality of the composite layers.

4. The semiconductor heterojunction composite substrate according to claim 1, characterized in that: The thickness of the first buffer layer is less than or equal to 0.5 μm.

5. A method for preparing a semiconductor heterojunction composite substrate, characterized in that: For preparing the semiconductor heterojunction composite substrate according to any one of claims 1 to 4, the preparation method comprises the following steps: Providing an epitaxial layer, and forming a first buffer layer on one side of the epitaxial layer, wherein the material of the first buffer layer is a two-dimensional van der Waals material; Providing a wafer, wherein the wafer and the epitaxial layer have different crystal forms, and performing a modification treatment on a partial area on one side of the wafer so that the wafer forms a first film layer and a second film layer which are stacked, wherein the first film layer is the area of ​​the wafer which has undergone the modification treatment, and the second film layer is the area of ​​the wafer which has not undergone the modification treatment; Bonding the first buffer layer on the epitaxial layer to the second film layer on the wafer to obtain a first composite structure; The first film layer is peeled off from the first composite structure, wherein the second film layer constitutes a first substrate.

6. The preparation method according to claim 5, characterized in that: The step of forming the first buffer layer on one side of the epitaxial layer comprises: Covering the two-dimensional van der Waals material with a high molecular weight polymer to obtain a first composite layer; Covering the first composite layer on the epitaxial layer, wherein the two-dimensional van der Waals material is in contact with the epitaxial layer; After the first composite layer and the epitaxial layer are bonded together, the high molecular polymer is peeled off, and the remaining two-dimensional van der Waals material constitutes the first buffer layer.

7. The preparation method according to claim 5, characterized in that: The modification process includes ion implantation or laser heating modification.

8. The preparation method according to claim 5, characterized in that: The step of bonding the first buffer layer on the epitaxial layer to the second film layer on the wafer comprises: Laminating the first buffer layer on the epitaxial layer and the second film layer on the wafer to obtain a preliminary composite structure; Applying pressure to the epitaxial layer in the prepared composite structure along a second direction, wherein the second direction is a direction from the epitaxial layer to the first buffer layer; The preliminary composite structure is subjected to a first annealing treatment to obtain the first composite structure.

9. The preparation method according to claim 8, characterized in that: The step of peeling off the second film layer comprises: performing a second annealing treatment on the first composite structure to obtain a second composite structure; peeling the second film layer from the second composite structure to obtain a third composite structure; A third annealing treatment is performed on the third composite structure, wherein the second film layer constitutes a first substrate.

10. The preparation method according to claim 9, characterized in that: The temperature of the first annealing treatment is less than or equal to the temperature of the second annealing treatment, and the temperature of the second annealing treatment is less than or equal to the temperature of the third annealing treatment.

Images