Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device, the array substrate comprises a plurality of electrodes, each electrode comprises a frame body part, and a plurality of domain regions are arranged in a region enclosed by the frame body part; the plurality of branch parts are positioned in the plurality of domain areas and are connected with the frame body part; in the same domain region, the slit between the adjacent branch parts comprises an arc-shaped corner; and at least part of the branch parts of at least one domain region are mutually disconnected on one side close to the adjacent domain region.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small size, low power consumption, high image quality, no radiation and easy to carry. It has been rapidly developed in recent years and has gradually replaced the traditional cathode ray tube display (CRT) and has occupied a dominant position in the current flat panel display market. At present, TFT-LCD has been widely used in various large, medium and small sized products, covering almost all major electronic products in today's information society, such as LCD TV, high-definition digital TV, computer (desktop and notebook), mobile phone, tablet computer, navigation system, car display, projection display, video camera, digital camera, electronic watch, calculator, electronic instrument, meter, public display and virtual display, etc. Summary of the invention

[0003] Embodiments of the present disclosure provide an array substrate, a display panel, and a display device for improving transmittance.

[0004] Therefore, an array substrate provided in an embodiment of the present disclosure includes a plurality of electrodes, wherein the electrodes include:

[0005] A frame portion, wherein the frame portion has a plurality of domains in an area enclosed by the frame portion;

[0006] A plurality of branch portions are provided, wherein the plurality of branch portions are located in the plurality of domains and connected to the frame portion; within the same domain, the slits between adjacent branch portions include arc-shaped corners; and at least part of the branch portions of at least one domain are disconnected from each other on a side close to the adjacent domain.

[0007] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, the slit further includes a middle portion having an acute angle, and the arc-shaped corner is arranged at the periphery of the acute angle of the middle portion.

[0008] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, the size of the arc-shaped corner in the vertical direction of a single side of the acute angle is 0.5 μm to 3 μm.

[0009] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the spacing between adjacent branch portions is a first size, the arc-shaped corner has a second size in the single-side extension direction of the acute angle, and the ratio of the second size to the first size is 1:2 to 3:4.

[0010] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, on the side where the single side of the acute angle is located, the arc corner extends away from the single side of the acute angle along a first direction, and the angle between the first direction and the single side of the acute angle is 25° to 65°.

[0011] In some embodiments, the above-mentioned array substrate provided by the embodiments of the present disclosure further includes scan lines extending along the row direction and data lines extending along the column direction, and a plurality of the domain regions are arranged along the extension direction of the data lines; in at least one of the first and last domain regions, at least part of the branch portions are disconnected from each other on the side close to the adjacent domain region; and / or, in at least one of the remaining domain regions other than the first and last domain regions, at least part of the branch portions are disconnected from each other on the side close to the adjacent domain region.

[0012] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, the branch portions that are disconnected from each other on a side close to the adjacent domain area are symmetrical with respect to the extending direction of the scan line.

[0013] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the multiple domain regions include a first domain region, a second domain region, a third domain region and a fourth domain region arranged along the extension direction of the data line, wherein at least part of the branch portions in the first domain region are disconnected from each other on a side close to the second domain region, and at least part of the branch portions in the fourth domain region are disconnected from each other on a side close to the third domain region.

[0014] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the multiple domain regions include a first domain region, a second domain region, a third domain region and a fourth domain region arranged along the extension direction of the data line, wherein at least part of the branch portions in the second domain region are disconnected from each other on a side close to the first domain region, and at least part of the branch portions in the third domain region are disconnected from each other on a side close to the fourth domain region.

[0015] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, in at least part of any one of the two adjacent domains, at least part of the branches are disconnected from each other on a side close to the adjacent domain.

[0016] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the multiple domain regions include a first domain region, a second domain region, a third domain region and a fourth domain region arranged along the extension direction of the data line, wherein at least part of the branch portions in the first domain region are disconnected from each other on a side close to the second domain region, and at least part of the branch portions in the second domain region are disconnected from each other on a side close to the first domain region.

[0017] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the multiple domain regions include a first domain region, a second domain region, a third domain region and a fourth domain region arranged along the extension direction of the data line, wherein at least part of the branches in the third domain region are disconnected from each other on a side close to the fourth domain region, and at least part of the branches in the fourth domain region are disconnected from each other on a side close to the third domain region.

[0018] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a connecting portion between the second domain region and the third domain region, and the branch portion in the second domain region and the branch portion in the third domain region are respectively connected to the connecting portion.

[0019] Based on the same inventive concept, an embodiment of the present disclosure provides a display panel, including the above-mentioned array substrate provided by an embodiment of the present disclosure.

[0020] In some embodiments, the display panel provided in the embodiments of the present disclosure further includes an opposing substrate disposed opposite to the array substrate, wherein the opposing substrate includes a common electrode.

[0021] Based on the same inventive concept, an embodiment of the present disclosure provides a display device, including the above-mentioned display panel provided by an embodiment of the present disclosure.

[0022] The beneficial effects of the present disclosure are as follows:

[0023] The array substrate, display panel and display device provided by the embodiments of the present disclosure include a plurality of electrodes, wherein the electrodes include a frame body and a plurality of branch parts, wherein the frame body has a plurality of domains in the area enclosed, and the plurality of branch parts are located in the plurality of domains and connected to the frame body; in the same domain, the slits between adjacent branch parts include arc-shaped corners; at least some of the branch parts of at least one domain are disconnected from each other on the side close to the adjacent domain. On the one hand, by setting the slits between adjacent branch parts to include arc-shaped corners, the transition of liquid crystal orientation at the position of the arc-shaped corner can be relatively smoother, the area of ​​disordered liquid crystal orientation is relatively small, and the transmittance is higher; on the other hand, by setting at least some of the branch parts in at least one domain to be disconnected from each other on the side close to the adjacent domain, the orientation of the liquid crystal at the disconnected position can be controlled by the direction of the slits between the branch parts and relatively orderly, and the disordered liquid crystal (dark lines are formed at the disordered position of the liquid crystal deflection) is basically controlled at the edge of the adjacent domain, so that the transition of liquid crystal orientation between domains is relatively smoother, the area of ​​disordered liquid crystal orientation is relatively small, and the transmittance is higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of the structure of an electrode in the related art;

[0025] Figure 2 for Figure 1 Schematic diagram of dark patterns in the electrode area shown;

[0026] Figure 3 for Figure 1 A simulation of dark patterns in the electrode area shown;

[0027] Figure 4 A schematic diagram of the structure of an array substrate provided in an embodiment of the present disclosure;

[0028] Figure 5 A schematic diagram of the structure of an electrode provided in an embodiment of the present disclosure;

[0029] Figure 6 for Figure 5 A magnified structural diagram of the middle Z1 region;

[0030] Figure 7 for Figure 6 A magnified structural diagram of the middle Z2 region;

[0031] Figure 8 A schematic diagram of another structure of an electrode provided in an embodiment of the present disclosure;

[0032] Fig. 9 A schematic diagram of another structure of an electrode provided in an embodiment of the present disclosure;

[0033] Fig.10 A schematic diagram of another structure of an electrode provided in an embodiment of the present disclosure;

[0034] Fig.11 A schematic diagram of another structure of an electrode provided in an embodiment of the present disclosure;

[0035] Fig.12 A schematic diagram of another structure of an electrode provided in an embodiment of the present disclosure;

[0036] Fig.13 for Fig.11 A simulation of dark patterns in the electrode area shown;

[0037] Fig.14 for Fig.12 A simulation of dark patterns in the electrode area shown;

[0038] Fig.15 A schematic diagram of the structure of a sub-pixel region provided in an embodiment of the present disclosure;

[0039] Fig.16 For along Fig.15 Cross-section along line I-II;

[0040] Fig.17 for Fig.15 The structural diagram of the layer where the middle scan line is located;

[0041] Fig.18 for Fig.15 Schematic diagram of the structure of the active layer;

[0042] Fig.19 for Fig.15 The structural diagram of the layer where the data line is located;

[0043] Fig. 20 for Fig.15 A schematic diagram of the structure of the first insulating layer, the layer where the color resist is located, and the second insulating layer;

[0044] Fig.21 for Fig.15 Schematic diagram of the structure of the layer where the middle electrode is located;

[0045] Fig. 22 A schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure;

[0046] Fig.23 A schematic diagram of the structure of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the embodiment of the present disclosure clearer, the technical solution of the embodiment of the present disclosure will be clearly and completely described in conjunction with the drawings of the embodiment of the present disclosure. It should be noted that in the drawings, the thickness of the layer, film, panel, area, etc. is magnified for clarity. In the present disclosure, exemplary embodiments are described with reference to cross-sectional views of schematic diagrams of idealized embodiments. In this way, deviations from the shape of the figure as a result of, for example, manufacturing technology and / or tolerances will be expected. Therefore, the embodiments described in the present disclosure should not be interpreted as being limited to the specific shape of the area shown in the present disclosure, but include deviations in shape caused by, for example, manufacturing. For example, an area illustrated or described as flat may typically have rough and / or nonlinear features; the illustrated sharp corners may be rounded, etc. Therefore, the areas shown in the figures are schematic in nature, and their sizes and shapes are not intended to illustrate the exact shape of the area, do not reflect the true proportion, and the purpose is only to illustrate the content of the present disclosure. And the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0048] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" and the like mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0049] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer may be directly on, directly connected to, or there may be an intermediate element or intermediate layer. When an element or layer is referred to as being "disposed on one side of" another element or layer, the element or layer may be directly on one side of, directly connected to, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0050] In the related art, liquid crystal display panels can be divided into vertical alignment (VA), twisted nematic (TN) or super twisted nematic (STN), in-plane switching (IPS), and fringe field switching (FFS). In the production process of liquid crystal display panels, alignment of the alignment layer is an important process, and the alignment process is used to realize the arrangement of liquid crystal molecules in a specific direction and angle. The traditional alignment process uses the rubbing method, which can only be aligned in one horizontal direction and is widely used by TN and IPS type liquid crystal display panels. The mainstream of optical alignment of VA type liquid crystal display panels is to apply an electric field to the liquid crystal display panel and use ultraviolet curing (UV curing) to make the liquid crystal molecules tilt in the expected direction. However, the VA type liquid crystal display panel needs to expand the viewing angle and divide the sub-pixels into multiple regions. The alignment direction in each region is different. Therefore, the rubbing method is usually not used, but the optical alignment method is used.

[0051] UV2A (UV VA) technology is a technology that uses ultraviolet light (UV) to align VA-type liquid crystal display panels. Its name comes from the multiplication of ultraviolet light UV and the VA mode of the liquid crystal display panel. The key is to use special polymer materials as the alignment layer to control the liquid crystal molecules to tilt along the ultraviolet direction with high precision, and its precision unit is picometer. The use of UV2A technology can eliminate the slits and protrusions currently used to control the alignment of liquid crystal molecules in VA-mode liquid crystal display panels, so the aperture ratio, contrast and response speed of the liquid crystal display panel can be improved, and the production process can be greatly reduced.

[0052] UV2A technology can achieve a state where all liquid crystal molecules are tilted in the designed direction through the alignment layer, so when the electric field is applied, the liquid crystal molecules tilt in the same direction at the same time. Since it can be divided into multiple areas without using protrusions and slits, the aperture ratio is increased by more than 20% compared with the original panel divided into multiple areas using protrusions. The backlight brightness is very small to obtain the same brightness as before, and reducing power consumption and reducing the number of backlight light sources are conducive to energy saving and cost saving.

[0053] Compared with UV2A technology, its upgraded version, SUVA (ultra-fine photo alignment) process, can further improve the light transmittance of the liquid crystal display panel and has better response time performance and color shift characteristics. When using SUVA technology, adjacent domains with different intra-domain slit extension directions (for example, in adjacent domains, one domain is provided with an intra-domain slit extending in a 45° direction, and the other domain is provided with an intra-domain slit extending in a 135° direction) will form dark lines between the adjacent domains due to the disordered orientation of liquid crystal molecules, thereby affecting the transmittance of the liquid crystal display panel.

[0054] For example Figure 1 The electrode shown includes a first domain region D1, a second domain region D2, a third domain region D3 and a fourth domain region D4 arranged in a longitudinal direction; wherein, the intra-domain slit of the first domain region D1 extends along a -45° direction, the intra-domain slit of the second domain region D2 extends along a -135° direction, the intra-domain slit of the third domain region D3 extends along a 135° direction, and the intra-domain slit of the fourth domain region D4 extends along a 45° direction. Figure 2 Shows Figure 1 Schematic diagram of the dark pattern in the electrode area shown, Figure 2 It can be seen that the liquid crystal molecules in the first domain D1 point to -45°, the liquid crystal molecules in the second domain D2 point to -135°, the liquid crystal molecules in the third domain D3 point to 135°, and the liquid crystal molecules in the fourth domain D4 point to 45°; however, between the first domain D1 and the second domain D2, between the second domain D2 and the third domain D3, and between the third domain D3 and the fourth domain D4, the disordered pointing of the liquid crystal molecules will lead to the generation of dark lines DS. Figure 3 for Figure 1 The dark pattern simulation in the electrode area is shown by Figure 3 It can be seen that obvious dark lines appear between the first domain area D1 and the second domain area D2, between the second domain area D2 and the third domain area D3, and between the third domain area D3 and the fourth domain area D4.

[0055] In order to improve the above technical problems existing in the related art, the present disclosure provides an array substrate, such as Figure 4 As shown, it includes a plurality of electrodes 101. Optionally, the electrodes 101 are pixel electrodes or common electrodes. The present disclosure is described by taking the electrode 101 as a pixel electrode as an example. In some embodiments, Figure 5 and Figure 6 As shown, the electrode 101 may include:

[0056] A frame portion 1011, wherein the frame portion 1011 has a plurality of domains (eg, a first domain D1, a second domain D2, a third domain D3, and a fourth domain D4);

[0057] Multiple branch portions 1012, multiple branch portions 1012 are located in multiple domains (for example, the first domain D1, the second domain D2, the third domain D3 and the fourth domain D4) and are connected to the frame portion 1011, for example, the branch portions 1012 are integrally arranged with the frame portion 1011; in the same domain (for example, the first domain D1, the second domain D2, the third domain D3 or the fourth domain D4), the slit S between adjacent branch portions 1012 includes an arc-shaped corner S1; at least part of the branch portions 1012 of at least one domain (for example, the first domain D1 or the fourth domain D4) are disconnected from each other on the side close to the adjacent domain (for example, the second domain D2 or the third domain D3).

[0058] In the above-mentioned array substrate provided in the embodiment of the present disclosure, by setting the slit S between adjacent branch portions 1012 to include an arc-shaped corner S1, the liquid crystal pointing transition at the position of the arc-shaped corner S1 can be relatively smoother, the area of ​​disordered liquid crystal pointing is relatively small, and the transmittance is higher; on the other hand, by setting at least part of the branches 1012 in at least one domain area (for example, the first domain area D1 or the fourth domain area D4) to be disconnected from each other on the side close to the adjacent domain area (for example, the second domain area D2 or the third domain area D3), the liquid crystal pointing at the disconnected position can be controlled by the direction of the slit between the branches 22 and relatively orderly, and the disordered liquid crystal (dark lines are formed at the disordered position of the liquid crystal deflection) is basically controlled at the edge of the adjacent domain area (for example, the second domain area D2 or the third domain area D3). In this way, the liquid crystal pointing transition between the domain areas (for example, the first domain area D1 and the second domain area D2, or the third domain area D3 and the fourth domain area D4) is relatively smoother, the area of ​​disordered liquid crystal pointing is relatively small, and the transmittance is higher.

[0059] In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, if Figure 6 and Figure 7 As shown, the slit S also includes a middle portion S2 having an acute angle β, and an arc-shaped corner S1 is provided around the acute angle β of the middle portion S2. In the case where the slit S only includes the middle portion S2, the liquid crystal orientation changes greatly at the acute angle β of the middle portion S2. For example, the liquid crystal orientations on the two sides of the acute angle β may differ by the degree of the acute angle β. The present disclosure provides an arc-shaped corner S1 around the acute angle β of the middle portion S2, and the arc-shaped corner S1 can be used to compensate for the acute angle β, so that the liquid crystal orientation transition is relatively smoother, thereby helping to reduce the area of ​​disordered liquid crystal orientation and effectively improve the transmittance.

[0060] In some embodiments, in order to make the transition of liquid crystal orientation relatively smoother, so as to better reduce the disordered area of ​​liquid crystal orientation and improve the transmittance, as shown in FIG. Figure 7 As shown, the size of the arc corner S1 in the vertical direction of the acute angle β can be set to 0.5 μm to 3 μm; specifically, Figure 7 A represents the size of the arc corner S1 in the direction perpendicular to the horizontal side of the acute angle β, and B represents the size of the arc corner S1 in the direction perpendicular to the hypotenuse of the acute angle β. Optionally, the size A and the size B may be 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, etc. In some embodiments, the size A and the size B may be equal or unequal, which is not limited here.

[0061] In some embodiments, Figure 7 As shown, the spacing between adjacent branches 1012 is a first dimension C, and the arc-shaped corner S1 has a second dimension in the single-side extension direction of the acute angle β, for example Figure 7 D represents the second dimension of the arc corner S1 in the extension direction of the horizontal side of the acute angle β, and E represents the second dimension of the arc corner S1 in the extension direction of the hypotenuse of the acute angle β. In order to make the liquid crystal pointing transition relatively smoother, to better reduce the liquid crystal pointing disorder area and improve the transmittance, the ratio of the second dimension to the first dimension C can be set to 1:2 to 3:4, such as 1:2, 3:5, 3:4, etc. In some embodiments, the dimension D and the dimension E can be equal or unequal, which is not limited here.

[0062] In some embodiments, in order to make the transition of liquid crystal orientation relatively smoother, so as to better reduce the disordered area of ​​liquid crystal orientation and improve the transmittance, the arc corner S1 can be arranged on the side where the single side of the acute angle β is located, and extends away from the single side of the acute angle β along the first direction, and the angle between the first direction and the single side of the acute angle β is 25° to 65°, for example, 25°, 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, etc. Exemplarily, Figure 7 It is shown that on the side where the horizontal side of the acute angle β is located, the arc corner S1 extends along the first direction that forms an angle α with the horizontal side of the acute angle β; on the side where the hypotenuse of the acute angle β is located, the arc corner S1 extends along the first direction that forms an angle γ with the hypotenuse of the acute angle β. Optionally, the angle α and the angle γ are 25° to 65° respectively, and the angle α and the angle γ may be equal or unequal, which is not limited here. In some embodiments, the angle α and the angle γ may be set to be consistent with the liquid crystal deflection direction (for example, 45°).

[0063] In some embodiments, Figure 4 , Figure 5 and Figure 8As shown, the array substrate provided by the embodiment of the present disclosure further includes a scan line GL extending along the row direction X and a data line DL extending along the column direction Y. The multiple domains (e.g., the first domain D1, the second domain D2, the third domain D3, and the fourth domain D4) within the area enclosed by the frame portion 1011 can be arranged along the extension direction of the data line DL (i.e., the column direction Y); the present disclosure can be arranged in at least one of the first and last domains (e.g., the first domain D1 and the fourth domain D4), and at least part of the branch portions 1012 are disconnected from each other on the side close to the adjacent domains (e.g., the second domain D2 and the third domain D3); and / or, in at least one of the remaining domains (e.g., the second domain D2 and the third domain D3) other than the first and the last, at least part of the branch portions 1012 are disconnected from each other on the side close to the adjacent domains (e.g., the first domain D1 and the fourth domain D4).

[0064] Optionally, the present disclosure may be arranged such that the branches 1012 that are disconnected from each other on one side close to the adjacent domain area may be symmetrical with respect to the extending direction of the scan line GL (ie, the row direction X). Figure 5 In the embodiment, at least some of the branches 1012 in the first domain area D1 are disconnected from each other on the side close to the second domain area D2, at least some of the branches 1012 in the fourth domain area D4 are disconnected from each other on the side close to the third domain area D4, and the branches 1012 in the first domain area D1 that are disconnected from each other on the side close to the second domain area D2 and the branches 1012 in the fourth domain area D4 that are disconnected from each other on the side close to the third domain area D3 are symmetrically arranged with respect to the extending direction of the scan line GL (i.e., the row direction X). For another example, in Figure 8 In the embodiment, at least some of the branches 1012 in the second domain area D2 are disconnected from each other on the side close to the first domain area D1, and at least some of the branches 1012 in the third domain area D3 are disconnected from each other on the side close to the fourth domain area D4, and the branches 1012 in the second domain area D2 that are disconnected from each other on the side close to the first domain area D1 and the branches 1012 in the third domain area D3 that are disconnected from each other on the side close to the fourth domain area D4 are symmetrically arranged with respect to the extension direction of the scan line GL (i.e., the row direction X).

[0065] Continue to see Figure 5 and Figure 8 It can be seen that Figure 5 and Figure 8 Only the branch portions 1012 on one side of the domain gap are shown to be disconnected from each other and symmetrical about the extension direction of the scan line GL (i.e., the row direction X). In some embodiments, the present disclosure may also set the branch portions 1012 on both sides of the domain gap to be disconnected from each other and symmetrical about the extension direction of the scan line GL (i.e., the row direction X), which is not limited here.

[0066] In some embodiments, the present disclosure may also be arranged such that the branch portions 1012 that are disconnected from each other on one side near the adjacent domain area are asymmetric with respect to the extension direction of the scan line GL (ie, the row direction X). For example, Fig. 9 and Fig.10 As shown, the present disclosure is disposed in any one of two domains that are at least partially adjacent to each other, and at least some of the branches 1012 are disconnected from each other on one side close to the adjacent domain. Fig. 9 In the embodiment, at least some of the branches 1012 in the first domain area D1 are disconnected from each other on the side close to the second domain area D2, and at least some of the branches 1012 in the second domain area D2 are disconnected from each other on the side close to the first domain area D1; Fig.10 In the embodiment, at least some of the branches 1012 in the third domain region D3 are disconnected from each other on the side close to the fourth domain region D4, and at least some of the branches 1012 in the fourth domain region D4 are disconnected from each other on the side close to the third domain region D3.

[0067] It should be noted that the technical solution disclosed in the present invention, in which at least part of the branch portions 1012 in at least one domain (e.g., the first domain D) are disconnected from each other on the side close to the adjacent domain (e.g., the second domain D2), so as to achieve a higher transmittance, is not only applicable to the electrode 101 having the arc-shaped corner S1 in the slit S, but also applicable to the electrode 101 having no arc-shaped corner S1 in the slit S, such as Fig.11 and Fig.12 shown.

[0068] For example, in Fig.11 In the embodiment, at least some of the branches 1012 in the first domain area D1 are disconnected from each other on the side close to the second domain area D2, at least some of the branches 1012 in the fourth domain area D4 are disconnected from each other on the side close to the third domain area D4, and the branches 1012 in the first domain area D1 that are disconnected from each other on the side close to the second domain area D2 and the branches 1012 in the fourth domain area D4 that are disconnected from each other on the side close to the third domain area D3 are symmetrically arranged with respect to the extension direction of the scan line GL (i.e., the row direction X). Fig.12 In the embodiment, at least part of the branch portions 1012 in the second domain area D2 are disconnected from each other on the side close to the first domain area D1, at least part of the branch portions 1012 in the third domain area D3 are disconnected from each other on the side close to the fourth domain area D4, and the branch portions 1012 in the second domain area D2 that are disconnected from each other on the side close to the first domain area D1 and the branch portions 1012 in the third domain area D3 that are disconnected from each other on the side close to the fourth domain area D4 are symmetrically arranged with respect to the extension direction of the scan line GL (i.e., the row direction X).

[0069] The present disclosure also provides Fig.11 and Fig.12 The dark pattern simulation diagram in the area where the electrode 101 is located is shown, specifically, Fig.13 for Fig.11 The dark pattern simulation diagram in the area where the electrode 101 is located is shown. Fig.14 for Fig.12 A simulation diagram of dark lines in the area where the electrode 101 is located is shown. Figure 3 This is a simulation diagram of dark lines in the area where the electrode 101 is located in the related art. Figure 3 , Fig.13 and Fig.14 visible, Fig.13 and Fig.14 The dark lines of the electrode 101 in the Z3 region using the technical solution of disconnecting the branch portion 1012 between domains disclosed in the present invention are smaller than Figure 3 The dark pattern area of ​​the electrode 101 in the Z3 region in the related art is shown. Figure 3 The simulated transmittance is 6.63%. Fig.13 The simulated transmittance is 6.78%. Fig.14 The simulated transmittance is 6.8%. This shows that the technical solution disclosed in the present disclosure can improve the transmittance by disconnecting the branch portion 1012 between domains.

[0070] In some embodiments, the branch portions 1012 of each domain region in adjacent domain regions are not disconnected between domains, and the branch portions 1012 of adjacent domain regions can be arranged to be connected to each other between domains. Figure 5 , Figures 8 to 10 In the figure, the branch portions 1012 of the second domain area D2 are connected to each other on the side close to the third domain area D3, and the branch portions 1012 of the third domain area D3 are connected to each other on the side close to the second domain area D2, and a connecting portion 1013 is provided between the second domain area D2 and the third domain area D3, so that the branch portions 1012 in the second domain area D2 and the branch portions 1012 in the third domain area D3 are respectively connected to the connecting portion 1013.

[0071] In some embodiments, the branches 1012 of each domain in adjacent domains are not disconnected between domains, and the branches 1012 of the same domain can be connected to each other, while the branches 1012 of adjacent domains are disconnected between domains. Fig. 9 In the embodiment, the branches 1012 of the third domain area D3 and the fourth domain area D4 are not disconnected between domains. Specifically, the branches 1012 of the third domain area D3 are connected to each other on the side close to the fourth domain area D4, and the branches 1012 of the fourth domain area D4 are connected to each other on the side close to the third domain area D3, and the branches 1012 of the third domain area D3 and the branches 1012 of the fourth domain area D4 are disconnected from each other between domains. Fig.10In the embodiment, the branches 1012 of the first domain region D1 and the second domain region D2 are not disconnected between domains. Specifically, the branches 1012 of the first domain region D1 are connected to each other on the side close to the second domain region D2, and the branches 1012 of the second domain region D2 are connected to each other on the side close to the first domain region D1, and the branches 1012 of the first domain region D1 and the branches 1012 of the second domain region D2 are disconnected from each other between domains.

[0072] In some embodiments, Figures 15 to 21 As shown, the array substrate provided by the present disclosure may also include a transistor TFT coupled to the electrode 101, a gate g of the transistor TFT and the scan line GL are integrally arranged, a first electrode s of the transistor TFT and the data line DL are integrally arranged, a second electrode d of the transistor TFT and the electrode 101 are coupled through a via h penetrating the first insulating layer 106, the color resist 105 (including but not limited to the red color resist, the green color resist, the blue color resist), and the second insulating layer 104, the active layer a of the transistor TFT may be made of amorphous silicon a-Si, polycrystalline silicon Poly, oxide (such as indium gallium zinc oxide IGZO), etc., and the transistor TFT may be a bottom-gate transistor, a top-gate transistor, or a bipolar transistor. The present disclosure uses the bottom-gate transistor TFT as an example for explanation. The transistor TFT can be a P-type transistor or an N-type transistor, which is not limited here. Optionally, the array substrate also includes a first base substrate 102, a third insulating layer 103 located between the layer where the scan line GL is located and the layer where the data line DL is located, a first common voltage line CL1 set in the same layer and material as the scan line GL, a second common voltage line CL2 set in the same layer and material as the electrode 101, and a first alignment layer 107 located on the side of the electrode 101 away from the first base substrate 102, and the first alignment layer 107 is treated by light through the SUVA process so that the liquid crystal has a set pre-tilt angle. Other essential components of the array substrate should be understood by ordinary technicians in the field, and will not be repeated here, nor should they be used as limitations to the present disclosure.

[0073] Based on the same inventive concept, the embodiment of the present disclosure provides a display panel, such as Fig. 22As shown, it includes the above-mentioned array substrate 001 provided in the embodiment of the present disclosure, and an opposing substrate 002 arranged opposite to the array substrate 001; optionally, the opposing substrate 002 includes a second base substrate 201, a black matrix 202, a common electrode 203 and a second alignment layer 204; wherein the common electrode 201 is arranged on the entire surface of the display area AA; the black matrix 202 is a grid structure, the orthographic projection of the scan line GL on the second base substrate 201 is located within the orthographic projection of the black matrix 202 on the second base substrate 201, and the orthographic projection of the data line DL on the second base substrate 201 is located within the orthographic projection of the black matrix 202 on the second base substrate 201; the second alignment layer 204 makes the liquid crystal have a set pre-tilt angle due to the SUVA process light treatment.

[0074] In some embodiments, the display panel provided by the embodiment of the present disclosure may further include a liquid crystal layer between the array substrate 001 and the counter substrate 002, and a first polarizer may be provided on the side of the array substrate 001 away from the counter substrate 002, and a second polarizer may be provided on the side of the counter substrate 002 away from the array substrate 001, and the polarization direction of the first polarizer is perpendicular to the polarization direction of the second polarizer. Other essential components of the display panel should be understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used as limitations to the present disclosure.

[0075] Based on the same inventive concept, the present disclosure provides a display device, such as Fig.23 As shown, it includes the above-mentioned display panel PNL provided by the embodiment of the present disclosure, and a backlight module BLU located on the light incident side of the display panel PNL. The backlight module BLU can be a direct-type backlight module or an edge-type backlight module. Optionally, the edge-type backlight module may include a light bar, a reflective sheet arranged in a stacked manner, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightness enhancement film arranged in a stacked manner on the light emitting side of the matrix light source, and the reflective sheet includes an opening arranged directly opposite to the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source may be light-emitting devices (LEDs), such as quantum dot light-emitting devices, micro light-emitting devices (such as Mini LED, MicroLED), etc.

[0076] Among them, submillimeter or even micron-scale micro-light-emitting devices are self-luminous devices like organic light-emitting devices (OLEDs). Like organic light-emitting devices, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because the light emission of inorganic light-emitting devices is based on metal semiconductors with more stable properties and lower resistance, compared with organic light-emitting devices based on organic matter, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life. And when micro-light-emitting devices are used as backlight sources, more precise dynamic backlight effects can be achieved. While effectively improving the brightness and contrast of the screen, it can also solve the glare caused by traditional dynamic backlighting between the bright and dark areas of the screen, optimizing the visual experience.

[0077] In some embodiments, the above-mentioned display device provided in the embodiments of the present disclosure may be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, and any other product or component with a display function. Optionally, the display device provided by the present disclosure includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip. Optionally, the control chip is a central processing unit, a digital signal processor, a system chip (SoC), and the like. For example, the control chip may also include a memory, and may also include a power module, and the like, and realize power supply and signal input and output functions through additionally provided wires, signal lines, and the like. For example, the control chip may also include a hardware circuit and a computer executable code, and the like. The hardware circuit may include a conventional very large scale integration (VLSI) circuit or gate array and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include a field programmable gate array, a programmable array logic, a programmable logic device, and the like. In addition, those skilled in the art will appreciate that the above structure does not constitute a limitation on the above display device provided in the embodiment of the present disclosure. In other words, the above display device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.

[0078] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0079] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, characterized in that: A plurality of electrodes are included, wherein the electrodes include: A frame portion, wherein the frame portion has a plurality of domains in an area enclosed by the frame portion; A plurality of branch portions are provided, wherein the plurality of branch portions are located in the plurality of domains and connected to the frame portion; within the same domain, the slits between adjacent branch portions include arc-shaped corners; and at least part of the branch portions of at least one domain are disconnected from each other on a side close to the adjacent domain.

2. The array substrate according to claim 1, characterized in that: The slit further comprises a middle portion having an acute angle, and the arc-shaped corner is disposed at the periphery of the acute angle of the middle portion.

3. The array substrate according to claim 2, characterized in that: The size of the arc-shaped corner in a vertical direction of a single side of the acute angle is 0.5 μm to 3 μm.

4. The array substrate according to claim 2 or 3, characterized in that: The spacing between adjacent branch portions is a first dimension, the arc-shaped corner has a second dimension in a single-side extension direction of the acute angle, and the ratio of the second dimension to the first dimension is 1:2 to 3:

4.

5. The array substrate according to claim 2 or 3, characterized in that: On the side where the single side of the acute angle is located, the arc-shaped corner extends along a first direction away from the single side of the acute angle, and the angle between the first direction and the single side of the acute angle is 25° to 65°.

6. The array substrate according to claim 1, characterized in that: It also includes a scan line extending in the row direction and a data line extending in the column direction, and a plurality of domains are arranged along the extending direction of the data lines; in at least one of the first and last domains, at least part of the branches are disconnected from each other on a side close to the adjacent domain; And / or, in at least one of the remaining domains other than the head and the tail, at least part of the branches are disconnected from each other on a side close to an adjacent domain.

7. The array substrate according to claim 6, characterized in that: The branch portions that are disconnected from each other at a side close to the adjacent domain region are symmetrical with respect to an extending direction of the scan line.

8. The array substrate according to claim 7, characterized in that: The multiple domain regions include a first domain region, a second domain region, a third domain region and a fourth domain region arranged along the extension direction of the data line, wherein at least part of the branch portions in the first domain region are disconnected from each other on a side close to the second domain region, and at least part of the branch portions in the fourth domain region are disconnected from each other on a side close to the third domain region.

9. The array substrate according to claim 7, characterized in that: The multiple domain regions include a first domain region, a second domain region, a third domain region and a fourth domain region arranged along the extension direction of the data line, wherein at least part of the branch portions in the second domain region are disconnected from each other on a side close to the first domain region, and at least part of the branch portions in the third domain region are disconnected from each other on a side close to the fourth domain region.

10. The array substrate according to claim 6, wherein: In at least part of any one of the two adjacent domains, at least part of the branches are disconnected from each other on a side close to the adjacent domain.

11. The array substrate according to claim 10, characterized in that: The multiple domain regions include a first domain region, a second domain region, a third domain region and a fourth domain region arranged along the extension direction of the data line, wherein at least part of the branches in the first domain region are disconnected from each other on a side close to the second domain region, and at least part of the branches in the second domain region are disconnected from each other on a side close to the first domain region.

12. The array substrate according to claim 10, characterized in that: The multiple domain regions include a first domain region, a second domain region, a third domain region and a fourth domain region arranged along the extension direction of the data line, wherein at least part of the branches in the third domain region are disconnected from each other on a side close to the fourth domain region, and at least part of the branches in the fourth domain region are disconnected from each other on a side close to the third domain region.

13. The array substrate according to claim 8, 9, 11 or 12, characterized in that: It also includes a connecting portion located between the second domain area and the third domain area, and the branch portion in the second domain area and the branch portion in the third domain area are respectively connected to the connecting portion.

14. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 13.

15. The display panel according to claim 14, wherein: Also included is an opposite substrate disposed opposite to the array substrate, wherein the opposite substrate includes a common electrode.

16. A display device, characterized in that: Comprising the display panel as claimed in claim 14 or 15.

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