Pixel structure and display device

Abstract

The invention discloses a pixel structure. The pixel structure comprises a substrate, two transistors, an insulating layer and a pixel electrode, the transistor is disposed on the substrate, and the insulating layer is disposed on the substrate and the transistor. The pixel electrode is disposed on the insulating layer and has two notches spaced apart from each other, where the notches overlap with the transistors, respectively, in a top view of the pixel structure.

Description

Technical Field

[0001] The invention relates to a pixel structure and a display device. Background Art

[0002] With the development trend of energy conservation and carbon reduction, electronic paper display devices with power saving functions have gradually been applied to electronic products in daily life. In existing electronic paper display devices, the screen display of the electronic ink layer is controlled by an array substrate. However, in order to reduce the number of masks used to make the array substrate, the pixel electrodes in the array substrate need to avoid the thin film transistors and have an electric field drive area, so that the part of the electronic ink overlapping with the electric field drive area is driven by an electric field that is too low or not driven, causing the electronic paper display device to produce abnormal screens. Summary of the invention

[0003] According to one embodiment of the present invention, a pixel structure is disclosed, which includes a substrate, two transistors, an insulating layer, and a pixel electrode. The transistor is disposed on the substrate, and the insulating layer is disposed on the substrate and the transistor. The pixel electrode is disposed on the insulating layer and has two recesses separated from each other, wherein in a top view of the pixel structure, the recesses overlap with the transistors respectively.

[0004] In the pixel structure of the present invention, by separating the notches corresponding to different transistors, the width of each notch can be reduced, thereby reducing the area where the pixel electrode does not generate an electric field, thereby avoiding the problem of abnormal images of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 FIG. 1 is a cross-sectional schematic diagram of a display device according to an embodiment of the present invention.

[0006] Figure 2 FIG. 1 is a schematic top view of a portion of a display device corresponding to a front panel according to an embodiment of the present invention.

[0007] Figure 3 FIG. 1 is a schematic top view of a portion of a display device corresponding to an array substrate according to an embodiment of the present invention.

[0008] Figure 4 Shown along Figure 3 A schematic cross-sectional view of the section line A-A'.

[0009] The reference numerals are described as follows:

[0010] 1 Display device

[0011] 10 Pixel Structure

[0012] 12 substrate

[0013] 14b,14a transistors

[0014] 16 Insulation layer

[0015] 18 pixel electrodes

[0016] 18a,18b Notch

[0017] 18S1,18S2 Side

[0018] 1S Display

[0019] 2 Array substrate

[0020] 20 scan lines

[0021] 22 Data cable

[0022] 24 Gate insulation layer

[0023] 26 Shared Line

[0024] 26a Electrode section

[0025] 28 Storage Electrode

[0026] 3 Front panel

[0027] 32 display area

[0028] 34 Dark Zone

[0029] 4 Adhesive layer

[0030] D1 First direction

[0031] D2 Second direction

[0032] DE Drain

[0033] DS1, DS2, DS3 spacing

[0034] GE Gate

[0035] M1 First conductive layer

[0036] M2 Second conductive layer

[0037] P1 Part 1

[0038] P2 Part 2

[0039] P3 Part 3

[0040] S1 First segment

[0041] S2 Second segment

[0042] SE Source

[0043] SEM Semiconductor Island

[0044] TD Looking down direction

[0045] TH Perforation

[0046] W1,W2,W3 Width DETAILED DESCRIPTION

[0047] In order to enable those skilled in the art to further understand the present invention, the preferred embodiments of the present invention are listed below, and the components of the present invention and the effects to be achieved are described in detail with the accompanying drawings. It should be noted that the drawings are simplified schematic diagrams, and therefore, only the components and combination relationships related to the present invention are shown to provide a clearer description of the basic architecture or implementation method of the present invention, while the actual components and layout may be more complex. In addition, for the convenience of explanation, the components shown in the drawings of the present invention are not drawn in proportion to the actual number, shape, and size, and the detailed proportions can be adjusted according to the design requirements.

[0048] Figure 1 FIG. 2 is a cross-sectional schematic diagram of a display device according to an embodiment of the present invention. Figure 1 As shown, the display device 1 may include an array substrate 2 and a front panel lamination (FPL) 3, and the front panel 3 may be disposed on the array substrate 2. The front panel 3 may be formed by, for example, an adhesive layer (e.g. Figure 4 The adhesive layer 4 shown is attached to the array substrate 2. The front panel 3 can be used to display images, and the surface of the front panel 3 facing away from the array substrate 2 can be used as the display surface 1S of the display device 1. The array substrate 2 can be used to control the front panel 3 so that the display surface 1S of the display device 1 can display images. The array substrate 2 and the front panel 3 of the display device 1 may include a plurality of pixel structures 10, wherein each pixel structure 10 can be used to display a pixel of a corresponding image or a sub-pixel of a single color, for example.

[0049] In one embodiment, the front panel 3 may include a display medium layer for displaying a picture. For example, the display medium layer may be an electronic ink layer, in which case the display device 1 may be an electronic paper display device, but is not limited thereto. The electronic ink layer may include electrophoresis, cholesterol liquid crystal or other suitable materials. In some embodiments, the display medium layer may also be other types of reflective display media. In some embodiments, the front panel 3 may also include a common electrode (not shown), and the display medium layer may be disposed between the array substrate 2 and the common electrode, but is not limited thereto.

[0050] Figure 2 FIG. 1 is a schematic top view of a portion of a display device corresponding to a front panel according to an embodiment of the present invention, wherein Figure 2 Omitting the array substrate (eg, Figure 1 The array substrate 2) is a part of the array substrate 2, but is not limited thereto. Figure 2As shown, the front panel 3 may include a plurality of display areas 32 and a dark area 34, wherein the display area 32 can be used to display images, and the dark area 34 cannot display images or colors, but is a black area. For example, the front panel 3 may include a plurality of microcapsules, the interior of which includes liquid and charged particles with colors, and the charged particles are disposed in the liquid. Each microcapsule may correspond to a display area 32, and by controlling the position of the charged particles, the display area 32 may present different colors or grayscales, but the present invention is not limited thereto. In some embodiments, the charged particles may have multiple colors, or the liquid may have a color different from that of the charged particles, but is not limited thereto. Since the charged particles used to display colors in different microcapsules are separated by capsule areas, a dark area 34 that cannot display colors will be formed at the junction of adjacent microcapsules, which is located between the display areas 32. Figure 2 In the embodiment of the present invention, the size or top-view area of ​​the display area 32 may be, for example, smaller than the size or top-view area of ​​the pixel structure 10 .

[0051] like Figure 2 As shown, the display area 32 is not aligned with the pixel structure 10 in the top view of the display device 1. For example, the display area 32 is arranged in a honeycomb manner, and the pixel structure 10 is arranged in an array manner. The row direction of the pixel structure 10 may be the first direction D1, and the column direction of the pixel structure 10 may be the second direction D2, but is not limited thereto. The first direction D1 may be, for example, perpendicular to the second direction D2. The top view shape of the display area 32 may be, for example, different from the top view shape of the pixel structure 10. The top view shape of the display area 32 may be, for example, a hexagon or other suitable shape. The top view shape of the pixel structure 10 may be, for example, a rectangle or other shape. The pitch of two adjacent display areas 32 projected onto the first direction D1 may be different from the pitch between two adjacent pixel structures 10 arranged in the first direction D1, and / or the pitch of two adjacent display areas 32 projected onto the second direction D2 may be different from the pitch between two adjacent pixel structures 10 arranged in the second direction D2. For example, the pitch between two adjacent display regions 32 may be about 150 microns, and the pitch between two adjacent pixel structures 10 may be about 167 microns, but the present invention is not limited thereto. The arrangement of the display units 32 and the arrangement of the pixel structures 10 and the matching method thereof are not limited to the above. Figure 2 The pitch may be, for example, the distance between the centers of two adjacent elements.

[0052] Figure 3 FIG. 1 is a schematic top view of a portion of a display device corresponding to an array substrate according to an embodiment of the present invention. Figure 4 Shown along Figure 3 A schematic cross-sectional view taken along the section line AA' of FIG. 1 , in which the portion of the pixel structure 10 located in the array substrate 2 is clearly shown. Figure 3 Omit the front panel (for example, Figure 1 The front panel 3) is a part of the device, but is not limited to this. Figure 3 to Figure 4 As shown, the pixel structure 10 may include a substrate 12, two transistors 14a, 14b, an insulating layer 16 and a pixel electrode 18, wherein the transistors 14a, 14b are disposed on the substrate 12, the insulating layer 16 is disposed on the substrate 12 and the transistors 14a, 14b, and the pixel electrode 18 is disposed on the insulating layer 16. In addition, the pixel electrode 18 has two recesses 18a, 18b separated from each other, and in the top view of the pixel structure 10, the recesses 18a, 18b overlap with the transistors 14a, 14b respectively. It should be noted that by separating the recesses 18a, 18b corresponding to different transistors 14a, 14b, the width W1 of each recess 18a, 18b can be reduced, thereby reducing the area where the pixel electrode 18 does not generate an electric field, thereby avoiding the problem of abnormal picture of the display device 1.

[0053] In one embodiment, the pixel electrode 18 may not overlap with the transistors 14a and 14b in the top-view direction TD of the pixel structure 10 to reduce the effect of the pixel electrode 18 on the transistors 14a and 14b, thereby avoiding leakage of the transistors 14a and 14b. For example, the width W1 of one of the notches 18a and 18b in the first direction D1 may be approximately greater than the width W2 of one of the transistors 14a and 14b in the first direction D1 or 0.5 times the width W2 to reduce the effect of the pixel electrode 18 on the transistors 14a and 14b while reducing the size of the area where no electric field is generated. In order to reduce the size of the area where no electric field is generated, the width W1 may be less than 4 times or 5 times the width W2, but is not limited thereto. In some embodiments, the width W1 of the notch 18a may be the same as or different from the width W1 of the notch 18b.

[0054] In detail, in a pixel structure 10, the recesses 18a and 18b may be arranged along the first direction D1, and the spacing DS1 between the recesses 18a and 18b may be less than or equal to two-thirds of the width W3 of the pixel structure 10 in the first direction D1 when they are separated from each other. Alternatively, the spacing DS1 may be less than or equal to one-half of the width W3 of the pixel structure 10 in the first direction D1. By designing the spacing DS1 to be less than or equal to a certain proportion of the width W3 of the pixel structure 10, the spacing between the recesses 18a and 18b of adjacent pixel structures 10 may be reduced to be too small, so as to avoid the problem of poor picture quality due to the excessive proximity of the area without generating an electric field. In detail, the pixel electrode 18 may have a first portion P1, a second portion P2, and a third portion P3, wherein the recess 18a may be located between the first portion P1 and the second portion P2, and the recess 18b may be located between the second portion P2 and the third portion P3. Moreover, the spacing DS1 may refer to the width of the second portion P2 in the first direction D1.

[0055] In addition, the minimum value of the spacing DS1 between the recesses 18a and 18b separated from each other may depend on the limit of the process technology. For example, the spacing DS1 between the recesses 18a and 18b may be greater than or equal to 1 micron, 5 microns or 8 microns under some process technologies, but is not limited thereto. In some embodiments, the spacing DS1 between the recesses 18a and 18b may be greater than or equal to the width W2 of one of the transistors 14a and 14b in the first direction D1, so that the spacing between the recesses 18a and 18b of the same pixel structure 10 will not be too small, thereby avoiding the problem of poor picture quality due to the excessive proximity of the area without generating an electric field.

[0056] like Figure 3 As shown, the pixel electrode 18 may have two side edges 18S1 and 18S2 opposite to each other, and the notches 18a and 18b are arranged between the side edges 18S1 and 18S2 and separated from the side edges 18S1 and 18S2, so that the spacing between the notches 18b and 18a in two adjacent pixel electrodes 18 will not be too small to avoid the problem of poor picture quality. In a pixel structure 10, the notch 18a may be arranged between the side edge 18S1 and the notch 18b of the pixel electrode 18, and the spacing DS2 between the notch 18a and the side edge 18S1 may be greater than or equal to the limit of the process technology, for example, 1 micron, 5 microns or 8 microns, but not limited thereto. In some embodiments, the spacing DS3 between the notch 18b and the side edge 18S2 may be greater than or equal to the limit of the process technology, but not limited thereto. In some embodiments, the pixel electrode 18 may, for example, include a metal or a transparent conductive material. The transparent conductive material may, for example, include indium tin oxide (ITO) or other suitable materials.

[0057] like Figure 3 and Figure 4 As shown, the plurality of pixel structures 10 may further include a plurality of scan lines 20 and a plurality of data lines 22. Figure 3 In the embodiment of the present invention, the scan line 20 may extend along the first direction D1 and be arranged in the second direction D2, and the data line 22 may extend along the second direction D2 and be arranged in the first direction D1, but the present invention is not limited thereto. The first direction D1 may be different from the second direction D2, for example, the first direction D1 is perpendicular to the second direction D2. In the present embodiment, a pixel structure 10 may be defined by, for example, an area surrounded by two adjacent scan lines 20 and two adjacent data lines 22, and each pixel structure 10 may include a scan line 20 and a data line 22. In this case, the width W3 of the pixel structure 10 in the first direction D1 may be defined, for example, as the distance between a side edge of an element in a pixel structure 10 and a corresponding side edge of an element in an adjacent pixel structure 10 that is the same as the element. For example, the width W3 of the pixel structure 10 may be the distance between the right sides of two adjacent data lines 22. The method of defining the pixel structure 10 of the present invention is not limited to the above, and the definition of the pixel structure 10 may be adjusted according to different design methods.

[0058] In addition, Figure 3 In the embodiment of the present invention, the scan line 20 can be electrically connected to the transistors 14a and 14b of the pixel structure 10 arranged in the same row, and in the top view of the pixel structure 10, the recesses 18a and 18b can face the scan line 20. The data line 22 can be electrically connected to the transistors 14a of the pixel structure 10 arranged in the same column, and each data line 22 can be electrically connected to the corresponding pixel electrode 18 through the corresponding transistor 14a and 14b.

[0059] like Figure 4 As shown, taking transistor 14a as an example, only an insulating layer 16 may be disposed between transistor 14a and pixel electrode 18 to reduce the number of masks for manufacturing the array substrate. In this case, insulating layer 16 may directly contact transistor 14a and pixel electrode 18, but is not limited thereto.

[0060] like Figure 3 and Figure 4 As shown, the transistors 14a and 14b of this embodiment may be, for example, bottom-gate thin film transistors. The transistors 14a and 14b may have the same or similar structures. Figure 4Take transistor 14a as an example, but not limited to this. Transistor 14a may include a gate GE, a gate insulating layer 24, a semiconductor island SEM, a source SE and a drain DE, wherein the gate GE may be disposed on the substrate 12, the gate insulating layer 24 may be disposed on the gate GE and the substrate 12, the semiconductor island SEM may be disposed on the gate insulating layer 24 and correspond to the gate GE in the top-down direction TD, and the source SE and the drain DE may be disposed on the semiconductor island SEM, respectively, and located on two parts of the semiconductor island SEM separated from each other. Taking transistor 14a as an example, the width W2 of transistor 14a may be the distance between the side of the source SE away from the drain DE and the side of the drain away from the source SE, but not limited to this. Figure 3 In the embodiment of FIG. 1 , the source SE of the transistor 14 a is electrically connected to the drain DE of the transistor 14 b , and the drain DE of the transistor 14 b is electrically connected to the pixel electrode 18 .

[0061] In one embodiment, the gate GE and the scan line 20 may be formed by the same first conductive layer M1, and the source SE, the drain DE and the data line 22 may be formed by the same second conductive layer M2, but not limited thereto. In this case, the gate GE may be directly connected to the same scan line 20. The second conductive layer M2 may also include a first line segment S1 and a second line segment S2, wherein the source SE of the transistor 14a may be electrically connected to the data line 22 through the first line segment S1, and the source SE of the transistor 14b may be electrically connected to the drain DE of the transistor 14a through the second line segment S2. When viewed along the top-view direction TD, the first line segment S1 and the second line segment S2 may be respectively located between the first portion P1 of the pixel electrode 18 and the scan line 20 and between the second portion P2 of the pixel electrode 18 and the scan line 20, but not limited thereto. The first conductive layer M1 and the second conductive layer M2 may, for example, include metal. In some embodiments, the transistors 14a and 14b may be other types of thin film transistors, but not limited thereto.

[0062] like Figure 3 and Figure 4 As shown, the pixel structure 10 may further include a storage electrode 28 formed by the second conductive layer M2. The storage electrode 28 may overlap with the pixel electrode 18 in the top-view direction TD, and the insulating layer 16 may have a through hole TH, so that the pixel electrode 18 can be electrically connected to the storage electrode 28 through the through hole TH. In addition, the first conductive layer M1 may further include a common line 26, and the common line 26 may have an electrode portion 26a, wherein the electrode portion 26a overlaps with the storage electrode 28 in the top-view direction TD, so that the electrode portion 26a, the gate insulating layer 24 and the storage electrode 28 can form a storage capacitor, but is not limited thereto. In one embodiment, the common line 26 may extend along the first direction D1, but is not limited thereto.

[0063] In summary, in the pixel structure of the present invention, by separating the notches corresponding to different transistors, the width of each notch can be reduced, thereby reducing the area where the pixel electrode does not generate an electric field, thereby avoiding the problem of abnormal images of the display device.

[0064] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A pixel structure, characterized in that: include: a substrate; Two transistors are disposed on the substrate; an insulating layer, disposed on the substrate and the transistor; as well as A pixel electrode is disposed on the insulating layer and has two recesses separated from each other, wherein in a top view of the pixel structure, the recesses overlap with the transistors respectively.

2. The pixel structure according to claim 1, characterized in that: The notches are arranged along a direction, and a spacing between the notches is less than or equal to two-thirds of a width of the pixel structure in the direction.

3. The pixel structure according to claim 2, characterized in that: The spacing is greater than or equal to a width of one of the transistors in the direction.

4. The pixel structure according to claim 1, wherein: The pixel electrode has two sides opposite to each other, and the notch is disposed between the sides and separated from the sides.

5. The pixel structure according to claim 4, characterized in that: One of the notches is disposed between one of the side edges and another of the notches, and a distance between the one of the notches and the one of the side edges is greater than 1 micrometer.

6. The pixel structure according to claim 1, wherein: The notches are arranged along a direction, and a width of one of the notches in the direction is greater than 0.5 times a width of one of the transistors in the direction.

7. The pixel structure according to claim 1, wherein: The notches are arranged along a direction, and a width of one of the notches in the direction is less than 5 times a width of one of the transistors in the direction.

8. A display device, characterized in that: include: an array substrate; as well as A front panel is disposed on the array substrate, and the array substrate and the front panel include a plurality of pixel structures as claimed in claim 1.

9. The display device according to claim 8, wherein: The front panel includes a plurality of display areas, and the display areas are not aligned with the pixel structure in a top view of the pixel structure.

10. The display device according to claim 9, characterized in that One of the pixel structures overlaps with at least two of the display areas in a top view of the pixel structure.

Images