Micro-operation extraction method, device and electronic device based on physical memory protection

Abstract

The present invention discloses a micro-operation extraction method, specifically relating to a micro-operation extraction method, device and electronic device based on physical memory protection. The method includes: matching based on the instruction virtual address in the fetch request in the micro-operation cache, and in the case of obtaining the target cache virtual address by matching from the micro-operation cache, obtaining the corresponding target physical address based on the target cache virtual address; checking the access permission of the target physical address; and in the case of legal check, extracting the target micro-operation from the micro-operation cache based on the target physical address or the target cache virtual address. By adding physical address permission check to the system that indexes the micro-operation cache using the instruction virtual address, the present invention can solve the problem of the decrease in cache hit rate caused by the need to refresh the micro-operation cache when modifying the physical memory access permission in the traditional micro-operation cache.

Description

Technical Field

[0001] The present invention belongs to the technical field of micro-operation extraction, and particularly relates to a micro-operation extraction method, device and electronic device based on physical memory protection. Background Art

[0002] In modern high-performance processor designs, the processor executes program code instructions, or more simply, instructions that cause the processor to perform corresponding operations. For example, a processor, such as a central processing unit (CPU), can execute instructions from software applications, operating systems, firmware, etc. Some processors are capable of executing one or more specific micro-operation instructions or "macro-instructions" decomposed by an instruction decoder. Each micro-operation is a simpler low-level processor instruction that, when executed by the processor, causes the processor execution unit to further decode the corresponding part of the entire operation of the micro-operation instruction from which it is decoded. When the processor executes an instruction, the steps of extracting the instruction to be executed from the instruction cache or memory subsystem and decoding the extracted instruction into micro-operations for execution take a relatively long time and consume a large amount of energy. Therefore, designers have proposed techniques for accelerating the acquisition of micro-operations from instructions. One such technique is to use a cache memory called a micro-operation cache (Micro-Op / uop Cache) to store copies of micro-operations decoded from instructions. For this technique, the micro-operations decoded from the instructions are forwarded to the execution unit in the processor for execution, and along with this operation, the processor stores a copy of the micro-operations in the micro-operation cache. When an instruction whose copy of the micro-operation is stored in the micro-operation cache is encountered again, the processor can directly obtain the micro-operations from the micro-operation cache without having to re-obtain the instruction code from the instruction cache or memory subsystem and perform complex decoding operations.

[0003] The micro-operation cache is mainly indexed by virtual addresses. When the instruction virtual address hits the micro-operation cache, the processor can quickly obtain the corresponding micro-operation information from the micro-operation cache without having to perform complex instruction decoding. Modern operating system kernels need to be isolated from the user space to prevent user programs from directly accessing kernel memory; especially in multi-tasking operating systems, multiple processes run simultaneously, and each process also needs to set up an independent memory space and access permissions, which all involve the process of physical memory protection (PMP) permission allocation and modification.

[0004] The existing micro-operation cache adopts the VIVT (Virtual Index Virtual Tag) indexing method. Therefore, only the virtual address needs to be recorded. When the PMP permission is modified, to ensure the correct execution permission of the instructions after hitting the micro-operation cache, the entire micro-operation cache needs to be refreshed. The direct refresh of the micro-operation cache will lead to a decrease in the cache hit rate, thereby affecting the performance and power consumption of the processor. Summary of the Invention

[0005] The technical problem to be solved by the present invention is that when the PMP permission is modified in the above-mentioned method commonly used in the prior art, the entire micro-operation cache needs to be refreshed, resulting in a decrease in the cache hit rate, thereby affecting the performance and power consumption of the processor. To solve the above problems, the present invention provides a micro-operation extraction method, device, and electronic device based on physical memory protection.

[0006] The content of the present invention includes:

[0007] In a first aspect, an embodiment of the present invention provides a micro-operation extraction method based on physical memory protection, including:

[0008] Matching based on the instruction virtual address in the fetch request in the micro-operation cache, where the micro-operation cache includes multiple groups of cache data, and each group of the cache data includes a cache virtual address, a cache physical address, and cache micro-operation information;

[0009] When the target cache virtual address is matched from the micro-operation cache, obtaining the corresponding target physical address based on the target cache virtual address;

[0010] Checking the access permission of the target physical address;

[0011] When the check is legal, extracting the target micro-operation from the micro-operation cache based on the target physical address or the target cache virtual address.

[0012] Optionally, the obtaining the corresponding target physical address based on the target cache virtual address includes:

[0013] Determining the physical address corresponding to the target cache virtual address as the target physical address.

[0014] Optionally, the matching based on the instruction virtual address in the fetch request in the micro-operation cache includes:

[0015] Matching the virtual page number in the instruction virtual address with the virtual page number in the cache virtual address;

[0016] When the first cached virtual address is matched, determine whether the offset within a page in the instruction virtual address is the same as the offset within a page in the first cached virtual address;

[0017] Determine the first cached virtual address with the same offset within a page as the instruction virtual address as the target cache address, otherwise the matching fails.

[0018] Optionally, after performing the matching in the micro-operation cache based on the instruction virtual address in the fetch request, the method further includes:

[0019] When the matching in the micro-operation cache fails, convert the instruction virtual address into a corresponding target physical address;

[0020] Perform matching in the instruction cache based on the target physical address;

[0021] When the matching is successful, obtain the instruction opcode based on the target physical address;

[0022] Obtain the corresponding micro-operations and information of the micro-operations based on the instruction opcode.

[0023] Optionally, after obtaining the corresponding micro-operations and information of the micro-operations based on the instruction opcode, the method further includes:

[0024] Store the information of the micro-operations, the instruction virtual address corresponding to the micro-operations, and the target physical address corresponding to the micro-operations into the micro-operation cache.

[0025] Optionally, the performing matching in the instruction cache based on the target physical address includes:

[0026] Check the access permission of the target physical address;

[0027] When the check is legal, perform matching in the instruction cache based on the target physical address.

[0028] In a second aspect, an embodiment of the present invention further provides a micro-operation extraction device based on physical memory protection, including:

[0029] A first matching module, configured to perform matching in a micro-operation cache based on an instruction virtual address in a fetch request, where the micro-operation cache includes multiple groups of cached data, and each group of the cached data includes a cached virtual address, a cached physical address, and cached micro-operation information;

[0030] A first acquisition module, configured to, when a target cache virtual address is matched from the micro-operation cache, acquire a corresponding target physical address based on the target cache virtual address;

[0031] An inspection module, configured to inspect the access permission of the target physical address;

[0032] An extraction module, configured to, when the inspection is legal, extract a target micro-operation from the micro-operation cache based on the target physical address or the target cache virtual address.

[0033] In a third aspect, an embodiment of the present invention further provides an implementation device for physical memory protection in a micro-operation cache, including:

[0034] A micro-operation cache, which is configured to store multiple groups of cache data, and each group of the cache data includes a cache virtual address, a cache physical address, and cache micro-operation information;

[0035] A processor fetch queue, which is configured to perform matching in the micro-operation cache based on an instruction virtual address in a fetch request;

[0036] An MMU unit, which is configured to, when a target cache virtual address is matched from the micro-operation cache, acquire a corresponding target physical address based on the target cache virtual address;

[0037] A PMP unit, which is configured to inspect the access permission of the target physical address.

[0038] In a fourth aspect, an embodiment of the present invention provides an electronic device, including: a memory, a processor, and a program stored in the memory and executable on the processor; the processor is configured to read the program in the memory to implement the steps in the micro-operation extraction method based on physical memory protection as described in the first aspect.

[0039] In a fifth aspect, an embodiment of the present invention provides a readable storage medium, which is used to store a program, and when the program is executed by a processor, the steps in the micro-operation extraction method based on physical memory protection as described in the first aspect are implemented.

[0040] The beneficial effects of the present invention are as follows. In the embodiments of the present invention, matching is performed in the micro-operation cache based on the instruction virtual address in the fetch request; in the case of obtaining the target cache virtual address by matching in the micro-operation cache, the corresponding target physical address is obtained based on the target cache virtual address; the access permission of the target physical address is checked; and in the case of legal check, the target micro-operation is extracted from the micro-operation cache based on the target physical address. The method provided by the present invention adds physical address permission check in the system that uses the instruction virtual address to index the micro-operation cache, which can reduce the refresh of micro-operations caused by the modification of physical memory protection permissions, improve the hit rate of the micro-operation cache, effectively reduce the power consumption of the processor, improve the performance of the processor, and has the advantages of small overhead, easy implementation, and flexible use. Description of the Drawings

[0041] Appendix Figure 1 It is one of the flowcharts of the micro-operation extraction method based on physical memory protection provided by the embodiments of the present invention;

[0042] Appendix Figure 2 It is a schematic diagram of the implementation device of physical memory protection in the micro-operation cache provided by the embodiments of the present invention;

[0043] Appendix Figure 3 It is a schematic diagram of the virtual address and physical address structures provided by the embodiments of the present invention;

[0044] Appendix Figure 4 It is a second flowchart of the micro-operation extraction method based on physical memory protection provided by the embodiments of the present invention;

[0045] Appendix Figure 5 It is a schematic diagram of the micro-operation extraction device based on physical memory protection provided by the embodiments of the present invention;

[0046] Appendix Figure 6 It is a schematic diagram of the structure of the electronic device provided by the embodiments of the present invention. Detailed Embodiments

[0047] In the embodiments of the present application, the term "and / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after. In the embodiments of the present application, the term "plural" refers to two or more, and other quantifiers are similar. The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first" and "second" are usually of the same category, and the number of objects is not limited. For example, the first object can be one or multiple.

[0048] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0050] The embodiments of the present application provide a micro-operation extraction method, device, and electronic device based on physical memory protection, aiming to solve the problem that the cache hit rate decreases due to the need to refresh the micro-operation cache when modifying the physical memory access permission in the traditional micro-operation cache.

[0051] Please refer to Figure 1 , Figure 1 , which is a schematic flow chart of the micro-operation extraction method based on physical memory protection provided by the embodiments of the present invention. The method specifically includes the following steps:

[0052] Step 101: Match based on the instruction virtual address in the fetch request in the micro-operation cache. The micro-operation cache includes multiple groups of cache data, and each group of cache data includes a cache virtual address, a cache physical address, and cache micro-operation information.

[0053] Step 102: In the case of obtaining the target cache virtual address by matching from the micro-operation cache, obtain the corresponding target physical address based on the target cache virtual address.

[0054] Step 103: Check the access permission of the target physical address.

[0055] Step 104: When the check is legal, extract the target micro-operation from the micro-operation cache based on the target physical address or the target cache virtual address.

[0056] In the embodiments of the present application, the present invention adds a check on the access permission of the physical address in the system that indexes the micro-operation cache using the instruction virtual address, which can solve the problem of the decrease in cache hit rate caused by the need to refresh the micro-operation cache when the traditional micro-operation cache modifies the access permission of the physical memory, and has significant technical advantages and application values.

[0057] As Figure 2 shown, the embodiments of the present invention also provide an implementation device for physical memory protection in a micro-operation cache for implementing the above-mentioned micro-operation extraction method based on physical memory protection. The implementation device for physical memory protection in the micro-operation cache includes:

[0058] A micro-operation cache 201, which is used to store multiple groups of cache data, and each group of the cache data includes a cache virtual address, a cache physical address, and cache micro-operation information;

[0059] A processor fetch queue 202, which is used to send a fetch request and perform a match in the micro-operation cache based on the instruction virtual address in the fetch request;

[0060] An MMU unit 203, which is used to obtain the corresponding target physical address based on the target cache virtual address when a target cache virtual address is matched from the micro-operation cache;

[0061] A PMP unit 204, which is used to check the access permission of the target physical address.

[0062] Specifically, the processor fetch queue issues a fetch request, and the fetch request includes an instruction virtual address, and the micro-operation cache is indexed through the instruction virtual address (Virtual Address, VA) PC (Program Counter). In step 101, a cache virtual address matching the instruction virtual address is searched for in the micro-operation cache. When the match is successful, the target cache virtual address can be obtained, and the corresponding target physical address (Physical Address, PA) is obtained through the target cache virtual address.

[0063] It should be understood that multiple sets of cached data are cached in the micro-operation cache, and each set of cached data consists of a cached virtual address, a cached physical address, and cached micro-operation information. In some embodiments, the micro-operation cache includes a VA cache entry and a PA cache entry.

[0064] Exemplarily, as Figure 3 shown, in the SV48 mode, the virtual address (VA) includes a virtual page number (Virtual PageNumber, VPN) part and a page offset part corresponding to the virtual address. The bit range of the virtual address in the processor is as follows: VA[49:0]. The physical address (Physical Address, PA) includes a physical page number (Physical PageNumber, PPN) part and a page offset part corresponding to the physical address. The bit range of the physical address in the processor is as follows: PA[39:12].

[0065] Optionally, in some embodiments, step 101 includes:

[0066] Matching the virtual page number in the instruction virtual address with the virtual page number in the cached virtual address;

[0067] When a first cached virtual address is obtained through the matching, determining whether the page offset in the instruction virtual address is the same as the page offset in the first cached virtual address;

[0068] Determining the first cached virtual address with the same page offset as the instruction virtual address as the target cached address; otherwise, the matching fails.

[0069] As Figure 3 shown, specifically, the virtual page number is the cache unit in the virtual address used to cache the physical page number (Physic PageNumber, PPN). The page offset can also be referred to as the tag value, which is generally the lower 12 bits of the virtual address.

[0070] In this embodiment, first, the virtual page number part in the virtual address is matched. In the case of a match, the offset part within the page is then matched. As a specific embodiment, the matching process of step 102 includes two stages: In the first stage, it is determined whether the virtual page number of the instruction virtual address hits. If there is no match for any entry in the micro-operation cache, vact_hit is set to 0 and the match is unsuccessful. If there is a match for any entry and the first cache virtual address is obtained, vact_hit is set to 1. In the second stage, it is determined whether the tag value in the first cache virtual address is the same as the tag value in the instruction virtual address. If the tags are different, mtag_hit is set to 0 and the match is unsuccessful. If the tag hits, mtag_hit is set to 1 and the target cache address is obtained.

[0071] Optionally, in some embodiments, obtaining the corresponding target physical address based on the target cache virtual address includes:

[0072] Determining the physical address corresponding to the target cache virtual address as the target physical address.

[0073] In this embodiment, the cache physical address corresponding to the cache data to which the target cache virtual address belongs is determined as the target physical address. Exemplarily, the target physical address is the cache physical address corresponding to the vact_hit hit entry during the process of matching based on the instruction virtual address in the micro-operation cache. In this way, there is no need for additional virtual-to-physical address conversion, improving the efficiency of obtaining the corresponding target address.

[0074] As a specific embodiment, step 103 is executed by a Memory Management Unit (MMU) to complete virtual-to-physical address conversion and obtain the target physical address. Exemplarily, the MMU includes a Translation Lookaside Buffer (TLB) and a Page Table Walk (PTW) component, and the virtual-to-physical page table translation mechanism involved includes multiple modes such as SV39 / SV48 / SV57.

[0075] In step 103, after obtaining the target physical address, the access permission of the target physical address is checked. As a specific embodiment, step 103 is performed by the PMP unit to check the access permission of the target physical address. In some embodiments, the PMP unit includes a set of configurable registers, specifically including 8 PMP configuration registers (denoted as pmpcfg0–pmpcfg8) and 8 PMP address registers (denoted as pmpaddr0–pmpaddr7). In other embodiments, it can be extended to more PMP configuration registers. In the above embodiments, the minimum protected physical memory granularity is 4KB, which is the same as the minimum granularity of the MMU translation page table. Each region can configure 3 memory access attributes, namely X (whether executable), R (whether readable), and W (whether writable).

[0076] Specifically, there are three representation methods for the PMP protection region: TOR, NA4, and NAPOT. TOR represents the start address and end address of the protected address space through two pmpaddr registers respectively, and the protection region is between these two addresses. NA4 indicates that the 4 bytes starting from the corresponding pmpaddr address are the protected space. NAPOT indicates that the region starting from the pmpaddr address and aligned by up to 2 (XLEN+3) bytes is the protected space, where XLEN represents the bit width of the integer register in the RISC-V instruction set architecture, usually the same as the address space size. Exemplarily, XLEN is 32, 64, or 128.

[0077] Optionally, in some embodiments, after the step 101, the method further includes:

[0078] In the case of unsuccessful matching in the micro-operation cache, converting the instruction virtual address into the corresponding target physical address;

[0079] Matching in the instruction cache based on the target physical address;

[0080] In the case of successful matching, obtaining the instruction opcode based on the target physical address;

[0081] Obtaining the corresponding micro-operation and the information of the micro-operation based on the instruction opcode.

[0082] Optionally, in some embodiments, the matching in the instruction cache based on the target physical address includes:

[0083] Checking the access permission of the target physical address;

[0084] In the case of legal check, matching in the instruction cache based on the target physical address.

[0085] In this embodiment, by checking the access permission of the target physical address, when the system modifies the physical memory access permission, it is not necessary to perform micro-operation cache flushing, which can improve the cache hit rate and the processor performance. It has the advantages of small overhead, easy implementation, low implementation cost, and flexible use, and can be flexibly applied to the existing processor design.

[0086] As Figure 2 shown, in some embodiments, the implementation device for physical memory protection in the micro-operation cache further includes:

[0087] An instruction cache 205 for caching multiple groups of instruction data, and each group of the instruction data includes an instruction cache physical address and a corresponding instruction opcode;

[0088] A decoding unit 206 for obtaining the corresponding micro-operations and information of the micro-operations based on the instruction opcode.

[0089] Specifically, the decoding unit splits the above instruction opcode into one or more micro-operations and decodes the information of each micro-operation.

[0090] Optionally, as Figure 2 shown, in some embodiments, the implementation device for physical memory protection in the micro-operation cache further includes a register renaming unit 207 for performing register renaming. In specific implementation, after extracting the target micro-operations from the micro-operation cache based on the target physical address, the obtained target micro-operations are sent to the register renaming unit for register renaming.

[0091] Optionally, in some embodiments, after obtaining the corresponding micro-operations and information of the micro-operations based on the instruction opcode, the method further includes:

[0092] Storing the information of the micro-operations, the instruction virtual address corresponding to the micro-operations, and the target physical address corresponding to the micro-operations into the micro-operation cache.

[0093] In this embodiment, through the above method, the uncached micro-operations can be added to the micro-operation cache, and it is not necessary to perform decoding again when extracting micro-operations later, which improves the efficiency of micro-operation extraction.

[0094] Next, taking a specific embodiment as an example, the specific implementation process of the micro-operation extraction method based on physical memory protection provided by the embodiment of the present invention will be described. As Figure 2 and Figure 4As shown, as a specific embodiment, the micro-operation extraction method based on physical memory protection specifically includes the following steps:

[0095] S0: The processor fetch queue 202 issues a fetch request to index the micro-operation cache through the instruction virtual address PC.

[0096] In one case, if the lookup in S0 hits and the target cache virtual address is obtained, then execute the following steps S1 - S3:

[0097] S1: Index the cache entry in the micro-operation cache 201 according to the target cache virtual address PC obtained in S0 to obtain the corresponding target physical address PA.

[0098] S2: Send the target physical address PA obtained in S1 to the PMP unit 204 for access permission check. If the permission check is legal, jump to execute S3. If the permission check is illegal, an access error is generated, this fetch request is ended, and the system is reported for exception handling.

[0099] S3: Extract the target micro-operation cached in the micro-operation cache 201 according to the target cache virtual address, and send the obtained target micro-operation to the register renaming unit 207 for register renaming.

[0100] In another case, if the lookup in step S0 misses, then jump from step S0 to execute the following steps S4 - S8:

[0101] S4: The MMU unit 203 completes the virtual - physical address translation to obtain the target physical address PA corresponding to the instruction virtual address PC.

[0102] S5: The PMP unit 204 performs an access permission check on the target physical address PA obtained in S21. If the permission check is legal, jump to execute step S6. If the check is illegal, an access error is generated, this fetch request is ended, and the system is reported for exception handling.

[0103] S6: Index the instruction cache 205 through the target physical address PA to extract the instruction opcode.

[0104] S7: The decoding unit 206 splits the above - mentioned instruction opcode into one or more micro - operations and decodes each micro - operation information.

[0105] S8: Send the micro - operations obtained in S7 to the register renaming unit 207 for register renaming; at the same time, cache the micro - operation information obtained in S7, as well as the physical address and virtual address corresponding to this micro - operation information, into the micro - operation cache 201.

[0106] The method provided by the embodiment of the present invention can improve the cache hit rate by adding a physical memory protection check to the index of the micro-operation cache, and when the system modifies the physical memory access permission, there is no need to perform a micro-operation cache refresh operation. At the same time, the method provided by the embodiment of the present invention has low overhead. Only the physical address needs to be cached corresponding to the virtual address when caching the VA, and a small amount of additional cache space is required. The PMP unit only needs to instantiate the PMP module already implemented in the system without special processing.

[0107] As Figure 5 shown, the embodiment of the present invention further provides a micro-operation extraction device 500 based on physical memory protection, including:

[0108] A first matching module 501, configured to match in the micro-operation cache based on the instruction virtual address in the fetch request, where the micro-operation cache includes multiple groups of cache data, and each group of the cache data includes a cache virtual address, a cache physical address, and cache micro-operation information;

[0109] A first obtaining module 502, configured to obtain a corresponding target physical address based on the target cache virtual address when the target cache virtual address is matched from the micro-operation cache;

[0110] An inspection module 503, configured to inspect the access permission of the target physical address;

[0111] An extraction module 504, configured to extract a target micro-operation from the micro-operation cache based on the target physical address or the target cache virtual address when the inspection is legal.

[0112] Optionally, the obtaining the corresponding target physical address based on the target cache virtual address includes:

[0113] Determining the physical address corresponding to the target cache virtual address as the target physical address.

[0114] Optionally, the matching module 501 includes:

[0115] A matching unit, configured to match the virtual page number in the instruction virtual address with the virtual page number in the cache virtual address;

[0116] A judging unit, configured to judge whether the page offset in the instruction virtual address is the same as the page offset in the first cache virtual address when the first cache virtual address is matched;

[0117] A determining unit, configured to determine the first cache virtual address with the page offset the same as the instruction virtual address as the target cache address, otherwise the matching fails.

[0118] Optionally, the micro-operation extraction device 500 based on physical memory protection further includes:

[0119] A conversion module, configured to convert the instruction virtual address into a corresponding target physical address when the matching in the micro-operation cache fails.

[0120] A second matching module, configured to perform matching in the instruction cache based on the target physical address.

[0121] A second obtaining module, configured to obtain an instruction opcode based on the target physical address when the matching is successful.

[0122] A third obtaining module, configured to obtain a corresponding micro-operation and information of the micro-operation based on the instruction opcode.

[0123] Optionally, the micro-operation extraction device 500 based on physical memory protection further includes:

[0124] A storage module, configured to store the information of the micro-operation, the instruction virtual address corresponding to the micro-operation, and the target physical address corresponding to the micro-operation into the micro-operation cache.

[0125] Optionally, the second matching module is specifically configured to:

[0126] Check the access permission of the target physical address;

[0127] When the check is legal, perform matching in the instruction cache based on the target physical address.

[0128] The micro-operation extraction device 500 based on physical memory protection provided in the embodiments of the present application can execute the above method embodiments, and its implementation principle and technical effects are similar, which will not be elaborated here in this embodiment.

[0129] It should be noted that the division of units in the embodiments of the present application is illustrative. It is only a logical function division, and there may be other division methods in actual implementation. In addition, in each embodiment of the present application, the functional units can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated units can be implemented in the form of hardware or in the form of software functional units.

[0130] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a processor-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0131] As Figure 6 As shown, an embodiment of this application provides an electronic device 600, including: a memory 602, a processor 601, and a program stored on the memory 602 and executable on the processor 601; the processor 601 is used to read the program in the memory 602 to implement the steps in the micro-operation extraction method based on physical memory protection as described above.

[0132] An embodiment of the present application further provides a readable storage medium. A program is stored on the readable storage medium. When the program is executed by a processor, it implements each process of the above-mentioned embodiment of the micro-operation extraction method based on physical memory protection and can achieve the same technical effect. To avoid repetition, it will not be elaborated here. Among them, the readable storage medium can be any available medium or data storage device that can be accessed by the processor, including but not limited to magnetic memories (such as floppy disks, hard disks, magnetic tapes, magneto-optical disks (MO), etc.), optical memories (such as compact disks (CD), digital versatile discs (DVD), Blu-ray discs (BD), high-definition versatile discs (HVD), etc.), and semiconductor memories (such as read-only memories (ROM), erasable programmable read-only memories (EPROM), electrically erasable programmable read-only memories (EEPROM), non-volatile memories (NAND FLASH), solid state disks (SSD), etc.).

[0133] It should be noted that in this article, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without more limitations, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including that element.

[0134] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-described embodiment methods can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, disk, optical disc), and includes several instructions for causing a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in various embodiments of the present application.

[0135] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific implementation manners. The above specific implementation manners are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all of them belong to the protection scope of the present application.

Claims

1. A micro-operation extraction method based on physical memory protection, characterized in that Comprising: Matching in a micro-operation cache based on the instruction virtual address in the fetch request, where the micro-operation cache includes multiple sets of cached data, and each set of the cached data includes a cached virtual address, a cached physical address, and cached micro-operation information; When a target cached virtual address is matched from the micro-operation cache, obtaining a corresponding target physical address based on the target cached virtual address; Checking the access permission of the target physical address; When the check is legal, extracting a target micro-operation from the micro-operation cache based on the target physical address or the target cached virtual address.

2. The method according to claim 1, characterized in that, The obtaining the corresponding target physical address based on the target cached virtual address includes: Determining the physical address corresponding to the target cached virtual address as the target physical address.

3. The method according to claim 1, characterized in that, The matching in the micro-operation cache based on the instruction virtual address in the fetch request includes: Matching the virtual page number in the instruction virtual address with the virtual page number in the cached virtual address; When a first cached virtual address is matched, determining whether the page offset in the instruction virtual address is the same as the page offset in the first cached virtual address; Determining the first cached virtual address with the page offset the same as the instruction virtual address as the target cached virtual address, otherwise the matching fails.

4. The method according to claim 1, characterized in that, After the matching in the micro-operation cache based on the instruction virtual address in the fetch request, the method further includes: When the matching in the micro-operation cache fails, converting the instruction virtual address into a corresponding target physical address; Matching in an instruction cache based on the target physical address; When the matching is successful, obtaining an instruction opcode based on the target physical address; Obtaining a corresponding micro-operation and information of the micro-operation based on the instruction opcode.

5. The method according to claim 4, characterized in that, After the obtaining the corresponding micro-operation and information of the micro-operation based on the instruction opcode, the method further includes: Storing the information of the micro-operation, the instruction virtual address corresponding to the micro-operation, and the target physical address corresponding to the micro-operation into the micro-operation cache.

6. The method according to claim 4, characterized in that, The matching in the instruction cache based on the target physical address includes: Checking the access permission of the target physical address; When the check is legal, matching in the instruction cache based on the target physical address.

7. A micro-operation extraction device based on physical memory protection, characterized in that Comprising: A first matching module, configured to match in a micro-operation cache based on the instruction virtual address in the fetch request, where the micro-operation cache includes multiple sets of cached data, and each set of the cached data includes a cached virtual address, a cached physical address, and cached micro-operation information; A first obtaining module, configured to obtain a corresponding target physical address based on the target cached virtual address when a target cached virtual address is matched from the micro-operation cache; A checking module, configured to check the access permission of the target physical address; An extraction module, configured to extract a target micro-operation from the micro-operation cache based on the target physical address or the target cache virtual address when the check is legal.

8. An implementation device for physical memory protection in a micro-operation cache, characterized in that, Comprising: A micro-operation cache, which is used to store multiple sets of cache data, and each set of the cache data includes a cache virtual address, a cache physical address, and cache micro-operation information; A processor instruction fetch queue, which is used to match in the micro-operation cache based on the instruction virtual address in the instruction fetch request; An MMU unit, which is used to obtain a corresponding target physical address based on the target cache virtual address when a target cache virtual address is matched from the micro-operation cache; A PMP unit, which is used to check the access permission of the target physical address; An extraction module, which is used to extract a target micro-operation from the micro-operation cache based on the target physical address or the target cache virtual address when the check is legal.

9. An electronic device, comprising: A memory, a processor, and a program stored on the memory and executable on the processor; characterized in that the processor is configured to read the program in the memory to implement the steps in the micro-operation extraction method based on physical memory protection according to any one of claims 1 to 6.

10. A readable storage medium for storing a program, characterized in that, When the program is executed by the processor, it implements the steps in the micro-operation extraction method based on physical memory protection according to any one of claims 1 to 6.

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