Instruction transmitting method, chip and storage medium

Abstract

The invention discloses an instruction transmitting method, a chip and a storage medium, and relates to the technical field of chips. The method comprises the following steps: acquiring an instruction time sequence matrix, wherein the instruction time sequence matrix is used for recording a time sequence relationship among a plurality of to-be-transmitted instructions in a transmission queue; a first instruction code is determined based on the instruction time sequence matrix, the first instruction code is used for indicating a first instruction through a coding value, and the moment when the first instruction enters a transmitting queue is earlier than that of other instructions; obtaining a ready instruction sequence, wherein the ready instruction sequence is used for indicating a plurality of ready instructions in the instructions to be transmitted; determining a first validity of the candidate transmission instruction and the first instruction based on the ready instruction sequence and the first instruction code, wherein the first validity is used for indicating an instruction state of the first instruction; and determining a target instruction from the candidate emission instruction and the first instruction based on the candidate emission instruction and the first validity for emission, thereby improving the instruction emission efficiency.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to an instruction transmission method, a chip and a storage medium. Background Art

[0002] In modern high-performance processors, the instruction emission stage is crucial. According to the order of instruction emission, it can be divided into processors with complete sequential emission and processors with out-of-order emission. For out-of-order processors, the emission logic will be much more complicated. Since the storage of instructions in the emission queue is hashed, it is necessary to select the ready instructions through the arbitration circuit. In the process of selecting the ready instructions, it is also necessary to consider the newness of the instructions. Generally speaking, the older the instructions, the higher the arbitration priority.

[0003] In the related art, a Compare Select Unit (CSU) is used to perform comparison based on a reorder buffer index vector (Robidx_Vec), where the length of the vector is the depth of the transmit queue. The age of the two instructions indicated by the reorder buffer index (Robidx) can be determined by comparing the two reorder buffer indexes (Robidx), and the oldest instruction in the vector is selected. In conjunction with the Leading One Detect (LOD) detection logic, if the candidate transmit instructions selected by the LOD detection logic include the oldest instruction, the result selected by the LOD detection logic is directly used, otherwise, the oldest instruction is used to replace an instruction selected by the LOD detection logic.

[0004] However, the above method selects the oldest instruction by comparing Robidx. When the transmission queue depth increases, the number and level of CSUs increase, the delay of the comparison logic is large, and the selected oldest instruction needs to be compared with the result selected by LOD and then merged, involving a comparison circuit. As the number of instructions transmitted in each clock cycle increases, the number of comparators will also increase, resulting in a large delay and low efficiency in the instruction arbitration process, thereby low instruction transmission efficiency. Summary of the invention

[0005] The embodiment of the present application provides an instruction transmission method, a chip and a storage medium, which can improve the efficiency of instruction transmission. The technical solution is as follows.

[0006] In one aspect, a method for transmitting an instruction is provided, the method comprising:

[0007] Obtaining an instruction timing matrix, wherein the instruction timing matrix is ​​used to record the timing relationship between multiple instructions to be issued in the issuance queue;

[0008] Determine a first instruction code based on the instruction timing matrix, the first instruction code is used to indicate a first instruction through a code value, and the first instruction enters the issue queue earlier than other instructions;

[0009] Acquire a ready instruction sequence, wherein the ready instruction sequence is used to indicate a plurality of ready instructions among the instructions to be transmitted, and the ready instructions are instructions in a ready state;

[0010] Determine first validity of candidate issuance instructions and the first instruction based on the ready instruction sequence and the first instruction code, wherein the first validity is used to indicate an instruction state of the first instruction, and the instruction state includes any one of the ready state and the not ready state;

[0011] A target instruction is determined for issuance from among the candidate issuance instructions and the first instruction based on the candidate issuance instructions and the first validity.

[0012] In another aspect, a chip is provided, comprising:

[0013] A state updating unit, used for obtaining an instruction timing matrix, wherein the instruction timing matrix is ​​used for recording a timing relationship between a plurality of instructions to be issued in an issue queue;

[0014] A reduction and unit, used for determining a first instruction code based on the instruction timing matrix, the first instruction code is used for indicating a first instruction through a code value, and a time when the first instruction enters the issue queue is earlier than other instructions;

[0015] The state updating unit is further used to obtain a ready instruction sequence, wherein the ready instruction sequence is used to indicate a plurality of ready instructions among the instructions to be transmitted, and the ready instructions are instructions belonging to a ready state;

[0016] A bitwise AND unit, used for determining first validity of a candidate issuance instruction and the first instruction based on the ready instruction sequence and the first instruction encoding, wherein the first validity is used to indicate an instruction state of the first instruction, wherein the instruction state includes any one of the ready state and the not ready state;

[0017] The selection logic unit is further configured to determine a target instruction to be issued from among the candidate issuing instructions and the first instruction based on the candidate issuing instructions and the first validity.

[0018] On the other hand, a computer-readable storage medium is provided, wherein at least one instruction, at least one program, a code set or an instruction set is stored in the storage medium, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by a processor to implement the instruction transmission method as described in any of the above-mentioned embodiments of the present application.

[0019] On the other hand, a computer program product or a computer program is provided, the computer program product or the computer program includes computer instructions, the computer instructions are stored in a computer-readable storage medium. A processor of a chip reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the chip executes the instruction transmission method described in any of the above embodiments.

[0020] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:

[0021] By determining the first instruction code for indicating the first instruction based on the instruction timing matrix, the first instruction enters the emission queue earlier than other instructions, thereby avoiding a large delay caused by using CSU to determine the first instruction. By determining the first validity of the candidate emission instruction and the first instruction based on the ready instruction sequence and the first instruction code, the candidate emission instruction determination process and the first validity determination process are processed in parallel, thereby reducing the timing delay of the two determination processes. By determining the target instruction from the candidate emission instructions and the first instruction based on the candidate emission instruction and the first validity for emission, it is avoided that the target instruction is determined by comparing the candidate emission instruction with the first instruction, resulting in a large delay in the comparison logic, thereby reducing the delay in the process of determining the target instruction and improving the instruction emission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 is a schematic diagram of the oldest instruction selection process provided by an exemplary embodiment of the present application;

[0024] Figure 2 It is a schematic diagram of an implementation environment provided by an exemplary embodiment of the present application;

[0025] Figure 3 is a flow chart of a command transmission method provided by an exemplary embodiment of the present application;

[0026] Figure 4 is a schematic diagram of an instruction timing matrix provided by an exemplary embodiment of the present application;

[0027] Figure 5 is a method flow chart of a candidate launch instruction determination process and a first validity determination process provided by an exemplary embodiment of the present application;

[0028] Figure 6 is a schematic diagram of a first validity determination method provided by an exemplary embodiment of the present application;

[0029] Figure 7 is a flow chart of a first instruction encoding determination method provided by an exemplary embodiment of the present application;

[0030] Figure 8 is a schematic diagram of a first instruction encoding acquisition method provided by an exemplary embodiment of the present application;

[0031] Fig. 9 is a flow chart of an instruction timing matrix updating method provided by an exemplary embodiment of the present application;

[0032] Fig.10 It is a schematic diagram of an instruction timing matrix update flow provided by an exemplary embodiment of the present application;

[0033] Fig.11 It is a schematic diagram of a framework of an instruction transmission method provided by an exemplary embodiment of the present application;

[0034] Fig.12 is a delay comparison schematic diagram provided by an exemplary embodiment of the present application;

[0035] Fig.13 is a schematic diagram of the position of a selection circuit provided by an exemplary embodiment of the present application;

[0036] Fig.14 is a structural block diagram of a chip provided by an exemplary embodiment of the present application;

[0037] Fig.15 is a structural block diagram of a chip provided by another exemplary embodiment of the present application;

[0038] Fig.16 It is a structural block diagram of a terminal provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0040] It should be understood that although the terms first, second, etc. may be used in the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first parameter may also be referred to as the second parameter, and similarly, the second parameter may also be referred to as the first parameter. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0041] In modern high-performance processors, the instruction issuance stage is crucial. According to the order of instruction issuance, it can be divided into processors with complete sequential issuance and processors with out-of-order issuance. For out-of-order processors, the issuance logic will be much more complicated. Since the instructions are stored in the issuance queue in a hashed manner, it is necessary to select the ready instructions through an arbitration circuit. In the process of selecting ready instructions, the newness of the instructions also needs to be considered. Generally speaking, the older the instructions, the higher the arbitration priority. In some embodiments, CSU is used to make comparisons based on Robidx_Vec, where the length of the vector is the depth of the issuance queue. The age between the two instructions indicated by the index can be determined through pairwise comparisons of Robidx, and the oldest instruction in the vector is selected. In conjunction with the LOD detection logic, if the candidate issuance instructions selected by the LOD detection logic include the oldest instruction, the result selected by the LOD detection logic is directly used. Otherwise, the oldest instruction is used to replace an instruction selected by the LOD detection logic. For illustration, please refer to Figure 1 , Figure 1 is a schematic diagram of the oldest instruction selection process provided by an exemplary embodiment of the present application, such as Figure 1 As shown, taking a transmission queue with a depth of 4 as an example, the reorder cache index vector 110 is used for 4 instructions to be transmitted in the transmission queue, wherein each transmission instruction corresponds to a reorder cache index, and two adjacent reorder cache indexes are compared in pairs by two first-level comparison and selection units to select two older instructions, and then the reorder cache indexes of the two older instructions are compared by a second-level comparison and selection unit to obtain the oldest instruction 120, and the oldest instruction 120 is used in conjunction with the LOD detection logic to determine the transmission instruction. However, the above method selects the oldest instruction by comparing Robidx. When the depth of the transmission queue increases, the number and level of CSUs increase, the delay of the comparison logic is large, and the selected oldest instruction needs to be compared with the result selected by LOD and then merged, involving a comparison circuit. As the number of instructions transmitted in each clock cycle increases, the number of comparators will also increase, resulting in a large delay and low efficiency in the instruction arbitration process, thereby low instruction transmission efficiency.

[0042] The instruction emission method provided in the embodiment of the present application determines the first instruction code for indicating the first instruction based on the instruction timing matrix. The time when the first instruction enters the emission queue is earlier than other instructions, thereby avoiding a large delay caused by using CSU to determine the first instruction. By determining the first validity of the candidate emission instruction and the first instruction based on the ready instruction sequence and the first instruction code, the parallel processing of the candidate emission instruction determination process and the first validity determination process is realized, thereby reducing the timing delay of the two determination processes. By determining the target instruction from the candidate emission instructions and the first instruction based on the candidate emission instruction and the first validity for emission, it is avoided that the target instruction is determined by comparing the candidate emission instruction with the first instruction, resulting in a large delay in the comparison logic, thereby reducing the delay in the process of determining the target instruction and improving the instruction emission efficiency.

[0043] First, let's introduce the implementation environment of this application. Figure 2 , which shows a schematic diagram of an implementation environment provided by an exemplary embodiment of the present application, and the implementation environment includes: a terminal 210.

[0044] The terminal 210 is used to perform command arbitration and transmit commands based on the command arbitration result.

[0045] In some embodiments, a chip is deployed in the terminal 210, and the chip is used to obtain an instruction stream and transmit the instructions in the instruction stream to the corresponding circuit inside the chip for processing. The chip communicates with the circuit inside the chip and passes the instruction stream to the corresponding instruction execution unit. Among them, the chip refers to a collection of electronic integrated circuits. The chip implements various functions by integrating and connecting circuits, and performs instruction processing and calculation tasks. Inside the chip, various circuits implement different functions, such as instruction decoding, register reading and writing, arithmetic and logical operations, etc. These circuits are interconnected through logic gates, clock signals, and data paths, and work together to execute instructions.

[0046] The instruction transmission method provided in the embodiment of the present application is illustrated by taking execution by a chip deployed in a terminal as an example.

[0047] Terminal 210 obtains an instruction timing matrix, which is used to record the timing relationship between multiple instructions to be transmitted in a transmission queue; determines a first instruction code based on the instruction timing matrix, and the first instruction code is used to indicate the first instruction through a code value, and the time when the first instruction enters the transmission queue is earlier than other instructions; obtains a ready instruction sequence, and the ready instruction sequence is used to indicate multiple ready instructions in the instructions to be transmitted, and the ready instruction is an instruction that belongs to a ready state; determines a first validity of a candidate transmission instruction and a first instruction based on the ready instruction sequence and the first instruction code, and the first validity is used to indicate the instruction state of the first instruction, and the instruction state includes any one of a ready state and a not ready state; determines a target instruction from the candidate transmission instructions and the first instruction based on the candidate transmission instructions and the first validity for transmission.

[0048] The above-mentioned terminal is optional. The terminal can be a desktop computer, a laptop computer, a mobile phone, a tablet computer, an e-book reader, a Moving Picture Experts Group Audio Layer III (MP3) player, a Moving Picture Experts Group Audio Layer IV (MP4) player, a smart TV, a smart car, and other forms of terminal devices, which are not limited to the embodiments of the present application.

[0049] It is worth noting that the above-mentioned servers can be independent physical servers, or they can be server clusters or distributed systems composed of multiple physical servers. They can also be cloud servers that provide basic cloud computing services such as cloud services, cloud security, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (CDN), as well as big data and artificial intelligence platforms.

[0050] Among them, cloud technology refers to a hosting technology that unifies hardware, software, network and other resources within a wide area network or local area network to achieve data computing, storage, processing and sharing.

[0051] In some embodiments, the above server can also be implemented as a node in a blockchain system.

[0052] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant regions. For example, the pending launch instructions and ready instructions involved in this application are all obtained with full authorization.

[0053] To further illustrate, before collecting relevant data of the user (for example, the pending instructions and ready instructions involved in this application, etc.) and during the process of collecting relevant data of the user, this application can display a prompt interface, pop-up window or output voice prompt information, and the prompt interface, pop-up window or voice prompt information is used to prompt the user that its relevant data is currently being collected, so that this application only starts to execute the relevant steps of obtaining relevant data of the user after obtaining the confirmation operation issued by the user to the prompt interface or pop-up window, otherwise (that is, when the confirmation operation issued by the user to the prompt interface or pop-up window is not obtained), the relevant steps of obtaining relevant data of the user are terminated, that is, the relevant data of the user is not obtained. In other words, all user data collected by this application are collected with the consent and authorization of the user, and the collection, use and processing of relevant user data need to comply with relevant laws, regulations and standards of the relevant regions.

[0054] For illustration, please refer to Figure 3 , which shows a flowchart of an instruction transmission method provided by an exemplary embodiment of the present application. The method can be executed by a terminal, or by a server, or by both a terminal and a server. The present application embodiment takes the method executed by a terminal as an example for explanation. Figure 3 As shown, the method comprises the following steps:

[0055] Step 310, obtaining the instruction timing matrix.

[0056] The instruction timing matrix is ​​used to record the timing relationship between multiple instructions to be issued in the issuance queue.

[0057] Instruction dispatch is a key process in computer architecture, which is used to send instructions from instruction queues (such as the dispatch queue) to execution units for actual execution. Depending on the design and instruction set architecture of the processor, there may be multiple execution units, such as integer units, floating point units, vector units, etc. The goal of instruction dispatch is to improve instruction-level parallelism, so that multiple instructions can be executed on different execution units at the same time, thereby improving the throughput and performance of the device.

[0058] A dispatch queue is a buffer or data structure used to store instructions to be dispatched. A dispatch queue has a queue depth, which indicates the threshold of the number of instructions to be dispatched in the dispatch queue. Each instruction to be dispatched is usually called an "entry" or "dispatch entry". Each entry in the dispatch queue contains an instruction and its related control information, such as instruction status, execution priority, dependencies, etc. This control information is used to guide the execution process of the instruction.

[0059] The instructions to be transmitted include at least one of a ready instruction and a not ready instruction.

[0060] Among them, a ready instruction is a waiting instruction whose instruction status belongs to the ready state. When the ready instruction is determined as the target instruction for transmission, it can be directly transmitted. When other external factors such as device status are not considered, the instruction can be successfully transmitted; a not ready instruction is a waiting instruction whose instruction status belongs to the not ready state. When the not ready instruction is determined as the target instruction for transmission, it cannot be directly transmitted. The not ready instruction depends on other instructions. For example, instruction A depends on instruction B. Instruction A can only be executed after instruction B is executed. In the case that instruction B is not transmitted, instruction A is a not ready instruction and cannot be successfully transmitted.

[0061] The instruction timing matrix refers to an age matrix (Age Matrix). The instruction timing matrix is ​​a binary coding matrix with a size of N*N, where N is a positive integer. The instruction timing matrix includes N matrix rows and N matrix columns.

[0062] Optionally, the size of the instruction timing matrix may be fixed or dynamically changeable.

[0063] If the size of the instruction timing matrix is ​​fixed, N is the depth of the issuance queue; if the size of the instruction timing matrix is ​​dynamically changing, N is the number of instructions to be issued in the issuance queue, and the size of the instruction timing matrix changes with the number of instructions to be issued.

[0064] The timing relationship between the multiple instructions to be issued recorded in the instruction timing matrix is ​​composed of multiple instruction age results, and the instruction age results are used to indicate the time when the instructions to be issued enter the issuance queue.

[0065] In some embodiments, the instruction timing matrix indicates the instruction age result of the instruction to be issued through the encoded values ​​corresponding to the matrix rows. For example, the i-th matrix row in the instruction timing matrix is ​​used to indicate the instruction age result corresponding to the i-th instruction to be issued in the issuance queue, where i is a positive integer.

[0066] The instruction timing matrix is ​​updated in real time based on the to-be-issued instructions in the emission queue. Optionally, the updating process of the instruction timing matrix includes updating the instruction timing matrix in response to the to-be-issued instruction entering the emission queue; or updating the instruction timing matrix in response to the to-be-issued instruction being removed from the emission queue. Wherein, after the to-be-issued instruction is determined as the target instruction to be emitted, the to-be-issued instruction is removed from the emission queue.

[0067] Step 320: Determine a first instruction encoding based on the instruction timing matrix.

[0068] The first instruction code is used to indicate the first instruction through a code value, and the first instruction enters the issue queue earlier than other instructions, that is, the first instruction is the oldest instruction in the issue queue.

[0069] The instruction timing matrix is ​​an age matrix with a size of N*N, where N is a positive integer, and the instruction timing matrix includes N matrix rows and N matrix columns.

[0070] Optionally, the size of the instruction timing matrix may be fixed or dynamically changeable.

[0071] If the size of the instruction timing matrix is ​​fixed, N is the depth of the issue queue; if the size of the instruction timing matrix is ​​dynamically changing, N is the number of instructions to be issued in the issue queue, and the size of the instruction timing matrix changes with the number of instructions to be issued. Take the example that the size of the instruction timing matrix is ​​fixed and N is the depth of the issue queue.

[0072] The timing relationship between the multiple instructions to be issued recorded in the instruction timing matrix is ​​composed of multiple instruction age results, and the instruction age results are used to indicate the time when the instructions to be issued enter the issuance queue.

[0073] In some embodiments, the instruction timing matrix indicates the instruction age result of the instruction to be issued through the encoded values ​​corresponding to the matrix rows. For example, when entry i in the issuance queue is assigned to a newly enqueued instruction, the i-th matrix row in the instruction timing matrix is ​​used to indicate the instruction age result corresponding to the instruction to be issued corresponding to entry i, where i is a positive integer.

[0074] In some embodiments, step 320 includes the following two steps:

[0075] In the first step, multiple instruction age results are obtained based on each matrix row of the instruction timing matrix.

[0076] Among them, the i-th matrix row is used to record the timing relationship of the i-th instruction to be issued in the issuance queue, and the i-th instruction age result obtained based on the i-th matrix row is used to indicate the moment when the i-th instruction to be issued enters the issuance queue, and i is a positive integer.

[0077] For illustration, please refer to Figure 4 , Figure 4 FIG. 1 is a schematic diagram of an instruction timing matrix provided by an exemplary embodiment of the present application. Figure 4 As shown, the size of the instruction timing matrix 400 is 4*4, wherein the encoding sequence 0000 corresponding to the first matrix row is used to indicate the instruction age result of the instruction to be issued corresponding to the emission item (entry) 0 in the emission queue, the second matrix row 1111 is used to indicate the instruction age result of the instruction to be issued corresponding to entry1 in the emission queue, the third matrix row 1010 is used to indicate the instruction age result of the instruction to be issued corresponding to entry2 in the emission queue, and the fourth matrix row 1011 is used to indicate the instruction age result of the instruction to be issued corresponding to entry3 in the emission queue.

[0078] In some embodiments, each matrix row corresponds to a binary code sequence, and a reduction and (Reduce And) operation is performed on the code sequence corresponding to each matrix row to obtain multiple instruction age results. The reduction and operation refers to performing an AND operation on each bit in a vector to obtain a result of one bit. For example, the result of the reduction and operation of the binary vector 0110 is 0, and the result of the reduction and operation of the binary vector 1111 is 1.

[0079] Indicative, such as Figure 4 As shown, the coding sequence corresponding to each matrix row in the instruction timing matrix 400 is bitwise ANDed to obtain multiple instruction age results. For example, the coding sequence 0000 corresponding to the first matrix row is reduced and operated to obtain the instruction age result corresponding to entry (transmitted item) 0, which is 0; the coding sequence 1111 corresponding to the second matrix row is reduced and operated to obtain the instruction age result corresponding to entry1, which is 1; the coding sequence 1010 corresponding to the third matrix row is reduced and operated to obtain the instruction age result corresponding to entry2, which is 0; the coding sequence 1011 corresponding to the fourth matrix row is reduced and operated to obtain the instruction age result corresponding to entry3, which is 0. Among them, the instruction age result corresponding to the second matrix row is 1, that is, the time when the instruction to be transmitted corresponding to entry1 enters the transmission queue is earlier than other instructions to be transmitted.

[0080] In the second step, in response to the i-th instruction age result meeting the instruction age requirement, the i-th instruction to be issued is determined as the first instruction, and a first instruction code is determined based on the first instruction.

[0081] In some embodiments, the instruction age requirement includes an instruction age result being a preset first value, in response to the i-th instruction age result being the first value, determining the i-th instruction to be issued as a first instruction, and determining a first instruction encoding based on the first instruction.

[0082] Among them, the first value is 1. When the coding sequence of the i-th matrix row in the instruction timing matrix is ​​all 1, that is, the instruction age result obtained by reducing and operating the coding sequence of the i-th matrix row is 1, then the i-th instruction to be issued corresponding to the i-th matrix row is the first instruction.

[0083] The first instruction encoding is a one-hot code, and the onehot signal is a coding vector in which only one bit is 1 and the rest of the bits are 0. Assuming that the i-th instruction to be issued is the first instruction, the first instruction encoding is determined based on the first instruction, and the encoding value of the i-th bit from right to left in the n-bit binary encoding vector is set to the first value (1), and the encoding values ​​of the rest of the bits are set to the second value (0), to obtain the first instruction encoding.

[0084] Indicative, such as Figure 4 As shown, in response to the instruction age result of the coding sequence 1111 corresponding to the second matrix row in the instruction timing matrix 400 being 1, which meets the instruction age requirement, the second instruction to be issued corresponding to entry1 is determined to be the first instruction, and the coding value of the second bit from right to left in the 4-bit binary coding vector is set to 1, and the coding values ​​of the remaining bits are set to 0, thereby obtaining the first instruction code 0010, which is used to indicate that the second instruction to be issued in the emission queue is the first instruction.

[0085] Step 330, obtaining a ready instruction sequence.

[0086] The ready instruction sequence is used to indicate a plurality of ready instructions among the instructions to be issued, and the ready instructions are instructions in a ready state.

[0087] Ready Instruction refers to an instruction in computer architecture that has met the execution conditions and is ready to be executed. Ready instructions usually refer to those instructions that have completed all preconditions and dependencies before execution and are no longer restricted by any waiting factors. In an instruction level parallelism (ILP) processor, multiple instructions can be executed on different execution units at the same time to improve the performance of the processor. In order to achieve instruction level parallelism, the processor needs to manage the scheduling and issuance of instructions through an emission queue or similar mechanism. When all the preconditions of an instruction in the emission queue are met, it is considered a ready instruction. This means that the operands required by the instruction are ready and are no longer affected by the dependencies or competition conditions of other instructions. Ready instructions can be immediately issued to the available execution units for actual computing operations.

[0088] In some embodiments, the device determines ready instructions from the transmit queue based on factors such as instruction dependencies, and generates a ready instruction sequence based on the ready instructions, and indicates multiple ready instructions through the ready instruction sequence.

[0089] In some embodiments, the ready instruction sequence is implemented as a binary encoding vector, denoted as valid_vec, wherein encoding bits with encoding values ​​of 1 are used to indicate ready instructions, and encoding bits with encoding values ​​of 0 are used to indicate not ready instructions.

[0090] Illustratively, assume that the transmit queue includes 4 instructions to be transmitted, and the ready instruction sequence is 1010, in which the second and fourth bits from right to left are 1, indicating that the second and fourth instructions to be transmitted in the transmit queue are ready instructions.

[0091] Step 340 , determining first validity of the candidate issue instruction and the first instruction based on the ready instruction sequence and the first instruction encoding.

[0092] The first validity is used to indicate the instruction state of the first instruction, and the instruction state includes any one of a ready state and a not ready state.

[0093] Step 340 includes a process of determining the candidate transmission quality and a process of determining the first validity, and the two processes are in a parallel independent relationship, that is, the process of determining the candidate transmission quality and the process of determining the first validity can be processed in parallel.

[0094] In some embodiments, step 340 includes the following two steps:

[0095] In the first step, a candidate issuing instruction is determined based on the ready instruction sequence and a first inverted code corresponding to the first instruction code.

[0096] The first inverted code is a code sequence obtained by inverting the code value in the first instruction code. The first inverted code is used to indicate other instructions to be issued except the first instruction.

[0097] Illustratively, taking the first instruction code of 0100 as an example, the first instruction code is used to indicate that the third instruction to be issued in the emission queue is the first instruction. The bitwise inversion operation is performed on the code value in the first instruction code to obtain the first inverted code of 1011, and the first inverted code is used to indicate the 1st, 2nd, and 4th instructions to be issued in the emission queue.

[0098] In some embodiments, the process of determining the candidate transmission quality is implemented by performing a bitwise inversion operation on the first instruction code to obtain a first inversion code; performing a bitwise AND operation on the ready instruction sequence and the first inversion code to obtain a candidate instruction sequence, where the candidate instruction sequence is used to indicate candidate instructions other than the first instruction in the ready instructions; and determining candidate transmission instructions based on the candidate instruction sequence.

[0099] Illustratively, taking the first inverted code as 1011 and the ready instruction sequence as 1111 as an example, a bitwise AND operation is performed on the ready instruction sequence 1111 and the first inverted code 1011 to obtain a candidate instruction sequence 1011, which is used to indicate that the 1st, 2nd, and 4th instructions to be issued in the emission queue are candidate instructions among the ready instructions.

[0100] In some embodiments, determining a candidate transmit instruction based on a candidate instruction sequence is implemented by performing an odd-even deinterleaving operation on the candidate instruction sequence to obtain an odd instruction sequence and an even instruction sequence, wherein the odd instruction sequence is used to indicate the 2k-1th ready instruction, and the even instruction sequence is used to indicate the 2kth ready instruction, where k is a positive integer; determining a first candidate transmit instruction based on the odd instruction sequence and determining a second candidate transmit instruction based on the even instruction sequence according to a preset selection logic.

[0101] The parity deinterleaving operation is used to separate the odd-numbered bit codes from the even-numbered bit codes in the candidate instruction sequence.

[0102] Taking the encoding order from right to left as an example for explanation, schematically, the candidate instruction sequence 1011 is subjected to an odd-even deinterleaving operation to obtain an odd instruction sequence 0001 and an even instruction sequence 1010. The odd instruction sequence is used to indicate the 1st and 3rd ready instructions, wherein the 1st bit is encoded as 1 to indicate that the 1st instruction to be transmitted is the 1st ready instruction, and the 3rd bit is encoded as to indicate that the 3rd ready instruction is empty; the even instruction sequence is used to indicate the 2nd and 4th ready instructions, wherein the 2nd and 4th bits are both encoded as 1 to indicate that the 2nd and 4th instructions to be transmitted are ready instructions.

[0103] In some embodiments, the preset selection logic is LOD logic, which is used to select the first coded bit with a coded value of 1 from right to left in the binary code.

[0104] Illustratively, according to the preset selection logic based on the odd instruction sequence 0001, the first coding bit with a coding value of 1 from right to left is selected as the first bit from left to right, and the first instruction to be issued (ready instruction) in the emission queue is determined to be the first candidate emission instruction; according to the preset selection logic based on the even instruction sequence 1010, the first coding bit with a coding value of 1 from right to left is selected as the fourth bit from left to right, and the fourth instruction to be issued in the emission queue is determined to be the second candidate emission instruction.

[0105] In a second step, a first validity is determined based on the ready instruction sequence and the first instruction encoding.

[0106] The process of determining the candidate emission quality and the process of determining the first validity are in a parallel and independent relationship.

[0107] The first validity is used to indicate an instruction state of the first instruction, where the instruction state includes at least one of a ready state and a not ready state.

[0108] In some embodiments, the first validity is determined by determining whether the ready instruction includes the first instruction. When the first instruction is included in multiple ready instructions, the first validity indicates that the first instruction is a ready instruction. When the first instruction is not included in multiple ready instructions, the first validity indicates that the first instruction is a not ready instruction.

[0109] In some embodiments, the ready instruction sequence and the first instruction code are binary code sequences, and determining the first validity based on the ready instruction sequence and the first instruction code is implemented by performing a bitwise AND operation on the ready instruction sequence and the first instruction code to obtain a first valid code, and the first valid code is used to indicate the inclusion of the first instruction in the ready instruction; reducing or operating the first valid code to obtain a first valid result, and the first valid result is used to indicate the first validity; and determining the first validity based on the first valid result.

[0110] In response to the first valid result being a first value, determining that the first validity indicates that the first instruction is in a ready state; and in response to the first valid result being a second value, determining that the first validity indicates that the first instruction is in a not ready state. The first value is 1, and the second value is 0.

[0111] Illustratively, a bitwise AND operation is performed on the ready instruction sequence 1111 and the first instruction code 0100 to obtain a first valid code 0100, and a reduction or operation is performed on the first valid code 0100 to obtain a first valid result of 1. In response to the first valid result being 1, it is determined that the first validity indication indicates that the first instruction is in a ready state.

[0112] Step 350 , determining a target instruction to be issued from the candidate issuing instructions and the first instruction based on the candidate issuing instructions and the first validity.

[0113] In some embodiments, step 350 includes the following two situations:

[0114] First, in response to a first validity indication that the first instruction belongs to a ready state, the first instruction is determined as a target instruction for issuance;

[0115] Second, in response to the first validity indication that the first instruction is in a not-ready state, the candidate issuing instruction is determined as the target instruction for issuing.

[0116] In which, when the ready instruction includes the first instruction, the first validity indicates that the first instruction is in a ready state; when the ready instruction includes the first instruction, the first validity indicates that the first instruction is in a not ready state.

[0117] In some embodiments, the device simultaneously determines multiple target instructions for transmission.

[0118] Taking the example of simultaneously determining two target instructions for transmission, when performing an odd-even deinterleaving operation on the candidate instruction sequence, the first candidate transmission instruction is determined based on the odd instruction sequence, and the second candidate transmission instruction is determined based on the even instruction sequence according to the preset selection logic. Then step 350 is implemented as follows: the first candidate transmission instruction is determined as the first target instruction for transmission, and the second target instruction is determined to be transmitted based on the second candidate transmission instruction and the first validity; or, the second candidate transmission instruction is determined as the first target instruction for transmission, and the second target instruction is determined to be transmitted based on the first candidate transmission instruction and the first validity.

[0119] Wherein, determining the second target instruction for emission based on the second candidate emission instruction and the first validity includes: in response to the first validity indicating that the first instruction belongs to the ready state, determining the first instruction as the second target instruction for emission, or, in response to the first validity indicating that the first instruction belongs to the not ready state, determining the second candidate emission instruction as the second target instruction for emission. Determining the second target instruction for emission based on the first candidate emission instruction and the first validity includes: in response to the first validity indicating that the first instruction belongs to the ready state, determining the first instruction as the second target instruction for emission, or, in response to the first validity indicating that the first instruction belongs to the not ready state, determining the first candidate emission instruction as the second target instruction for emission.

[0120] To summarize, the method provided in the embodiment of the present application determines the first instruction code for indicating the first instruction based on the instruction timing matrix. The time when the first instruction enters the transmission queue is earlier than other instructions, thereby avoiding a large delay caused by using CSU to determine the first instruction. By determining the first validity of the candidate transmission instruction and the first instruction based on the ready instruction sequence and the first instruction code, the parallel processing of the candidate transmission instruction determination process and the first validity determination process is realized, thereby reducing the timing delay of the two determination processes. By determining the target instruction from the candidate transmission instructions and the first instruction based on the candidate transmission instruction and the first validity for transmission, it is avoided that the target instruction is determined by comparing the candidate transmission instruction and the first instruction, resulting in a large delay in the comparison logic, thereby reducing the delay in the process of determining the target instruction and improving the instruction transmission efficiency.

[0121] The method provided in the embodiment of the present application determines the first instruction as the target instruction for emission in response to the first validity indication that the first instruction is in a ready state; or, in response to the first validity indication that the first instruction is in a not ready state, determines the candidate emission instruction as the target instruction for emission. The method clarifies the method for determining the target instruction from the first instruction and the candidate emission instructions based on the first validity. While ensuring the priority emission of the first instruction, it avoids the situation where the first instruction is determined as the target instruction for emission when the first instruction is in a not ready state, resulting in instruction emission failure and waste of computing resources, thereby improving the instruction emission efficiency.

[0122] The method provided in the embodiment of the present application determines the first candidate emission instruction as the first target instruction for emission, and determines the second target instruction for emission based on the second candidate emission instruction and the first validity; or determines the second candidate emission instruction as the first target instruction for emission, and determines the second target instruction for emission based on the first candidate emission instruction and the first validity. It is clarified that when two instructions are emitted at the same time, it is possible to ensure that the first instruction is emitted first and the emission efficiency of other ready instructions is guaranteed, thereby improving the instruction emission efficiency as a whole.

[0123] Please refer to Figure 5 , Figure 5 is a method flow chart of a candidate launch instruction determination process and a first validity determination process provided by an exemplary embodiment of the present application, such as Figure 5 As shown, the method can be executed by a terminal, or by a server, or by both a terminal and a server. The embodiment of the present application takes the method executed by a terminal as an example for explanation. The above step 340 includes the following steps:

[0124] Step 341 , determining a candidate issuing instruction based on the ready instruction sequence and a first inverted code corresponding to the first instruction code.

[0125] The first inverted code is a code sequence obtained by inverting the code value in the first instruction code. The first inverted code is used to indicate other instructions to be issued except the first instruction.

[0126] Illustratively, taking the first instruction code of 0100 as an example, the first instruction code is used to indicate that the third instruction to be issued in the emission queue is the first instruction. The bitwise inversion operation is performed on the code value in the first instruction code to obtain the first inverted code of 1011, and the first inverted code is used to indicate the 1st, 2nd, and 4th instructions to be issued in the emission queue.

[0127] In some embodiments, the process of determining the candidate transmission quality includes the following three steps:

[0128] The first step is to perform a bitwise inversion operation on the first instruction code to obtain a first inverted code.

[0129] Since the first instruction is encoded as a one-hot code, the first instruction is indexed by the encoding bit with a value of 1. Assuming that the first instruction is encoded as an n-bit binary code, the i-th encoding bit in the first instruction encoding has a value of 1, which indicates that the i-th instruction to be issued in the emission queue with a depth of n is the first instruction. Then, the first instruction encoding is bitwise inverted, and the first inverted encoding obtained can index other instructions to be issued except the first instruction through the encoding bit with a value of 1.

[0130] In the second step, a bitwise AND operation is performed on the ready instruction sequence and the first inverted code to obtain a candidate instruction sequence, where the candidate instruction sequence is used to indicate candidate instructions other than the first instruction in the ready instructions.

[0131] The ready instruction sequence indexes the ready instructions in the transmission queue through the coding bit with a value of 1. Assuming that the ready instruction sequence is an n-bit binary code, the i-th coding bit in the ready instruction sequence has a value of 1 to indicate that the i-th instruction to be transmitted in the transmission queue is a ready instruction. Then, by performing a bitwise AND operation on the ready instruction sequence and the first inverted code, the obtained candidate instruction sequence can index other instructions to be transmitted except the first instruction through the coding bit with a value of 1, thereby excluding the first instruction from the candidate transmission instructions, avoiding duplication of the candidate transmission instructions determined based on the leading one logic with the first instruction, and improving the instruction transmission efficiency.

[0132] The third step is to determine candidate emission instructions based on the candidate instruction sequence.

[0133] Illustratively, taking the first inverted code as 1011 and the ready instruction sequence as 1111 as an example, a bitwise AND operation is performed on the ready instruction sequence 1111 and the first inverted code 1011 to obtain a candidate instruction sequence 1011, which is used to indicate that the 1st, 2nd, and 4th instructions to be issued in the emission queue are candidate instructions among the ready instructions.

[0134] In some embodiments, determining a candidate transmit instruction based on a candidate instruction sequence is implemented by performing an odd-even deinterleaving operation on the candidate instruction sequence to obtain an odd instruction sequence and an even instruction sequence, wherein the odd instruction sequence is used to indicate the 2k-1th ready instruction, and the even instruction sequence is used to indicate the 2kth ready instruction, where k is a positive integer; determining a first candidate transmit instruction based on the odd instruction sequence and determining a second candidate transmit instruction based on the even instruction sequence according to a preset selection logic.

[0135] The parity deinterleaving operation is used to separate the odd-numbered bit codes from the even-numbered bit codes in the candidate instruction sequence.

[0136] Taking the encoding order from right to left as an example for explanation, schematically, the candidate instruction sequence 1011 is subjected to an odd-even deinterleaving operation to obtain an odd instruction sequence 0001 and an even instruction sequence 1010. The odd instruction sequence is used to indicate the 1st and 3rd ready instructions, wherein the 1st bit is encoded as 1 to indicate that the 1st instruction to be transmitted is the 1st ready instruction, and the 3rd bit is encoded as to indicate that the 3rd ready instruction is empty; the even instruction sequence is used to indicate the 2nd and 4th ready instructions, wherein the 2nd and 4th bits are both encoded as 1 to indicate that the 2nd and 4th instructions to be transmitted are ready instructions.

[0137] In some embodiments, the preset selection logic is LOD logic, which is used to select the first coded bit with a coded value of 1 from right to left in the binary code.

[0138] Illustratively, according to the preset selection logic based on the odd instruction sequence 0001, the first coding bit with a coding value of 1 from right to left is selected as the first bit from left to right, and the first instruction to be issued (ready instruction) in the emission queue is determined to be the first candidate emission instruction; according to the preset selection logic based on the even instruction sequence 1010, the first coding bit with a coding value of 1 from right to left is selected as the fourth bit from left to right, and the fourth instruction to be issued in the emission queue is determined to be the second candidate emission instruction.

[0139] Step 342 , determining a first validity based on the ready instruction sequence and the first instruction encoding.

[0140] The process of determining the candidate emission quality and the process of determining the first validity are in a parallel and independent relationship.

[0141] The first validity is used to indicate an instruction state of the first instruction, where the instruction state includes at least one of a ready state and a not ready state.

[0142] In some embodiments, the first validity is determined by determining whether the ready instruction includes the first instruction. When the first instruction is included in multiple ready instructions, the first validity indicates that the first instruction is a ready instruction. When the first instruction is not included in multiple ready instructions, the first validity indicates that the first instruction is a not ready instruction.

[0143] In some embodiments, the ready instruction sequence and the first instruction code are binary code sequences, and determining the first validity based on the ready instruction sequence and the first instruction code is implemented by performing a bitwise AND operation on the ready instruction sequence and the first instruction code to obtain a first valid code, and the first valid code is used to indicate the inclusion of the first instruction in the ready instruction; reducing or operating the first valid code to obtain a first valid result, and the first valid result is used to indicate the first validity; and determining the first validity based on the first valid result.

[0144] In response to the first valid result being a first value, determining that the first validity indicates that the first instruction is in a ready state; and in response to the first valid result being a second value, determining that the first validity indicates that the first instruction is in a not ready state. The first value is 1, and the second value is 0.

[0145] Illustratively, a bitwise AND operation is performed on the ready instruction sequence 1111 and the first instruction code 0100 to obtain a first valid code 0100, and a reduction or operation is performed on the first valid code 0100 to obtain a first valid result of 1. In response to the first valid result being 1, it is determined that the first validity indication indicates that the first instruction is in a ready state.

[0146] For illustration, please refer to Figure 6 , Figure 6 is a schematic diagram of a first validity determination method provided by an exemplary embodiment of the present application, such as Figure 6As shown, a bitwise AND operation is performed on the ready instruction sequence 611 (1101) and the first instruction code 612 (0100) to obtain a first valid code 613 (0100), wherein the first instruction code 612 is used to indicate that the third instruction to be issued in the emission queue is the first instruction, and the first valid code 613 is reduced or operated to obtain a first valid result 614 (1). In response to the first valid result 614 being 1, it is determined that the first validity 614 indicates that the first instruction (the third emission instruction in the emission queue) is in a ready state. A bitwise AND operation is performed on the ready instruction sequence 621 (1101) and the first instruction code 622 (0010) to obtain a first valid code 623 (0000), wherein the first instruction code 622 is used to indicate that the second instruction to be issued in the emission queue is the first instruction. The first valid code 623 is reduced or operated to obtain a first valid result 624 (0). In response to the first valid result 624 being 0, it is determined that the first validity 624 indicates that the first instruction (the second emission instruction in the emission queue) is in a not ready state.

[0147] To summarize, the method provided in the embodiment of the present application determines the candidate emission instruction based on the first inverted code corresponding to the ready instruction sequence and the first instruction code, and determines the first validity of the first instruction based on the ready instruction sequence and the first instruction code, thereby realizing parallel processing of the determination process of the candidate emission instruction and the determination process of the first validity, reducing the timing delay between the two determination processes, improving the determination efficiency of the candidate emission instruction and the first validity, and thus improving the instruction emission efficiency.

[0148] The method provided in the embodiment of the present application obtains a candidate instruction sequence by performing a bitwise AND operation on the ready instruction sequence and the first inverted code, excludes the first instruction, and avoids the situation where the candidate emission instructions determined from the ready instructions based on the candidate instruction sequence are repeated with the first instruction, thereby avoiding repeated emission of the same instruction, improving the determination efficiency of the target instruction, and thus improving the instruction emission efficiency.

[0149] The method provided in the embodiment of the present application performs an odd-even deinterleaving operation on the candidate instruction sequence to decompose the candidate instruction sequence into an odd instruction sequence and an even instruction sequence, thereby determining a first candidate emission instruction and a second candidate emission instruction in two parallel branches based on the odd instruction sequence and the even instruction sequence, respectively. When the device is capable of simultaneously transmitting multiple instructions, the parallelism of the candidate emission instruction determination process is improved while avoiding instruction duplication, thereby improving the instruction emission efficiency.

[0150] Please refer to Figure 7 , Figure 7 is a flow chart of a first instruction encoding determination method provided by an exemplary embodiment of the present application, such as Figure 7As shown, the method can be executed by a terminal, or by a server, or by both a terminal and a server. The embodiment of the present application takes the method executed by a terminal as an example for explanation. The above step 320 includes the following steps:

[0151] Step 321 , obtaining a plurality of instruction age results based on each matrix row of the instruction timing matrix.

[0152] The i-th matrix row is used to record the timing relationship of the i-th instruction to be issued in the emission queue, and the i-th instruction age result obtained based on the i-th matrix row is used to indicate the time when the i-th instruction to be issued enters the emission queue, and i is a positive integer;

[0153] Indicative, such as Figure 4 As shown, the size of the instruction timing matrix 400 is 4*4, wherein the encoding sequence 0000 corresponding to the first matrix row is used to indicate the instruction age result of the instruction to be issued corresponding to entry0 in the emission queue, the second matrix row 1111 is used to indicate the instruction age result of the instruction to be issued corresponding to entry1 in the emission queue, the third matrix row 1010 is used to indicate the instruction age result of the instruction to be issued corresponding to entry2 in the emission queue, and the fourth matrix row 1011 is used to indicate the instruction age result of the instruction to be issued corresponding to entry3 in the emission queue.

[0154] In some embodiments, each matrix row corresponds to a binary code sequence, and the code sequence corresponding to each matrix row is reduced and operated respectively to obtain multiple instruction age results. The reduction and operation refers to performing an AND operation on each bit in a vector to obtain a result of one bit, for example, the result of the reduction and operation of the binary vector 0110 is 0, and the result of the reduction and operation of the binary vector 1111 is 1.

[0155] Indicative, such as Figure 4 As shown, the coding sequence corresponding to each matrix row in the instruction timing matrix 400 is bitwise ANDed to obtain multiple instruction age results. For example, the coding sequence 0000 corresponding to the first matrix row is reduced and operated to obtain the instruction age result corresponding to entry0 as 0, the coding sequence 1111 corresponding to the second matrix row is reduced and operated to obtain the instruction age result corresponding to entry1 as 1, the coding sequence 1010 corresponding to the third matrix row is reduced and operated to obtain the instruction age result corresponding to entry2 as 0, the coding sequence 1011 corresponding to the fourth matrix row is reduced and operated to obtain the instruction age result corresponding to entry3 as 0, wherein the instruction age result corresponding to the second matrix row is 1, that is, the time when the instruction to be issued corresponding to entry1 enters the issuance queue is earlier than other instructions to be issued.

[0156] Step 322 , in response to the i th instruction age result meeting the instruction age requirement, determining the i th instruction to be issued as the first instruction, and determining a first instruction code based on the first instruction.

[0157] In some embodiments, the instruction age requirement includes an instruction age result being a preset first value, in response to the i-th instruction age result being the first value, determining the i-th instruction to be issued as a first instruction, and determining a first instruction encoding based on the first instruction.

[0158] Among them, the first value is 1. When the coding sequence of the i-th matrix row in the instruction timing matrix is ​​all 1, that is, the instruction age result obtained by reducing and operating the coding sequence of the i-th matrix row is 1, then the i-th instruction to be issued corresponding to the i-th matrix row is the first instruction.

[0159] The first instruction encoding is a onehot signal, which is a coding vector with only one bit being 1 and the rest being 0. Assuming that the i-th instruction to be issued is the first instruction, the first instruction encoding is determined based on the first instruction as follows: the encoding value of the i-th bit from right to left in the n-bit binary encoding vector is set to the first value (1), and the encoding values ​​of the rest are set to the second value (0), to obtain the first instruction encoding.

[0160] Indicatively, Figure 4 As shown, in response to the instruction age result of the coding sequence 1111 corresponding to the second matrix row in the instruction timing matrix 400 being 1, which meets the instruction age requirement, the second instruction to be issued corresponding to entry1 is determined to be the first instruction, and the coding value of the second bit from right to left in the 4-bit binary coding vector is set to 1, and the coding values ​​of the remaining bits are set to 0, thereby obtaining the first instruction code 0010, which is used to indicate that the second instruction to be issued in the emission queue is the first instruction.

[0161] For illustration, please refer to Figure 8 , Figure 8 is a schematic diagram of a first instruction encoding acquisition method provided by an exemplary embodiment of the present application, such as Figure 8 As shown, the instruction timing matrix 810 is obtained, and each matrix row of the instruction timing matrix is ​​reduced and operated to obtain four instruction age results, which are 0, 1, 0, and 0 respectively. The four instruction age results are merged to obtain the first instruction code 0010, which is used to indicate that the second instruction to be issued in the issuance queue is the first instruction.

[0162] In some embodiments, after obtaining the first instruction code, a binary conversion (Onehot To Binary, Oh2bin) operation is performed on the first instruction code to obtain a first identification code, thereby reducing the number of coding bits used to indicate the first instruction and saving data resources. The Oh2bin operation is used to represent the coding bits with a code value of 1 in Onehot with a binary number, for example, 001000, where 1 is in the third position (counting from right to left, starting from 0), and the result of Oh2bin is 011, which is 3 in decimal. It is also possible to count from right to left, starting from 1, and this application is not limited to this.

[0163] In summary, the method provided in the embodiment of the present application obtains multiple instruction age results based on each matrix row of the instruction timing matrix, and determines the first instruction based on the instruction age results that meet the instruction age requirements. A method for determining the first instruction is provided, avoiding the large delay caused by using CSU to determine the first instruction, and can adapt to a large number of instructions to be issued without using multiple levels of CSU to determine the first instruction, thereby saving computing resources and improving the efficiency of determining the first instruction.

[0164] The method provided in the embodiment of the present application obtains multiple instruction age results by reducing or operating the coding sequence corresponding to each matrix row, determines the first instruction based on the instruction age result of the first value, and provides a method for determining the first instruction. The comparison process of the CSU is replaced by the reduction or operation based on the instruction timing matrix. Since the reduction or operation is a bit operation, the delay in the chip circuit is small, which can reduce the delay in determining the first instruction, reduce the data processing amount, and improve the efficiency of determining the first instruction.

[0165] Please refer to Fig. 9 , Fig. 9 1 is a flow chart of an instruction timing matrix updating method provided by an exemplary embodiment of the present application. The method can be executed by a terminal, or by a server, or by both a terminal and a server. The present application embodiment takes the method executed by a terminal as an example for explanation. Fig. 9 As shown, before the above step 320, an instruction timing matrix updating process is also included, and the process includes the following steps:

[0166] Step 910: in response to the jth instruction to be issued entering the issue queue, update the instruction timing matrix.

[0167] In some embodiments, the matrix rows and the matrix columns in the instruction timing matrix correspond to binary encoding vectors respectively.

[0168] Before updating the instruction timing matrix, an initialized instruction timing matrix is ​​created according to the issue queue depth, and the encoding value of the initialized instruction timing matrix is ​​0.

[0169] Optionally, step 910 includes the following three steps:

[0170] The first step is to obtain a first encoding vector corresponding to the j-th matrix column in the instruction timing matrix in response to the j-th instruction to be issued entering the issuance queue.

[0171] Wherein, j is a positive integer, j<n, and n is the depth of the transmission queue.

[0172] Taking the initialized 4*4 instruction timing matrix as an example, in response to the first instruction to be issued entering the issuance queue, the first encoding vector corresponding to the first matrix column in the instruction timing matrix is ​​obtained as 0000.

[0173] In the second step, the first coding vector is bitwise inverted to obtain the second coding vector.

[0174] Illustratively, taking the above-mentioned first coding vector 0000 as an example, a bitwise inversion operation is performed on the first coding vector 0000 to obtain a second coding vector of 1111.

[0175] The third step is to assign the second encoding vector to the j-th matrix row in the instruction timing matrix.

[0176] Illustratively, the second encoding vector 1111 is assigned to the first matrix row in the instruction timing matrix, and the encoding value corresponding to the first matrix row is 1111.

[0177] Step 920 : In response to the jth instruction to be issued being removed from the issue queue, update the instruction timing matrix.

[0178] Wherein, j is a positive integer, j<n, and n is the depth of the transmission queue.

[0179] When the to-be-issued instruction is determined as a target instruction to be issued, the issued instruction is removed from the issue queue.

[0180] In some embodiments, the matrix rows and the matrix columns in the instruction timing matrix correspond to binary encoding vectors respectively.

[0181] Optionally, step 920 is implemented by, in response to the jth instruction to be issued being removed from the issuance queue, setting the jth matrix column in the instruction timing matrix to a first value and setting the jth matrix row in the instruction timing matrix to a second value according to a preset rule.

[0182] Among them, the first value is 1 and the second value is 0.

[0183] The preset rule is used to indicate that when assigning values ​​to the matrix columns based on the dequeue status of the to-be-issued instructions, the encoding position of the to-be-issued instruction in the j-th matrix column is taken as the first value.

[0184] For illustration, please refer to Fig.10 , Fig.10 FIG. 1 is a schematic diagram of an instruction timing matrix update flow chart provided by an exemplary embodiment of the present application. Fig.10 As shown, in the initial state, the entire instruction timing matrix is ​​0, and the matrix rows and columns are sorted with natural numbers starting from 0. Assuming that the emission item (entry) 1 is assigned to the queue, the first column is bit-inverted and updated to the first row. The first column is 0000, and the bit-inverted value is 1111. Therefore, after entry1 is queued, the first row is 1; entry3 is queued, and the third column is read as 0100, which is bit-inverted to 1011 and assigned to the third row; entry2 is queued , read the second column as 0101, and after bitwise inversion, it is 1010, which is assigned to the second row; entry1 is dequeued, the first row is cleared, and the elements in the first column that are 0 are set to 1 (as shown by the bold grid points in the figure). Since there is no instruction in entry0, it is not set to 1, and the position of the 0th row and 1st column is also 0; entry2 is dequeued, the second row is cleared, and since the position of the 3rd row and the 2nd column is already 1, there is no need to change it; entry3 is dequeued, and the 3rd row is cleared. Fig.10 As shown, when all elements of a row are 1, the entry corresponding to the row corresponds to the first instruction. If the i-th column in the j-th row is 0, it means that entry i is queued before the j-th row, and the entry corresponding to the j-th row is not the first instruction yet.

[0185] To summarize, the method provided in the embodiment of the present application updates the instruction timing matrix according to the situation where the instruction to be issued enters the emission queue or the instruction to be issued is removed from the emission queue, clarifies the updating method of the instruction timing matrix, and ensures that the timing relationship recorded by the instruction timing matrix is ​​consistent with the actual situation of the instruction to be issued in the emission queue, thereby improving the accuracy of determining the first instruction.

[0186] The method provided in the embodiment of the present application obtains the first coding vector corresponding to the j-th matrix column in the instruction timing matrix in response to the j-th instruction to be issued entering the emission queue; performs a bitwise inversion operation on the first coding vector to obtain a second coding vector; and assigns the second coding vector to the j-th matrix row in the instruction timing matrix. This clarifies the method of updating the instruction timing matrix based on the situation of the instruction to be issued entering the emission queue, improves the efficiency of timing recording of the latest instruction to be issued that enters the emission queue, and thus improves the accuracy of determining the first instruction.

[0187] The method provided in the embodiment of the present application, in response to the jth instruction to be issued being removed from the emission queue, sets the encoding value corresponding to the jth matrix column in the instruction timing matrix to the first value according to a preset rule, and sets the encoding value corresponding to the jth matrix row in the instruction timing matrix to the second value. This clarifies the method for updating the instruction timing matrix based on the situation where the instruction to be issued is removed from the emission queue, avoids the problem of participating in the target instruction determination process after the instruction is still determined as the first instruction after being removed from the emission queue, thereby improving the accuracy of determining the first instruction and improving the efficiency of instruction emission.

[0188] For illustration, please refer to Fig.11 , Fig.11 FIG. 1 is a schematic diagram of a framework of an instruction transmission method provided by an exemplary embodiment of the present application. Fig.11 As shown, in combination with the above steps 310-350, taking the terminal executing the instruction transmission method provided by the embodiment of the present application as an example, the terminal transmits instructions according to the following process: the terminal obtains the instruction timing matrix 1110, reduces and operates each matrix row in the instruction timing matrix to obtain multiple instruction age results, and merges the instruction age results to obtain the first instruction code, and the instruction timing matrix 1110 is updated based on the instruction timing matrix update logic 1101; the terminal obtains the ready instruction code 1120, bitwise inverts the first instruction code to obtain a first inverted code, and bitwise ANDs the first inverted code with the ready instruction code to obtain a candidate instruction code; performs parity deinterleaving operation on the candidate instruction sequence to obtain an odd instruction sequence 1121 and an even instruction sequence 1122; determines the first candidate transmission instruction based on the odd instruction sequence according to the preset selection logic, and determines the second candidate transmission instruction based on the even instruction sequence; When determining the candidate instruction codes, in parallel, a bitwise AND operation is performed on the first instruction code and the candidate instruction code to obtain a first valid code, the first valid code is reduced or operated to obtain a first valid result, and the first validity is determined based on the first valid result; the first instruction code is converted into a binary value to obtain a first identification code, recorded as Oh2bin code, to reduce the number of bits required to indicate the code of the first instruction and save data resources; the first candidate emission instruction is determined as the first target instruction for emission, and the second target instruction is determined from the second candidate emission instruction and the first instruction based on the first validity to be emitted, wherein, in response to the first validity indicating that the first instruction is in a ready state, the first instruction indicated by the Oh2bin code is determined as the second target instruction for emission, and in response to the first validity indicating that the first instruction is in a not ready state, the second candidate emission instruction is determined as the second target instruction for emission.

[0189] In some embodiments, the chip provided in the embodiments of the present application is implemented as follows Fig.11 The frame structure shown.

[0190] As Fig.11 The instruction transmission method provided in the embodiment of the present application is compared with the delay of the related technology. For example, please refer to Fig.12 , Fig.12 is a schematic diagram of delay comparison provided by an exemplary embodiment of the present application, such as Fig.12 As shown in sub-figure a, the related technology includes the delays required for the leading one logic, comparison and selection unit, instruction matching, and instruction merging processes. The related technology uses a multi-level comparison and selection unit to select the oldest instruction, including a first-level comparison and selection unit, a second-level comparison and selection unit, and a third-level comparison and selection unit. Although the comparison process of the comparison and selection unit is processed in parallel with the leading one detection logic, the comparator delay required by the comparison and selection unit is relatively large, and it is essentially a subtractor. Therefore, the delay of the comparison and selection unit is higher than the leading one detection logic, and the delay required for subsequent instruction matching is also relatively large; sub-figure b shows the delay required for the instruction issuance method provided in an embodiment of the present application, specifically, including the delays required for bit operations, leading one detection logic, and instruction merging processes, wherein the bit operations include reduction and operations, bitwise inversion operations, bitwise and operations, binary conversion (Onehot To Binary, Oh2bin) operations, and reduction or operations. In terms of timing relationships, the bitwise inversion operations, bitwise and operations, and Oh2bin operations are performed in parallel. Since the bit operation delay is small and there is no need to perform an instruction matching process, the instruction issuance method provided in the embodiment of the present application has a smaller delay than the prior art and a higher instruction issuance efficiency.

[0191] In order to further reduce the delay required by the instruction transmission method provided in the embodiment of the present application, the selection logic and the wake-up logic in the circuit are usually placed in the same clock cycle. For example, please refer to Fig.13 , Fig.13 This is a schematic diagram of the position of the selection circuit provided by an exemplary embodiment of the present application. Assume that two instructions to be issued are respectively, instruction A: add out x1, in x2, 1; instruction B: sub out x3, in x1, 8; wherein instruction A is used to instruct to add 1 to the data in register x2 and store it in register x1, and instruction B is used to instruct to subtract 8 from the data in register x1 and store it in register x3, and instruction B depends on instruction A. In the circuit logic of the chip, the circuit logic corresponding to an instruction generally includes wake-up logic, selection logic, load read logic, data read logic and execution logic, such as Fig.13As shown, register x2 is awakened by the wake-up logic 1310, and the register x1 to be stored in which the data obtained by executing instruction A is determined to be stored is determined to be x1 by the selection logic 1320, and register x1 is awakened by the wake-up logic 1330. Since the selection logic 1320 and the wake-up logic 1330 are placed in the same clock cycle 1301, the selection logic 1340 corresponding to instruction B can be performed in parallel with the load reading logic 1350 corresponding to instruction A in the next clock cycle, thereby improving the circuit logic parallelism and reducing the circuit delay.

[0192] Fig.14 is a block diagram of a chip provided by an exemplary embodiment of the present application. Fig.14 As shown, the chip includes the following parts:

[0193] The state updating unit 1410 is used to obtain an instruction timing matrix, where the instruction timing matrix is ​​used to record the timing relationship between multiple instructions to be issued in the issuing queue;

[0194] A reduction and unit 1420 is used to determine a first instruction code based on the instruction timing matrix, the first instruction code is used to indicate a first instruction through a code value, and a time when the first instruction enters the issue queue is earlier than other instructions;

[0195] The state updating unit 1410 is further used to obtain a ready instruction sequence, where the ready instruction sequence is used to indicate a plurality of ready instructions in the to-be-issued instructions, and the ready instructions are instructions in a ready state;

[0196] A bitwise AND unit 1430 is used to determine a first validity of a candidate issuance instruction and the first instruction based on the ready instruction sequence and the first instruction encoding, wherein the first validity is used to indicate an instruction state of the first instruction, and the instruction state includes any one of the ready state and the not ready state;

[0197] The instruction merging unit 1440 is configured to determine a target instruction to be emitted from among the candidate emission instructions and the first instruction based on the candidate emission instructions and the first validity.

[0198] Please refer to Fig.15 , Fig.15 is a block diagram of a chip provided by another exemplary embodiment of the present application. Fig.15 As shown, in some embodiments, the bitwise AND unit 1430 is used to determine the candidate issuing instruction based on the ready instruction sequence and the first inverted code corresponding to the first instruction code, where the first inverted code is a code sequence obtained by inverting the code value in the first instruction code;

[0199] The bitwise AND unit 1430 is further used to determine the first validity based on the ready instruction sequence and the first instruction encoding;

[0200] The process of determining the candidate transmission quality and the process of determining the first validity are in a parallel and independent relationship.

[0201] In some embodiments, the ready instruction sequence and the first instruction code are binary code sequences; the chip further includes a bitwise inversion unit 1450 and a selection logic unit 1460;

[0202] The bitwise inversion unit 1450 is used to perform a bitwise inversion operation on the first instruction code to obtain the first inverted code;

[0203] The bitwise AND unit 1430 is further used to perform a bitwise AND operation on the ready instruction sequence and the first inverted code to obtain a candidate instruction sequence, where the candidate instruction sequence is used to indicate candidate instructions other than the first instruction in the ready instructions;

[0204] The selection logic unit 1460 is configured to determine the candidate transmit instruction based on the candidate instruction sequence.

[0205] In some embodiments, the ready instruction sequence and the first instruction encoding are binary encoding sequences; the chip further comprises a reduction or unit 1470;

[0206] The bitwise AND unit 1430 is further used to perform a bitwise AND operation on the ready instruction sequence and the first instruction code to obtain a first valid code, where the first valid code is used to indicate whether the ready instruction contains the first instruction;

[0207] The reduction or operation unit 1470 is used to reduce or operate the first valid code to obtain a first valid result, where the first valid result is used to indicate the first validity;

[0208] The instruction merging unit 1440 is further configured to determine the first validity based on the first valid result;

[0209] In which, in response to the first valid result being a first value, determining that the first validity indicates that the first instruction belongs to the ready state; in response to the first valid result being a second value, determining that the first validity indicates that the first instruction belongs to the not ready state.

[0210] In some embodiments, the instruction merging unit 1440 is used to determine the first instruction as the target instruction for emission in response to the first validity indication that the first instruction belongs to the ready state; or, in response to the first validity indication that the first instruction belongs to the not ready state, determine the candidate emission instruction as the target instruction for emission.

[0211] In some embodiments, the reduction and unit 1420 is used to obtain multiple instruction age results based on each matrix row of the instruction timing matrix, wherein the i-th matrix row is used to record the timing relationship of the i-th instruction to be issued in the issuance queue, and the i-th instruction age result obtained based on the i-th matrix row is used to indicate the time when the i-th instruction to be issued enters the issuance queue, and i is a positive integer;

[0212] The reduction and unit 1420 is further configured to, in response to the i-th instruction age result meeting the instruction age requirement, determine the i-th instruction to be issued as the first instruction, and determine the first instruction encoding based on the first instruction.

[0213] In some embodiments, the status update unit 1410 is further used to update the instruction timing matrix in response to the jth instruction to be issued entering the issuance queue; or, in response to the jth instruction to be issued being removed from the issuance queue, update the instruction timing matrix, where j is a positive integer.

[0214] To summarize, the chip provided in the embodiment of the present application determines the first instruction code for indicating the first instruction based on the instruction timing matrix. The time when the first instruction enters the transmission queue is earlier than other instructions, thereby avoiding a large delay caused by using CSU to determine the first instruction. By determining the first validity of the candidate transmission instruction and the first instruction based on the ready instruction sequence and the first instruction code, the parallel processing of the candidate transmission instruction determination process and the first validity determination process is realized, thereby reducing the timing delay of the two determination processes. By determining the target instruction from the candidate transmission instructions and the first instruction based on the candidate transmission instruction and the first validity for transmission, it is avoided that the target instruction is determined by comparing the candidate transmission instruction and the first instruction, resulting in a large delay in the comparison logic, thereby reducing the delay in the process of determining the target instruction and improving the instruction transmission efficiency.

[0215] It should be noted that the chip provided in the above embodiment is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0216] Fig.16The structure block diagram of a terminal 1600 provided by an exemplary embodiment of the present application is shown. The terminal 1600 is deployed with a chip for executing the instruction transmission method, and the terminal 1600 may be: a smart phone, a tablet computer, an MP3 player, an MP4 player, a notebook computer or a desktop computer. The terminal 1600 may also be called a user equipment, a portable terminal, a laptop terminal, a desktop terminal, and other names.

[0217] Typically, the terminal 1600 includes a processor 1601 and a memory 1602 .

[0218] The processor 1601 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 1601 may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 1601 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 1601 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 1601 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0219] The memory 1602 may include one or more computer-readable storage media, which may be non-transitory. The memory 1602 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 1602 is used to store at least one instruction, which is used to be executed by the processor 1601 to implement the instruction transmission method provided in the method embodiment of the present application.

[0220] In some embodiments, the terminal 1600 also includes other components, which can be understood by those skilled in the art. Fig.16The structure shown in the figure does not constitute a limitation on the terminal 1600, and the terminal 1600 may include more or less components than those shown in the figure, or combine some components, or adopt a different component arrangement.

[0221] The embodiment of the present application also provides a chip, which can be implemented as follows Figure 1 The chip deployed in the terminal or server shown in the figure includes a processor and a memory, the memory stores at least one instruction, at least one program, code set or instruction set, and the at least one instruction, at least one program, code set or instruction set is loaded and executed by the processor to implement the instruction transmission method provided by the above-mentioned method embodiments.

[0222] An embodiment of the present application also provides a computer-readable storage medium, on which is stored at least one instruction, at least one program, code set or instruction set, and the at least one instruction, at least one program, code set or instruction set is loaded and executed by a processor to implement the instruction transmission method provided by the above-mentioned method embodiments.

[0223] The embodiments of the present application also provide a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. The processor of the chip reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the chip executes the instruction transmission method provided by the above-mentioned method embodiments.

[0224] Optionally, the computer readable storage medium may include: Read Only Memory (ROM), Random Access Memory (RAM), Solid State Drives (SSD) or optical disks, etc. Among them, the random access memory may include resistance random access memory (ReRAM) and dynamic random access memory (DRAM). The serial numbers of the above embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

[0225] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0226] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A command transmission method, characterized in that: The method comprises: Obtaining an instruction timing matrix, wherein the instruction timing matrix is ​​used to record the timing relationship between multiple instructions to be issued in the issuance queue; Determine a first instruction code based on the instruction timing matrix, the first instruction code is used to indicate a first instruction through a code value, and the first instruction enters the issue queue earlier than other instructions; Acquire a ready instruction sequence, wherein the ready instruction sequence is used to indicate a plurality of ready instructions among the instructions to be transmitted, and the ready instructions are instructions in a ready state; Determine first validity of candidate issuance instructions and the first instruction based on the ready instruction sequence and the first instruction code, the first validity being used to indicate an instruction state of the first instruction, the instruction state including any one of the ready state and the not ready state; A target instruction is determined for issuance from among the candidate issuance instructions and the first instruction based on the candidate issuance instructions and the first validity.

2. The method according to claim 1, characterized in that The determining, based on the ready instruction sequence and the first instruction encoding, first validity of a candidate issue instruction and the first instruction comprises: Determine the candidate issuing instruction based on the ready instruction sequence and a first inverted code corresponding to the first instruction code, wherein the first inverted code is a code sequence obtained by inverting a code value in the first instruction code; determining the first validity based on the ready instruction sequence and the first instruction encoding; The process of determining the candidate transmission quality and the process of determining the first validity are in a parallel and independent relationship.

3. The method according to claim 2, characterized in that The ready instruction sequence and the first instruction code are binary code sequences; The determining the candidate issuing instruction based on the ready instruction sequence and a first inverted code corresponding to the first instruction code comprises: Performing a bitwise inversion operation on the first instruction code to obtain the first inverted code; Performing a bitwise AND operation on the ready instruction sequence and the first inverted code to obtain a candidate instruction sequence, where the candidate instruction sequence is used to indicate candidate instructions other than the first instruction in the ready instructions; The candidate issue instructions are determined based on the candidate instruction sequence.

4. The method according to claim 3, characterized in that The determining the candidate transmit instruction based on the candidate instruction sequence comprises: Performing an odd-even deinterleaving operation on the candidate instruction sequence to obtain an odd instruction sequence and an even instruction sequence, wherein the odd instruction sequence is used to indicate the 2k-1th ready instruction, and the even instruction sequence is used to indicate the 2kth ready instruction, where k is a positive integer; A first candidate issuing instruction is determined based on the odd instruction sequence according to a preset selection logic, and a second candidate issuing instruction is determined based on the even instruction sequence.

5. The method according to claim 4, characterized in that The step of determining a target instruction to be emitted from the candidate emission instructions and the first instruction based on the candidate emission instructions and the first validity includes: Determine the first candidate emission instruction as a first target instruction for emission, and determine a second target instruction for emission based on the second candidate emission instruction and the first validity; or, The second candidate issue instruction is determined as a first target instruction for issuance, and a second target instruction is determined to be issued based on the first candidate issue instruction and the first validity.

6. The method according to claim 2, characterized in that The ready instruction sequence and the first instruction code are binary code sequences; The determining the first validity based on the ready instruction sequence and the first instruction encoding comprises: Performing a bitwise AND operation on the ready instruction sequence and the first instruction code to obtain a first valid code, where the first valid code is used to indicate whether the ready instruction contains the first instruction; reducing or operating the first valid code to obtain a first valid result, where the first valid result is used to indicate the first validity; Determining the first validity based on the first valid result; In which, in response to the first valid result being a first value, determining that the first validity indicates that the first instruction belongs to the ready state; in response to the first valid result being a second value, determining that the first validity indicates that the first instruction belongs to the not ready state.

7. The method according to any one of claims 1 to 6, characterized in that: The step of determining a target instruction to be emitted from the candidate emission instructions and the first instruction based on the candidate emission instructions and the first validity includes: In response to the first validity indication that the first instruction belongs to the ready state, determining the first instruction as the target instruction for issuance; or, In response to the first validity indication that the first instruction belongs to the not-ready state, the candidate issue instruction is determined as the target instruction for issuance.

8. The method according to any one of claims 1 to 6, characterized in that: The determining a first instruction sequence based on the instruction timing matrix comprises: A plurality of instruction age results are obtained based on each matrix row of the instruction timing matrix, wherein the i-th matrix row is used to record the timing relationship of the i-th instruction to be issued in the issuance queue, and the i-th instruction age result obtained based on the i-th matrix row is used to indicate the time when the i-th instruction to be issued enters the issuance queue, and i is a positive integer; In response to the i-th instruction age result meeting the instruction age requirement, the i-th instruction to be issued is determined as the first instruction, and the first instruction encoding is determined based on the first instruction.

9. The method according to claim 8, characterized in that Each matrix row corresponds to a binary code sequence; The obtaining of a plurality of instruction age results based on each matrix row of the instruction timing matrix includes: Reducing and operating the coding sequence corresponding to each matrix row respectively to obtain the plurality of instruction age results; In response to the i-th instruction age result meeting the instruction age requirement, determining the i-th instruction to be issued as the first instruction, and determining the first instruction code based on the first instruction, comprises: In response to the i-th instruction age result being a first value, determining the i-th instruction to be issued as the first instruction; The first instruction encoding is determined based on the first instruction, wherein the encoding value of the i-th bit from right to left in the n-bit binary encoding vector is set to a first value, and the encoding values ​​of the remaining bits are set to second values, to obtain the first instruction encoding, and n is used to indicate the transmit queue depth.

10. The method according to any one of claims 1 to 6, characterized in that: Before determining the first instruction sequence based on the instruction timing matrix, the method further includes: In response to the jth to-be-issued instruction entering the issue queue, updating the instruction timing matrix; or, In response to the jth to-be-issued instruction being removed from the issue queue, the instruction timing matrix is ​​updated, where j is a positive integer.

11. The method according to claim 10, characterized in that The matrix rows and matrix columns in the instruction timing matrix correspond to binary encoding vectors respectively; In response to the jth to-be-issued instruction entering the issue queue, updating the instruction timing matrix comprises: In response to the jth instruction to be issued entering the issuance queue, obtaining a first encoding vector corresponding to the jth matrix column in the instruction timing matrix; Performing a bitwise inversion operation on the first encoding vector to obtain a second encoding vector; Assign the second encoding vector to the j-th matrix row in the instruction timing matrix.

12. The method according to claim 10, characterized in that The matrix rows and matrix columns in the instruction timing matrix correspond to binary encoding vectors respectively; In response to the jth to-be-issued instruction being removed from the issue queue, updating the instruction timing matrix comprises: In response to the jth instruction to be issued being removed from the issuance queue, the encoding value corresponding to the jth matrix column in the instruction timing matrix is ​​set to a first value according to a preset rule, and the encoding value corresponding to the jth matrix row in the instruction timing matrix is ​​set to a second value.

13. A chip, characterized in that: The chip comprises: A state updating unit, used for obtaining an instruction timing matrix, wherein the instruction timing matrix is ​​used for recording a timing relationship between a plurality of instructions to be issued in an issue queue; A reduction and unit, used for determining a first instruction code based on the instruction timing matrix, the first instruction code is used for indicating a first instruction through a code value, and a time when the first instruction enters the issue queue is earlier than other instructions; The state updating unit is further used to obtain a ready instruction sequence, wherein the ready instruction sequence is used to indicate a plurality of ready instructions among the instructions to be transmitted, and the ready instructions are instructions belonging to a ready state; A bitwise AND unit, used for determining first validity of a candidate issuance instruction and the first instruction based on the ready instruction sequence and the first instruction encoding, wherein the first validity is used to indicate an instruction state of the first instruction, wherein the instruction state includes any one of the ready state and the not ready state; An instruction merging unit is used to determine a target instruction to be issued from the candidate issuing instructions and the first instruction based on the candidate issuing instructions and the first validity.

14. The chip according to claim 13, characterized in that: The bitwise AND unit is used to determine the candidate issuing instruction based on the ready instruction sequence and a first inverted code corresponding to the first instruction code, where the first inverted code is a code sequence obtained by inverting a code value in the first instruction code; The bitwise AND unit is further used to determine the first validity based on the ready instruction sequence and the first instruction encoding; The process of determining the candidate transmission quality and the process of determining the first validity are in a parallel and independent relationship.

15. The chip according to claim 14, characterized in that: The ready instruction sequence and the first instruction code are binary code sequences; the chip further comprises a bitwise inversion unit and a selection logic unit; The bitwise inversion unit is used to perform a bitwise inversion operation on the first instruction code to obtain the first inverted code; The bitwise AND unit is further used to perform a bitwise AND operation on the ready instruction sequence and the first inverted code to obtain a candidate instruction sequence, wherein the candidate instruction sequence is used to indicate candidate instructions other than the first instruction in the ready instructions; The selection logic unit is used to determine the candidate issuing instruction based on the candidate instruction sequence.

16. The chip according to claim 14, characterized in that: The ready instruction sequence and the first instruction code are binary code sequences; the chip also includes a reduction or unit; The bitwise AND unit is further used to perform a bitwise AND operation on the ready instruction sequence and the first instruction code to obtain a first valid code, where the first valid code is used to indicate whether the ready instruction contains the first instruction; The reduction or unit is used to reduce or operate the first valid code to obtain a first valid result, and the first valid result is used to indicate the first validity; The instruction merging unit is further used to determine the first validity based on the first valid result; In which, in response to the first valid result being a first value, determining that the first validity indicates that the first instruction belongs to the ready state; in response to the first valid result being a second value, determining that the first validity indicates that the first instruction belongs to the not ready state.

17. The chip according to any one of claims 13 to 16, characterized in that: The instruction merging unit is used to determine the first instruction as the target instruction for issuance in response to the first validity indication that the first instruction belongs to the ready state; or, in response to the first validity indication that the first instruction belongs to the not ready state, determine the candidate issuance instruction as the target instruction for issuance.

18. The chip according to any one of claims 13 to 16, characterized in that: The reduction and unit is used to obtain multiple instruction age results based on each matrix row of the instruction timing matrix, wherein the i-th matrix row is used to record the timing relationship of the i-th instruction to be issued in the issuance queue, and the i-th instruction age result obtained based on the i-th matrix row is used to indicate the time when the i-th instruction to be issued enters the issuance queue, and i is a positive integer; The reduction and unit is further configured to determine the i-th instruction to be issued as the first instruction in response to the i-th instruction age result meeting the instruction age requirement, and determine the first instruction encoding based on the first instruction.

19. The chip according to any one of claims 13 to 16, characterized in that: The state update unit is further used to update the instruction timing matrix in response to the jth instruction to be issued entering the issuance queue; or, in response to the jth instruction to be issued being removed from the issuance queue, update the instruction timing matrix, where j is a positive integer.

20. A computer-readable storage medium, characterized in that: The storage medium stores at least one computer program, and the at least one computer program is loaded and executed by the processor to implement the instruction transmission method according to any one of claims 1 to 12.

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