A system, method, apparatus, and medium for in-core instruction concurrent out-of-order execution

Abstract

The application provides a kind of nuclear instruction concurrent out-of-order execution system, method, equipment and medium, belongs to instruction scheduling technical field.The system includes: thread bundle scheduling module, for managing thread bundle slot, through program counter switching computing core task;Instruction fetch module, for reading instruction from L1 cache to in-core cache;Instruction decoding module, for sending register information to decoding identification module after instruction is translated;Decoding identification module is used to jump, access, barrier, dependency and out-of-order five kinds of instructions, and generates identification instruction and stores into the corresponding cache group of emission cache module;Operand collection module, for reading data from register according to instruction;Computing execution module contains four kinds of units of shaping, floating point, special function and access, and synchronously executes multiple computing tasks;Result write-back module, for writing back result data to operand collection module.The application realizes instruction concurrent out-of-order execution, improves computing efficiency and resource utilization.

Description

Technical Field

[0001] This invention belongs to the field of instruction scheduling technology, and more specifically relates to a system, method, device and medium for concurrent out-of-order execution of kernel instructions. Background Technology

[0002] With the advent of the information age, the scale and diversity of data are growing exponentially, further triggering a sharp increase in the demand for data processing capabilities. Therefore, the development of high-performance computing chips has become a global research hotspot, with general-purpose graphics processing units (GPGPUs) being particularly prominent.

[0003] Currently, GPGPU product architectures often achieve their superior data processing capabilities by integrating multiple computing cores. Each computing core is equipped with a complete fetch, decode, issue, execute, and write-back pipeline, forming the foundation of an efficient execution unit. Furthermore, each execution unit integrates numerous dedicated computing units, collectively supporting the implementation of the GPGPU Single Instruction Multithreaded (SIMT) architecture. The SIMT architecture enables GPGPUs to perform parallel processing on a large number of threads under the guidance of a single instruction, thereby achieving high-concurrency computation on large-scale datasets.

[0004] However, in the classic SIMT architecture of GPGPU, instruction execution follows a strict sequential order, and within a given computational core, all threads execute the same instructions in parallel. This execution model will cause the entire execution pipeline to stall when faced with long-cycle instructions, thus affecting overall computational efficiency. Furthermore, since at any given moment, all threads are limited to a single instruction and can only execute one computational operation, and the execution unit within a GPGPU actually integrates multiple computational modules, this computational mode will result in only some of the computational modules in the GPGPU performing computations at any given time, while other computational modules remain idle. This will further lead to a waste of computing resources and a reduction in computing power. Summary of the Invention

[0005] To address the above problems, the present invention aims to provide a system, method, device, and medium for concurrent out-of-order execution of kernel instructions. Through refined instruction classification, dependency management, flexible instruction execution strategies, and efficient instruction processing flow, concurrent out-of-order execution of kernel instructions is achieved, thereby improving computational efficiency and utilization of computing resources.

[0006] To achieve the above objectives, the present invention employs the following technical solution:

[0007] In a first aspect, embodiments of this application provide an in-kernel instruction concurrent out-of-order execution system, comprising:

[0008] The module includes a thread scheduling module, an instruction fetch module, an instruction decoding module, a decoding flag module, an issue buffer module, an operand collection module, a computation execution module, and a result write-back module.

[0009] The thread bundle scheduling module is a register group used to maintain the number of thread bundle slots. It performs core task switching by calculating the thread bundle granularity by sending the program counter count value to the instruction fetch module.

[0010] The instruction fetch module is used to use the program counter value as the fetch PC, use the fetch PC as the address to read instruction data from the L1 cache outside the computing core, and then store the instruction data in the core instruction cache.

[0011] The instruction decoding module is used to read instruction data from the kernel instruction cache in a first-in-first-out manner, decode the instruction data into register information that the computing core can recognize, and send it to the decoding identification module.

[0012] The decoding and identification module is used to determine the classification of kernel instructions based on register information, classifying kernel instructions into five instruction types, classifying and identifying them according to the instruction type, generating identification instructions and sending them to the issue buffer module, and sending corresponding control signals to ensure concurrent out-of-order execution of instructions; the five instruction types include: jump instructions, memory access instructions, barrier instructions, dependent instructions, and out-of-order instructions;

[0013] The issue cache module contains multiple cache groups to store identification instructions from the decoding identification module. The issue cache module divides the cache groups into five types. Based on the instruction type of the identification instruction, it stores the instruction into the corresponding type of cache group and synchronously sends the identification instructions in the cache group to the computation execution module for synchronous execution based on the storage status in the cache group. The types of cache groups include out-of-order instruction cache group, integer-dependent calculation cache group, floating-point-dependent calculation cache group, special function-dependent cache group, and memory access instruction cache group.

[0014] The operand collection module maintains multiple sets of register values ​​on a thread-by-thread basis and reads specific data from the corresponding register address of the corresponding thread according to the instruction information issued by the issue buffer module.

[0015] The computation execution module has four types of computation execution units, which are used to synchronously receive the identification instructions issued by the transmit buffer module, and synchronously execute various computational task loads according to the instruction type of the identification instructions, and generate result data after the computation is completed; the computation execution units include integer computation unit, floating-point computation unit, special function computation unit and memory access computation unit;

[0016] The result write-back module receives the result data generated by the computation execution module and writes it back to the corresponding position in the operand collection module according to the corresponding thread identifier and register address.

[0017] In an optional implementation, the register information includes: the addresses of three source operand registers, the address of one destination register, the type of computation execution unit required for the instruction data, the type of computation to be performed, the immediate value required for the computation, and the instruction fetch PC of the current instruction required for the computation.

[0018] In an optional implementation, the step of classifying and identifying instructions according to their types, generating identification instructions and sending them to the transmit buffer module, and sending corresponding control signals to ensure concurrent out-of-order execution of instructions includes:

[0019] When the instruction type is a jump instruction, a pause instruction is sent to the instruction fetch module and the instruction decode module to pause their execution; a clear signal is sent to the kernel instruction cache to clear all instruction information existing in the kernel instruction cache;

[0020] When the instruction type is a memory access instruction, a dependency judgment is performed on the memory access instruction; if the memory access instruction has no dependency, the memory access instruction is sent first; if there is a dependency, the dependent parent instruction of the memory access instruction is sent first, and the memory access instruction is sent first after all dependent parent instructions have been executed.

[0021] When the instruction type is a barrier instruction, a pause instruction is sent to the instruction fetch module and the instruction decode module to pause their execution until all instructions and barrier instructions in the issue buffer module have been executed.

[0022] In an optional implementation, the step of classifying and identifying instructions according to their types, generating identification instructions and sending them to the transmit buffer module, and sending corresponding control signals to ensure concurrent out-of-order execution of instructions further includes:

[0023] If the instruction type of the current kernel instruction is not a jump instruction, memory access instruction, or barrier instruction, then the kernel instruction is considered a computation instruction.

[0024] The computation instruction is evaluated for dependency. If the computation instruction has a dependency relationship with the instruction in the launch buffer module, the computation instruction is marked as a dependent instruction and sent to the launch buffer module, and the corresponding dependent parent instruction is identified. If the computation instruction does not have a dependency relationship with the instruction in the launch buffer module, the computation instruction is marked as an out-of-order instruction and sent to the launch buffer module.

[0025] In an optional implementation, the transmit buffer module is specifically used for:

[0026] When the identifier instruction sent by the decoding identifier module is a jump instruction, barrier instruction, or out-of-order instruction, the identifier instruction is placed in the highest bit of the out-of-order instruction cache group for maintenance.

[0027] When the identifier instruction sent by the decoding identifier module is a dependent instruction, the dependent parent instruction of the dependent instruction is extracted from the out-of-order instruction cache group, and the dependent parent instruction and the dependent instruction are stored in the corresponding instruction cache group for maintenance according to the calculation and execution unit of the dependent instruction.

[0028] When the identifier instruction sent by the decoding identifier module is a memory access instruction, it is determined whether the memory access instruction is a dependent memory access instruction. If the memory access instruction is a dependent memory access instruction, the dependent parent instruction of the memory access instruction is extracted from the out-of-order instruction cache group, and the dependent parent instruction and the memory access instruction are stored in the memory access instruction cache group in turn. If the memory access instruction is not a dependent memory access instruction, the memory access instruction is placed in the least significant bit of the memory access instruction cache group for maintenance.

[0029] Secondly, embodiments of this application also provide a method for concurrent out-of-order execution of kernel instructions, including:

[0030] The decoding and identification module obtains the register information sent by the instruction decoding module, extracts the number register address, destination register address, and the type of computation execution unit required by the instruction, and converts the extracted information into binary information.

[0031] Based on the computational execution unit category information required by the instruction, set the corresponding computational execution module identifier bit in the instruction, and based on the register address information involved in the instruction execution, set the corresponding register identifier bit in the instruction;

[0032] The decoding and identification module compares the register identifier information of the current instruction with the instruction register identifier information maintained in the issue buffer module. Based on the comparison result, dependent instructions and out-of-order instructions are identified, and the instructions are sent to the corresponding type of buffer group for caching according to the identification result.

[0033] When all dependent instructions exist in the dependent integer calculation cache group, dependent floating-point calculation cache group, dependent special function cache group, and memory access instruction cache group in the issue cache module, the instructions in these cache groups are prioritized and synchronously sent to the corresponding computation execution unit of the computation execution module for computation. If any of these cache groups does not contain dependent instructions, an out-of-order instruction is extracted from the out-of-order instruction cache group and sent to the corresponding computation execution unit of the computation execution module for computation.

[0034] In an optional implementation, the step of setting the corresponding computation execution module identifier bit in the instruction according to the computation execution unit category information required by the instruction, and setting the corresponding register identifier bit in the instruction according to the register address information involved in the instruction execution, includes:

[0035] If the computation execution unit required by the instruction is an integer computation unit, then the computation execution module identifier is set to 00;

[0036] If the computation execution unit required by the instruction is a floating-point computation unit, then the computation execution module identifier position is set to 01;

[0037] If the computation execution unit required by the instruction is a special function computation unit, then the computation execution module identifier position is set to 10;

[0038] If the computation execution unit required by the instruction is a memory access computation unit, then the computation execution module identifier position is set to 11;

[0039] Based on the register address information involved in the instruction execution, set the corresponding register identifier in the instruction to 1.

[0040] In an optional implementation, the step of comparing the register identifier information of the current instruction with the instruction register identifier information maintained in the issue buffer module, identifying dependent instructions and out-of-order instructions based on the comparison result, and sending the instructions to the corresponding type of buffer group for caching based on the identification result includes:

[0041] The decoding and identification module compares the register identifier information of the current instruction with the instruction register identifier information maintained in the issue buffer module.

[0042] If the same position is 1, the current instruction is a dependent instruction, and the instruction maintained in the emit buffer module is a dependent parent instruction; according to the identifier information of the calculation execution module, the dependent parent instruction and the dependent instruction are sent together to the corresponding buffer group for caching;

[0043] If there are no instances where all positions are 1, then the current instruction is an out-of-order instruction, and the out-of-order instruction is sent to the out-of-order instruction cache group for caching.

[0044] Thirdly, embodiments of this application also provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the kernel instruction concurrent out-of-order execution method described in any of the above.

[0045] Fourthly, embodiments of this application also provide a storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the steps of the kernel instruction concurrent out-of-order execution method as described in any of the above.

[0046] As can be seen from the above technical solutions, the present invention has the following advantages:

[0047] This application adds a decoding identifier module and an issue buffer module to the traditional GPGPU-SIMT architecture pipeline, dividing instructions into dependent execution and out-of-order execution. Dependent instructions must be executed sequentially, while out-of-order instructions can be executed across orders, thus solving the pipeline stalling problem caused by long-cycle instructions. At the same time, this application uses the decoding identifier module and the issue buffer module to further divide instructions according to the computation execution unit, and instructions from different computation execution units are executed synchronously, further improving the efficiency of computing resource utilization in GPGPU.

[0048] This application utilizes a decoding identifier module to classify kernel instructions into five types (jump instructions, memory access instructions, barrier instructions, dependent instructions, and out-of-order instructions), and then classifies, identifies, and sends these instructions to the corresponding issue buffers based on their type. This fine-grained instruction classification helps optimize the execution order of instructions and reduce the waiting time between instructions, thereby improving computational efficiency.

[0049] This application achieves a highly efficient instruction processing flow by decoding and classifying instructions through a decoding and identification module, and caching and synchronously executing instructions through an issue buffer module. This flow reduces instruction processing time and waiting time, thereby improving computational efficiency. Attached Figure Description

[0050] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 A schematic diagram of the structure of the kernel instruction concurrent out-of-order execution system provided in this application.

[0052] Figure 2 A flowchart illustrating the kernel instruction concurrent out-of-order execution method provided in this application.

[0053] Figure 3 A schematic diagram illustrating the execution principle of the kernel instruction concurrent out-of-order execution method provided in this application.

[0054] Figure 4 A schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0055] The various embodiments of this disclosure will be described more fully in the detailed description of the specific architecture and functionality of the in-kernel instruction concurrent out-of-order execution system below. This disclosure may have various embodiments, and adjustments and changes may be made therein. However, it should be understood that there is no intention to limit the various embodiments of this disclosure to the specific embodiments disclosed herein, but rather this disclosure should be understood to cover all adjustments, equivalents, and / or alternatives falling within the spirit and scope of the various embodiments of this disclosure.

[0056] In the following, the terms “comprising” or “may include”, which may be used in various embodiments of this disclosure, indicate the presence of the disclosed functions, operations, or elements, and do not limit the addition of one or more functions, operations, or elements. Furthermore, as used in various embodiments of this disclosure, the terms “comprising,” “having,” and their cognates are intended only to indicate a particular feature, number, step, operation, element, component, or combination of the foregoing, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing, or the possibility of adding one or more combinations of the foregoing.

[0057] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0058] Please see Figure 1The diagram shows a system architecture of an in-core instruction concurrent out-of-order execution system in a specific embodiment. This system adds functionality to the traditional sequential execution SIMT architecture without altering the external interface of the computing core. This achieves transparency of the overall module to the upper layers of the computing core; that is, the system requires no software or upper-layer hardware adaptation and can be directly applied to traditional GPGPU hardware implementations. The system includes: a thread beam scheduling module, an instruction fetch module, an instruction decode module, a decoder identification module, an issue buffer module, an operand collection module, a computation execution module, and a result write-back module.

[0059] The thread bundle scheduling module is a register set used to maintain the number of thread bundle slots. It performs core task switching by calculating the thread bundle granularity by sending the program counter count value to the instruction fetch module.

[0060] The thread beam scheduling module is located at the top level of the pipeline within the compute core. It maintains a register set for the number of thread beam slots and is responsible for switching compute core tasks at the thread beam level. In this system, thread beam switching only occurs to ensure the efficient use of GPGPU hardware resources when a specific compute execution unit within the compute execution module of the compute core is idle and the currently executing thread beam no longer has any tasks assigned to that compute execution unit. Otherwise, the current thread beam is executed first.

[0061] The instruction fetch module is used to use the program counter value as the fetch PC, use the fetch PC as the address to read instruction data from the L1 cache outside the computing core, and then store the instruction data in the instruction cache inside the core.

[0062] For example, the instruction fetch module is responsible for fetching the instructions to be executed in the current thread bundle. Specifically, this module is responsible for reading instruction data from the L1 cache outside the computing core, using the fetch PC as the address, based on the fetch PC sent by the thread bundle scheduling module, and then storing the instruction data in the core's instruction cache. In this system, the instruction fetching operation of this module is performed sequentially to ensure the stability of the computing core's external interface signals; that is, the fetch PC is continuously incremented. Furthermore, the instruction fetching operation of this module only stops when the subsequent decoding flag module and issue buffer module send a pause signal; otherwise, it continues continuously. This mode further prevents the computing core instruction pipeline from stalling.

[0063] The instruction decoding module is used to read instruction data from the kernel instruction cache in a first-in-first-out manner, decode the instruction data into register information that the computing core can recognize, and send it to the decoding identification module.

[0064] For example, the instruction decoding module is responsible for reading instruction data from the kernel instruction cache and then decoding the instruction data into register values ​​that the computing core can recognize. Specifically, this includes the addresses of three source operand registers, one destination register address, the type of execution unit (CMU) required by the instruction, the type of computation performed by the CMU, the immediate values ​​required for the computation, and the current instruction program (PC) required for the computation. In this system, the instruction decoding module reads instruction data from the kernel instruction cache in a FIFO (First-In, First-Out) manner for decoding, and this process only stops when it receives a pause signal from the subsequent decoding flag module and the issue cache module; otherwise, it continues continuously.

[0065] The decoding and identification module is used to determine the classification of kernel instructions based on register information, classify kernel instructions into five instruction types, classify and identify them according to the instruction type, generate identification instructions and send them to the issue buffer module, and send corresponding control signals to ensure concurrent out-of-order execution of instructions; the five instruction types include: jump instructions, memory access instructions, barrier instructions, dependent instructions and out-of-order instructions.

[0066] The issue cache module contains multiple cache groups for storing identification instructions from the decoding identification module. The issue cache module divides the cache groups into five types. Based on the instruction type of the identification instruction, the cache group stores the instruction into the corresponding type of cache group. Based on the storage status in the cache group, the issue cache module synchronously sends the identification instructions in the cache group to the computation execution module for synchronous execution. The types of cache groups include out-of-order instruction cache group, integer-dependent calculation cache group, floating-point-dependent calculation cache group, special function-dependent calculation cache group, and memory access instruction cache group.

[0067] The operand collection module maintains multiple sets of register values ​​on a thread-by-thread basis and reads specific data from the corresponding register address of the corresponding thread based on the instruction information issued by the issue buffer module.

[0068] For example, the operand collection module maintains multiple sets of register values ​​on a thread-by-thread basis, and is responsible for reading specific data from the corresponding register address of the corresponding thread according to the instruction information issued by the issue buffer module. In this system, since the issue buffer module will simultaneously issue multiple instructions from different computation execution units, the registers of the operand collection module have multi-end read and write capabilities, that is, it can read and write multiple sets of registers of a certain thread at the same time.

[0069] The computation execution module has four types of computation execution units, which are used to synchronously receive the identification instructions issued by the transmit buffer module, and synchronously execute various computational task loads according to the instruction type of the identification instructions, and generate result data after the computation is completed; the computation execution units include integer computation unit, floating-point computation unit, special function computation unit and memory access computation unit.

[0070] For example, the computation execution module is the specific execution module for computation within the GPGPU core. It is divided into four computation execution units: an integer computation unit, a floating-point computation unit, a special function computation unit, and a memory access computation unit. Each computation execution unit has a hardware unit capable of executing a certain number of threads simultaneously. In this system, unlike the traditional GPGPU-SIMT architecture which only receives one type of computation instruction and executes one type of computation operation, the computation execution module simultaneously receives and executes multiple computational tasks.

[0071] The result write-back module receives the result data generated by the computation execution module and writes it back to the corresponding position in the operand collection module according to the corresponding thread identifier and register address.

[0072] For example, the result write-back module is responsible for receiving the result data calculated by the computation execution module and writing it back to the corresponding location in the operand collection module according to the corresponding thread identifier and register address. In this system, since the computation execution module will execute multiple different computation tasks simultaneously, the result write-back module has multi-channel signal write-back capability, that is, it can simultaneously write back integer, floating-point, special function, and memory-loaded result data to the operand collection module.

[0073] In this embodiment, by integrating modules such as thread bundle scheduling, sequential instruction fetching and decoding, instruction classification and identification, intelligent issue cache management, multi-terminal read and write operand collection, and diversified synchronous computation execution, concurrent out-of-order execution of core instructions is achieved, which significantly improves the computing performance and resource utilization of GPGPU, while maintaining compatibility with existing software and hardware, and can be directly applied to traditional GPGPU hardware without additional adaptation.

[0074] In one embodiment of the present invention, based on the decoding identification module, the following will provide a possible embodiment and describe its specific implementation in a non-limiting manner.

[0075] The decoding and identification module is a novel module added to this invention to ensure efficient concurrent out-of-order execution of instructions. This module is responsible for receiving various register values ​​sent from the instruction decoding module and then classifying and identifying the instructions according to the corresponding register values. Specifically, the decoding and identification module divides instructions into five types and performs different operations for each type. The five instruction types are jump instructions, memory access instructions, barrier instructions, dependent instructions, and out-of-order instructions.

[0076] The decoding and identification module can classify and identify instructions according to their type, generate identification instructions, send them to the transmit buffer module, and send corresponding control signals to ensure concurrent out-of-order execution of instructions. The specific implementation is as follows:

[0077] 1. When the instruction type is a jump instruction, a pause instruction is sent to the instruction fetch module and the instruction decode module to pause their execution; a clear signal is sent to the kernel instruction cache to clear all instruction information existing in the kernel instruction cache.

[0078] For jump instructions, since their execution result is a change to the thread bundle PC value in the top-level thread bundle scheduling module of the pipeline, the execution of this instruction requires ensuring that all previous instructions have been executed. Specifically, when the decoding flag module recognizes a jump instruction, it sends a pause instruction to the instruction fetch and instruction decode modules. Simultaneously, while pausing the execution of these modules, a clear signal is sent to the kernel instruction cache, clearing all instruction information present in the kernel instruction cache.

[0079] 2. When the instruction type is a memory access instruction, a dependency judgment is performed on the memory access instruction; if the memory access instruction has no dependency, the memory access instruction is sent first; if there is a dependency, the dependent parent instruction of the memory access instruction is sent first, and the memory access instruction is sent first after all dependent parent instructions have been executed.

[0080] When the identified instruction is a memory access instruction, it needs to be sent and executed first because it has the longest execution cycle in the entire GPGPU computing core. Specifically, after the decoding and identification module identifies a memory access instruction, it first performs a dependency check. If the memory access instruction has no dependencies, it is sent first; if dependencies exist, the dependent parent instructions are sent first, and the memory access instruction is sent only after all dependent parent instructions have been executed.

[0081] 3. When the instruction type is a barrier instruction, a pause instruction is sent to the instruction fetch module and the instruction decode module to pause the execution of the instruction fetch module and the instruction decode module. The execution of the instruction fetch module and the instruction decode module will only resume after all instructions and barrier instructions in all issue buffer modules have been executed.

[0082] When the identified instruction is a barrier instruction, since the barrier instruction itself is a thread synchronization instruction defined by the GPGPU, it needs to wait for all existing instructions to finish executing before proceeding. Specifically, when the decoding identifier module identifies a barrier instruction, it sends a pause instruction to the instruction fetch and decode modules, pausing their execution until all instructions in the issue buffer and the barrier instruction have finished executing.

[0083] 4. If the instruction type of the current kernel instruction is not a jump instruction, memory access instruction, or barrier instruction, then the kernel instruction will be treated as a computation instruction. A dependency check will then be performed on this instruction.

[0084] Specifically, when the decoding and identification module recognizes a computation instruction, it first performs a dependency judgment on the computation instruction. If the computation instruction has a dependency relationship with the instructions in the transmit buffer module, it marks the computation instruction as a dependent instruction and sends it to the transmit buffer module, and identifies the corresponding dependent superior instruction. If the computation instruction does not have a dependency relationship with the instructions in the transmit buffer module, it marks the computation instruction as an out-of-order instruction and sends it to the transmit buffer module.

[0085] In one embodiment of the present invention, based on the launch buffer module, the following will provide a possible embodiment and describe its specific implementation in a non-limiting manner.

[0086] The issue cache module is a brand-new module added in this invention to ensure efficient concurrent out-of-order execution of instructions. The issue cache module maintains n cache groups (n represents an unknown number that can be set freely) to store the identification instructions sent from the decoding identification module. The n cache groups are divided into 5 categories: out-of-order instruction cache group, integer calculation dependent cache group, floating-point calculation dependent cache group, special function dependent cache group, and memory access instruction cache group.

[0087] The specific functions of the launch buffer module are as follows:

[0088] When the identifier instruction sent by the decoding identifier module is a jump instruction, barrier instruction, or out-of-order instruction, the transmit buffer module places the identifier instruction in the highest bit of the out-of-order instruction buffer group for maintenance.

[0089] When the identifier instruction sent by the decoding identifier module is a memory access instruction, it is first necessary to determine whether the memory access instruction is a dependent memory access instruction. If the memory access instruction is a dependent memory access instruction, the dependent parent instruction of the memory access instruction is extracted from the out-of-order instruction cache group, and the dependent parent instruction and the memory access instruction are stored in the memory access instruction cache group in turn. If the memory access instruction is not a dependent memory access instruction, the memory access instruction is placed in the least significant bit of the memory access instruction cache group for maintenance.

[0090] When the identifier instruction sent by the decoding identifier module is a dependent instruction, the dependent parent instruction is retrieved from the out-of-order instruction cache group. Based on the computation execution unit of the dependent instruction, both the parent instruction and the dependent instruction are then stored in the corresponding instruction cache group for maintenance. For example, when the identifier instruction sent by the decoding identifier module is a dependent instruction, the issue cache module will retrieve the dependent parent instruction from the out-of-order instruction cache group and, based on the computation execution unit corresponding to the dependent instruction, store both the parent instruction and the dependent instruction in the corresponding integer / floating-point / special function instruction cache group for maintenance.

[0091] As can be seen, in this system, because the issue buffer module divides instructions into dependent instructions and out-of-order instructions, it can issue and execute dependent instructions and out-of-order instructions simultaneously, thus breaking the sequential execution of instructions in the original SIMT architecture of GPGPU. At the same time, because the issue buffer module also classifies instructions according to the computational execution unit of the instruction execution, it can issue execution instructions of different computational execution units simultaneously, thus ensuring the synchronous execution of all computational execution units within the GPGPU core at the same time, and improving the utilization efficiency of GPGPU core computing resources.

[0092] like Figure 2 As shown, the following is an embodiment of a method for concurrent out-of-order execution of kernel instructions provided by this disclosure. This method and the kernel instruction concurrent out-of-order execution system of the above embodiments belong to the same inventive concept. For details not described in detail in the embodiments of the kernel instruction concurrent out-of-order execution method, please refer to the embodiments of the kernel instruction concurrent out-of-order execution system described above.

[0093] A method for concurrent out-of-order execution of kernel instructions, comprising the following steps:

[0094] S101: Obtain the register information sent by the instruction decoding module through the decoding identifier module, extract the number register address, destination register address, and the type of computation execution unit required by the instruction, and convert the extracted information into binary information.

[0095] S102: Based on the computation execution unit category information required by the instruction, set the corresponding computation execution module identifier bit in the instruction, and based on the register address information involved in the instruction execution, set the corresponding register identifier bit in the instruction.

[0096] For example, specifically, the decoding identification module first sets the corresponding computation execution module identifier bit in the instruction based on the category information of the computation execution unit required by the instruction:

[0097] If integer calculation is required, the corresponding calculation execution module identifier is 00; if floating-point calculation is required, the corresponding calculation execution module identifier is 01; if special function calculation is required, the corresponding calculation execution module identifier is 10; and if memory access calculation is required, the corresponding calculation execution module identifier is 11.

[0098] Then, based on the register address information involved in the instruction execution, the corresponding register flag bits in the instruction are set. For example, if the instruction execution involves register addresses 0 / 1 / 3, then the 0 / 1 / 3 bits in the register flag bits are set to 1.

[0099] S103: The decoding and identification module compares the register identifier information of the current instruction with the instruction register identifier information maintained in the issue buffer module. Based on the comparison result, it identifies dependent instructions and out-of-order instructions, and sends the instructions to the corresponding type of buffer group for caching.

[0100] For example, the decoding identifier module compares the register identifier information of the current instruction with the instruction register identifier information maintained in the issue cache module. If both bits are 1, the current instruction is a dependent instruction, and the instruction maintained in the issue cache module is a dependent parent instruction. Then, the dependent parent instruction and the dependent instruction are sent together to the corresponding cache group (dependent integer calculation cache group, dependent floating-point calculation cache group, dependent special function cache group, memory access instruction cache group) according to the calculation module identifier information. If no bits are 1, the current instruction is an out-of-order instruction, and the out-of-order instruction is sent to the out-of-order instruction cache group.

[0101] S104: When all dependent instructions exist in the dependent integer calculation cache group, dependent floating-point calculation cache group, dependent special function cache group, and memory access instruction cache group in the issue cache module, the instructions in these cache groups are sent synchronously to the corresponding computation execution units of the computation execution module for computation. If any of these cache groups does not contain dependent instructions, an out-of-order instruction is extracted from the out-of-order instruction cache group and sent to the corresponding computation execution unit of the computation execution module for computation.

[0102] In this step, when all four dependent computation module cache groups (dependent integer computation cache group, dependent floating-point computation cache group, dependent special function cache group, and memory access instruction cache group) in the launch cache module have dependent instructions, the instructions in the four dependent computation module cache groups are launched synchronously first. If a dependent computation cache module does not have dependent instructions, the out-of-order instructions of the corresponding computation module are selected from the out-of-order instruction cache group to be launched, ensuring that four sets of instructions to be executed are successfully launched at the same time.

[0103] The kernel instruction concurrent out-of-order execution method provided in this embodiment achieves high efficiency and flexibility in instruction execution through the fine processing of the decoding and identification module and the intelligent scheduling of the launch buffer module.

[0104] This method first uses a decoding and identification module to accurately extract key information from the instruction, such as register address, destination register address, and computation execution unit type, and converts this information into binary form, laying a solid foundation for subsequent processing. Based on this, the corresponding computation execution module identifier bit is set according to the computation execution unit type information required by the instruction, and the corresponding register identifier bit is set according to the register address information involved in the instruction execution. This step ensures that the instruction can be accurately classified and identified.

[0105] Next, through the collaborative work of the decoding identification module and the issue buffer module, effective differentiation between dependent instructions and out-of-order instructions is achieved. Dependent instructions are sent to the corresponding dependent buffer group along with the parent instructions, while out-of-order instructions are sent to the out-of-order instruction buffer group. This mechanism not only ensures the sequential execution of instructions but also makes full use of idle computing resources, improving overall computational efficiency.

[0106] During the instruction issuance phase, this method prioritizes the synchronous issuance of instructions from four dependent computation module cache groups. If a dependent computation module has no dependent instructions, it selects and issues out-of-order instructions from the out-of-order instruction cache group to the corresponding computation module. This strategy ensures that four sets of instructions to be executed are successfully issued at the same time, maximizing the utilization of the computational execution unit's computing power while avoiding the waste of computing resources.

[0107] In summary, this in-core instruction concurrent out-of-order execution method, through refined instruction classification and intelligent scheduling strategies, achieves efficient utilization of computing resources and continuous operation of the instruction pipeline, significantly improving the computing performance and flexibility of GPGPUs.

[0108] Furthermore, as a refinement and extension of the specific implementation methods described above, and to fully illustrate the specific implementation process in this embodiment, 10 specific instructions are used as an example, with reference to... Figure 3 The execution principle diagram shown provides another method for concurrent out-of-order execution of kernel instructions. The specific steps are as follows:

[0109] S201: The decoding and identification module receives instruction 0, identifies that its instruction execution calculation module is an integer calculation, so it sets the calculation module identifier to 00; it identifies that the required register address is 0 / 1 / 3, so it pulls the register identifier bit 0 / 1 / 3 high; it identifies the instruction register identifier information in the issue buffer module. Since the issue buffer module is empty at this time, instruction 0 has no dependency relationship, so it stores instruction 0 in the out-of-order execution buffer group.

[0110] S202: The decoding and identification module receives instruction 1, identifies that its instruction execution calculation module is an integer calculation, so it sets the calculation module identifier to 00; it identifies that the required register address is 5 / 6 / 7, so it pulls the register identifier bits 5 / 6 / 7 high; it identifies the instruction register identifier information in the issue buffer module. Since the issue buffer module only has the 0 / 1 / 3 register identifier information of instruction 0 at this time, there is no register conflict with instruction 1, so instruction 1 has no dependency relationship and is stored in the out-of-order execution buffer group.

[0111] S203: The decoding and identification module receives instruction 2, identifies that its instruction execution calculation module is an integer calculation, so it sets the calculation module identifier to 00; it identifies that the required register address is 2 / 4 / 8, and pulls up the corresponding register identifier bits 2 / 4 / 8; it identifies the instruction register identifier information in the issue buffer module. Since the issue buffer module has the 0 / 1 / 3 and 5 / 6 / 7 register identifier information of instruction 0 and instruction 1 at this time, there is no register conflict with instruction 2, so instruction 2 has no dependency relationship and is stored in the out-of-order execution buffer group.

[0112] S204: The decoding and identification module receives instruction 3, identifies that its instruction execution calculation module is a floating-point calculation, so it sets the calculation module identifier to 01; it identifies that the required register address is 9 / 10 / 11, and pulls up the corresponding register identifier bits 9 / 10 / 11; it identifies the instruction register identifier information in the issue buffer module, because at this time the issue buffer module has the register identifier information 0 / 1 / 3, 5 / 6 / 7, 2 / 4 / 8 of instructions 0, 1, and 2, and there is no register conflict with instruction 3, so instruction 3 has no dependency relationship, and stores instruction 3 in the out-of-order execution buffer group.

[0113] S205: The decoding and identification module receives instruction 4, identifies that its instruction execution calculation module is a special function calculation, so it sets the calculation module identifier to 10; it identifies that the required register address is 12 / 13 / 14, and pulls the corresponding register identifier bits 12 / 13 / 14 high; it identifies the instruction register identifier information in the issue buffer module, because at this time the issue buffer module has the register identifier information 0 / 1 / 3, 5 / 6 / 7, 2 / 4 / 8, 9 / 10 / 11 of instructions 0, 1, 2, 3, which does not conflict with the register of instruction 4, so instruction 4 has no dependency relationship, and stores instruction 4 in the out-of-order execution buffer group.

[0114] S206: The decoding and identification module receives instruction 5, identifies its instruction execution calculation module as a memory access module, so it sets the calculation module identifier to 11; it identifies the required register addresses as 15 / 18 / 19, and pulls up the corresponding register identifier bits 15 / 18 / 19; it identifies the instruction register identifier information in the issue buffer module, because at this time the issue buffer module has the register identifier information 0 / 1 / 3, 5 / 6 / 7, 2 / 4 / 8, 9 / 10 / 11, 12 / 13 / 14 for instructions 0, 1, 2, 3, and 4, and there is no register conflict with instruction 5, so instruction 5 has no dependency relationship. However, since instruction 5 is a memory access instruction, instruction 5 is stored in the memory access instruction cache group.

[0115] S207: The decoding and identification module receives instruction 6, identifies its instruction execution calculation module as an integer module, so it sets the calculation module identifier to 00; it identifies the required register address as 2 / 16 / 17, and pulls up the corresponding register identifier bits 2 / 16 / 17; it identifies the instruction register identifier information in the issue buffer module. Because the identifier information of registers 2 / 4 / 8 of instruction 2 in the issue buffer module conflicts with register 2 of instruction 6, instruction 5 is a dependent instruction and instruction 2 is a dependent parent instruction. Subsequently, since instruction 6 is an integer instruction, instruction 2 and instruction 6 are stored in the dependent integer calculation buffer group in sequence.

[0116] S208: The decoding and identification module receives instruction 7, identifies its instruction execution calculation module as a floating-point module, so it sets the calculation module identifier to 01; it identifies the required register address as 9 / 21 / 22, and pulls up the corresponding register identifier bits 9 / 21 / 22; it identifies the instruction register identifier information in the issue buffer module. Because the 9 / 10 / 11 register identifier information of instruction 3 in the issue buffer module conflicts with register 9 of instruction 7, instruction 7 is a dependent instruction and instruction 3 is a dependent super-instruction. Subsequently, since instruction 7 is a floating-point instruction, instruction 3 and instruction 7 are stored in the dependent floating-point calculation buffer group in sequence.

[0117] S209: The decoding and identification module receives instruction 8, identifies its instruction execution calculation module as a special function calculation module, so it sets the calculation module identifier to 10; it identifies the required register address as 13 / 20, and pulls the corresponding register identifier bits 13 / 20 high; it identifies the instruction register identifier information in the issue buffer module. Because the identifier information of registers 12 / 13 / 14 of instruction 4 in the issue buffer module conflicts with register 13 of instruction 8, instruction 8 is a dependent instruction and instruction 4 is a dependent super-instruction. Subsequently, based on the fact that instruction 8 is a special function calculation instruction, instruction 4 and instruction 8 are stored in the dependent special function cache group in sequence.

[0118] S210: The decoding and identification module receives instruction 9, identifies its instruction execution calculation module as a memory access module, so it sets the calculation module identifier to 11; it identifies the required register address as 19 / 23, and pulls up the corresponding register identifier bits 19 / 23; it identifies the instruction register identifier information in the issue buffer module. Because the 15 / 18 / 19 register identifier information of instruction 5 in the issue buffer module conflicts with register 19 of instruction 9, instruction 9 is a dependent instruction and instruction 5 is a dependent parent instruction. Subsequently, since instruction 9 is a memory access instruction, instruction 5 and instruction 9 are stored in the memory access instruction cache group in sequence.

[0119] Figure 4 A schematic diagram of the hardware structure of an electronic device for implementing various embodiments of the present invention.

[0120] The kernel instruction concurrent out-of-order execution method provided in this application can be applied to electronic devices. Those skilled in the art will understand that the electronic device structure involved in the embodiments of this invention does not constitute a limitation on the electronic device. An electronic device may include more or fewer components than illustrated, or combine certain components, or have different component arrangements. In the embodiments of this invention, electronic devices include, but are not limited to, laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic devices may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the embodiments of this application described and / or claimed herein.

[0121] Electronic devices may include processors, external memory interfaces, internal memory, universal serial bus (USB) interfaces, charging management modules, power management modules, batteries, wireless communication modules, audio modules, speakers, microphones, sensor modules, buttons, cameras, displays, and SIM card interfaces, etc.

[0122] A processor may include one or more processing units, such as: a central processing unit (CPU), an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors.

[0123] The processor can serve as the nerve center and command center of an electronic device. The controller can generate operation control signals based on the instruction opcode and timing signals to control the fetching and execution of instructions.

[0124] The processor may also include memory for storing instructions and data. In some embodiments, the memory in the processor is a cache memory. This memory can store instructions or data that the processor has just used or that are used repeatedly. If the processor needs to use the instruction or data again, it can retrieve it directly from this memory. This avoids repeated accesses, reduces processor latency, and thus improves system efficiency.

[0125] An external storage interface (ESI) can be used to connect external memory cards, such as microSD cards, to expand the storage capacity of electronic devices. The external memory card communicates with the processor through the ESI to perform data storage functions, such as saving music and video files on the external memory card.

[0126] Internal memory can be used to store computer executable program code, which includes instructions. The processor executes various functional applications and data processing of electronic devices by running the instructions stored in internal memory. Internal memory can include a program storage area and a data storage area. Internal memory can include high-speed random access memory, and can also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc.

[0127] Wireless communication functionality in electronic devices can be achieved through antennas, wireless communication modules, modem processors, and baseband processors.

[0128] Wireless communication modules can provide solutions for wireless communication applications in electronic devices, including wireless local area networks (WLANs) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) technologies.

[0129] Electronic devices can implement audio functions through audio modules, speakers, receivers, microphones, headphone jacks, and application processors.

[0130] Electronic devices can achieve shooting functions through ISPs, cameras, video codecs, GPUs, displays, and application processors.

[0131] Electronic devices can achieve display functions through GPUs, displays, and application processors.

[0132] A GPU is a microprocessor for image processing, connected to the display screen and application processor. GPUs are used to perform mathematical and geometric calculations for graphics rendering. A processor may include one or more GPUs, which execute program instructions to generate or modify display information.

[0133] A display screen is used to display images, videos, etc. A display screen includes a display panel.

[0134] The aforementioned electronic device achieves the following technical effects of the kernel instruction concurrent out-of-order execution method of this application:

[0135] First, the instruction information is accurately extracted by the decoding and identification module, and the instructions are classified and identified according to the type of computation execution unit and register address information. Then, the issue cache module intelligently distinguishes between dependent instructions and out-of-order instructions, caching them in their respective cache groups. During the instruction issuance phase, instructions from the four dependent computation module cache groups are issued synchronously first. When a dependent cache group is idle, out-of-order instructions are issued to ensure full utilization of computing resources. This electronic device, by executing in-core instructions concurrently out of order, not only improves the computational efficiency of the GPGPU but also enhances the flexibility of instruction execution, effectively avoiding idle and wasted computing resources. Overall, this electronic device, through the execution of in-core instructions concurrently out of order for fine-grained instruction classification and intelligent scheduling, achieves efficient allocation and utilization of computing resources, providing strong support for improving GPGPU performance.

[0136] The storage medium provided in this application stores a program product capable of implementing a method for concurrent out-of-order execution of kernel instructions.

[0137] In-kernel instruction concurrent out-of-order execution methods include:

[0138] The decoding and identification module obtains the register information sent by the instruction decoding module, extracts the number register address, destination register address, and the type of computation execution unit required by the instruction, and converts the extracted information into binary information.

[0139] Based on the computational execution unit category information required by the instruction, set the corresponding computational execution module identifier bit in the instruction, and based on the register address information involved in the instruction execution, set the corresponding register identifier bit in the instruction;

[0140] The decoding and identification module compares the register identifier information of the current instruction with the instruction register identifier information maintained in the issue buffer module. Based on the comparison result, dependent instructions and out-of-order instructions are identified, and the instructions are sent to the corresponding type of buffer group for caching according to the identification result.

[0141] When all dependent instructions exist in the dependent integer calculation cache group, dependent floating-point calculation cache group, dependent special function cache group, and memory access instruction cache group in the issue cache module, the instructions in these cache groups are prioritized and synchronously sent to the corresponding computation execution unit of the computation execution module for computation. If any of these cache groups does not contain dependent instructions, an out-of-order instruction is extracted from the out-of-order instruction cache group and sent to the corresponding computation execution unit of the computation execution module for computation.

[0142] In some possible implementations, the kernel instruction concurrent out-of-order execution method of this disclosure can be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure.

[0143] The storage medium disclosed herein may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0144] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A kernel-based concurrent out-of-order instruction execution system, characterized in that, include: The module includes a thread scheduling module, an instruction fetch module, an instruction decoding module, a decoding flag module, an issue buffer module, an operand collection module, a computation execution module, and a result write-back module. The thread bundle scheduling module is a register group used to maintain the number of thread bundle slots. It performs core task switching by calculating the thread bundle granularity by sending the program counter count value to the instruction fetch module. The instruction fetch module is used to use the program counter value as the fetch PC, use the fetch PC as the address to read instruction data from the L1 cache outside the computing core, and then store the instruction data in the core instruction cache. The instruction decoding module is used to read instruction data from the kernel instruction cache in a first-in-first-out manner, decode the instruction data into register information that the computing core can recognize, and send it to the decoding identification module. The decoding and identification module is used to determine the classification of kernel instructions based on register information, classifying kernel instructions into five instruction types, classifying and identifying them according to the instruction type, generating identification instructions and sending them to the issue buffer module, and sending corresponding control signals to ensure concurrent out-of-order execution of instructions; the five instruction types include: jump instructions, memory access instructions, barrier instructions, dependent instructions, and out-of-order instructions; The issue cache module contains multiple cache groups to store identification instructions from the decoding identification module. The issue cache module divides the cache groups into five types. Based on the instruction type of the identification instruction, it stores the instruction into the corresponding type of cache group and synchronously sends the identification instructions in the cache group to the computation execution module for synchronous execution based on the storage status in the cache group. The types of cache groups include out-of-order instruction cache group, integer-dependent calculation cache group, floating-point-dependent calculation cache group, special function-dependent cache group, and memory access instruction cache group. The operand collection module maintains multiple sets of register values ​​on a thread-by-thread basis and reads specific data from the corresponding register address of the corresponding thread according to the instruction information issued by the issue buffer module. The computation execution module has four types of computation execution units, which are used to synchronously receive the identification instructions issued by the transmit buffer module, and synchronously execute various computational task loads according to the instruction type of the identification instructions, and generate result data after the computation is completed; the computation execution units include integer computation unit, floating-point computation unit, special function computation unit and memory access computation unit; The result write-back module receives the result data generated by the computation execution module and writes it back to the corresponding position in the operand collection module according to the corresponding thread identifier and register address.

2. The kernel instruction concurrent out-of-order execution system according to claim 1, characterized in that, The register information includes: the addresses of three source operand registers, the address of one destination register, the type of computation execution unit required for the instruction data, the type of computation to be performed, the immediate value required for the computation, and the instruction fetch PC of the current instruction required for the computation.

3. The kernel instruction concurrent out-of-order execution system according to claim 1, characterized in that, The step of classifying and identifying instructions according to their types, generating identification instructions, sending them to the transmit buffer module, and sending corresponding control signals to ensure concurrent out-of-order execution of instructions includes: When the instruction type is a jump instruction, a pause instruction is sent to the instruction fetch module and the instruction decode module to pause their execution; a clear signal is sent to the kernel instruction cache to clear all instruction information existing in the kernel instruction cache; When the instruction type is a memory access instruction, a dependency judgment is performed on the memory access instruction; if the memory access instruction has no dependency, the memory access instruction is sent first; if there is a dependency, the dependent parent instruction of the memory access instruction is sent first, and the memory access instruction is sent first after all dependent parent instructions have been executed. When the instruction type is a barrier instruction, a pause instruction is sent to the instruction fetch module and the instruction decode module to pause their execution until all instructions and barrier instructions in the issue buffer module have been executed.

4. The kernel instruction concurrent out-of-order execution system according to claim 3, characterized in that, The step of classifying and identifying instructions according to their types, generating identification instructions and sending them to the transmit buffer module, and sending corresponding control signals to ensure concurrent out-of-order execution of instructions also includes: If the instruction type of the current kernel instruction is not a jump instruction, memory access instruction, or barrier instruction, then the kernel instruction is considered a computation instruction. The computation instruction is evaluated for dependency. If the computation instruction has a dependency relationship with the instruction in the launch buffer module, the computation instruction is marked as a dependent instruction and sent to the launch buffer module, and the corresponding dependent parent instruction is identified. If the computation instruction does not have a dependency relationship with the instruction in the launch buffer module, the computation instruction is marked as an out-of-order instruction and sent to the launch buffer module.

5. The kernel instruction concurrent out-of-order execution system according to claim 4, characterized in that, The transmit buffer module is specifically used for: When the identifier instruction sent by the decoding identifier module is a jump instruction, barrier instruction, or out-of-order instruction, the identifier instruction is placed in the highest bit of the out-of-order instruction cache group for maintenance. When the identifier instruction sent by the decoding identifier module is a dependent instruction, the dependent parent instruction of the dependent instruction is extracted from the out-of-order instruction cache group, and the dependent parent instruction and the dependent instruction are stored in the corresponding instruction cache group for maintenance according to the calculation and execution unit of the dependent instruction. When the identifier instruction sent by the decoding identifier module is a memory access instruction, it is determined whether the memory access instruction is a dependent memory access instruction. If the memory access instruction is a dependent memory access instruction, the dependent parent instruction of the memory access instruction is extracted from the out-of-order instruction cache group, and the dependent parent instruction and the memory access instruction are stored in the memory access instruction cache group in turn. If the memory access instruction is not a dependent memory access instruction, the memory access instruction is placed in the least significant bit of the memory access instruction cache group for maintenance.

6. A method for concurrent out-of-order execution of kernel instructions, characterized in that, The method employs the kernel instruction concurrent out-of-order execution system as described in any one of claims 1 to 5; The method includes: The decoding and identification module obtains the register information sent by the instruction decoding module, extracts the number register address, destination register address, and the type of computation execution unit required by the instruction, and converts the extracted information into binary information. Based on the computational execution unit category information required by the instruction, set the corresponding computational execution module identifier bit in the instruction, and based on the register address information involved in the instruction execution, set the corresponding register identifier bit in the instruction; The decoding and identification module compares the register identifier information of the current instruction with the instruction register identifier information maintained in the issue buffer module. Based on the comparison result, dependent instructions and out-of-order instructions are identified, and the instructions are sent to the corresponding type of buffer group for caching according to the identification result. When all dependent instructions exist in the dependent integer calculation cache group, dependent floating-point calculation cache group, dependent special function cache group, and memory access instruction cache group in the issue cache module, the instructions in these cache groups are prioritized and synchronously sent to the corresponding computation execution unit of the computation execution module for computation. If any of these cache groups does not contain dependent instructions, an out-of-order instruction is extracted from the out-of-order instruction cache group and sent to the corresponding computation execution unit of the computation execution module for computation.

7. The method for concurrent out-of-order execution of kernel instructions according to claim 6, characterized in that, The step of setting the corresponding computation execution module identifier bit in the instruction based on the computation execution unit category information required by the instruction, and setting the corresponding register identifier bit in the instruction based on the register address information involved in the instruction execution, includes: If the computation execution unit required by the instruction is an integer computation unit, then the computation execution module identifier is set to 00; If the computation execution unit required by the instruction is a floating-point computation unit, then the computation execution module identifier position is set to 01; If the computation execution unit required by the instruction is a special function computation unit, then the computation execution module identifier position is set to 10; If the computation execution unit required by the instruction is a memory access computation unit, then the computation execution module identifier position is set to 11; Based on the register address information involved in the instruction execution, set the corresponding register identifier in the instruction to 1.

8. The method for concurrent out-of-order execution of kernel instructions according to claim 7, characterized in that, The decoding and identification module compares the register identifier information of the current instruction with the instruction register identifier information maintained in the issue buffer module, identifies dependent instructions and out-of-order instructions based on the comparison result, and sends the instructions to the corresponding type of buffer group for caching based on the identification result, including: The decoding and identification module compares the register identifier information of the current instruction with the instruction register identifier information maintained in the issue buffer module. If the same position is 1, the current instruction is a dependent instruction, and the instruction maintained in the emit buffer module is a dependent parent instruction; according to the identifier information of the calculation execution module, the dependent parent instruction and the dependent instruction are sent together to the corresponding buffer group for caching; If there are no instances where all positions are 1, then the current instruction is an out-of-order instruction, and the out-of-order instruction is sent to the out-of-order instruction cache group for caching.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the in-core instruction concurrent out-of-order execution method as described in any one of claims 6 to 8.

10. A storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the in-kernel instruction concurrent out-of-order execution method as described in any one of claims 6 to 8.

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