Display device and inspection method thereof

Abstract

A display device and an inspection method thereof are provided. The display device includes: a touch sensor including a touch panel and a touch controller; and a crystal unit connected to the touch controller. The touch controller includes: a plurality of sensing channels connected to the touch panel; and a feedback circuit. The crystal unit is connected to at least one of the sensing channels in a first mode, and is connected to the feedback circuit in a second mode.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0153805 filed in the Korean Intellectual Property Office on November 8, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of the present disclosure relate to a display device and a method for inspecting the display device. Background Art

[0003] As information technology advances, the importance of display devices as a connecting medium between users and information has been increasing. Summary of the invention

[0004] Embodiments of the present disclosure provide a display device and an inspection method of the display device, which can accurately inspect the cause of a defect in a crystal unit.

[0005] According to an embodiment of the present disclosure, a display device includes: a touch sensor including a touch panel and a touch controller; and a crystal unit connected to the touch controller. The touch controller includes: a plurality of sensing channels connected to the touch panel; and a feedback circuit. The crystal unit is connected to at least one of the sensing channels in a first mode and is connected to the feedback circuit in a second mode.

[0006] In an embodiment, a crystal unit includes: a crystal oscillator disposed between a first terminal and a second terminal; a first external capacitor disposed between the first terminal and a ground power supply; and a second external capacitor disposed between the second terminal and the ground power supply.

[0007] In an embodiment, in the first mode, at least one sensing channel measures at least one of a capacitance of a first external capacitor and a capacitance of a second external capacitor.

[0008] In an embodiment, the first terminal is connected to one of the sensing channels, and the one of the sensing channels measures a capacitance of the first external capacitor.

[0009] In an embodiment, the second terminal is connected to one of the sensing channels, and one of the sensing channels measures the capacitance of the second external capacitor.

[0010] In an embodiment, the first terminal is connected to a first sensing channel among the sensing channels, and the second terminal is connected to a second sensing channel among the sensing channels that is different from the first sensing channel, and the first sensing channel measures the capacitance of the first external capacitor and the second sensing channel measures the capacitance of the second external capacitor.

[0011] In an embodiment, each of the sensing channels includes: an amplifier; and a feedback capacitor connected in parallel with the amplifier.

[0012] In an embodiment, the touch controller includes a checking unit that checks whether the capacitance of the first external capacitor and the capacitance of the second external capacitor are normal values.

[0013] In an embodiment, when the capacitance of the first external capacitor and the capacitance of the second external capacitor are normal values, the first mode is switched to the second mode.

[0014] In an embodiment, in the second mode, the feedback circuit outputs an oscillation frequency of the crystal oscillator.

[0015] In an embodiment, the feedback circuit includes: an inverter; and a feedback resistor connected in parallel with the inverter.

[0016] In an embodiment, a touch panel includes a plurality of sensor electrodes that sense touch input using a self-capacitance method.

[0017] According to an embodiment of the present disclosure, a method for inspecting a display device includes: connecting a crystal unit to at least one of a plurality of sensing channels of a touch controller; measuring an external capacitance of the crystal unit; and inspecting whether the external capacitance is a normal value, wherein the display device includes a touch sensor and a crystal unit, and the touch sensor includes a touch panel and a touch controller.

[0018] In an embodiment, a crystal unit includes: a crystal oscillator disposed between a first terminal and a second terminal; a first external capacitor disposed between the first terminal and a ground power supply; and a second external capacitor disposed between the second terminal and the ground power supply.

[0019] In an embodiment, the step of connecting the crystal unit to at least one of the sensing channels comprises connecting a first terminal to at least one of the sensing channels, and the step of measuring an external capacitance of the crystal unit comprises measuring a capacitance of a first external capacitor.

[0020] In an embodiment, the step of connecting the crystal unit to at least one of the sensing channels comprises connecting the second terminal to at least one of the sensing channels, and the step of measuring the external capacitance of the crystal unit comprises measuring the capacitance of a second external capacitor.

[0021] In an embodiment, the step of connecting the crystal unit to at least one of the sensing channels includes: connecting the first terminal to a first sensing channel of the sensing channels; and connecting the second terminal to a second sensing channel of the sensing channels that is different from the first sensing channel, and the step of measuring the external capacitance of the crystal unit includes: measuring the capacitance of the first external capacitor and the capacitance of the second external capacitor.

[0022] In an embodiment, the method of inspecting a display device further comprises the step of connecting the crystal unit to a feedback circuit of a touch controller when the external capacitance is a normal value.

[0023] In an embodiment, each of the sensing channels includes: an amplifier; and a feedback capacitor connected in parallel with the amplifier.

[0024] In an embodiment, the feedback circuit includes: an inverter; and a feedback resistor connected in parallel with the inverter. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0026] Figure 1 A display device according to an embodiment of the present disclosure is shown.

[0027] Figure 2 A connection structure in a first mode according to an embodiment of the present disclosure is shown.

[0028] Figure 3 A connection structure in the second mode according to an embodiment of the present disclosure is shown.

[0029] Figure 4 A sensing channel according to an embodiment of the present disclosure is shown.

[0030] Figure 5 A connection structure of a crystal unit in a first mode according to an embodiment of the present disclosure is shown.

[0031] Figure 6 A connection structure of a crystal unit in a first mode according to an embodiment of the present disclosure is shown.

[0032] Figure 7 A connection structure of a crystal unit in a first mode according to an embodiment of the present disclosure is shown.

[0033] Figure 8 A feedback circuit according to an embodiment of the present disclosure is shown.

[0034] Fig. 9 A method for inspecting a display device according to an embodiment of the present disclosure is shown.

[0035] Figures 10 to 16 The configuration of a display device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0036] Hereinafter, embodiments of the present disclosure will be described more fully with reference to the accompanying drawings.Throughout the drawings, like reference numerals may refer to like elements.

[0037] It will be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another element, and the elements are not limited by these terms. Therefore, the "first" element in an embodiment may be described as the "second" element in another embodiment.

[0038] Herein, when two or more processes or events are described as being performed or occurring at substantially the same time or simultaneously, it will be understood that the processes or events may be performed at exactly the same time or at approximately the same time as would be understood by one of ordinary skill in the art, or may occur at exactly the same time or at approximately the same time as would be understood by one of ordinary skill in the art. For example, as would be understood by one of ordinary skill in the art, the processes or events may be performed at approximately the same time within a measurement error or may occur at approximately the same time within a measurement error.

[0039] The terms used here are only for the purpose of describing specific embodiments, and are not intended to be limited. As used herein, unless the context clearly indicates otherwise, the singular "one", "one (kind / person)", "described / should" and "at least one (kind / person)" do not represent the limitation of quantity, but are intended to include both singular and plural. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one (kind / person)" should not be interpreted as the "one" or "one (kind / person)" of limitation. As used herein, the word "or" means logical "or", so that unless the context indicates otherwise, the expression "A, B or C" means "A and B and C", "A and B but not C", "A and C but not B", "B and C but not A", "A but not B nor C", "B but not A nor C" and "C but not A nor B".

[0040] It will also be understood that when the term "comprise" and its variations are used in this specification, it indicates the presence of stated features, integers, steps, operations, elements or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components or groups thereof.

[0041] It will be understood that when a component such as a film, region, layer, etc. is referred to as being "on," "connected to," "bound to," or "adjacent to" another component, the component such as a film, region, layer, etc. may be directly on, directly connected to, directly bound to, or directly adjacent to the other component, or there may be intervening components. It will also be understood that when a component is referred to as being "between" two components, the component may be the only component between the two components, or there may also be one or more intervening components. It will also be understood that when a component is referred to as "overlying" another component, the component may be the only component that overlies the other component, or one or more intervening components may also overlie the other component. Other words used to describe relationships between components should be interpreted in a similar manner.

[0042] Figure 1 A display device according to an embodiment of the present disclosure is shown.

[0043] Reference Figure 1 , the display device 1000 may include a touch sensor 100 and a crystal unit 200. The crystal unit 200 may also be referred to as a crystal circuit or a crystal oscillator. The touch sensor 100 may include a touch panel 110 and a touch controller 120. The touch controller 120 may also be referred to as a touch controller circuit.

[0044] The touch panel 110 may include a plurality of touch electrodes TSE that sense a touch input using a self-capacitance method. Each of the touch electrodes TSE may have a self-capacitance relative to a reference potential (e.g., a ground potential). The touch electrodes TSE may be distributed and arranged in a touch region of the touch panel 110. For example, the touch electrodes TSE may be distributed in a matrix form at a predetermined density or resolution at positions corresponding to coordinates (e.g., two-dimensional coordinates) defined in the touch region.

[0045] A plurality of touch wirings TSL may be connected to the touch electrode TSE. The touch electrode TSE may be connected to the touch controller 120 through the touch wirings TSL. A driving signal may be applied to the touch electrode TSE through the touch wirings TSL. In addition, a change in capacitance generated in the touch electrode TSE may be sensed through the touch wirings TSL.

[0046] However, the present disclosure is not limited to the above-described embodiments. For example, according to an embodiment, the touch panel 110 may be formed in a structure for sensing a touch input in a mutual capacitance method.

[0047] The touch controller 120 may be electrically connected to the touch panel 110. For example, the touch controller 120 may be connected to the touch electrode TSE through the touch wiring TSL. The touch controller 120 may sense a touch input generated on the touch panel 110. For example, when the touch controller 120 applies a driving signal to the touch electrode TSE, each of the touch electrodes TSE may form a predetermined capacitance. In this case, when a touch input (e.g., a user's touch) occurs on the touch electrode TSE, an additional capacitance may be generated between the touch electrode TSE and the user, so that the capacitance of the touch electrode TSE may be changed. The touch controller 120 may sense whether a touch input occurs, a touch position, etc., through changes in the capacitance formed in each of the touch electrodes TSE.

[0048] The active pen AP is an input device that generates a pen signal by itself. The touch controller 120 may receive the pen signal to sense a position touched by the active pen AP on the touch panel 110. For example, the active pen AP may output the pen signal in synchronization with a driving signal of the touch controller 120.

[0049] The crystal unit 200 may be connected to the touch controller 120. The crystal unit 200 may provide a predetermined frequency signal to the touch controller 120. The predetermined frequency signal may be set to a frequency suitable for sensing a touch position of the active pen AP. The touch controller 120 may generate a driving signal for sensing a touch position of the active pen AP based on the predetermined frequency signal provided from the crystal unit 200.

[0050] The crystal unit 200 may constantly provide a predetermined frequency signal to the touch controller 120. However, when a defect occurs in the crystal unit 200, the predetermined frequency may change. In this case, it may be difficult to determine whether the defect of the crystal unit 200 is caused by the first external capacitor Ce1 and / or the second external capacitor Ce2, or by the crystal oscillator X-TAL (see Figure 5 ). The crystal oscillator X-TAL can also be called a crystal oscillator circuit.

[0051] Figure 2 A connection structure in a first mode according to an embodiment of the present disclosure is shown. Figure 3 A connection structure in the second mode according to an embodiment of the present disclosure is shown.

[0052] Reference Figure 2 and Figure 3 , the crystal unit 200 may include a first terminal X1 and a second terminal X2. The crystal unit 200 may be connected to the touch controller 120 through the first terminal X1 and the second terminal X2. The connection structure of the crystal unit 200 may be different in the first mode MODE1 and the second mode MODE2.

[0053] The touch controller 120 may include at least one sensing channel 121, a feedback circuit 122, and a checking unit 123. The checking unit 123 may also be referred to as a checking circuit.

[0054] Reference Figure 2 , the first mode MODE1 may be a mode for inspecting the crystal unit 200 to determine whether the crystal unit 200 is defective. For example, in the first mode MODE1, an inspection may be performed to determine whether the first external capacitor Ce1 and / or the second external capacitor Ce2 (see Figure 5 ) whether there are defects.

[0055] In the first mode MODE1, the first terminal X1 and the second terminal X2 of the crystal unit 200 may be connected to at least one sensing channel 121. The at least one sensing channel 121 may measure at least one of the capacitance of the first external capacitor Ce1 and the capacitance of the second external capacitor Ce2. The capacitance of the first external capacitor Ce1 and / or the capacitance of the second external capacitor Ce2 measured in the at least one sensing channel 121 may be provided to the inspection unit 123. Figure 4 The specific structure of the at least one sensing channel 121 is further described in detail.

[0056] The inspection unit 123 may be connected to at least one sensing channel 121. In the first mode MODE1, the inspection unit 123 may detect whether the first and second external capacitors Ce1 and Ce2 are defective based on capacitances of the first and second external capacitors Ce1 and Ce2 provided from the at least one sensing channel 121.

[0057] For example, the inspection unit 123 may be configured to generate a crystal oscillator X-TAL (see Figure 5 ) to detect whether the first external capacitor Ce1 and the second external capacitor Ce2 are defective. The load capacitance refers to the capacitance value at which the crystal oscillator X-TAL can oscillate normally, and can be specified when the crystal oscillator X-TAL is manufactured. The load capacitance is mathematically the capacitance of the crystal unit 200 observed from the first terminal X1 and the second terminal X2, and can be expressed as the following equation 1.

[0058] [Equation 1] C L =C1×C2 / (C1+C2)+Cs Here, C Lis the load capacitance, C1 is the capacitance of the first external capacitor Ce1, C2 is the capacitance of the second external capacitor Ce2, and Cs is the stray capacitance. The stray capacitance means the sum of the parasitic capacitance of the first terminal X1 and the second terminal X2 and the capacitance generated from the printed circuit board (PCB), and the sum may be known in advance through measurement.

[0059] When the capacitance of the first external capacitor Ce1 and the capacitance of the second external capacitor Ce2 do not satisfy the load capacitance, the inspection unit 123 may determine that a defect has occurred in the first external capacitor Ce1 and the second external capacitor Ce2 .

[0060] On the contrary, when the capacitance of the first external capacitor Ce1 and the capacitance of the second external capacitor Ce2 meet the load capacitance, the inspection unit 123 can determine that the first external capacitor Ce1 and the second external capacitor Ce2 are normal. In this case, the first mode MODE1 can be terminated and the crystal unit 200 can be switched to operate in the second mode MODE2.

[0061] For example, the inspection unit 123 may detect whether the first external capacitor Ce1 and the second external capacitor Ce2 are defective through a negative resistance of the crystal oscillator X-TAL. Negative resistance is a conceptual term and may be expressed as Equation 2 below.

[0062] [Equation 2] -R=-g m / (w 2 ×C1×C2) Here, -R is a negative resistance, C1 is the capacitance of the first external capacitor Ce1, C2 is the capacitance of the second external capacitor Ce2, and w is the oscillation frequency of the crystal oscillator X-TAL. m refers to the inverter INV (see Figure 8 ) and this value may be known in advance through measurement.

[0063] The inspection unit 123 may compare the negative resistance with an equivalent series resistance (ESR) of the crystal oscillator X-TAL (refer to Equation 3 below) to detect whether the first external capacitor Ce1 and the second external capacitor Ce2 are defective.

[0064] [Equation 3] -R≥5×ESR Equivalent series resistance (ESR) refers to the resistance of the crystal oscillator X-TAL at the series resonant frequency.

[0065] When the value of negative resistance derived from the capacitance of the first and second external capacitors Ce1 and Ce2 is less than about 5 times the value of equivalent series resistance (ESR), the inspection unit 123 may determine that a defect has occurred in the first and second external capacitors Ce1 and Ce2.

[0066] On the contrary, when the value of the negative resistance derived from the capacitance of the first external capacitor Ce1 and the capacitance of the second external capacitor Ce2 exceeds about 5 times the value of the equivalent series resistance (ESR) of the crystal oscillator X-TAL, the inspection unit 123 can determine that the first external capacitor Ce1 and the second external capacitor Ce2 are normal. In this case, the first mode MODE1 can be terminated, and the crystal unit 200 can be switched to operate in the second mode MODE2.

[0067] In some embodiments, when the capacitance of the first external capacitor Ce1 and the capacitance of the second external capacitor Ce2 satisfy both the load capacitance and the negative resistance, the inspection unit 123 can determine that the first external capacitor Ce1 and the second external capacitor Ce2 are normal. In this case, the first mode MODE1 can be terminated, and the crystal unit 200 can be switched to operate in the second mode MODE2.

[0068] Reference Figure 3 The second mode MODE2 may be an oscillation mode of outputting an oscillation frequency OF. For example, the frequency signal generated by the crystal unit 200 may be modulated by the feedback circuit 122 to output the oscillation frequency OF.

[0069] In the second mode MODE2, the first terminal X1 and the second terminal X2 of the crystal unit 200 may be connected to the feedback circuit 122. The feedback circuit 122 may amplify and output the frequency signal generated by the crystal unit 200. Therefore, the feedback circuit 122 may output the oscillation frequency OF of the crystal oscillator X-TAL. The oscillation frequency OF output by the feedback circuit 122 may be used to sense the active pen AP (refer to Figure 1 ) of the touch position. Figure 8 The specific structure of the feedback circuit 122 is further described in detail.

[0070] Figure 4 Schematic diagram of a sensing channel according to an embodiment of the present disclosure. Figure 4 Only one touch electrode TSE and one sensing channel 121 connected thereto are shown.

[0071] Reference Figure 4 , the touch electrode TSE may have a self capacitance Cs with respect to the ground potential. The touch electrode TSE may be connected to the sensing channel 121 through the touch wiring TSL.

[0072] The sensing channel 121 may include an amplifier AMP and a feedback capacitor Cf connected in parallel with the amplifier AMP.

[0073] The first input terminal (-) of the amplifier AMP may be connected to the touch wiring TSL. A change in capacitance generated at the touch electrode TSE may be input to the first input terminal (-) of the amplifier AMP. For example, a change in capacitance of the touch electrode TSE due to the generation of an additional capacitance Cp according to a user's touch may be input to the first input terminal (-) of the amplifier AMP.

[0074] The second input terminal (+) of the amplifier AMP may be connected to a reference power source Vref. The reference power source Vref may have a potential (eg, a ground potential) suitable for sensing a changed capacitance of the touch electrode TSE.

[0075] The feedback capacitor Cf may be connected between the first input terminal (-) and the output terminal OUT of the amplifier AMP. The feedback capacitor Cf may generate a potential difference between the output terminal OUT and the first input terminal (-) of the amplifier AMP, and the feedback capacitor Cf may store charges.

[0076] The amplifier AMP may operate as a comparator. That is, the amplifier AMP may output a signal corresponding to a voltage difference between the first input terminal (-) and the second input terminal (+). The signal output from the amplifier AMP may be sent to the processor. The processor may detect a touch input based on the signal output from the sensing channel 121.

[0077] Figure 5 FIG. 2 shows a connection structure of a crystal unit in a first mode according to an embodiment of the present disclosure. For ease of explanation, Figure 5 Only one touch electrode TSE and one sensing channel 1211 connected thereto are shown.

[0078] Reference Figure 5 In the first mode MODE1, the first terminal X1 of the crystal unit 200 can be connected to the sensing channel 121 (see Figure 2 ) in one of the sensing channels 1211. For example, the first terminal X1 of the crystal unit 200 may be connected to the first input terminal (-) of the sensing channel 1211. The capacitance of the first external capacitor Ce1 of the crystal unit 200 may be measured through the sensing channel 1211. That is, in some embodiments, the capacitance of the first external capacitor Ce1 of the crystal unit 200 may be selectively measured.

[0079] Figure 6 FIG. 2 shows a connection structure of a crystal unit in a first mode according to an embodiment of the present disclosure. For ease of explanation, Figure 6Only one touch electrode TSE and one sensing channel 1211 connected thereto are shown.

[0080] Reference Figure 6 In the first mode MODE1, the second terminal X2 of the crystal unit 200 can be connected to the sensing channel 121 (see Figure 2 ) in one of the sensing channels 1211. For example, the second terminal X2 of the crystal unit 200 may be connected to the first input terminal (-) of the sensing channel 1211. The capacitance of the second external capacitor Ce2 of the crystal unit 200 may be measured through the sensing channel 1211. That is, in some embodiments, the capacitance of the second external capacitor Ce2 of the crystal unit 200 may be selectively measured.

[0081] Figure 7 FIG. 2 shows a connection structure of a crystal unit in a first mode according to an embodiment of the present disclosure. For ease of explanation, Figure 7 Only two touch electrodes TSE and two sensing channels 1211 and 1212 connected thereto are shown.

[0082] Reference Figure 7 In the first mode MODE1, the first terminal X1 and the second terminal X2 of the crystal unit 200 may be connected to different sensing channels 1211 and 1212. For example, in the first mode MODE1, the first terminal X1 of the crystal unit 200 may be connected to the sensing channel 121 (see Figure 2 ) in one sensing channel (or first sensing channel) 1211, and its second terminal X2 may be connected to another sensing channel (or second sensing channel) 1212 in the sensing channels 121. The first sensing channel 1211 and the second sensing channel 1212 may be different from each other.

[0083] The first terminal X1 of the crystal unit 200 may be connected to the first input terminal (-) of the first sensing channel 1211, and the second terminal X2 thereof may be connected to the first input terminal (-) of the second sensing channel 1212. The capacitance of the first external capacitor Ce1 of the crystal unit 200 may be measured through the first sensing channel 1211. The capacitance of the second external capacitor Ce2 of the crystal unit 200 may be measured through the second sensing channel 1212. That is, in some embodiments, the capacitance of the first external capacitor Ce1 and the capacitance of the second external capacitor Ce2 of the crystal unit 200 may be measured simultaneously.

[0084] Figure 8 A feedback circuit according to an embodiment of the present disclosure is shown.

[0085] Reference Figure 8, the feedback circuit 122 may include an inverter INV and a feedback resistor Rf connected in parallel with the inverter INV.

[0086] In the second mode MODE2, the crystal unit 200 can be connected to the feedback circuit 122. For example, the first terminal X1 of the crystal unit 200 can be connected to the input terminal IN of the inverter INV, and the second terminal X2 thereof can be connected to the output terminal OUT of the inverter INV. The feedback circuit 122 can amplify the frequency signal generated by the crystal unit 200. Therefore, the feedback circuit 122 can output the oscillation frequency OF of the crystal oscillator X-TAL through the output terminal OUT.

[0087] In this way, by measuring the capacitance of the first external capacitor Ce1 and the second external capacitor Ce2 of the crystal unit 200 using the sensing channel 121 of the touch controller 120 , the embodiment can accurately check defects of the crystal unit 200 caused by the first external capacitor Ce1 and the second external capacitor Ce2 .

[0088] In addition, when the oscillation frequency OF outputted by the feedback circuit 122 in the second mode MODE2 is defective (for example, when the oscillation frequency OF deviates from the natural frequency of the crystal oscillator X-TAL or is unstable), it can be determined that a defect has occurred in the crystal oscillator X-TAL. Therefore, the embodiment can accurately check whether the defect of the crystal unit 200 is caused by the crystal oscillator X-TAL rather than the first external capacitor Ce1 and the second external capacitor Ce2.

[0089] Fig. 9 A method for inspecting a display device according to an embodiment of the present disclosure is shown. For ease of explanation, further description of previously described components and technical aspects will be simplified or omitted.

[0090] Reference Figure 2 and Fig. 9 , the crystal unit 200 is connected to at least one sensing channel 121 of the touch controller 120 (S100), and the external capacitance of the crystal unit 200 is measured (S200). The external capacitance may refer to the capacitance of the first external capacitor Ce1 and the second external capacitor Ce2 (see Figure 5 ) capacitance.

[0091] Reference Figure 5 and Fig. 9 , according to an embodiment, connecting the first terminal X1 of the crystal unit 200 to one sensing channel 1211 ( S100 ) allows the capacitance of the first external capacitor Ce1 to be measured ( S200 ).

[0092] Reference Figure 6 and Fig. 9, according to an embodiment, connecting the second terminal X2 of the crystal unit 200 to one sensing channel 1211 ( S100 ) allows the capacitance of the second external capacitor Ce2 to be measured ( S200 ).

[0093] The order of measuring the capacitance of the first external capacitor Ce1 and the capacitance of the second external capacitor Ce2 is not particularly limited.

[0094] Reference Figure 7 and Fig. 9 According to an embodiment, the first terminal X1 of the crystal unit 200 may be connected to one sensing channel 1211 and the second terminal X2 thereof may be connected to another sensing channel 1212 ( S100 ), allowing the capacitance of the first external capacitor Ce1 and the capacitance of the second external capacitor Ce2 to be measured simultaneously ( S200 ).

[0095] Reference Fig. 9 , determine whether the measured external capacitance is a normal value (S300). For example, when the capacitance of the first external capacitor Ce1 and the capacitance of the second external capacitor Ce2 meet the load capacitance and / or the negative resistance, it can be determined that the capacitance of the first external capacitor Ce1 and the capacitance of the second external capacitor Ce2 are normal values. Otherwise, it can be determined that the capacitance of the first external capacitor Ce1 and the capacitance of the second external capacitor Ce2 are not normal values.

[0096] Reference Figure 8 and Fig. 9 , when the measured external capacitance is a normal value, the crystal unit 200 is connected to the touch controller 120 (see Figure 2 ) of the feedback circuit 122 (S400). When the oscillation frequency OF output from the feedback circuit 122 is normal, it is determined that the first external capacitor Ce1, the second external capacitor Ce2, and the crystal oscillator X-TAL are normal, and the inspection is terminated. When the oscillation frequency OF output from the feedback circuit 122 is defective, it is determined that the crystal oscillator X-TAL is defective, and the inspection is terminated.

[0097] Reference Fig. 9 When the measured external capacitance is not a normal value, the external capacitance is adjusted to a normal value (S500). For example, the first external capacitor Ce1 and / or the second external capacitor Ce2 may be replaced or repaired. Thereafter, the crystal unit 200 is connected to the feedback circuit 122 of the touch controller 120 (see Figure 2 ) (S400), and the subsequent operations are the same as above.

[0098] Figures 10 to 16 The configuration of a display device according to an embodiment of the present disclosure is shown.

[0099] Fig.10shows a substrate according to an embodiment of the present disclosure, Fig.11 A display device according to an embodiment of the present disclosure is shown.

[0100] In the following description, the position of the plane may be defined by the first direction DR1 and the second direction DR2, and the position of the height may be defined by the third direction DR3 (see Fig.12 The first direction DR1, the second direction DR2 and the third direction DR3 may be directions orthogonal to each other.

[0101] The substrate SUB may include a display area DA, a non-display area NDA, a first additional area ADA1, and a second additional area ADA2.

[0102] The display area DA may have a rectangular shape. Each corner of the display area DA may have an angled shape or a curved shape. In addition, in the case of a circular display, the display area DA may have a circular shape. In addition, the display area DA may have a polygonal shape and an elliptical shape other than a quadrilateral shape. In this way, the shape of the display area DA may be set differently according to the product.

[0103] Pixels may be disposed in the display area DA. Depending on the type of the display device DP, each pixel may include a light emitting diode or a liquid crystal layer.

[0104] The non-display area NDA may surround the periphery of the display area DA. For example, the non-display area NDA may have a rectangular shape. Each corner of the non-display area NDA may have an angled shape or a curved shape. Fig.10 A case where each corner of the non-display area NDA has a curved shape is shown. The non-display area NDA may have a circular shape. The shape of the non-display area NDA may be similar to that of the display area DA, and as a result, the size of the non-display area NDA may be reduced and a narrow frame structure may be achieved.

[0105] The first additional area ADA1 may be disposed between the non-display area NDA and the second additional area ADA2. The first additional area ADA1 may be connected to the non-display area NDA at a first boundary ED1. The first additional area ADA1 may be connected to the second additional area ADA2 at a second boundary ED2. The first boundary ED1 and the second boundary ED2 may extend in the first direction DR1, respectively.

[0106] The width of the first additional area ADA1 may become narrower from the first boundary ED1 to the second boundary ED2. That is, the width of the first additional area ADA1 in the first direction DR1 may become narrower toward the second direction DR2. Therefore, the first additional area ADA1 may include a curved first side surface RC1 and a curved second side surface RC2. The side surfaces RC1 and RC2 may be recessed toward the inside of the substrate (e.g., the center of the substrate).

[0107] exist Fig.11 In the embodiment, the first additional area ADA1 is shown to include two side surfaces RC1 and RC2 in the first direction DR1 and the opposite direction thereof. In the embodiment, because the boundary located in the first direction DR1 coincides with the boundary of the non-display area NDA, the first additional area ADA1 may include only the first side surface RC1. In the embodiment, because the boundary located in the opposite direction of the first direction DR1 coincides with the boundary of the non-display area NDA, the first additional area ADA1 may include only the second side surface RC2.

[0108] The second additional area ADA2 may have a rectangular shape. Each corner of the second additional area ADA2 located in the second direction DR2 may have an angled shape or a curved shape. Fig.11 A case is shown in which each corner of the second additional area ADA2 in the second direction DR2 has an angled shape.

[0109] The encapsulation film TFE may be disposed on the pixel. For example, the encapsulation film TFE may cover the pixel in the display area DA, and the boundary of the encapsulation film TFE may be disposed in the non-display area NDA. The encapsulation film TFE covers the light emitting elements and circuit elements of the pixel in the display area DA, which may prevent damage from external moisture or impact.

[0110] Sensing electrodes SC1 and SC2 (equivalent to Figure 1 The touch electrodes TSE in the packaging film TFE may be disposed on the packaging film TFE. For example, the sensing electrodes SC1 and SC2 may detect touch, hovering, gesture, proximity, etc., performed by the user's body (e.g., the user's finger). The sensing electrodes SC1 and SC2 have different shapes according to various types (such as, for example, resistive type, capacitive type, electromagnetic (EM) type, and optical type). For example, when the sensing electrodes SC1 and SC2 are configured as capacitive type, the sensing electrodes SC1 and SC2 may be configured as self-capacitive type or mutual-capacitive type. Hereinafter, for better understanding and ease of description, a case in which the sensing electrodes SC1 and SC2 are configured as mutual-capacitive type will be described as an example.

[0111] When the sensing electrodes SC1 and SC2 are configured as a mutual capacitance type, a drive signal is sent through the sensing wiring corresponding to the first sensing electrode SC1, and a sensing signal can be received through the sensing wiring corresponding to the second sensing electrode SC2, and the second sensing electrode SC2 forms a mutual capacitance with the first sensing electrode SC1. When the user's body approaches, the mutual capacitance between the first sensing electrode SC1 and the second sensing electrode SC2 can change, and the touch input from the user can be detected based on the difference between the sensing signals. In an embodiment, a drive signal is sent through the sensing wiring corresponding to the second sensing electrode SC2, and a sensing signal can be received through the sensing wiring corresponding to the first sensing electrode SC1, and the first sensing electrode SC1 forms a mutual capacitance with the second sensing electrode SC2.

[0112] Pads (or "pads") PDE1, PDE2, and PDE3 may be disposed in the second additional area ADA2. Pads PDE1 and PDE3 may be connected to sensing electrodes SC1 and SC2 disposed on the encapsulation film TFE through sensing wirings IST1 and IST2. Pads PDE1 and PDE3 may be connected to an external touch integrated chip (IC). In addition, pad PDE2 may be connected to a pixel or a driver of a pixel disposed under the encapsulation film TFE through a display wiring DST. The driver may include, for example, a scan driver, a light emitting driver, a data driver, and the like. The driver may be disposed under the encapsulation film TFE, or may be disposed on an external display IC connected through pad PDE2.

[0113] When the display device DP is a mutual capacitance type, the touch IC can send a drive signal through the first sensing wiring IST1, and can receive a sensing signal through the second sensing wiring IST2. In an embodiment, a drive signal can be sent through the second sensing wiring IST2, and a sensing signal can be received through the first sensing wiring IST1. For reference, when the display device DP is a self-capacitance type, there may be no difference in the driving method of the first sensing wiring IST1 and the second sensing wiring IST2. The display wiring DST may include, for example, a control line, a data line, a power line, etc., and may provide a signal so that the pixel can display an image. These signals may be provided from a driver connected to the display wiring DST.

[0114] Fig.10 shows the state of the substrate SUB being bent, Fig.11 A state in which the substrate SUB is not bent is shown.

[0115] The display device DP may be Fig.11 After stacking components on the substrate SUB in the unbent state shown in FIG. Fig.10 Bend as shown in FIG.

[0116] The substrate SUB may include a first curved area BA1 extending from a first side surface RC1 of the first additional area ADA1 to overlap with the non-display area NDA. In addition, the first curved area BA1 may extend to overlap with the display area DA. That is, each of the display area DA, the non-display area NDA, and the first additional area ADA1 may partially overlap with the first curved area BA1. The first curved area BA1 may have a width in the first direction DR1 and may extend in length in the second direction DR2. The first bending axis BX1 may be defined as a folding line extending from the center of the first curved area BA1 in the second direction DR2. In some embodiments, the first curved area BA1 may be a portion in which stress is reduced by removing a portion of its insulating film, unlike other portions near it. In some embodiments, the first curved area BA1 may have the same configuration as other portions around it.

[0117] The substrate SUB may include a third curved area BA3 extending from the second side surface RC2 of the first additional area ADA1 to overlap with the non-display area NDA. In addition, the third curved area BA3 may extend to overlap with the display area DA. That is, each of the display area DA, the non-display area NDA, and the first additional area ADA1 may partially overlap with the third curved area BA3. The third curved area BA3 may have a width in the first direction DR1 and may extend in length in the second direction DR2. The third bending axis BX3 may be defined as a folding line extending from the center of the third curved area BA3 in the second direction DR2. In some embodiments, the third curved area BA3 may be a portion in which stress is reduced by removing a portion of its insulating film, unlike other portions near it. In some embodiments, the third curved area BA3 may have the same configuration as other portions around it.

[0118] The second additional area ADA2 may include a second bending area BA2. The second bending area BA2 may have a width in the second direction DR2 and may extend in length in the first direction DR1. The second bending axis BX2 may be defined as a folding line extending from the center of the second bending area BA2 in the first direction DR1. In some embodiments, the second bending area BA2 may be a portion in which stress is reduced by removing a portion of its insulating film, unlike other portions near it. In some embodiments, the second bending area BA2 may have the same configuration as other portions around it.

[0119] According to an embodiment, the first bending area BA1, the second bending area BA2, and the third bending area BA3 do not overlap each other.

[0120] Here, the term "folding" means that the shape is not fixed, but the original shape can be changed into another shape and the shape is folded, bent or curled along one or more bending axes. Through the first bending area BA1 and the third bending area BA3, the width of the side frame in the opposite direction of the first direction DR1 of the display device DP and the width of the side frame in the first direction DR1 can be reduced. In addition, due to the second bending area BA2, the width of the side frame in the second direction DR2 of the display device DP can be reduced.

[0121] Fig.12 Shown along Fig.11 A cross-sectional view taken along line I-I'. Assume Fig.11 The line II′ in FIG. 1 passes through the first pad PDE1 and the first sensing wiring IST1 .

[0122] First, the display area DA will be described. In an embodiment, the pixels PX are provided in the display area DA. Each pixel PX may include a transistor connected to a corresponding wiring among the display wirings DST, a light emitting element connected to the transistor, and a capacitor Cst. Fig.12 In the figure, for better understanding and ease of description, one transistor, one light emitting element, and one capacitor Cst are shown as an example for one pixel PX.

[0123] The substrate SUB may be made of an insulating material such as glass or resin, for example. In addition, the substrate SUB may be made of a bendable or foldable flexible material, and may have a single-layer structure or a multi-layer structure.

[0124] For example, the substrate SUB may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, the material included in the substrate SUB may be variously changed and may also include, for example, fiber reinforced plastic (FRP).

[0125] For example, when the substrate SUB has a multi-layer structure, an inorganic material such as silicon nitride, silicon oxide, and silicon oxynitride may be interposed between the layers in a single layer or in multiple layers.

[0126] The buffer film BF may cover the substrate SUB. The buffer film BF may prevent impurities from diffusing into the channel of the transistor. The buffer film BF may be an inorganic insulating film made of an inorganic material. For example, the buffer film BF may be made of silicon nitride, silicon oxide, silicon oxynitride, etc., and may be omitted according to the material and process conditions of the substrate SUB. In some embodiments, a barrier layer may be further provided.

[0127] The active film ACT may be disposed on the buffer film BF. The active film ACT may be patterned to form a channel, a source electrode, and a drain electrode of a transistor, or may be patterned to form wiring. The active film ACT may be made of a semiconductor material. The active film ACT may be a semiconductor pattern made of, for example, polysilicon, amorphous silicon, or an oxide semiconductor. The channel of the transistor is a semiconductor pattern not doped with impurities, and may be an intrinsic semiconductor. The source electrode, the drain electrode, and the wiring may be a semiconductor pattern doped with impurities. N-type impurities, P-type impurities, and other impurities such as metals may be used as impurities.

[0128] The first gate insulating film GI1 may cover the active film ACT. The first gate insulating film GI1 may be an inorganic insulating film made of an inorganic material. For example, an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride may be used as the inorganic material, or the first gate insulating film GI1 may be made of polysiloxane.

[0129] The gate electrode GE of the transistor and the lower electrode LE of the capacitor Cst may be disposed on the first gate insulating film GI1. The gate electrode GE may overlap a region corresponding to a channel.

[0130] The gate electrode GE and the lower electrode LE may be made of metal. For example, the gate electrode GE may be made of at least one of metals such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. In addition, the gate electrode GE may be formed as a single-layer film, or may be formed as a multilayer film in which two or more materials among metals and alloys are stacked.

[0131] The second gate insulating film GI2 may cover the gate electrode GE and the lower electrode LE. The second gate insulating film GI2 may be an inorganic insulating film made of an inorganic material. For example, silicon nitride, silicon oxide, and silicon oxynitride may be used as the inorganic material, or the second gate insulating film GI2 may be made of polysiloxane.

[0132] The upper electrode UE of the capacitor Cst may be disposed on the second gate insulating film GI2. The upper electrode UE of the capacitor Cst may be made of a metal. For example, the upper electrode UE may be made of at least one of metals such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. In addition, the upper electrode UE may be formed as a single-layer film, or may be formed as a multilayer film in which two or more materials among metals and alloys are stacked.

[0133] The lower electrode LE and the upper electrode UE may constitute a capacitor Cst, with the second gate insulating film GI2 interposed between the lower electrode LE and the upper electrode UE. Fig.12 , the capacitor Cst is shown as having a double-layer electrode structure of a lower electrode LE and an upper electrode UE. However, the embodiment is not limited thereto. For example, in the embodiment, the capacitor Cst may have a three-layer electrode structure by using an active film ACT, or may have a three-layer electrode structure or a four-layer or more structure by using an electrode of the same layer as the first connection pattern CNP1.

[0134] The interlayer insulating film ILD may cover the upper electrode UE. The interlayer insulating film ILD may be an inorganic insulating film made of an inorganic material. For example, silicon nitride, silicon oxide, and silicon oxynitride may be used as the inorganic material, or the interlayer insulating film ILD may be made of polysiloxane.

[0135] For better understanding and ease of description, the first gate insulating film GI1, the second gate insulating film GI2 and the interlayer insulating film ILD may be referred to as a first insulating film group ING1. The first insulating film group ING1 may cover a portion of the transistor. In some embodiments, the first insulating film group ING1 may further include a buffer film BF.

[0136] The first connection pattern CNP1 may be disposed on the interlayer insulating film ILD and may contact the source electrode and the drain electrode of the active film ACT through contact holes formed in the interlayer insulating film ILD, the second gate insulating film GI2, and the first gate insulating film GI1, respectively.

[0137] The first connection pattern CNP1 may be made of metal. For example, the first connection pattern CNP1 may be made of at least one of metals such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0138] In some embodiments, a passivation film may cover the first connection pattern CNP1. The passivation film may be an inorganic insulating film made of an inorganic material. For example, silicon nitride, silicon oxide, and silicon oxynitride may be used as the inorganic material, or the passivation film may be made of polysiloxane.

[0139] The first via film VIA1 may cover a passivation film or a transistor. The first via film VIA1 may be an organic insulating film made of an organic material. For example, an organic insulating material such as a polyacrylic acid compound, a polyimide compound, a fluorine-based carbon compound (such as Teflon), a benzocyclobutene compound, etc. may be used as the organic material. The organic insulating film may be deposited by a method such as evaporation.

[0140] The second connection pattern CNP2 may be connected to the first connection pattern CNP1 through the opening of the first via film VIA1. The second connection pattern CNP2 may be made of at least one of metals such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0141] The second via film VIA2 may cover the first via film VIA1 and the second connection pattern CNP2. The second via film VIA2 may be an organic insulating film made of an organic material. For example, an organic insulating material such as a polyacrylic compound, a polyimide compound, a fluorine-based carbon compound (such as Teflon), a benzocyclobutene compound, etc. may be used as the organic material.

[0142] The first light emitting element electrode LDE1 may be connected to the second connection pattern CNP2 through the opening of the second via film VIA2. Here, in some embodiments, the first light emitting element electrode LDE1 may be an anode of the light emitting element.

[0143] In some embodiments, the configuration of the second via film VIA2 and the second connection pattern CNP2 may be omitted, and the first light emitting element electrode LDE1 may be directly connected to the first connection pattern CNP1 through the opening of the first via film VIA1 .

[0144] The first light emitting element electrode LDE1 may be made of a metal film such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and alloys thereof and / or a transparent conductive film such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO). The first light emitting element electrode LDE1 may be made of one type of metal, but is not limited thereto, and may be made of two or more types of metals (e.g., an alloy of Ag and Mg).

[0145] When an image is to be provided in a lower direction of the substrate SUB, the first light emitting element electrode LDE1 may be formed of a transparent conductive film, and when an image is to be provided in an upper direction of the substrate SUB, the first light emitting element electrode LDE1 may be formed of a metal reflective film and / or a transparent conductive film.

[0146] The pixel defining film PDL that separates the light emitting area of ​​each pixel PX is disposed on the substrate SUB on which the first light emitting element electrode LDE1 is formed. The pixel defining film PDL may be an organic insulating layer made of an organic material. For example, an organic insulating material such as a polyacrylic compound, a polyimide compound, a fluorine-based carbon compound (such as Teflon), a benzocyclobutene compound, etc. may be used as the organic material.

[0147] The pixel defining film PDL may expose the upper surface of the first light emitting element electrode LDE1 and may protrude from the substrate SUB along the circumference of the pixel PX. The light emitting film EML may be disposed in a region of the pixel PX surrounded by the pixel defining film PDL.

[0148] The light-emitting film EML may include a low molecular weight material or a high molecular weight material. The low molecular weight material may include, for example, copper phthalocyanine (CuPc), N,N'-di(naphthalene-1-yl)-N,N'-diphenylbenzidine (NPB), tri-8-hydroxyquinoline aluminum (Alq 3 ) etc. These materials can be formed by, for example, vacuum deposition. The polymer material can include, for example, PEDOT, polyphenylene vinylene (PPV)-based materials and polyfluorene-based materials.

[0149] The light-emitting film EML may be provided as a single layer, or may be provided as a multilayer including various functional layers. When the light-emitting film EML is provided as a multilayer, the light-emitting film EML may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer, an electron transport layer (ETL), and an electron injection layer (EIL) are stacked in a single structure or a composite structure. Such a light-emitting film EML may be formed by, for example, a screen printing method, an inkjet printing method, or a laser induced thermal imaging (LITI) method.

[0150] In some embodiments, at least a portion of the light emitting film EML may be integrally formed on the plurality of first light emitting element electrodes LDE1 , or may be individually disposed to correspond to each of the plurality of first light emitting element electrodes LDE1 .

[0151] The second light emitting element electrode LDE2 may be disposed on the light emitting film EML. The second light emitting element electrode LDE2 may be disposed for each pixel PX, but may be disposed to cover most of the display area DA, and may be shared by a plurality of pixels PX.

[0152] In some embodiments, the second light emitting element electrode LDE2 may be used as a cathode or an anode. When the first light emitting element electrode LDE1 is an anode, the second light emitting element electrode LDE2 may be used as a cathode. When the first light emitting element electrode LDE1 is a cathode, the second light emitting element electrode LDE2 may be used as an anode.

[0153] The second light emitting element electrode LDE2 may be formed of a metal film such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and / or a transparent conductive film such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) and indium tin zinc oxide (ITZO). In an embodiment, the second light emitting element electrode LDE2 may be formed of a multilayer film including a double film or more films of a metal thin film (e.g., a triple film of ITO / Ag / ITO).

[0154] When an image is to be provided in a lower direction of the substrate SUB, the second light emitting element electrode LDE2 may be formed of a metal reflective film and / or a transparent conductive film, and when an image is to be provided in an upper direction of the substrate SUB, the second light emitting element electrode LDE2 may be formed of a transparent conductive film.

[0155] The above-mentioned group of the first light emitting element electrode LDE1 , the light emitting film EML, and the second light emitting element electrode LDE2 may be referred to as a light emitting element.

[0156] The encapsulation film TFE may be disposed on the second light emitting element electrode LDE2. The encapsulation film TFE may be formed as a single layer or may be formed as a multilayer. In an embodiment, the encapsulation film TFE may include a first encapsulation film ENC1, a second encapsulation film ENC2, and a third encapsulation film ENC3. The first encapsulation film ENC1, the second encapsulation film ENC2, and the third encapsulation film ENC3 may be made of an organic material and / or an inorganic material. The third encapsulation film ENC3 disposed at the outermost portion may be made of an inorganic material. For example, the first encapsulation film ENC1 may be an inorganic film made of an inorganic material, the second encapsulation film ENC2 may be an organic film made of an organic material, and the third encapsulation film ENC3 may be an inorganic film made of an inorganic material. Inorganic materials have lower permeability to moisture and oxygen than organic materials, but are more susceptible to rupture due to their low elasticity or flexibility. The propagation of cracks may be prevented by forming the first encapsulation film ENC1 and the third encapsulation film ENC3 with an inorganic material and forming the second encapsulation film ENC2 with an organic material. Here, in an embodiment, a layer made of an organic material (i.e., the second encapsulation film ENC2) may be completely covered by the third encapsulation film ENC3 so that the end of the second encapsulation film ENC2 is not exposed to the outside. Organic insulating materials such as polyacrylic acid compounds, polyimide compounds, fluorine-based carbon compounds (such as Teflon), benzocyclobutene compounds, etc. may be used as organic materials, and silicon nitride, silicon oxide, silicon oxynitride, etc. may be used as inorganic materials. In addition, polysiloxane may be used to form the first encapsulation film ENC1 and the third encapsulation film ENC3.

[0157] The light-emitting film EML forming the light-emitting element may be damaged by moisture or oxygen from the outside. The encapsulation film TFE protects the light-emitting film EML by covering the light-emitting film EML. The encapsulation film TFE covers the display area DA and may extend to the non-display area NDA arranged outside the display area DA. However, although the insulating film made of organic material can provide flexibility and elasticity, they allow moisture and oxygen to penetrate more easily than the insulating film made of inorganic material. In an embodiment, in order to prevent moisture or oxygen from penetrating through the insulating film made of organic material, the end of the insulating film made of organic material may be covered by an insulating film made of inorganic material so as not to be exposed to the outside. For example, in an embodiment, the first via film VIA1, the second via film VIA2 and the pixel defining film PDL made of organic material extend discontinuously to the non-display area NDA and may be covered by the first encapsulation film ENC1. Therefore, the upper surface of the pixel defining film PDL and the side surfaces of the first via film VIA1, the second via film VIA2 and the pixel defining film PDL are encapsulated by the encapsulation film TFE including inorganic material, so as to prevent them from being exposed to the outside.

[0158] However, whether the encapsulation film TFE is multi-layered or its material is not limited thereto and may be variously changed. For example, according to an embodiment, the encapsulation film TFE may include a plurality of organic material layers and a plurality of inorganic material layers alternately stacked.

[0159] The first sensing electrode layer ISM1 may be disposed on the packaging film TFE. In some embodiments, an additional buffer film may be disposed between the first sensing electrode layer ISM1 and the packaging film TFE. The first sensing electrode layer ISM1 may be formed of a metal film such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and / or a transparent conductive film such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) and indium tin zinc oxide (ITZO).

[0160] The first sensing insulating film ISI1 may be disposed on the first sensing electrode layer ISM1. The first sensing insulating film ISI1 may be an inorganic insulating film made of an inorganic material. For example, an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride may be used as the inorganic material, or the first sensing insulating film ISI1 may be made of polysiloxane.

[0161] The second sensing electrode layer ISM2 may be disposed on the first sensing insulating film ISI1. The second sensing electrode layer ISM2 may be formed of a metal film such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and / or a transparent conductive film such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) and indium tin zinc oxide (ITZO).

[0162] Various input detectors may be constructed by using the first sensing electrode layer ISM1, the first sensing insulating film ISI1, and the second sensing electrode layer ISM2, which will be referred to below. Figures 13 to 15 Described in further detail.

[0163] exist Fig.12 In the embodiment of FIG. 5 , the second sensing electrode layer ISM2 may be patterned to configure the first pattern IST1a of the first sensing wiring IST1.

[0164] The second sensing insulating film ISI2 may be disposed on the second sensing electrode layer ISM2. The second sensing insulating film ISI2 may be formed of an organic film. For example, an organic insulating material such as a polyacrylic compound, a polyimide compound, a fluorine-based carbon compound (such as Teflon), a benzocyclobutene compound, etc. may be used as the organic material. For example, the second sensing insulating film ISI2 may be made of polymethyl methacrylate, polydimethylsiloxane, polyimide, acrylate, polyethylene terephthalate, or polyethylene naphthalate.

[0165] Hereinafter, the non-display area NDA, the first additional area ADA1, and the second additional area ADA2 will be described. Fig.12 In the cross-sectional view of the non-display area NDA, since the difference between the non-display area NDA and the first additional area ADA1 is not a feature related to the gist of the present invention, the non-display area NDA and the first additional area ADA1 will not be described separately. Hereinafter, in the description of the non-display area NDA and the second additional area ADA2, for the convenience of explanation, further description of the previously described components and technical aspects will be omitted or simply described.

[0166] The dam DAM may be disposed at the boundary of the second encapsulation film ENC2. For example, the dam DAM may be disposed between the planarization film FLT and the second encapsulation film ENC2. The dam DAM may have a multilayer structure and may include, for example, a first dam DAM1 and a second dam DAM2. For example, the first dam DAM1 and the second dam DAM2 may be made of an organic material. Each of the first dam DAM1 and the second dam DAM2 may correspond to one of the first via film VIA1, the second via film VIA2, and the pixel defining film PDL. For example, when the first dam DAM1 and the first via film VIA1 are made of the same material by the same process, the second dam DAM2 may be made of the same material by the same process as the second via film VIA2 or the pixel defining film PDL. In an embodiment, when the first dam DAM1 and the second via film VIA2 are made of the same material by the same process, the second dam DAM2 may be made of the same material by the same process as the pixel defining film PDL. In addition, when the spacer is formed on the pixel defining layer PDL of the display area DA, the dam DAM may be formed by using the same material as the spacer.

[0167] The dam DAM can prevent the organic material with strong fluidity of the second encapsulation film ENC2 from overflowing to the outside of the dam DAM during the process. The first encapsulation film ENC1 and the third encapsulation film ENC3 made of inorganic material cover the dam DAM and extend beyond the dam DAM, thereby increasing adhesion with the substrate SUB or other films disposed on the substrate SUB.

[0168] The first pad PDE1 is disposed on the substrate SUB, but may be spaced apart from the planarization film FLT. The first pad PDE1 may be supported by the second insulating film group ING2. The respective insulating films in the second insulating film group ING2 may correspond to the respective insulating films in the first insulating film group ING1. The first pad PDE1 may include a first pad electrode PDE1a and a second pad electrode PDE1b. The first pad electrode PDE1a may be made of the same material as the first connection pattern CNP1. The second pad electrode PDE1b may be made of the same material as the second connection pattern CNP2.

[0169] The planarization film FLT is disposed on the substrate SUB, but may be spaced apart from the area covered by the encapsulation film TFE. The planarization film FLT may be an organic insulating film made of an organic material. For example, an organic insulating material such as a polyacrylic compound, a polyimide compound, a fluorine-based carbon compound (such as Teflon), a benzocyclobutene compound, etc. may be used as the organic material.

[0170] In an embodiment, the planarization film FLT may be formed after forming the interlayer insulating film ILD and before forming the first connection pattern CNP1. Therefore, the planarization film FLT and the first via film VIA1 may be formed by different processes. In some embodiments, the planarization film FLT and the first via film VIA1 may include different organic materials.

[0171] One end of the planarization film FLT may cover the first insulation film group ING1. In addition, a portion of the planarization film FLT corresponding to the second bending area BA2 may fill the first trench TCH1 provided between the first insulation film group ING1 and the second insulation film group ING2.

[0172] Since the inorganic insulating film has high hardness and low flexibility compared to the organic insulating film, the probability of crack generation is relatively high. When cracks occur in the inorganic insulating film, the cracks may propagate to the wiring provided on the inorganic insulating film, and eventually defects such as wiring breakage may occur.

[0173] Therefore, if Fig.12 As shown in , in the embodiment, the inorganic insulating film is removed from the second bending area BA2 so that the first trench TCH1 can be formed and the first insulating film group ING1 and the second insulating film group ING2 can be divided. Fig.12 In the embodiment shown in , it is shown that all of the inorganic insulating film corresponding to the region of the first trench TCH1 is removed. However, the embodiments of the present disclosure are not limited thereto. For example, in an embodiment, some of the inorganic insulating film may be retained. In this case, some of the retained inorganic insulating film may include slits to disperse the bending stress.

[0174] The second pattern IST1b of the first sensing wiring IST1 may extend on the planarization film FLT and may be electrically connected to the first pad PDE1. In an embodiment, the second pattern IST1b may be made of the same material as the first connection pattern CNP1 through the same process.

[0175] The first wiring protection film LPL1 may cover the planarization film FLT and the second pattern IST1b. In addition, the second wiring protection film LPL2 may cover the first wiring protection film LPL1. In some embodiments, the construction of the second wiring protection film LPL2 may be omitted. The first wiring protection film LPL1 and the second wiring protection film LPL2 may be made of an organic material. Each of the first wiring protection film LPL1 and the second wiring protection film LPL2 may correspond to one of the first via film VIA1, the second via film VIA2, and the pixel definition film PDL. For example, when the first wiring protection film LPL1 and the first via film VIA1 are made of the same material by the same process, the second wiring protection film LPL2 may be made of the same material by the same process as the second via film VIA2 or the pixel definition film PDL. In an embodiment, when the first wiring protection film LPL1 and the second via film VIA2 are made of the same material by the same process, the second wiring protection film LPL2 may be made of the same material by the same process as the pixel definition film PDL.

[0176] The first and second wiring protection films LPL1 and LPL2 and the first sensing insulating film ISI1 may include first openings OPN1 exposing the second patterns IST1 b .

[0177] The first pattern IST1a may be connected to the second pattern IST1b through the first opening OPN1. According to an embodiment, the second pattern IST1b disposed on one end of the first insulating film group ING1 and the planarization film FLT may have a height greater than that of the second pattern IST1b disposed on the planarization film FLT corresponding to the first trench TCH1.

[0178] Therefore, the first pattern IST1a and the second pattern IST1b can be directly connected without a bridge wiring, and since there is no bridge wiring, the connection reliability between the first pattern IST1a and the second pattern IST1b can be improved. In addition, since the length of the non-display area NDA can be reduced as much as the length of the bridge wiring, the embodiment can reduce the ineffective area and allow a thin frame.

[0179] The third pattern IST1c of the first sensing wiring IST1 may connect the first pad PDE1 and the second pattern IST1b. The third pattern IST1c may be made of the same material as the gate electrode GE of the transistor through the same process. In some embodiments, the third pattern IST1c may be made of the same material as the upper electrode UE through the same process. In some embodiments, the odd-numbered third pattern IST1c may be formed of the same material as the gate electrode GE of the transistor in the same process, and the even-numbered third pattern IST1c may be formed of the same material as the upper electrode UE in the same process. On the contrary, the even-numbered third pattern IST1c may be formed of the same material as the gate electrode GE of the transistor in the same process, and the odd-numbered third pattern IST1c may be formed of the same material as the upper electrode UE in the same process. Therefore, short circuits between adjacent wirings can be more effectively prevented.

[0180] The second insulating film group ING2 may include second openings OPN2 exposing the third pattern IST1c. In addition, the planarization film FLT may include openings corresponding to the second openings OPN2. The second pattern IST1b may be connected to the third pattern IST1c through the second openings OPN2.

[0181] Fig.13 Shown along Fig.11 A cross-sectional view taken along line II-II'.

[0182] Fig.11 The line II-II' may correspond to the first bending axis BX1. However, the same embodiment may be applied not only to the first side surface RC1 but also to the second side surface RC2.

[0183] The display wiring DST may be composed of a single-layer wiring or a multi-layer wiring by using at least one of the wirings G1L, G2L, and SDL. The wiring G1L may be made of the same material as the gate electrode GE through the same process. The wiring G2L may be made of the same material as the upper electrode UE through the same process. The wiring SDL may be made of the same material as the first connection pattern CNP1 through the same process.

[0184] Patterns IST1a and IST2a of the sensing wirings IST1 and IST2 are disposed on the packaging film TFE and the first sensing insulating film ISI1 (based on the third direction DR3) and between the dam DAM and the display area DA (based on the second direction DR2). The first sensing insulating film ISI1 may be disposed between the packaging film TFE and the sensing wirings IST1 and IST2.

[0185] Fig.14 and Fig.15 Embodiments of sensing electrodes and bridging electrodes are shown. Fig.15Shown along Fig.14 A cross-sectional view taken along line III-III'.

[0186] By patterning the first sensing electrode layer ISM1 , a bridge electrode CP1 may be disposed on the packaging film TFE.

[0187] The first sensing insulating film ISI1 covers the bridge electrode CP1 and may include a contact hole CNT exposing a portion of the bridge electrode CP1 .

[0188] By patterning the second sensing electrode layer ISM2, the first sensing electrode SC1 and the second sensing electrode SC2 may be formed on the first sensing insulating film ISI1. The first sensing electrode SC1 may be connected to the bridge electrode CP1 through the contact hole CNT.

[0189] By patterning the second sensing electrode layer ISM2, the second sensing electrode SC2 may have the connection pattern CP2 in the same layer. Therefore, a separate bridge electrode may not be required to connect the second sensing electrode SC2.

[0190] In some embodiments, each of the sensing electrodes SC1 and SC2 may cover a plurality of pixels PX. In this case, when each of the sensing electrodes SC1 and SC2 is formed of an opaque conductive film, a plurality of openings through which the covered plurality of pixels PX may be exposed may be included. For example, each of the sensing electrodes SC1 and SC2 may be configured in a grid shape. When each of the sensing electrodes SC1 and SC2 is formed of a transparent conductive film, each of the sensing electrodes SC1 and SC2 may be formed in the form of a plate without an opening.

[0191] Fig.16 Sensing electrodes and bridging electrodes according to an embodiment of the present disclosure are shown. Fig.16 Shown along Fig.14 A cross-sectional view taken along line III-III'.

[0192] By patterning the first sensing electrode layer ISM1 disposed on the packaging film TFE, the first sensing electrode SC1 and the second sensing electrode SC2 may be formed.

[0193] The first sensing insulating film ISI1 may cover the first and second sensing electrodes SC1 and SC2 , and may include a contact hole CNT exposing a portion of the first sensing electrode SC1 .

[0194] The bridge electrode CP1 may be formed by patterning the second sensing electrode layer ISM2 disposed on the first sensing insulating film ISI1. The bridge electrode CP1 may be connected to the first sensing electrode SC1 through the contact hole CNT.

[0195] As is customary in the field of the present disclosure, embodiments are described and illustrated in the accompanying drawings with respect to functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. Optionally, each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and associated circuits) for performing other functions.

[0196] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the claims.

Claims

1. A display device, comprising: Touch sensors, including touch panels and touch controllers; as well as The crystal unit is connected to the touch controller, Wherein, the touch controller comprises: a plurality of sensing channels connected to the touch panel; and Feedback circuit, Wherein the crystal unit is connected to at least one of the sensing channels in a first mode and to the feedback circuit in a second mode.

2. The display device according to claim 1, wherein: The crystal unit comprises: A crystal oscillator is arranged between the first terminal and the second terminal; a first external capacitor disposed between the first terminal and a ground power source; and The second external capacitor is provided between the second terminal and the ground power supply.

3. The display device according to claim 2, wherein: In the first mode, the at least one sensing channel measures at least one of a capacitance of the first external capacitor and a capacitance of the second external capacitor.

4. The display device according to claim 3, wherein: The first terminal is connected to one of the sensing channels, and the one of the sensing channels measures the capacitance of the first external capacitor.

5. The display device according to claim 3, wherein: The second terminal is connected to one of the sensing channels, and the one of the sensing channels measures the capacitance of the second external capacitor.

6. The display device according to claim 3, wherein: The first terminal is connected to a first sensing channel among the sensing channels, and the second terminal is connected to a second sensing channel among the sensing channels that is different from the first sensing channel, and the first sensing channel measures the capacitance of the first external capacitor and the second sensing channel measures the capacitance of the second external capacitor.

7. The display device according to claim 1, wherein: Each of the sensing channels comprises: amplifier; and A feedback capacitor is connected in parallel with the amplifier.

8. The display device according to claim 3, wherein: The touch controller further includes a checking unit that checks whether the capacitance of the first external capacitor and the capacitance of the second external capacitor are normal values.

9. The display device according to claim 8, wherein: When the capacitance of the first external capacitor and the capacitance of the second external capacitor are the normal values, the first mode is switched to the second mode.

10. The display device according to claim 9, wherein: In the second mode, the feedback circuit outputs the oscillation frequency of the crystal oscillator.

11. The display device according to claim 1, wherein: The feedback circuit comprises: an inverter; and A feedback resistor is connected in parallel with the inverter.

12. The display device according to claim 1, wherein: The touch panel includes a plurality of sensor electrodes that sense a touch input using a self-capacitance method.

13. A method for inspecting a display device, the display device comprising a touch sensor and a crystal unit, the touch sensor comprising a touch panel and a touch controller, the method comprising the following steps: connecting the crystal unit to at least one sensing channel of a plurality of sensing channels of the touch controller; measuring an external capacitance of the crystal unit; as well as Check whether the external capacitor is a normal value.

14. The method according to claim 13, wherein: The crystal unit comprises: A crystal oscillator is arranged between the first terminal and the second terminal; a first external capacitor disposed between the first terminal and a ground power source; and The second external capacitor is provided between the second terminal and the ground power supply.

15. The method according to claim 14, wherein: The step of connecting the crystal unit to the at least one of the plurality of sensing channels includes connecting the first terminal to the at least one of the plurality of sensing channels, and the step of measuring the external capacitance of the crystal unit includes measuring the capacitance of the first external capacitor.

16. The method according to claim 14, wherein: The step of connecting the crystal unit to the at least one of the plurality of sensing channels includes connecting the second terminal to the at least one of the plurality of sensing channels, and the step of measuring the external capacitance of the crystal unit includes measuring the capacitance of the second external capacitor.

17. The method according to claim 14, wherein: The step of connecting the crystal unit to at least one of the multiple sensing channels includes: connecting the first terminal to a first sensing channel among the multiple sensing channels; and connecting the second terminal to a second sensing channel among the multiple sensing channels that is different from the first sensing channel, and the step of measuring the external capacitance of the crystal unit includes: measuring the capacitance of the first external capacitor and the capacitance of the second external capacitor.

18. The method according to claim 13, further comprising the steps of: When the external capacitance is the normal value, the crystal unit is connected to a feedback circuit of the touch controller.

19. The method according to claim 13, wherein: Each of the plurality of sensing channels comprises: amplifier; and A feedback capacitor is connected in parallel with the amplifier.

20. The method according to claim 18, wherein: The feedback circuit comprises: an inverter; and A feedback resistor is connected in parallel with the inverter.

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