A pressure testing method, device, apparatus and storage medium

Abstract

The application provides a stress test method and device, equipment and storage medium, relates to the storage technical field, and aims at the problems that in the related art, the number of TLP packets cannot be effectively controlled in the stress test of a RAID card chip, and the stress of PCIe data transmission cannot be effectively evaluated. The method comprises the following steps: receiving a test task request sent by a central processor of a host; in response to the test task request, suspending the response to a target transaction layer data packet sent by the central processor, so as to accumulate the number of target transaction layer data packets to a target number; when the number of target transaction layer data packets is accumulated to the target number, responding to the target number of target transaction layer data packets to perform a stress test; and in the case that the response of the target transaction layer data packet by the disk array card chip and the expected response of the target transaction layer data packet by the central processor are consistent, it is determined that the disk array card chip passes the stress test.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of storage, and in particular, to a stress testing method and device, equipment and a storage medium. BACKGROUND

[0002] RAID (Redundant Array of Independent Disks) card chips are chips based on PCIe and NVMe protocols. TLP (Transaction Layer Packet) packets are crucial in the communication between RAID cards and host systems, and are used to transmit user data, metadata and any necessary control information. Therefore, it is necessary to increase the test pressure and scene coverage of TLP packets to achieve reliable and stable transmission of TLP packets. The stress testing scheme for RAID card chips in the related art is usually based on the host end issuing test commands for testing. This way cannot effectively control the number of TLP packets and cannot effectively evaluate the pressure of PCIe data transmission. SUMMARY

[0003] Embodiments of the present application provide a stress testing method, device, equipment and storage medium, aiming to solve the problem that the stress testing of RAID card chips in the related art cannot effectively control the number of TLP packets and cannot effectively evaluate the pressure of PCIe data transmission.

[0004] The first aspect of the embodiments of the present application provides a stress testing method applied to a disk array card chip, and the method comprises:

[0005] receiving a test task request sent by a central processor of a host;

[0006] in response to the test task request, suspending the response to a target transaction layer data packet sent by the central processor, so as to accumulate the number of target transaction layer data packets to a target number;

[0007] when the number of target transaction layer data packets is accumulated to the target number, responding to the target number of target transaction layer data packets to perform stress testing;

[0008] determining whether the response of the disk array card chip to the target transaction layer data packet and the expected response of the central processor to the target transaction layer data packet are consistent;

[0009] in the case where the response of the disk array card chip to the target transaction layer data packet and the expected response of the central processor to the target transaction layer data packet are consistent, determining that the disk array card chip passes the stress testing.

[0010] In an optional implementation, the method further comprises:

[0011] in response to the test task request, detecting whether a switch that is immediately responsive to the target transaction layer data packet sent by the central processor is turned on;

[0012] in the case that the switch is turned on, responding to the target transaction layer data packet sent by the central processor;

[0013] in response to the test task request, suspending the response to the target transaction layer data packet sent by the central processor, comprising:

[0014] in the case that the switch is turned off, obtaining an interval time, and suspending the response to the target transaction layer data packet sent by the central processor within the interval time;

[0015] in the case that the number of the target transaction layer data packets accumulates to a target number, responding to the target number of the target transaction layer data packets to perform the stress test, comprising: after waiting for the interval time, responding to the target number of the target transaction layer data packets to perform the stress test.

[0016] In an optional implementation, the method further comprises:

[0017] detecting whether the central processor is responding to other task requests;

[0018] in the case that it is detected that the central processor is responding to other task requests, sending an interrupt indication to the central processor to trigger the central processor to interrupt the response to other task requests.

[0019] In an optional implementation, the central processor comprises a first core and a second core, and the method further comprises:

[0020] binding the test task request of the IO task to the first core and binding the test task request of the management task to the second core;

[0021] detecting whether the first core is responding to other task requests;

[0022] in the case that it is detected that the first core is responding to other task requests and the test task request of the IO task is received, sending an interrupt indication to the first core to trigger the first core to interrupt the response to other task requests and to respond to the test task request of the IO task preferentially;

[0023] detecting whether the second core is responding to other task requests;

[0024] In a case where it is detected that the second core is responding to other task requests and receives a test task request of a management task, an interrupt indication is sent to the second core to trigger the second core to interrupt the response to other task requests and to respond to the test task request of the management task in priority.

[0025] In an optional implementation, the method further comprises:

[0026] Obtaining an interrupt mode;

[0027] In a case where it is detected that the central processor is responding to other task requests, an interrupt indication is sent to the central processor to trigger the central processor to interrupt the response to other task requests, comprising:

[0028] In a case where it is detected that the central processor is responding to other task requests, an interrupt indication is sent to the central processor to trigger the central processor to interrupt the response to other task requests in the interrupt mode;

[0029] In a case where the number of target transaction layer data packets accumulates to a target number, the target number of target transaction layer data packets are responded to for stress testing, comprising:

[0030] In a case where the number of target transaction layer data packets accumulates to a target number, the target number of target transaction layer data packets are responded to for stress testing in the interrupt mode.

[0031] In an optional implementation, the method further comprises:

[0032] Obtaining a data transmission mode;

[0033] In a case where the number of target transaction layer data packets accumulates to a target number, the target number of target transaction layer data packets are responded to for stress testing, comprising:

[0034] In a case where the number of target transaction layer data packets accumulates to a target number, the target number of target transaction layer data packets are responded to for stress testing in the data transmission mode.

[0035] In an optional implementation, the receiving of the test task request sent by the central processor of the receiving host comprises:

[0036] Using a stress testing tool to simulate multiple load conditions to obtain one or more test task requests;

[0037] Converting the one or more test task requests into target transaction layer data packets conforming to PCIe data requests;

[0038] receive the target transaction layer data packet sent by a central processor of the host;

[0039] The one or more test task requests include writing specific data, writing random data, repeatedly writing the same or different data, and writing data using a specified mode.

[0040] The second aspect of the embodiment of the present application provides a stress testing device applied to a disk array card chip, and the device comprises:

[0041] A receiving module is configured to receive a test task request sent by a central processor of a host;

[0042] A suspension processing module is configured to suspend response to a target transaction layer data packet sent by the central processor in response to the test task request, so as to accumulate the number of target transaction layer data packets to a target number.

[0043] A response resuming module is configured to respond to the target number of target transaction layer data packets to perform stress testing when the number of target transaction layer data packets is accumulated to the target number.

[0044] A judging module is configured to judge whether the response of the disk array card chip to the target transaction layer data packet is consistent with the expected response of the central processor to the target transaction layer data packet.

[0045] A determining module is configured to determine that the disk array card chip passes the stress testing when the response of the disk array card chip to the target transaction layer data packet is consistent with the expected response of the central processor to the target transaction layer data packet.

[0046] The third aspect of the embodiment of the present application provides an electronic device, which comprises a memory, a processor, and a computer program stored in the memory and capable of running on the processor, and the computer program is executed by the processor to implement the stress testing method of the first aspect of the embodiment of the present application.

[0047] The fourth aspect of the embodiment of the present application provides a computer readable storage medium, and the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the stress testing method of the first aspect of the embodiment of the present application.

[0048] In the embodiment, a test task request sent by a central processor of a host is received, in response to the test task request, a response to a target transaction layer data packet sent by the central processor is suspended, and a number of the target transaction layer data packets is accumulated to a target number; when the number of the target transaction layer data packets is accumulated to the target number, the target number of target transaction layer data packets is responded to, so as to perform a stress test. By controlling the suspension of the response to the target transaction layer data packet and accumulating the number of the target transaction layer data packets to the target number, the PCIe data transmission stress can be controllably generated, and the performance of the RAID card chip can be flexibly and efficiently tested. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0050] Figure 1 is a step flow chart of a stress test method according to an embodiment of the present application;

[0051] Figure 2 is a structural schematic diagram of a stress test system according to an embodiment of the present application;

[0052] Figure 3 is a test step flow chart of a stress test method according to an embodiment of the present application;

[0053] Figure 4 is a structural schematic diagram of a stress test device according to an embodiment of the present application;

[0054] Figure 5 is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0056] The high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) protocol uses an "end-to-end data transmission mode", has the characteristics of high bandwidth and high reliability, supports active power management, supports error reporting, supports hot plug and other functions, and its performance is continuously improved with the iteration of the version. The PCIe data transmission performance test in the related art is mostly realized based on the normal communication process between the PCIe protocol communication host (PCIe Host) and the PCIe protocol communication device end (End Point), but the number of PCIe transaction layer data packets (Transaction Layer Packet, TLP packet) produced is very limited, and the pressure of PCIe data transmission cannot be effectively evaluated, so it cannot be effectively verified.

[0057] As a disk array (Redundant Arrays of Independent Disks, RAID) card chip based on the PCIe protocol and its upper layer NVMe protocol, TLP plays a crucial role in the RAID card chip and has multiple purposes, especially in the communication between the RAID card and the host system or other storage devices. TLP packets are used to transmit data between the RAID controller and the host system, including user data, metadata (such as checksums, RAID level information, etc.), and any necessary control information. The RAID card receives and executes commands from the host system, such as read and write requests, configuration changes, firmware updates, etc., which are usually sent to the transaction layer of the RAID card in the form of messages through TLP packets and parsed and executed by the processing logic of the RAID card. The RAID card chip also reports its status information to the host system through TLP packets, such as the health status of the RAID array, error logs, performance statistics, etc. The transmission of TLP packets in the PCIe network also involves traffic control mechanisms, and the RAID card chip can manage the data transmission rate with the host system or other devices by sending specific TLP packets (such as traffic control credit packets) to avoid data congestion and packet loss. In addition, TLP packets may contain CRC (Cyclic Redundancy Check) or other types of check codes for detecting data errors during transmission. If an error is detected, the RAID card chip can take appropriate measures to recover the data or notify the host system of the error. In some cases, TLP packets are also used for power management and energy-saving related communication between the RAID card chip and the host system. For example, when the RAID card is in an idle state, it may send a power management request to the host system through a TLP packet to reduce power consumption. Therefore, reliable and stable transmission of TLP packets is a fundamental function for RAID chips, and how to increase the test pressure and scene coverage of TLP packets is a core problem for RAID card chips.

[0058] To solve this problem, the test scheme in the related art is mostly based on the host end issuing test commands to test the RAID card chip. One major problem of this test method is that it cannot effectively control the number of TLP packets. In addition, when testing, the central processor will also process some other data, and the performance limitation of the central processor will cause the test to slow down. At the same time, the processing of data such as memory and hard disk in the test will also make the test period longer, and the test efficiency is low.

[0059] Therefore, how to increase the test pressure of TLP packets, while removing the performance limitation of the central processor to shorten the stress test period and ultimately improve the stress test efficiency, is crucial for the stress test of the RAID card chip product, especially the stress test of TLP packets.

[0060] Referring toFigure 1 , Figure 1 is a step flow chart of a pressure test method proposed by an embodiment of the present application, the pressure test method is applied to a disk array card chip, and includes the following steps S11-S15:

[0061] Step S11: receiving a test task request sent by a central processor of a host.

[0062] The test task request sent by the central processor of the host can be divided into NVMe Admin and NVMe IO requests. The NVMe Admin command is mainly used for the management and control of the host to the SSD (solid state disk). These commands include but are not limited to: deleting an I / O submission queue, creating an I / O submission queue. The NVMe IO command is used for data transmission and is the basis for the storage device to perform read and write operations. These commands include but are not limited to: write operation, read operation.

[0063] Further, the test task request sent by the central processor of the host includes:

[0064] Using a pressure test tool to simulate multiple load conditions to obtain one or more test task requests;

[0065] Converting the one or more test task requests into target transaction layer data packets conforming to PCIe data requests;

[0066] Receiving the target transaction layer data packets sent by the central processor of the host;

[0067] The one or more test task requests include: writing specific data, writing random data, repeatedly writing the same or different data, and writing data using a specified mode.

[0068] Multiple load conditions can be simulated through a pressure test tool,

[0069] The received test task request is derived from one or more test task requests obtained by simulating multiple load conditions through a pressure test tool of the host. The test task request at least includes: writing specific data, writing random data, repeatedly writing the same or different data, and writing data using a specified mode. For example, different test tasks are issued through an FIO tool. FIO is a flexible I / O test tool that can simulate various I / O operations through multiple threads or processes.

[0070] The PCIe host is a bridge device between the central processor and the PCIe bus, and is responsible for converting the data request sent by the processor into a transaction layer data packet conforming to the PCIe protocol specification, and sending the target device through the PCIe bus. The operating system sends a test task request to the PCIe host for the disk array (RAID) card chip, and the PCIe host converts the test task request into a transaction layer data packet conforming to the PCIe data request. The transaction layer data at least includes: header information (such as type, length, address, etc.), payload data (i.e. the converted test task request) and check information (such as CRC check code). The transaction layer data packet is sent to the RAID card chip through the PCIe bus, and then the RAID card chip receives the target transaction layer data packet sent. Ensure that the data request can be transmitted on the bus in the format supported by the PCIe protocol, so that the RAID card chip can correctly receive and process.

[0071] Step S12: In response to the test task request, the response to the target transaction layer data packet sent by the central processor is suspended to accumulate the number of target transaction layer data packets to a target number.

[0072] The received target transaction layer data packet is parsed, and in response to the obtained test task request, the response to the corresponding target transaction layer data packet is suspended to accumulate the number of target transaction layer data packets to a target number. In this process, the response time is set to achieve different response times to accumulate different numbers of target transaction layer data packets. The response time can be set according to different needs, and the target number of data packets is accumulated to simulate a high-load scenario and create PCIe data transmission pressure. After parsing the received target transaction layer data packet, the data is checked to ensure data integrity and correctness. For example, when the transaction layer data packet passes through the data link layer of PCIe, a CRC (Cyclic Redundancy Check) code is added; the RAID card chip will recalculate the CRC code of the data after receiving the data packet, and compare it with the CRC code attached to the data packet; if the two do not match, it means that the data has an error in the transmission process, and the RAID card chip will take appropriate error handling measures (such as requesting retransmission).

[0073] Step S13: When the number of target transaction layer data packets accumulates to a target number, the target number of target transaction layer data packets is responded to for stress testing.

[0074] When the number of target transaction layer data packets accumulates to the target number, the response to the target number of target transaction layer data packets is resumed, so as to perform the stress test. In this process, the RAID card chip waits for the response time to be set in advance, and then resumes the response to the target transaction layer data packets to process the corresponding test task request and perform the stress test to obtain the stress test result. The stress test result can be saved to a log file, so as to find the corresponding stress test result through the log file. The information saved in the log file at least includes test task information, stress degree, timestamp, test duration, and result acquisition time.

[0075] Step S14: Determine whether the response of the disk array card chip to the target transaction layer data packet and the expected response of the central processor to the target transaction layer data packet are consistent.

[0076] In the stress test process, the response of the RAID card chip to the target transaction layer data packet is recorded. The response to the target transaction layer data packet after the test is compared with the expected response of the central processor to determine whether they are consistent. By comparing the actual response and the expected response, the accuracy and reliability of the RAID card chip in processing a large number of transaction layer data packets can be evaluated.

[0077] Step S15: In the case where the response of the disk array card chip to the target transaction layer data packet and the expected response of the central processor to the target transaction layer data packet are consistent, it is determined that the disk array card chip passes the stress test.

[0078] If the response of the disk array card chip to the target transaction layer data packet and the expected response of the central processor to the target transaction layer data packet are consistent, it is determined that the disk array card chip passes the stress test; otherwise, the stress test fails. After obtaining the failed stress test result of the RAID card chip, the failed test task request is resumed, and a new task execution window is started to re-execute the task. At the same time, other windows continue to issue test task requests to continue the stress test until all test tasks are completed, so as to maintain the continuity of the test.

[0079] In this embodiment, by receiving the test task request sent by the central processor of the host, the response to the target transaction layer data packet sent by the central processor is suspended in response to the test task request, so as to accumulate the number of target transaction layer data packets to the target number; when the number of target transaction layer data packets accumulates to the target number, the target number of target transaction layer data packets is responded to, so as to perform the stress test. By controlling the suspension of the response to the target transaction layer data packet and accumulating the number of target transaction layer data packets to the target number, the PCIe data transmission pressure can be controllably generated, which is helpful for flexibly and efficiently testing the performance of the RAID card chip.

[0080] Further, the method further comprises:

[0081] In response to the test task request, detecting whether the switch for immediate response to the target transaction layer data packet sent by the central processor is turned on;

[0082] In the case that the switch is turned on, responding to the target transaction layer data packet sent by the central processor;

[0083] In response to the test task request, suspending the response to the target transaction layer data packet sent by the central processor, comprising:

[0084] In the case that the switch is turned off, obtaining an interval time, and suspending the response to the target transaction layer data packet sent by the central processor within the interval time;

[0085] When the number of the target transaction layer data packets accumulates to a target number, responding to the target number of target transaction layer data packets to perform stress testing, comprising: after waiting for the interval time, responding to the target number of target transaction layer data packets to perform stress testing.

[0086] A switch function for immediate response to a request task is added inside a RAID card chip. The received target transaction layer data packet is parsed, and in response to the obtained test task request, it is detected whether the switch for immediate response to the target transaction layer data packet is turned on. In the case that the switch is turned on, the target transaction layer data packet is immediately responded. In the case that the switch is turned off, the response to the target transaction layer data packet is suspended in response to the obtained test task request. Specifically, in the case that the switch is turned off, a pre-set interval time is obtained, and the response to the target transaction layer data packet is suspended within the interval time; after waiting for the interval time, when the number of the target transaction layer data packets accumulates to a target number, the target number of target transaction layer data packets are responded to perform stress testing. By controlling the suspension of the response to the current target transaction layer data packet, the number of target transaction layer data packets is accumulated, and PCIe data transmission pressure is created, which is helpful for efficiently testing the performance of the RAID card chip.

[0087] Further, the method further comprises:

[0088] Detecting whether the central processor is responding to other task requests;

[0089] In the case that it is detected that the central processor is responding to other task requests, sending an interrupt indication to the central processor to trigger the central processor to interrupt the response to other task requests.

[0090] The central processor can be monitored in real time by an operating system or monitoring software to detect whether the central processor is responding to other task requests in addition to the test task requests. If the central processor is detected to be responding to other task requests, an interrupt indication is sent to the central processor to trigger an interrupt handling mechanism. After the central processor receives the interrupt indication, the response to the other task requests is interrupted, and the restrictions on the central processor and other test facilities are removed. This avoids the problem of low test efficiency caused by the performance of the central processor when stress testing the RAID card, i.e., the stability of the RAID card chip can be tested to the maximum extent in the same test period.

[0091] Further, the central processor includes a first core and a second core, and the method further includes:

[0092] binding the test task request of the IO task to the first core and binding the test task request of the management task to the second core;

[0093] detecting whether the first core is responding to other task requests;

[0094] In a case where the first core is detected to be responding to other task requests and the test task request of the IO task is received, an interrupt indication is sent to the first core to trigger the first core to interrupt the response to the other task requests and to respond to the test task request of the IO task preferentially;

[0095] detecting whether the second core is responding to other task requests;

[0096] In a case where the second core is detected to be responding to other task requests and the test task request of the management task is received, an interrupt indication is sent to the second core to trigger the second core to interrupt the response to the other task requests and to respond to the test task request of the management task preferentially.

[0097] The core of the central processor is the main part inside the central processor that executes instructions and processes data, which is usually referred to as a "core". In a multi-core processor, each core is an independent processing unit that can execute instruction sets in parallel to speed up the running of programs. The central processor includes a first core and a second core, where the first core is a core that can be configured with an IO task, and the second core is a core that can be configured with an Admin task.

[0098] The operating system can determine the type of test task request by a task identifier or a task type label, and thus bind the test task request of the IO task to the first core and the test task request of the management task to the second core. The operating system or the monitoring software can monitor the central processor in real time to detect whether the first core is responding to other task requests. In the case that the first core is responding to other task requests and the test task request of the IO task is received, an interrupt indication is sent to the first core to trigger the first core to interrupt the response to other task requests and to respond to the test task request of the IO task preferentially. Similarly, whether the second core is responding to other task requests is detected to respond to the test task request of the management task preferentially. By binding the test task to a specific core, the execution efficiency of the test task can be improved.

[0099] Further, the method further comprises:

[0100] obtaining an interrupt mode;

[0101] In the case that the central processor is responding to other task requests, an interrupt indication is sent to the central processor to trigger the central processor to interrupt the response to other task requests, comprising:

[0102] In the case that the central processor is responding to other task requests, an interrupt indication is sent to the central processor to trigger the central processor to interrupt the response to other task requests in the interrupt mode;

[0103] When the number of target transaction layer data packets accumulates to a target number, the target number of target transaction layer data packets are responded to for stress testing, comprising:

[0104] When the number of target transaction layer data packets accumulates to a target number, the target number of target transaction layer data packets are responded to for stress testing in the interrupt mode.

[0105] According to the test requirement, the PCIe interrupt mode of the RAID card chip is set from the host side, and a special hardware monitoring software or a driver management tool can be used to view and modify the interrupt mode setting. When the central processor is detected to respond to other task requests, an interrupt indication is sent to the central processor to trigger the central processor to interrupt the response to other task requests in the interrupt mode. When the number of target transaction layer data packets accumulates to a target number, the target number of target transaction layer data packets are responded to for stress testing in the interrupt mode. By setting the interrupt mode, the RAID card chip can process test task requests from the host side in different modes, and the stress test tasks in different scenarios can be tested to comprehensively evaluate the performance of the RAID card.

[0106] Further, the method further comprises:

[0107] obtaining a data transmission mode;

[0108] When the number of target transaction layer data packets accumulates to a target number, the target number of target transaction layer data packets are responded to for stress testing, comprising:

[0109] When the number of target transaction layer data packets accumulates to a target number, the target number of target transaction layer data packets are responded to for stress testing in the data transmission mode.

[0110] According to the test requirement, an appropriate data transmission mode can be selected, such as a bypass mode, a normal mode, etc. The bypass mode usually bypasses some processing logic (such as cache, check, etc.) of the RAID card and directly accesses the storage medium; and the normal mode uses all functions of the RAID card. Thus, when the number of target transaction layer data packets accumulates to a target number, the target transaction layer data packets are responded to and stress tested in the selected data transmission mode. The RAID card functions can be efficiently stress tested in different levels of RAID and in bypass and normal modes of data transmission, and the stress test tasks in different scenarios can be tested to comprehensively evaluate the performance of the RAID card.

[0111] Reference Figure 2 , Figure 2 is a structural schematic diagram of a stress test system according to an embodiment of the present application. As shown in Figure 2 , the stress test system comprises a stress test tool, a central processor and a RAID card.

[0112] The pressure testing tool is mainly responsible for issuing different test task requests and control requests, and one or more test task requests can be obtained by simulating multiple load conditions. The test task request includes writing specific data, writing random data, repeatedly writing the same or different data, writing data using a specified mode, etc.

[0113] The central processor has multiple cores, which are mainly responsible for binding with the corresponding core according to the type of the test task request. Each test task request is bound to at least one core of the central processor. The test task request bound by the central processor is converted into a target transaction layer data packet conforming to the PCIe data request, encapsulated into a command in the NVMe queue, and sent to the RAID card through the PCIe bus. By binding the test task with a specific core, the execution efficiency of the test task can be improved.

[0114] The RAID card (disk array card chip) is mainly responsible for controlling the suspension of the response to the target transaction layer data packet, accumulating the number of target transaction layer data packets to a target number, and then resuming the response to the target transaction layer data packet to perform stress testing. The number of transaction layer data packets can be controlled to effectively generate PCIe data transmission pressure, so as to flexibly and efficiently test the performance and stability of the RAID card chip.

[0115] Further, the RAID card includes a control task module, an NVMe RAID controller, and an SSD.

[0116] The NVMe RAID controller is mainly responsible for receiving and analyzing and responding to the transaction layer data packet, ensuring that the test task request can be executed in a predetermined manner.

[0117] The control task module is mainly responsible for receiving the control request, controlling the suspension of the response to the target transaction layer data packet, and accumulating the number of target transaction layer data packets to a target number.

[0118] The SSD is mainly responsible for responding to the data request (such as writing random data) from the NVMe RAID controller, storing data or returning data. The SSD can test the function and stability of the RAID card on different manufacturer SSDs, and then detect the stability of the RAID card.

[0119] Reference Figure 3 , Figure 3 is a test step flowchart of the stress testing method according to an embodiment of the present application. As shown in Figure 3 , the test process specifically includes:

[0120] The test task request is sent from a host end, and the operating system binds according to a type of a test task to be tested and a corresponding core; the operating system judges what type of test task request is and binds to a specific CPU (central processing unit); when the test task type of the test task request is an IO task, the core of the central processing unit of the IO task is configured, and when the test task type of the test task request is an Admin (management) task, the core of the central processing unit of the Admin task is configured. Whether the CPU processes other tasks is monitored through an interruption module, when the CPU processes other tasks, the core of the central processing unit is interrupted to respond to other task requests, so as to preferentially respond to the test task request of the IO task or the Admin task; when the CPU does not process other tasks, the RAID card chip is controlled according to the type of the test task request, and the response to the test task request is suspended, so that the number of TLP (transaction layer packet) is accumulated to a certain extent, and the PCIe data transmission pressure is generated. Whether the interval time is reached is judged through an interval time setting module; when the interval time is not reached, the response to the data request is continued to be suspended; when the interval time is reached, the RAID card chip responds to the test task request to perform the pressure test. The result of the pressure test is saved into a log file, so that the corresponding pressure test result can be found through the log file. Whether the actual response is consistent with the expected response is judged; when the actual response is not consistent with the expected response, the test fails, and the test task request before the failure is recovered to be retried; when the actual response is consistent with the expected response, the test succeeds.

[0121] Based on the same inventive concept, an embodiment of the present application provides a pressure testing device. Referring to Figure 4 , Figure 4 FIG. 1 is a structural schematic diagram of a pressure testing device provided by an embodiment of the present application, which is applied to a disk array card chip and includes:

[0122] a receiving module, configured to receive a test task request sent by a central processing unit of a host;

[0123] a suspension processing module, configured to suspend a response to a target transaction layer packet sent by the central processing unit in response to the test task request, so as to accumulate the number of the target transaction layer packet to a target number;

[0124] a recovery response module, configured to respond to the target number of target transaction layer packets when the number of the target transaction layer packets is accumulated to the target number, so as to perform a pressure test;

[0125] a judging module, configured to judge whether the response of the disk array card chip to the target transaction layer packet and the expected response of the central processing unit to the target transaction layer packet are consistent;

[0126] The determining module is configured to determine that the disk array card chip passes the stress test when the response of the disk array card chip to the target transaction layer data packet and the expected response of the central processor to the target transaction layer data packet are consistent.

[0127] In an optional embodiment, the receiving module is specifically configured to:

[0128] simulate a plurality of load conditions using a stress testing tool to obtain one or more test task requests;

[0129] convert the one or more test task requests into target transaction layer data packets conforming to PCIe data requests;

[0130] receive the target transaction layer data packets sent by the central processor of the host;

[0131] The one or more test task requests include writing specific data, writing random data, repeatedly writing the same or different data, and writing data using a specified mode.

[0132] In an optional embodiment, the device further includes:

[0133] The control module is configured to, in response to the test task request, detect whether a switch for immediately responding to the target transaction layer data packets sent by the central processor is turned on;

[0134] respond to the target transaction layer data packets sent by the central processor when the switch is turned on;

[0135] suspend the response to the target transaction layer data packets sent by the central processor in response to the test task request, including:

[0136] acquire an interval time and suspend the response to the target transaction layer data packets sent by the central processor within the interval time when the switch is turned off;

[0137] respond to the target number of target transaction layer data packets to perform stress testing when the number of target transaction layer data packets accumulates to a target number, including responding to the target number of target transaction layer data packets to perform stress testing after waiting for the interval time.

[0138] In an optional embodiment, the device further includes:

[0139] The interrupt module is configured to detect whether the central processor is responding to other task requests.

[0140] In response to detecting that the central processor is responding to other task requests, sending an interrupt indication to the central processor to trigger the central processor to interrupt responding to the other task requests.

[0141] In an optional implementation, the apparatus further includes:

[0142] a processing module, configured to bind a test task request of an IO task to the first core and bind a test task request of a management task to the second core;

[0143] detecting whether the first core is responding to other task requests;

[0144] In response to detecting that the first core is responding to other task requests and receiving a test task request of an IO task, sending an interrupt indication to the first core to trigger the first core to interrupt responding to the other task requests and to respond to the test task request of the IO task preferentially;

[0145] detecting whether the second core is responding to other task requests;

[0146] In response to detecting that the second core is responding to other task requests and receiving a test task request of a management task, sending an interrupt indication to the second core to trigger the second core to interrupt responding to the other task requests and to respond to the test task request of the management task preferentially.

[0147] In an optional implementation, the apparatus further includes:

[0148] a first obtaining module, configured to obtain an interrupt mode;

[0149] In response to detecting that the central processor is responding to other task requests, sending an interrupt indication to the central processor to trigger the central processor to interrupt responding to the other task requests, including:

[0150] In response to detecting that the central processor is responding to other task requests, sending an interrupt indication to the central processor to trigger the central processor to interrupt responding to the other task requests in the interrupt mode;

[0151] In response to the number of the target transaction layer data packets accumulating to a target number, responding to the target number of the target transaction layer data packets to perform the stress test, including:

[0152] In response to the number of the target transaction layer data packets accumulating to a target number, responding to the target number of the target transaction layer data packets to perform the stress test in the interrupt mode.

[0153] In an alternative embodiment, the apparatus further comprises:

[0154] a second obtaining module, configured to obtain the data transmission mode;

[0155] when the number of the target transaction layer data packets accumulates to a target number, responding to the target number of the target transaction layer data packets to perform the stress test in the data transmission mode.

[0156] when the number of the target transaction layer data packets accumulates to a target number, responding to the target number of the target transaction layer data packets to perform the stress test in the data transmission mode.

[0157] Based on the same inventive concept, another embodiment of the present application provides an electronic device, referring to Figure 5 , Figure 5 is a schematic diagram of an electronic device according to an embodiment of the present application. As shown in Figure 5 , the electronic device 100 comprises a memory 110 and a processor 120, the memory 110 and the processor 120 are communicatively connected through a bus, and the memory 110 stores a computer program, which can be run on the processor 120, thereby implementing the steps in the stress test method according to any of the above embodiments of the present application.

[0158] Based on the same inventive concept, the present disclosure further provides a computer readable storage medium, when the instructions in the computer readable storage medium are executed by the processor of a computer device, the computer device can perform the steps in the stress test method according to any of the above embodiments of the present application.

[0159] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the related parts are described in the part of the method embodiment.

[0160] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts between each embodiment can be referred to each other.

[0161] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, device, or computer program product. Therefore, the embodiments of the present application can be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present application can be in the form of a computer program product implemented on one or more computer usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0162] The embodiments of the present application are described with reference to the flowchart illustrations and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present application. It is understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal devices to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal devices, create means for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0163] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal devices to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0164] These computer program instructions can also be loaded into a computer or other programmable data processing terminal devices, such that a series of operational steps are carried out on the computer or other programmable terminal devices to produce a computer implemented process so that the instructions executed on the computer or other programmable terminal devices provide steps for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0165] Although the preferred embodiments of the present application have been described, those skilled in the art will be able to make additional modifications and variations to these embodiments once they have the benefit of the foregoing description. Accordingly, it is intended that the appended claims be construed to include all such modifications and variations as fall within the scope of the embodiments of the present application.

[0166] Finally, it is to be understood that the phraseology or terminology such as "first" and "second" etc. used herein is merely intended to differentiate one entity or operation from another entity or operation, without necessarily requiring or implying any actual such relationship or order between such entities or operations. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0167] The pressure test method, device, equipment and storage medium provided by the application are described in detail above, and the principles and implementation manners of the application are described by applying specific examples. The above example description is only used to help understand the method and core idea of the application. Meanwhile, for those skilled in the art, the specific implementation manners and application ranges will be changed according to the idea of the application. In conclusion, the content of the specification should not be understood as a limitation of the application.

Claims

1. A pressure testing method, characterized in that, Applied to a disk array card chip, the method includes: Receive test task requests sent by the host's central processing unit; In response to the test task request, the response to the target transaction layer data packets sent by the central processing unit is paused, so that the number of target transaction layer data packets is accumulated to the target number; When the number of target transaction layer data packets accumulates to the target number, a response is sent to the target number of target transaction layer data packets to perform a stress test; Determine whether the response of the disk array card chip to the target transaction layer data packet is consistent with the expected response of the central processing unit to the target transaction layer data packet; If the response of the disk array card chip to the target transaction layer data packet is consistent with the expected response of the central processing unit to the target transaction layer data packet, the disk array card chip is determined to have passed the stress test.

2. The pressure testing method according to claim 1, characterized in that, The method further includes: In response to the test task request, detect whether the switch for immediate response to the target transaction layer data packet sent by the central processing unit is turned on; When the switch is turned on, respond to the target transaction layer data packet sent by the central processing unit; In response to the test task request, pausing the response to the target transaction layer data packets sent by the central processing unit includes: With the switch off, obtain the interval time, and during the interval time, suspend the response to the target transaction layer data packet sent by the central processing unit; When the number of target transaction layer data packets accumulates to the target number, a response is made to the target number of target transaction layer data packets to perform a stress test, including: after waiting for the interval time, a response is made to the target number of target transaction layer data packets to perform a stress test.

3. The pressure testing method according to claim 1, characterized in that, The method further includes: Detect whether the central processing unit is responding to other task requests; If the CPU detects that it is responding to other task requests, an interrupt indication is sent to the CPU to trigger the CPU to interrupt its response to other task requests.

4. The stress testing method according to claim 3, wherein the central processing unit comprises a first core and a second core, characterized in that, The method further includes: Bind the test task request of the IO task to the first core, and bind the test task request of the management task to the second core; Detect whether the first core is responding to other task requests; If the system detects that the first core is responding to other task requests and receives a test task request for an IO task, an interrupt indication is sent to the first core to trigger the first core to interrupt its response to other task requests and prioritize responding to the test task request for the IO task. Detect whether the second core is responding to other task requests; If the system detects that the second core is responding to other task requests and receives a test task request from the management task, it sends an interrupt indication to the second core to trigger the second core to interrupt its response to other task requests and prioritize responding to the test task request from the management task.

5. The pressure testing method according to claim 3, characterized in that, The method further includes: Get interrupt mode; Upon detecting that the central processing unit (CPU) is responding to other task requests, an interrupt indication is sent to the CPU to trigger the CPU to interrupt its response to the other task requests, including: If it is detected that the central processing unit is responding to other task requests, an interrupt indication is sent to the central processing unit to trigger the central processing unit to interrupt the response to other task requests in the interrupt mode; When the number of target transaction layer packets accumulates to a target number, a response is sent to the target number of target transaction layer packets to perform a stress test, including: When the number of target transaction layer packets accumulates to the target number, a response is made to the target number of target transaction layer packets to perform stress testing in the interrupt mode.

6. The pressure testing method according to claim 3, characterized in that, The method further includes: Obtain the data transmission mode; When the number of target transaction layer packets accumulates to a target number, a response is sent to the target number of target transaction layer packets to perform a stress test, including: When the number of target transaction layer data packets accumulates to the target number, a response is made to the target number of target transaction layer data packets to perform stress testing in the data transmission mode.

7. The pressure testing method according to claim 1, characterized in that, The test task request sent by the central processing unit of the receiving host includes: Use load testing tools to simulate various load conditions and obtain test task requests, including one or more. The test task request, which includes one or more test tasks, is converted into a target transaction layer data packet that conforms to a PCIe data request. Receive the target transaction layer data packet sent by the central processing unit of the host; The test task requests include: writing specific data, writing random data, repeatedly writing the same or different data, and writing data using a specified pattern.

8. A pressure testing device, characterized in that, The device, applied to a disk array card chip, includes: The receiving module is used to receive test task requests sent by the host's central processing unit; The pause processing module is used to pause the response to the target transaction layer data packets sent by the central processing unit in response to the test task request, so as to accumulate the number of target transaction layer data packets to the target number; The recovery response module is used to respond to the target number of target transaction layer data packets when the number of target transaction layer data packets accumulates to the target number, so as to perform stress testing; The judgment module is used to determine whether the response of the disk array card chip to the target transaction layer data packet is consistent with the expected response of the central processing unit to the target transaction layer data packet; The determination module is used to determine whether the disk array card chip has passed the stress test if the response of the disk array card chip to the target transaction layer data packet is consistent with the expected response of the central processing unit to the target transaction layer data packet.

9. An electronic device, characterized in that, include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the stress testing method according to any one of claims 1 to 7.

10. A readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device is able to perform the stress testing method according to any one of claims 1 to 7.

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