Large-scale FPGA chip interconnection system and method

Abstract

The invention discloses a large-scale FPGA (Field Programmable Gate Array) chip interconnection system and method. The system comprises a board card group and an upper computer, the board card group comprises a plurality of board cards, and the plurality of board cards are interconnected through cables; at least one management chip and a plurality of FPGA chips are arranged in each board card; the management chip is connected with the plurality of FPGA chips, and the management chip is used for managing the plurality of FPGA chips in the board card; the management chip is in network communication with the upper computer, obtains an action instruction, and issues the action instruction to the FPGA chips in the board card where the action instruction is located for processing. A plurality of board cards are interconnected, and each board card is provided with a plurality of FPGA chips which are interconnected, so that required logic resources and processing capability can be combined, the prototype verification requirements of current larger and larger chip scales are met, different board cards and FPGA chips can be flexibly combined and configured according to specific requirements of chip verification, and the utilization efficiency of verification resources is improved.

Description

Technical Field

[0001] The present application relates to the field of FPGA, and in particular to a large-scale FPGA chip interconnection system and method. Background Art

[0002] Field Programmable Gate Array (FPGA) is an integrated circuit with programmable features pre-designed and implemented on silicon wafers. It can be configured into a specified circuit structure according to the needs of designers, so that customers do not have to rely on ASIC chips designed and manufactured by chip manufacturers. It is widely used in prototype verification, communications, automotive electronics, industrial control, aerospace, data centers and other fields.

[0003] Nowadays, the scale of chips is getting larger and larger. The capacity of a single FPGA is no longer able to meet the requirements of chip prototype verification. Usually, dozens, hundreds or even thousands of FPGAs are needed to complete the prototype verification of large chips, and it is difficult to ensure the interconnection between FPGA chips. Summary of the invention

[0004] In order to solve the above problems, the present application proposes a large-scale FPGA chip interconnection system, including a board group and a host computer;

[0005] The board group includes a plurality of boards, and the plurality of boards are interconnected via cables;

[0006] At least one management chip and a plurality of FPGA chips are provided in each of the boards; the management chip and the plurality of FPGA chips are connected to each other, and the management chip is used to manage the plurality of FPGA chips in the board;

[0007] The management chip communicates with the host computer through a network to obtain action instructions, and sends the action instructions to the multiple FPGA chips in the board for processing.

[0008] In one example, the plurality of boards in the board group include at least one management board and a plurality of parsing boards;

[0009] The management board communicates with the host computer through the network to obtain the action instruction, and sends the action instruction to the management chip in the parsing board in the board group so that the parsing board processes it; the management board monitors the status of the parsing board in the board group through the management chip in the parsing board;

[0010] The management board synchronizes the system clocks of the plurality of analysis boards.

[0011] In one example, the management board generates a test task, and sends a test file corresponding to the test task to the management chip of the parsing board;

[0012] The parsing board sends the test file to the multiple FPGA chips in the board through the management chip, receives the parsing results of the test file fed back by the multiple FPGA chips, determines the status of the multiple FPGA chips in the board through the management chip, and feeds back to the management board.

[0013] In one example, the host computer determines the execution task of the board group for the chip file, and divides the execution task into a plurality of subtasks; wherein the number of the subtasks is lower than the task execution upper limit corresponding to the board group, and the task execution upper limit is determined according to the number of parsing boards in the board group and the number of FPGA chips in the parsing board;

[0014] The host computer sends a plurality of subtasks corresponding to the execution task to the management board;

[0015] The management board sends the multiple subtasks to the management chips of the corresponding analysis boards respectively; wherein the number of subtasks received by each analysis board is less than the number of its internal FPGA chips;

[0016] The management chip sends the received subtask to the FPGA chip of the board where the chip is located, and the FPGA chip parses the subfile corresponding to the chip file according to the subtask.

[0017] In one example, if the management chip determines that the FPGA chip is faulty based on the feedback from the FPGA chip, the management chip allocates the subtask corresponding to the FPGA chip to other FPGA chips with redundant settings in the board where the chip is located;

[0018] If the management board determines that the management chip or the parsing board corresponding to the management chip is faulty based on the feedback from the management chip, the management board allocates the subtask corresponding to the parsing board to other parsing boards in a redundant setting.

[0019] In one example, if the management chip determines that there are no other FPGA chips with redundant settings in the board where it is located, it will reallocate the received subtask to the FPGA chip that is not faulty.

[0020] In one example, if the management board determines that there is no redundant parsing board in the board group, the management board determines the status of a parsing board that is not faulty in the board group, and estimates the task execution time of the parsing board according to the status of the parsing board;

[0021] If the estimated task execution time is higher than the preset time, it is reported to the host computer so that the host computer can mark the subtasks corresponding to the faulty analysis board and distribute them to other board groups;

[0022] If the estimated task execution time is lower than the preset time, the subtask corresponding to the faulty parsing board will be allocated to the parsing board with the shortest task execution time.

[0023] In one example, the host computer receives the subtask corresponding to the faulty parsing board reported by the management board, and marks the subtask;

[0024] Determine the chip file corresponding to the subtask, and determine, among all the board groups, a designated board group that executes the subtask corresponding to the chip file;

[0025] If the designated board group has redundant parsing boards, assigning the marked subtasks to the designated board group;

[0026] Otherwise, the marked subtask is assigned to a preset standby board group; wherein, if the status of all parsing boards in the preset standby board group is in a working state, the marked subtask is queued in the preset standby board group;

[0027] The parsing result of the marked subtask is received, and the parsing result is sent to the management board in the board group where the parsing board with the fault is located.

[0028] In one example, each of the boards includes a management chip and six FPGA chips, and the management chip is interconnected with the six FPGA chips via a dual-ring method.

[0029] On the other hand, the present application also proposes a large-scale FPGA chip interconnection method, characterized in that it is performed by a large-scale FPGA chip interconnection system as described in any of the above examples, and the method includes:

[0030] The host computer generates a corresponding execution task according to the chip file, and divides the execution task into multiple subtasks;

[0031] Sending the subtask to one or more management boards of the board group;

[0032] The management board sends the received subtask to the management chip of the parsing board in the board group;

[0033] The management chip sends the received subtask to the FPGA chip of the board where it is located, so that the subtask is executed by the FPGA chip and the chip file is parsed.

[0034] The large-scale FPGA chip interconnection system proposed in this application can bring the following beneficial effects:

[0035] 1. By interconnecting multiple boards, and each board has multiple FPGA chips interconnected, the required logic resources and processing capabilities can be combined to meet the current prototype verification requirements of increasingly large chip scales. Different boards and FPGA chips can be flexibly combined and configured according to the specific needs of chip verification, thereby improving the utilization efficiency of verification resources.

[0036] 2. Each board group is equipped with a management board, and each board is equipped with a management chip, forming a hierarchical management architecture. The management board can uniformly manage and schedule the entire board group, and the management chip is responsible for coordinating the FPGA chips in the board, making the management of large-scale FPGA chips more orderly, reducing management complexity, and facilitating rapid fault location.

[0037] 3. The system formed by interconnecting multiple boards and FPGA chips has a certain degree of redundancy. If a board or FPGA chip fails, other normal parts can continue to work, ensuring the continuity of verification work and improving the reliability of the entire verification system. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0039] Figure 1 This is a schematic diagram of the structure of a large-scale FPGA chip interconnection system in an embodiment of the present application;

[0040] Figure 2 This is a schematic diagram of the structure of the board group in the embodiment of the present application;

[0041] Figure 3 Schematic diagram of the process of large-scale FPGA chip interconnection method in the embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0043] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0044] like Figure 1 As shown, the embodiment of the present application provides a large-scale FPGA chip interconnection system, including a board group and a host computer (not shown in the figure);

[0045] The host computer may be a computing device with data processing capabilities, for example, it may be a processor with data processing capabilities.

[0046] The board group includes multiple boards, which are interconnected by cables. The boards are placed in the chassis in a high-density stacking manner to reduce the length of interconnected cables, and multiple chassis are interconnected by optical fibers. One or more board groups can be placed in each chassis.

[0047] like Figure 2 As shown, each board is provided with at least one management chip and multiple FPGA chips, for example, Figure 2 A management chip is provided in the system, which is implemented by the ZYNQ platform, and six FPGA chips are provided, namely FPGA1 to FPGA6.

[0048] The management chip has a connection relationship with multiple FPGA chips, for example Figure 2 As shown in FIG. 1 , the management chip is interconnected with six FPGA chips through a dual-ring method. The dual-ring method refers to a method consisting of two physical or logical ring networks ( Figure 2 In the example, FPGA1, FPGA2, FPGA5, and FPGA6 form a ring network, and FPGA3, FPGA4, FPGA5, and FPGA6 form another ring network. Nodes are connected to both rings at the same time. Data can be transmitted in the same or opposite directions on the two rings, forming a redundant network architecture.

[0049] The management chip is used to manage the board ( Figure 2 Taking board 1 as an example for explanation, multiple FPGA chips in the board are managed.

[0050] The management chip communicates with the host computer over the network, obtains action instructions, and sends the action instructions to multiple FPGA chips in the board for processing. It can also upload the FPGA management data to the host computer.

[0051] 1. By interconnecting multiple boards, and each board has multiple FPGA chips interconnected, the required logic resources and processing capabilities can be combined to meet the current prototype verification requirements of increasingly large chip scales. Different boards and FPGA chips can be flexibly combined and configured according to the specific needs of chip verification, thereby improving the utilization efficiency of verification resources.

[0052] 2. Each board group is equipped with a management board, and each board is equipped with a management chip, forming a hierarchical management architecture. The management board can uniformly manage and schedule the entire board group, and the management chip is responsible for coordinating the FPGA chips in the board, making the management of large-scale FPGA chips more orderly, reducing management complexity, and facilitating rapid fault location.

[0053] 3. The system formed by interconnecting multiple boards and FPGA chips has a certain degree of redundancy. If a board or FPGA chip fails, other normal parts can continue to work, ensuring the continuity of verification work and improving the reliability of the entire verification system.

[0054] In one embodiment, the plurality of boards in the board group include at least one management board and a plurality of analysis boards. Figure 1 As shown, there is a management board and four parsing boards (board 1 to board 4), and the management board (for example, it can be implemented through the ZYNQ platform) communicates with the host computer through the network, obtains the action instruction, and sends the action instruction to the management chip in the parsing board in the board group, so that the parsing board can process it. At this time, the management chip realizes communication with the host computer through the management board.

[0055] The management board monitors the status of the analysis boards in the board group through the management chip in the analysis board. The management chip feeds back the status of each FPGA chip in the board to the management board in real time, so that the management board can grasp the status of each analysis board.

[0056] The management board synchronizes the system clocks of several analysis boards to facilitate the subsequent log synchronization and management of each analysis board.

[0057] In one embodiment, before the actual operation, each board group needs to be tested to ensure that the board group is working correctly before the actual operation is performed.

[0058] During the test, the management board generates a test task and sends the test file corresponding to the test task to the management chip of the analysis board.

[0059] Parsing board, send the test file to multiple FPGA chips in the board through the management chip, and receive the parsing results of the test file fed back by multiple FPGA chips. That is equivalent to the management chip sending the message corresponding to the test file, and the FPGA chip parses the message and feeds back the corresponding parsing results.

[0060] Through the management chip, the status of multiple FPGA chips in the board is determined according to the analysis results. If the analysis result is correct, the status of the FPGA chip is normal, otherwise, the status is abnormal and feedback is given to the management board. The management board can also obtain the status of all FPGA chips in all analysis boards in the board group.

[0061] In one embodiment, after executing the status test of the FPGA chip, the host computer marks the FPGA chip in the abnormal state, so that the task is only assigned to the FPGA chip in normal operation. Corresponding numbers are assigned to each board group, analysis board, and FPGA chip in advance to facilitate data transmission.

[0062] The host computer determines the execution task of the board group for the chip file and divides the execution task into multiple subtasks. Generally speaking, each chip file execution task only needs one board group to execute, but sometimes the number of chip files is large. In this case, multiple board groups may be selected to execute the task together. In this case, the corresponding execution task can be assigned to each board group.

[0063] Among them, the number of subtasks is lower than the upper limit of task execution corresponding to the board group. The upper limit of task execution is determined by the number of parsing boards in the board group and the number of FPGA chips in the parsing boards. For example, the host computer divides the chip file to be tested corresponding to the board group into N parts and encodes these N parts. At this time, it is assumed that there are m parsing boards in the board group, which are numbered 1 to m respectively, and each parsing board has k FPGA chips, which are numbered 1 to k respectively. Figure 1 and Figure 2 For example, at this time, m = 4, k = 6. At this time, the upper limit of task execution is m*k, and the number of subtasks is lower than the upper limit of task execution.

[0064] The host computer sends multiple subtasks corresponding to the execution task to the management board, and the management board sends the multiple subtasks to the management chip of the corresponding analysis board respectively. Of course, it is necessary to ensure that the number of subtasks received by each analysis board is lower than the number of its internal FPGA chips.

[0065] The management chip sends the received subtask to the FPGA chip of the board where it is located. The FPGA chip downloads the corresponding subfile according to the subtask and parses the subfile corresponding to the chip file.

[0066] Furthermore, during the actual analysis and operation process, an FPGA chip or an analysis board may suddenly fail. In this case, if the management chip determines that the FPGA chip has a fault based on the feedback from the FPGA chip, the subtask corresponding to the FPGA chip will be allocated to other FPGA chips with redundant settings in the board.

[0067] Generally speaking, there are redundant FPGA chips in each analysis board, which means that there are always idle FPGA chips when allocating subtasks.

[0068] However, in some cases, if the management chip determines that there are no other FPGA chips with redundant settings in the board where it is located, it will reallocate the received subtask to the FPGA chip that is not at fault, that is, it will still retain the subtask in the current parsing board for parsing. If the other FPGA chips are in working state, they can be allocated to the FPGA chip that is not at fault by queuing, so that the FPGA chip that is not at fault completes its own work and then continues to execute the newly allocated subtask.

[0069] In the event of a failure on the parsing board, if the management board determines that the management chip or the parsing board corresponding to the management chip has a fault based on the feedback from the management chip (for example, the management chip reports that multiple FPGA chips have failed at the same time, or the management chip fails to provide correct feedback, thereby determining that the management chip itself has failed), then the subtask corresponding to the parsing board will be assigned to other parsing boards in a redundant setting.

[0070] Similar to the existence of redundant FPGA chips in a single analysis board, in a single board group, there are usually redundant analysis boards that are not working.

[0071] Of course, there is also a situation where the management board determines that there is no redundant parsing board in the board group. At this time, due to the large amount of data on the parsing board and the fact that the data exchange and communication between different board groups is not as convenient as the data exchange between parsing boards within the board group, the management board prioritizes determining the status of the parsing board in the board group that has no faults, and estimates the task execution time of the parsing board based on the status of the parsing board. It can be determined based on the number of subtasks that need to be executed in each parsing board. Usually, the estimated task execution time of the last FPGA chip that completes the task in each parsing board is selected as the estimated task execution time of the board to which it belongs.

[0072] If the estimated task execution time is higher than the preset time, it means that continuing to wait for other parsing boards in the board group to complete their work before executing the work of the currently faulty parsing board will result in too long waiting time. Therefore, it is reported to the host computer so that the host computer can mark the subtasks corresponding to the faulty parsing board and assign them to other board groups.

[0073] Of course, if the estimated task execution time is lower than the preset time, the subtask corresponding to the faulty analysis board will be assigned to the analysis board with the shortest task execution time. After the analysis board completes its existing subtask, it can continue to execute the newly assigned marked subtask.

[0074] Furthermore, in the case where the estimated task execution time is higher than the preset time, the host computer needs to assign the subtasks to other board groups. At this time, if they are directly randomly assigned, it is easy to cause abnormal execution results of the execution tasks corresponding to the chip files.

[0075] Based on this, the host computer receives the subtask corresponding to the faulty parsing board reported by the management board, marks the subtask, determines the chip file corresponding to the subtask, and determines the designated board group to execute the subtask corresponding to the chip file among all board groups.

[0076] As mentioned above, for some chip files, they may be parsed by one board group alone, or by multiple board groups at the same time. At this time, it is determined whether to parse them by multiple board groups at the same time.

[0077] If the designated board group has a parsing board with redundant settings, the marked subtask is assigned to the designated board group, and the parsing board with redundant settings in the designated board group executes the corresponding subtask.

[0078] Otherwise, the marked subtask is assigned to the preset standby board group. The preset standby board group refers to a separate board group that is preset. When subtasks are normally assigned, subtasks will not be assigned to this board group. Instead, this board group will be temporarily enabled when other board groups fail.

[0079] If the status of all parsing boards in the preset standby board group is in working status, the marked subtask will be queued in the preset standby board group, and the marked subtask can be continued to be executed after a parsing board among all parsing boards completes the assigned subtask.

[0080] Receive the parsing result of the marked subtask and send the parsing result to the management board in the board group where the faulty parsing board is located. If the parsing result affects the parsing results of other subsequent subtasks, the management board can continue to perform the parsing of other subtasks based on the parsing result.

[0081] like Figure 3 As shown, the embodiment of the present application also provides a large-scale FPGA chip interconnection method, which is performed by the large-scale FPGA chip interconnection system as described in any of the above embodiments, and the method includes:

[0082] S301: The host computer generates a corresponding execution task according to the chip file, and divides the execution task into multiple subtasks.

[0083] S302: Send the subtask to one or more management boards of the board group.

[0084] S303: The management board sends the received subtask to the management chip of the parsing board in the board group.

[0085] S304: The management chip sends the received subtask to the FPGA chip of the board where it is located, so that the subtask is executed by the FPGA chip and the chip file is parsed.

[0086] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A large-scale FPGA chip interconnection system, characterized in that: Including board group and host computer; The board group includes a plurality of boards, and the plurality of boards are interconnected via cables; At least one management chip and a plurality of FPGA chips are provided in each of the boards; the management chip and the plurality of FPGA chips are connected to each other, and the management chip is used to manage the plurality of FPGA chips in the board; The management chip communicates with the host computer through a network to obtain action instructions, and sends the action instructions to the multiple FPGA chips in the board for processing.

2. The method according to claim 1, characterized in that The plurality of boards in the board group include at least one management board and a plurality of analysis boards; The management board communicates with the host computer through the network to obtain the action instruction, and sends the action instruction to the management chip in the analysis board in the board group, so that the analysis board processes it; The management board monitors the status of the analysis boards in the board group through the management chip in the analysis board; The management board synchronizes the system clocks of the plurality of analysis boards.

3. The method according to claim 2, characterized in that The management board generates a test task, and sends the test file corresponding to the test task to the management chip of the analysis board; The parsing board sends the test file to the multiple FPGA chips in the board through the management chip, receives the parsing results of the test file fed back by the multiple FPGA chips, determines the status of the multiple FPGA chips in the board through the management chip, and feeds back to the management board.

4. The method according to claim 2, characterized in that: The host computer determines the execution task of the board group for the chip file, and divides the execution task into a plurality of subtasks; wherein the number of the subtasks is lower than the task execution upper limit corresponding to the board group, and the task execution upper limit is determined according to the number of parsing boards in the board group and the number of FPGA chips in the parsing board; The host computer sends a plurality of subtasks corresponding to the execution task to the management board; The management board sends the multiple subtasks to the management chips of the corresponding analysis boards respectively; wherein the number of subtasks received by each analysis board is less than the number of its internal FPGA chips; The management chip sends the received subtask to the FPGA chip of the board where the chip is located, and the FPGA chip parses the subfile corresponding to the chip file according to the subtask.

5. The method according to claim 4, characterized in that The management chip, if it is determined based on the feedback of the FPGA chip that the FPGA chip is faulty, allocates the subtask corresponding to the FPGA chip to other FPGA chips with redundant settings in the board where the chip is located; If the management board determines that the management chip or the parsing board corresponding to the management chip is faulty based on the feedback from the management chip, the management board allocates the subtask corresponding to the parsing board to other parsing boards in a redundant setting.

6. The method according to claim 5, characterized in that If the management chip determines that there are no other FPGA chips with redundant settings in the board where it is located, the management chip will reallocate the received subtasks to the FPGA chip that is not faulty.

7. The method according to claim 5, characterized in that The management board, if it is determined that there is no redundant parsing board in the board group, determines the status of a parsing board that is not faulty in the board group, and estimates the task execution time of the parsing board according to the status of the parsing board; If the estimated task execution time is higher than the preset time, it is reported to the host computer so that the host computer can mark the subtasks corresponding to the faulty analysis board and distribute them to other board groups; If the estimated task execution time is lower than the preset time, the subtask corresponding to the faulty parsing board will be allocated to the parsing board with the shortest task execution time.

8. The method according to claim 7, characterized in that The host computer receives the subtask corresponding to the faulty parsing board reported by the management board, and marks the subtask; Determine the chip file corresponding to the subtask, and determine, among all the board groups, a designated board group that executes the subtask corresponding to the chip file; If the designated board group has redundant parsing boards, assigning the marked subtasks to the designated board group; Otherwise, the marked subtask is assigned to a preset standby board group; wherein, if the status of all parsing boards in the preset standby board group is in a working state, the marked subtask is queued in the preset standby board group; The parsing result of the marked subtask is received, and the parsing result is sent to the management board in the board group where the parsing board with the fault is located.

9. The method according to claim 1, characterized in that: Each of the boards includes a management chip and six FPGA chips, and the management chip is interconnected with the six FPGA chips via a dual-ring method.

10. A large-scale FPGA chip interconnection method, characterized in that: The method is performed by the large-scale FPGA chip interconnection system according to any one of claims 1 to 9, and comprises: The host computer generates a corresponding execution task according to the chip file, and divides the execution task into multiple subtasks; Sending the subtask to one or more management boards of the board group; The management board sends the received subtask to the management chip of the parsing board in the board group; The management chip sends the received subtask to the FPGA chip of the board where it is located, so that the subtask is executed by the FPGA chip and the chip file is parsed.

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