Method for storing critical data

Abstract

The invention relates to a method for storing critical data. The present disclosure provides a method and an electrical device for storing critical data blocks of the electrical device in a memory external to the electrical device. An example method includes obtaining a first encrypted data block by encrypting a key data block using a first encryption key; obtaining a second encrypted data block by encrypting the key data block using a second encryption key different from the first encryption key; and storing the first encrypted data block and the second encrypted data block in a memory.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATION(S)

[0002] This application claims the benefit of priority of French Patent Application No. FR2312138, filed on November 8, 2023, entitled “Method for storing critical data”, which is hereby incorporated herein by reference to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to electrical circuits and devices, and more particularly to the security of critical data used in such circuits and devices. The present disclosure more particularly relates to a method for storing critical data in an external memory. Background Art

[0004] Storing critical data in electrical equipment is a task that is part of the overall safety management of the electrical equipment.

[0005] It would be desirable to improve, at least in part, certain aspects of known methods for storing critical data in external memory. Summary of the invention

[0006] A more secure method for storing critical data is needed.

[0007] What is needed is a more secure method for storing critical data in external memory.

[0008] What is needed is a method for storing critical data that does not increase the complexity of the method.

[0009] What is needed is a method for storing critical data that is capable of immediately detecting modifications to the critical data.

[0010] There is a need for an electrical device capable of performing the above described method for storing critical data.

[0011] One embodiment addresses all or part of the disadvantages of known methods for storing critical data.

[0012] One embodiment provides a method for storing a critical data block of an electrical device in a memory external to the electrical device, comprising the following steps:

[0013] - obtaining a first encrypted data block by encrypting the key data block using a first encryption key;

[0014] - obtaining a second encrypted data block by encrypting the key data block using a second encryption key different from the first encryption key; and

[0015] - Storing the first encrypted data block and the second encrypted data block in a memory.

[0016] Another embodiment provides an electrical device configured to store a critical data block in a memory external to the electrical device by performing the following steps:

[0017] - obtaining a first encrypted data block by encrypting the key data block using a first encryption key;

[0018] - obtaining a second encrypted data block by encrypting the key data block using a second encryption key different from the first encryption key; and

[0019] - Storing the first encrypted data block and the second encrypted data block in a memory.

[0020] According to an embodiment, the first encrypted data block and the second encrypted data block are mixed into the memory.

[0021] According to an embodiment, in the memory, each data constituting each first encrypted data block is stored immediately before the corresponding second encrypted data block.

[0022] According to an embodiment, the first encrypted data block and the second encrypted data block are obtained by applying AES to the key data.

[0023] According to an embodiment, the first encrypted data block is obtained by using the following steps:

[0024] (a) combining a key data block with a first data word; and

[0025] (b) Encrypting the result of step (a) using the first encryption key.

[0026] According to an embodiment, the second encrypted data block is obtained by using the following steps:

[0027] (c) combining the key data block with the first encrypted data block; and

[0028] (d) Encrypting the result of step (c) using a second encryption key.

[0029] According to an embodiment, the memory is a DRAM memory.

[0030] According to an embodiment, the electrical device comprises a processor capable of processing critical data blocks.

[0031] Another embodiment provides a method for retrieving a key data block stored in a memory by using the method described above.

[0032] Another embodiment provides a device capable of retrieving a key data block stored in a memory by using the method described above.

[0033] According to an embodiment, the method comprises the following steps:

[0034] - obtaining a first encrypted data block and a second encrypted data block from a memory;

[0035] - decrypting the first encrypted data block using the first encryption key;

[0036] - decrypting the second encrypted data block using the second encryption key; and

[0037] - Compare the results of both decryption steps, if they are identical then the key data block can be used.

[0038] According to an embodiment, if the results of the two decryption steps are not identical, the critical data block cannot be used.

[0039] According to an embodiment, the step of retrieving the first encrypted data block and the second encrypted data block from the memory comprises the step of separating the first encrypted data and the second encrypted data. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0041] Figure 1 The process of performing the combination is illustrated very schematically in block diagram form. Figures 2 to 4 Examples of electronic devices of the described embodiments;

[0042] Figure 2 A first embodiment of a method for storing critical data is schematically illustrated in block diagram form;

[0043] Figure 3 The block diagram shows Figure 2 The steps of the embodiment;

[0044] Figure 4 The block diagram schematically illustrates Figure 2 An example of an implementation of the first embodiment; and

[0045] Figure 5 A second embodiment of a method for storing critical data is schematically illustrated in block diagram form. DETAILED DESCRIPTION

[0046] In the various figures, similar features are indicated by similar reference numerals. In particular, common structural and / or functional features among various embodiments may have the same reference numerals and may be deployed with the same structure, size and material properties.

[0047] For clarity, only the operations and elements that are helpful for understanding the embodiments described herein are illustrated and described in detail.

[0048] Unless otherwise specified, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0049] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers, such as terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as terms "above", "below", "higher", "lower", etc., or orientation qualifiers, such as "horizontal", "vertical", etc., reference is made to the orientation shown in the figure.

[0050] Unless otherwise indicated, the expressions "about", "approximately", "substantially" and "approximately" all mean within 10%, preferably within 5%.

[0051] The embodiments described below relate to storing critical data in a memory and corresponding retrieval methods. In the following, critical data is data that is limited to access by one or more specific people and / or devices. In most cases, when a processor or circuit is processing sensitive data, these data are stored in a memory that the processor or circuit trusts. For security purposes, this is more convenient.

[0052] Trusted memory is usually a memory mounted on the same die as a processor or circuit and with which it can communicate securely. Due to space limitations of electronic devices, trusted memory usually does not have enough storage capacity to handle all necessary critical data. For this reason, it is more convenient to use untrusted memory to store critical data. Untrusted memory, hereinafter referred to as external memory, is memory with which it is not possible to communicate securely. In this regard, untrusted memory is usually not mounted on the same die as a processor or circuit.

[0053] If critical data is stored in an untrusted memory, then a method of protecting the critical data still needs to be implemented. The embodiments described below relate to a secure method for storing critical data in an untrusted memory, and a corresponding retrieval method. In this regard, the method includes a double encryption step using different encryption keys and a step of mixing the encrypted data. This will prevent unauthorized persons or circuits from accessing the data and / or modifying the data. In combination Figures 2 to 4 Such methods are described in more detail.

[0054] Figure 1 A block diagram is shown very schematically to enable the combination Figures 2 to 4 An electronic device 100 for storing critical data is described.

[0055] The device 100 is an electronic device configured to process data, more particularly, to process critical data.

[0056] The device 100 comprises a processor 101 (CPU) enabling processing of data. According to an example, the device 100 may comprise a plurality of processors, each processor being configured to process a different type of data. According to a specific example, the device 100 may comprise at least one processor configured to process critical data.

[0057] The device 100 also includes one or more memories 102 (MEM) in which data (e.g., critical data) is stored. According to an example, the device 100 includes multiple types of memory, such as ROM, RAM, volatile memory, and / or non-volatile memory. According to a specific example, the device 100 may include one or more memories that are trusted by the processor 101 and can be securely accessed by the processor 101. According to an embodiment, the device 100 includes one or more external memories or untrusted memories that cannot be securely accessed by the processor 101. In combination Figures 2 to 4 The described method for storing critical data involves storing the critical data by the processor 101 in an external memory.

[0058] The device 100 also includes one or more security elements 103 (SE) configured to process critical and / or secret data. The security element 103 may include its own (one or more) processors, its own one or more memories, etc. According to an example, in combination with Figures 2 to 4 The described method for storing critical data may involve storing the critical data by the secure element 103 in an external memory.

[0059] Device 100 also optionally includes one or more input / output circuits 104 (I / O) that enable device 100 to send and / or receive data and / or power with one or more external electronic devices.

[0060] The device 100 further comprises one or more circuits 105 (FCT1) and 106 (FCT2) implementing one or more functions of the device 100. According to an example, the circuits 105 and 106 may comprise certain data processing circuits, such as ciphering circuits, or circuits enabling measurements to be performed, such as sensors.

[0061] The device 100 also includes one or more communication buses 107 that enable all circuits of the device 100 to communicate. Figure 1 In FIG. 1 , a single bus 107 is shown coupling the processor 101 , the one or more memories 102 , the secure element 103 and the circuits 104 to 106 , but in practice the device 100 includes multiple communication buses coupling these different elements.

[0062] Figure 2 An embodiment of a method for storing critical data in a memory performed by the device 200 is represented in block diagram form.

[0063] According to an embodiment, the device 200 includes a combination of Figure 1 A processor 201 (CPU) of the type of processor 101 described, and a memory 202 (external RAM) considered untrusted by the processor 201. The memory 202 is hereinafter referred to as the external memory. The processor 201 is capable of processing critical data and needs to store the critical data in the memory 202.

[0064] The processor 201 can access a private bus 204 (PRIVATE BUS) to ensure secure communication with other circuits or components of the device 200.

[0065] The memory 202 can only access the public bus 205 (Public BUS) to communicate with other components of the device 200, in particular with the processor 201. According to an example, the memory 202 is a random access memory, also called RAM, and more particularly a dynamic random access memory, also called DRAM.

[0066] The device 201 also comprises an encryption and decryption unit 206 (Crypt / Decrypt) configured to connect the buses 204 and 205. More specifically, the unit 206 is able to exchange critical data with the dedicated bus 204 and encrypted data with the common bus 205.

[0067] According to an embodiment, unit 206 comprises two identical encryption and decryption engines 2061 and 2062 capable of:

[0068] - encrypting critical data received from the dedicated bus 204; and

[0069] - Decrypting encrypted data received from the common bus 204.

[0070] The only difference between engines 2061 and 2062 is that they operate using different encryption and decryption keys 2063 (KeyA) and 2064 (KeyB). Figure 2 , engine 2061 is using encryption and decryption key 2063, and engine 2062 is using encryption and decryption key 2064.

[0071] To this end, engines 2061 and 2062 may implement different types of symmetric encryption and decryption algorithms. One example of an encryption and decryption algorithm that may be used is the Advanced Encryption Standard, also known as AES. This particular example will be combined with Figure 5 Describe in detail.

[0072] The method for storing the critical data of the processor 201 in the external memory 202 is as follows. Here, some critical data of the processor 201 are considered. The critical data is divided into critical data blocks Data200 of the same size. The critical data blocks Data200 are sent to the encryption and decryption unit 206 via the dedicated bus 204. Then, the unit 206 uses engines 2061 and 2062 to encrypt each critical data block Data200. More specifically, the engine 2061 encrypts each critical data block Data200 using the encryption and decryption key 2063 to provide a first encrypted data block EA (Data200). At the same time, the engine 2062 encrypts each critical data block Data200 using the encryption and decryption key 2064 to provide a second encrypted data block EB (Data200).

[0073] The first encrypted data block EA (Data 200) and the second encrypted data block EB (Data 200) are both sent to the memory 202 via the common bus 205 for storage. According to a preferred embodiment, the first encrypted data block EA (Data 200) and the second encrypted data block EB (Data 200) are mixed in the memory 202. Figure 3 A preferred manner of mixing the first encrypted data block EA (Data 200) and the second encrypted data block EB (Data 200) in the memory 202 is described in detail.

[0074] Therefore, the method for storing the key data block Data200 in the external memory 202 includes the following steps:

[0075] - Encrypt each key data block Data200 using the first encryption and decryption key 2063 to obtain a first encrypted data block EA(Data200);

[0076] - encrypting each key data block Data200 using the second encryption and decryption key 2064 to obtain a second encrypted data block EB(Data200); and

[0077] - Each first encrypted data block EA (Data200) and the second encrypted data block EB

[0078] (Data200) is stored in the external memory 202, and for example, the first encrypted data block EA (Data200) and the second encrypted data block EB (Data200) are stored in the external memory 202.

[0079] Mix.

[0080] Once the first encrypted data block EA (Data 200) and the second encrypted data block EB (Data 200) are stored in the memory, the method for retrieving the key data is as follows: The first encrypted data block EA (Data 200) and the second encrypted data block EB (Data 200) are both retrieved from the external memory 202.

[0081] The first encrypted data block EA (Data 200) and the second encrypted data block EB (Data 200) are sent to the encryption and decryption unit 206 via the common bus 205. Each encrypted data block is decrypted by the engine 2061 or 2062. More specifically, the first encrypted data block EA (Data 200) is decrypted using the engine 2061 and the key 2063, because the key 2063 was used to obtain the encrypted data block EA (Data 200). The second encrypted data block EB (Data 200) is decrypted using the engine 2062 and the key 2064, because the key 2064 was used to obtain the encrypted data block EB (Data 200). The two decrypted data blocks are then compared. If they are the same, then the correct key data block Data 200 has been retrieved and can be sent to the processor 201 via the dedicated bus 204. If they are not the same, then the correct key data block Data 200 has not been retrieved because it has been damaged. The processor cannot use the decrypted data block.

[0082] Therefore, the method for retrieving the key data block Data 200 that has been stored in the external memory 202 using the previous method includes the following steps:

[0083] - Obtain the first encrypted data block EA (Data200) from the external memory 202 and

[0084] The second encrypted data block EB (Data200);

[0085] - Decrypt the first encrypted data block EA (Data 200) using the first encryption key 2063;

[0086] - Decrypt the second encrypted data block EB (Data200) using the second encryption key 2064;

[0087] as well as

[0088] - The results of both decryption steps are compared, if they are identical then the key data block can be used by the processor.

[0089] One advantage of these approaches is that they allow the processor to store critical data in untrusted memory.

[0090] Figure 3 Represented in block diagram form Figure 2 An embodiment of the mixing step of encrypted data.

[0091] exist Figure 3 , it shows the status of some key data blocks Data300 in the processor 301 (CPU) before being stored in the external memory.

[0092] exist Figure 3 In the paper, it is also stated that according to the combination Figure 2 The first encrypted data block EA (Data 300) and the second encrypted data block EB (Data 300) generated by the storage method described in the embodiment of the present invention are both stored in the external memory 302 (external RAM).

[0093] According to an embodiment, the first encrypted data block EA(Data300) and the second encrypted data block EB(Data300) are mixed in memory 302. In other words, the entire two versions of the encrypted data are not written in one block in memory 302, but are divided into several data blocks written in different parts of the memory.

[0094] According to a preferred embodiment, each first encrypted data block EA (Data300) is stored between two second encrypted data blocks EB (Data300). Similarly, each second encrypted data block EB (Data300) is stored between two first encrypted data blocks EA (Data300). In other words, each first encrypted data block EA (Data300) is stored immediately before the corresponding second encrypted data block EB (Data300). Similarly, each second encrypted data block EB (Data300) is stored immediately before the corresponding first encrypted data block EA (Data300).

[0095] Therefore, if someone wants to damage the key data block Data300 by accessing the memory 302, then it is most likely that two different parts of the first encrypted data block and the second encrypted data block are damaged. Then, it is extremely unlikely that the two damaged data blocks will decrypt to the same result. There is a concept of "diffusion" in the encryption algorithm, whereby if only 1 bit of the encrypted data is changed, then this will be correlated with all the bits of the decrypted block (not just the nearby bits) and will change about half of them on average.

[0096] Figure 4 The block diagram shows the combination Figure 2 Examples of implementations of embodiments of the described methods.

[0097] More specifically, Figure 4 Indicates that according to the combination Figure 2 Method 340 for storing critical data in a memory according to the described embodiment, and Figure 2 A method 350 of the described embodiment is used to retrieve such critical data in memory.

[0098] Therefore, method 340 includes the following steps.

[0099] At the initial step 341 (Data 200), Figure 2 The processor 201 wants to store some key data blocks Data200 in the external memory 202.

[0100] At step 342 (copy) following step 341 , the processor 201 creates a copy of the critical data block Data200 and sends both copies to the encryption and decryption unit 206 via the dedicated bus 204 .

[0101] At step 343 (encryption KeyA) following step 342, the engine 2061 of the encryption and decryption unit 206 encrypts the first copy of the key data block Data200 using the first encryption and decryption key 2063. The first encrypted data EA (Data200) is generated.

[0102] At step 344 (encryption KeyB) following step 342, the engine 2062 of the encryption and decryption unit 206 encrypts the second copy of the key data block Data200 using the second encryption and decryption key 2064. The second encrypted data EB (Data200) is generated.

[0103] At step 345 (EAB (Data 200)) after steps 343 and 344, the first encrypted data block EA (Data 200) and the second encrypted data block EB (Data 200) are sent to the memory 202 via the common bus 205 for storage. According to a preferred embodiment, the first encrypted data block EA (Data 200) and the second encrypted data block EB (Data 200) are combined, for example, using Figure 3 The mixing method described in detail is mixed in the memory 202.

[0104] The method 350 includes the following steps.

[0105] At initial step 351 (Retrieve), data EAB(Data 200) is retrieved from memory 202 as a first encrypted data block EA(Data 200) and a second encrypted data block EB(Data 200).

[0106] At step 352 (Decryption KeyA) following step 351, each first encrypted data block EA(Data200) is then decrypted by using the encryption and decryption key 2063 to obtain a first copy of the data block Data200.

[0107] At step 353 (Decryption KeyB) following step 351, each second encrypted data block EB(Data200) is then decrypted by using the encryption and decryption key 2064 to obtain a second copy of the data block Data200.

[0108] At step 354 (Comp) after step 352 and 352, the two copies of each key data block Data200 are compared. If the comparison is successful (output Y of block 354), the next step is step 355 (Use). Otherwise (output N of block 354), the next step is step 356 (Error).

[0109] At step 355 (Use), each copy of the critical data block Data200 is identical, which means that the data EAB(Data200) has not been corrupted during its storage in the memory 202. The processor 201 can safely use the critical data Data200.

[0110] At step 356 (Error), at least one copy of the critical data block Data200 is not identical, which means that the data EAB(Data200) has been corrupted during its storage in the memory 202. According to an example, an error message may be sent to the processor 201. According to another example, both copies of the critical data block Data200 may be sent to the processor for analysis.

[0111] Figure 5 Represent the combination in block diagram form Figure 2 Implementation of variants of the embodiments of the described methods.

[0112] More specifically, Figure 5 401 and 402 are used to store key data in external memory and to retrieve data. According to an embodiment, both methods 401 and 402 are using the AES algorithm to encrypt and decrypt data. More specifically, both methods 401 and 402 are using the chaining of several AES operations, commonly referred to as AES-CBC (AES-Cipher-Block-Chaining).

[0113] The method 401 for storing key data in an external memory is as follows. The key data is stored in an external memory. Figure 2 The processor 201 type of processor is sent to Figure 2 The encryption and decryption unit 206 of the encryption and decryption unit creates two copies of the key data block, hereinafter referred to as Data 400-1 (plaintext block 1) and Data 400-2 (plaintext block 2).

[0114] The first copy Data400-1 is combined with the first data word Seed400-1 using an exclusive OR logic operation 403 (also called an XOR operation), and then an encryption operation 404 is used using the encryption key KeyA4 to obtain the first encrypted copy data EA4 (Data400-1) (ciphertext block 1A). According to the example, the encryption operation 404 is an implementation of the AES encryption operation. Then, the second copy Data400-2 is combined with the first encrypted copy data EA4 (Data400-1) using an XOR operation 403, and then an encryption operation 404 is used using the encryption key KeyA4 to obtain the second encrypted copy data EA4 (Data400-2) (ciphertext block 2A). Therefore, two different encrypted data are obtained.

[0115] In parallel, the second copy Data400-2 is also combined with the second data word Seed400-2 using an XOR operation 403, and then an encryption operation 404 is used using another encryption key KeyB4 to obtain the second encrypted copy data EB4 (Data400-2) (ciphertext block 1B). Then, the first copy Data400-1 is also combined with the second encrypted copy data EB4 (Data400-2) using an XOR operation 403, and an encryption operation 404 is used using the encryption key KeyB4 to obtain the first encrypted copy data EB4 (Data400-1) (ciphertext block 2B). Therefore, two different encrypted data blocks are obtained again.

[0116] All encrypted data blocks EA4(Data400-1), EA4(Data400-2), EB4(Data400-1) and EB4(Data400-2) can be stored in the memory. According to a preferred variation, all encrypted data EA4(Data400-1), EA4(Data400-2), EB4(Data400-1) and EB4(Data400-2) can be mixed and stored in the memory, such as in combination Figure 3 as described.

[0117] The method 402 for retrieving the key data blocks is as follows: All encrypted data blocks EA4 (Data 400-1), EA4 (Data 400-2), EB4 (Data 400-1) and EB4 (Data 400-2) are retrieved from the memory.

[0118] Each encrypted data block EA4 (Data400-1) is decrypted by using a decryption operation 405 and a key KeyA4, and then separated from the data word Seed400-1 by using an XOR operation 403. According to the example, the encryption operation 404 is an implementation of an AES decryption operation. Each encrypted data block EA4 (Data400-2) is decrypted by using a decryption operation 405, and then separated from the encrypted data block EA4 (Data400-1) by using an XOR operation 403. Then as a result of both operations, a copy Data400-1 should be retrieved.

[0119] Similarly, each encrypted data block EB4 (Data400-2) is decrypted by using the decryption operation 405 and the key KeyB4, and then separated from the data word Seed400-2 by using the XOR operation 403. Each encrypted data block EB4 (Data400-1) is decrypted by using the decryption operation 405, and then separated from the encrypted data block EB4 (Data400-2) by using the XOR operation 403. Then as a result of both operations, the copy Data400-2 should be retrieved.

[0120] According to a preferred embodiment, method 401 uses a 256-bit encryption key and uses it to encrypt 128-bit data blocks. It must be noted that random damage in both 128-bit cipher blocks in memory has a 1 in 2128 chance of resulting in the same decrypted plaintext. This means that the security strength of collision resistance is 128 bits. In order to achieve 256 bits of collision resistance, the two 128-bit blocks must be linked together using the Cipher-Block-Chaining (CBC) method, which is why the XOR operation 403 is performed with data EA4 (Data 400-1) and Data 400-2, and with data EA4 (Data 400-2) and Data 400-1. According to an example, if the XOR operation 403 is performed with data EA4 (Data 400-2) and Data 400-1, and with data EB4 (Data 400-1) and Data 400-2, under attack, data Data 400-2 may be link-damaged, so the method will only have 128-bit collision resistance.

[0121] A comparison step is then performed for each block of data to determine if the decrypted blocks are all identical. The advantage of using the AES-CBC algorithm is that it ensures that an attacker cannot just look for two encrypted blocks that happen to decrypt to the same value via two keys. They must look for two pairs of encrypted blocks that happen to decrypt to two pairs of the same value. This doubles the resistance to brute force attacks.

[0122] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined, and those skilled in the art will readily conceive of other variations.

[0123] Finally, actual implementation of the embodiments and variations described herein are within the capabilities of those skilled in the art based on the functional description provided above.

Claims

1. A method for storing a critical data block of an electrical device in a memory external to the electrical device, comprising: Obtaining a first encrypted data block by encrypting the key data block using a first encryption key; Obtaining a second encrypted data block by encrypting the key data block using a second encryption key different from the first encryption key; as well as A first encrypted data block and a second encrypted data block are stored in the memory.

2. The method of claim 1, wherein the first encrypted data block and the second encrypted data block are mixed into the memory.

3. The method of claim 1, wherein: In the memory, each data constituting each first encrypted data block is stored immediately before the corresponding second encrypted data block.

4. The method of claim 1, wherein the first encrypted data block and the second encrypted data block are obtained by applying AES to the key data block.

5. The method of claim 4, wherein the first copy of the first encrypted data block is obtained by: (a) combining a first key data block with a first data word; (b) encrypting the result of step (a) using a first encryption key; The first copy of the second encrypted data block is obtained by the following steps: (a') combining the second key data block with the first copy of the first encrypted data block; and (b') Encrypting the result of step (a') using the first encryption key.

6. The method of claim 4, wherein the second copy of the second encrypted data block is obtained by: (c) combining the second key data block with the first encrypted data block; (d) encrypting the result of step (c) using a second encryption key; The second copy of the first encrypted data block is obtained by the following steps: (c') combining the first key data block with the second copy of the second encrypted data block; and (d') Encrypting the result of step (c') using a second encryption key.

7. The method of claim 1, wherein the memory is a DRAM memory.

8. The method of claim 1, wherein the electrical device comprises a processor configured to process the critical data block.

9. A method for retrieving a key data block stored in the memory by using the method of claim 1.

10. A device configured to retrieve a critical data block stored in the memory by using the method of claim 1.

11. The method of claim 9, further comprising: Acquire a first encrypted data block and a second encrypted data block from the memory; decrypting the first encrypted data block using the first encryption key; decrypting the second encrypted data block using the second encryption key; as well as The results of the two decryption steps are compared, and if the results are identical, the key data block can be used.

12. The method of claim 9, wherein: If the results of the two decryption steps are not identical, the key data block cannot be used.

13. The method of claim 9, wherein the step of retrieving the first encrypted data block and the second encrypted data block from the memory comprises separating the first encrypted data from the second encrypted data.

14. An electrical device, configured to store a critical data block in a memory external to the electrical device by performing the following steps: Obtaining a first encrypted data block by encrypting the key data block using a first encryption key; Obtaining a second encrypted data block by encrypting the key data block using a second encryption key different from the first encryption key; as well as A first encrypted data block and a second encrypted data block are stored in the memory.

15. The electrical device of claim 14, wherein the first encrypted data block and the second encrypted data block are mixed into the memory.

16. The electrical device of claim 14, wherein: In the memory, each data constituting each first encrypted data block is stored immediately before the corresponding second encrypted data block.

17. The electric device of claim 14, wherein the first encrypted data block and the second encrypted data block are obtained by applying AES to the key data block.

18. The electrical device of claim 17, wherein the electrical device is configured to obtain a first copy of the first encrypted data block by: (a) combining a first key data block with a first data word; (b) encrypting the result of step (a) using a first encryption key; The electrical device is further configured to obtain a first copy of the second encrypted data block by: (a') combining the second key data block with the first copy of the first encrypted data block; and (b') Encrypting the result of step (a') using the first encryption key.

19. The electrical device of claim 17, wherein the electrical device is configured to obtain a second copy of the second encrypted data block by: (c) combining the second key data block with the first encrypted data block; (d) encrypting the result of step (c) using a second encryption key; The electrical device is further configured to obtain a second copy of the first encrypted data block by: (c') combining the first key data block with the second copy of the second encrypted data block; and (d') Encrypting the result of step (c') using a second encryption key.

20. The electrical device of claim 17, wherein the memory is a DRAM memory.

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