Network-on-chip cutting method and system

Abstract

The invention provides a network-on-chip cutting method and system, and relates to the field of network-on-chip, and the method comprises the steps: splitting a network-on-chip of an SOC chip into at least two networks-on-chip, including a first network-on-chip and a second network-on-chip; and integrating a plurality of peripheral interfaces on the second network-on-chip into a first AXI bus interface and a second AXI bus interface, and interconnecting the first network-on-chip and the second network-on-chip through the first AXI bus and the second AXI bus. According to the FPGA prototype verification method and device, the problems of resource shortage and difficulty in time sequence convergence caused by complex SoC design in the prior art are solved, a simpler and more efficient FPGA prototype verification technical scheme is provided, the performance of collaborative verification of multiple FPGAs is remarkably improved, the chip verification period is shortened, and the system-on-chip is easier to expand.

Description

Technical Field

[0001] The present disclosure relates to the field of on-chip networks, and in particular to a method and system for cutting an on-chip network. Background Art

[0002] With the rapid development of integrated circuit technology and the continuous advancement of chip manufacturing processes, the logic scale of large-scale system-on-chip (SoC) continues to expand, bringing new challenges to its verification process. Traditional FPGA prototype verification methods usually rely on single-chip FPGAs for verification, but due to the resource limitations of a single FPGA, they often cannot meet the needs of complex SoCs. Therefore, engineers need to divide the logic of the SoC into multiple modules and spread them across multiple FPGAs for collaborative verification.

[0003] At present, related technologies use third-party prototype verification platforms to provide automated logic cutting and verification solutions that can reduce manual intervention. However, when these platforms expand peripheral daughter cards in specific application scenarios, the complexity and difficulty of verification increase significantly. In addition, for self-developed FPGA platforms, manual logic cutting is usually required, and the cutting boundaries are usually set at the interfaces between modules. This method is suitable for modules with clear functional divisions, but it faces many limitations when facing complex SoC designs. In complex SoCs, there are many peripheral interfaces and the network on-chip interconnect (NOC) structure is complex. The traditional module boundary cutting solution causes the main FPGA to occupy too many resources and make timing convergence difficult. Summary of the invention

[0004] The embodiments of the present disclosure provide a method and system for cutting a network on a chip, aiming to solve the problems existing in the above-mentioned background technology.

[0005] In order to solve the above technical problems, the present disclosure is implemented as follows: In a first aspect, an embodiment of the present disclosure provides a method for cutting a network on chip, the method comprising: Splitting the on-chip network of the SOC chip into at least two on-chip networks, wherein the at least two on-chip networks include a first on-chip network and a second on-chip network, wherein the first on-chip network and the second on-chip network are respectively mounted with respective peripheral modules through peripheral interfaces; The multiple peripheral interfaces on the second network on chip are integrated into a first AXI bus interface and a second AXI bus interface, and the first network on chip and the second network on chip are interconnected through a first AXI bus and a second AXI bus, the first AXI bus interface and the second AXI bus interface are mutually inverse master-slave interfaces, and the first AXI bus and the second AXI bus are buses to which the first AXI bus interface and the second AXI bus interface are respectively connected.

[0006] Optionally, splitting the on-chip network of the SOC chip into at least two on-chip networks includes: In the on-chip network of the SOC chip, determining the peripheral interfaces that need to be split; Splitting the network on chip of the SOC chip into the first network on chip and the second network on chip according to the peripheral interfaces that need to be split in the network on chip of the SOC chip; Respectively define the bus used by each peripheral interface of the first network on chip and the second network on chip, the mounted peripheral modules, and the address space of each peripheral module; The address space of each peripheral module mounted on the second network on chip is mapped to the first AXI bus and the second AXI bus through the second network on chip.

[0007] Optionally, interconnecting the first network on chip and the second network on chip through a first AXI bus and a second AXI bus includes: An AXI conversion interface is configured on the first AXI bus and the second AXI bus respectively, and the AXI conversion interface is used to convert the AXI bus interface into an AXI stream interface; A high-speed physical layer interface is configured between the AXI conversion interface and the first AXI bus interface, and between the AXI conversion interface and the second AXI bus interface, respectively. The high-speed physical layer interface transmits data from the AXI stream interface based on the Aurora protocol.

[0008] Optionally, interconnecting the first network on chip and the second network on chip through a first AXI bus and a second AXI bus includes: interconnecting the first network on chip and the second network on chip through the first AXI bus and the second AXI bus, wherein the first AXI bus is configured as a master bus and the second AXI bus is configured as a slave bus; The method further comprises: In response to a communication instruction from a master device, determining an address space of the master device and an address space of a slave device, the slave device being a recipient of the communication instruction; According to the address space where the master device is located and the address space where the slave device is located, judging the network on chip mounted by the master device and the network on chip mounted by the slave device; When it is determined that the master device is mounted on the first network on chip and the slave device is mounted on the second network on chip, the communication instruction is sent to the slave device through the first AXI bus, and a response result of the communication instruction returned by the slave device is received through the first AXI bus; When it is determined that the master device is mounted on the second network on chip and the slave device is mounted on the first network on chip, the communication instruction is sent to the slave device through the second AXI bus, and a response result of the communication instruction returned by the slave device is received through the second AXI bus.

[0009] Optionally, the method further comprises: Merging the first network on chip and the second network on chip into a merged network on chip, and replacing the network on chip of the SOC chip with the merged network on chip; Performing consistency simulation verification on the merged on-chip network to check the response time, data integrity and data correctness of each peripheral module mounted on the merged on-chip network; When the merged network on chip passes the consistency simulation verification, it is determined that the functions of the first network on chip and the second network on chip are consistent with the network on chip of the SOC chip.

[0010] Optionally, the AXI conversion interface includes an asynchronous clock cross-domain module; the method includes: The clock domains of the first network on chip and the second network on chip are converted by the asynchronous clock cross-domain module, and the clock domains of the first network on chip and the second network on chip are asynchronous.

[0011] In a second aspect, an embodiment of the present disclosure provides a network on chip system, which is applied to execute a network on chip cutting method, and the system includes: At least two on-chip networks, the at least two on-chip networks include a first on-chip network and a second on-chip network, the first on-chip network and the second on-chip network are respectively mounted with respective peripheral modules via peripheral interfaces; The first on-chip network and the second on-chip network are interconnected through a first AXI bus and a second AXI bus. The first AXI bus interface and the second AXI bus interface are mutually inverse master-slave interfaces. The first AXI bus and the second AXI bus are buses to which the first AXI bus interface and the second AXI bus interface are respectively connected.

[0012] Optionally, an AXI conversion interface is configured on the first AXI bus and the second AXI bus respectively, and the AXI conversion interface is used to convert the AXI bus interface into an AXI stream interface; A high-speed physical layer interface is configured between the AXI conversion interface and the first AXI bus interface, and between the AXI conversion interface and the second AXI bus interface, respectively. The high-speed physical layer interface transmits data from the AXI stream interface based on the Aurora protocol.

[0013] Optionally, the first AXI bus is configured as a master bus, and the second AXI bus is configured as a slave bus; the address space of each peripheral module mounted on the second on-chip network is mapped to the first AXI bus and the second AXI bus through the second on-chip network; In response to a communication instruction from a master device, determining an address space of the master device and an address space of a slave device, the slave device being a recipient of the communication instruction; According to the address space where the master device is located and the address space where the slave device is located, judging the network on chip mounted by the master device and the network on chip mounted by the slave device; When it is determined that the master device is mounted on the first network on chip and the slave device is mounted on the second network on chip, the communication instruction is sent to the slave device through the first AXI bus, and a response result of the communication instruction returned by the slave device is received through the first AXI bus; When it is determined that the master device is mounted on the second network on chip and the slave device is mounted on the first network on chip, the communication instruction is sent to the slave device through the second AXI bus, and a response result of the communication instruction returned by the slave device is received through the second AXI bus.

[0014] Optionally, the AXI conversion interface includes an asynchronous clock cross-domain module; The clock domains of the first network on chip and the second network on chip are converted by the asynchronous clock cross-domain module, and the clock domains of the first network on chip and the second network on chip are asynchronous.

[0015] The technical solution provided by the embodiments of the present disclosure brings at least the following beneficial effects: The present disclosure effectively modularizes the complex logic structure by splitting the on-chip network of the SOC chip into at least two on-chip networks (i.e., the first on-chip network and the second on-chip network), so that each on-chip network can independently process its corresponding peripheral module, thereby avoiding the situation of processing too many logic resources on a single FPGA, reducing the resource occupation of the main FPGA, and improving the possibility of timing convergence. Secondly, the present disclosure integrates multiple peripheral interfaces on the second on-chip network into a first AXI bus interface and a second AXI bus interface, and interconnects the first on-chip network and the second on-chip network through these AXI bus interfaces, which not only reduces the number of interconnection interfaces between FPGAs, reduces the difficulty of logic cutting and reconnection, but also improves the overall performance and efficiency of the system. In summary, the cutting method disclosed in the present disclosure effectively overcomes the problems of resource shortage and timing convergence difficulties caused by complex SoC design in the related art, provides a more simple and efficient FPGA prototype verification technology solution, significantly improves the performance of multi-chip FPGA collaborative verification, shortens the chip verification cycle, and makes the on-chip system easier to expand. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 It is a schematic diagram of the overall logic of a complex SOC chip in the related technology; Figure 2 It is a schematic diagram of steps of a cutting method of a network on chip provided by an embodiment of the present disclosure; Figure 3 is a diagram of an on-chip network system architecture provided by an embodiment of the present disclosure; Figure 4 This is another on-chip network system architecture diagram provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure. In the description of the embodiments of the present disclosure, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In the present disclosure, "at least one" means one or more, and "multiple" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple. With the continuous advancement of integrated circuit technology, the complexity of SoC chips is increasing. Figure 1 It is a schematic diagram of the overall logic of a complex SOC chip in a related technology, such as Figure 1 As shown in the figure, peripheral modules including ARM core, DDR4, QSPI, SRAM, ROM, VGA, JEPG, EMAC, USB, UART, PCIE, I2C, GPIO, SD, eMMC, etc. are interconnected in a star shape through the NOC on-chip network. There may be multiple peripheral modules of each type, and the overall logic resource requirements are very large. This makes it difficult for even the largest FPGA (such as AMD VU19P) to accommodate the logic of the entire SOC chip. Due to resource constraints, the SOC chip logic must be divided into multiple parts and distributed on multiple FPGAs for prototype verification. This cutting not only needs to consider the allocation of logic modules, but also needs to deal with interface conversion and physical layer logic to ensure effective communication between each FPGA. When cutting, the logic resource occupancy of the main FPGA is still very tight, which brings great difficulties to timing convergence. Timing convergence refers to the process of ensuring that all signals reach a stable state within a specified time. Any tension in logic resources will affect the stability and reliability of timing.

[0019] Therefore, the present disclosure aims to optimize the use of logic resources and verification efficiency of large-scale system-on-chip (SoC) in the process of FPGA prototype verification. The core is to split the on-chip network of the SOC chip into at least two independent on-chip networks, corresponding to different peripheral modules, so as to achieve reasonable allocation and utilization of resources. By integrating the peripheral interface of the second on-chip network into an AXI bus interface and realizing the interconnection of the two on-chip networks through the AXI bus, the present disclosure not only reduces the number of interconnection interfaces between FPGAs, but also improves the efficiency and reliability of data transmission. In addition, the present disclosure also includes consistency simulation verification of the merged on-chip network to ensure functional consistency and data integrity. Through the scheme of the present disclosure, the limitations in the relevant technology are effectively solved, the performance of multi-chip FPGA collaborative verification is improved, the chip verification cycle is shortened, and an efficient and scalable solution is provided for the development and verification of complex SoCs. The technical scheme in the embodiment of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiment of the present disclosure. Obviously, the described embodiment is a part of the embodiment of the present disclosure, not all of the embodiments.

[0020] Figure 2 FIG. 1 is a schematic diagram of a method for cutting a network on a chip according to an embodiment of the present disclosure. Figure 2 As shown, the method includes: Step S101, splitting the on-chip network of the SOC chip into at least two on-chip networks, wherein the at least two on-chip networks include a first on-chip network and a second on-chip network, wherein the first on-chip network and the second on-chip network are respectively mounted with respective peripheral modules via peripheral interfaces; Step S102: Integrate multiple peripheral interfaces on the second network on chip into a first AXI bus interface and a second AXI bus interface, and interconnect the first network on chip and the second network on chip through a first AXI bus and a second AXI bus, wherein the first AXI bus interface and the second AXI bus interface are mutually inverse master-slave interfaces, and the first AXI bus and the second AXI bus are buses to which the first AXI bus interface and the second AXI bus interface are respectively connected.

[0021] In step S101, the on-chip network of the SOC chip is composed of a plurality of interconnected nodes, which may be processor cores, storage units or peripheral interfaces. Figure 3 This is a diagram of a network-on-chip system architecture provided by an embodiment of the present disclosure, see Figure 3, the present disclosure splits the on-chip network into at least two on-chip networks, such as NOC0, NOC1...NOCn, including the first on-chip network NOC0 and the second on-chip network NOC1, and these nodes can be allocated to different FPGAs to achieve more efficient resource utilization. The first on-chip network and the second on-chip network each include an independent interconnection structure, which can include hardware components such as routers and switches. Each on-chip network is connected to a specific peripheral module through a peripheral interface. For example, the first on-chip network can be connected to peripheral modules such as DD4 and QSPI, while the second on-chip network can be connected to peripheral modules such as ROM and VGA. The selection and configuration of these peripheral modules need to be optimized according to the system design requirements to ensure that each on-chip network can independently complete its function. In terms of software-level implementation, an unrestricted algorithm tool is first used to identify and determine the on-chip network part that needs to be split in the SOC chip, which involves analyzing the existing network topology structure, identifying the number and type of peripheral interfaces, and the dependencies between them. The algorithm is configured to divide the on-chip network into the first on-chip network and the second on-chip network according to the functional requirements and communication modes of the peripherals, ensuring that each on-chip network can operate independently and meet performance requirements. After the split, the peripheral interface of each on-chip network is configured, including defining the communication protocol and data format of each peripheral interface to ensure that they can interact correctly with their respective peripheral modules. In addition, the corresponding driver needs to be implemented to support the operation and management of the peripheral modules and ensure that data can be smoothly transmitted between the on-chip network and the peripherals.

[0022] In step S102, there are multiple peripheral interfaces on the second network on chip (NOC1), and these interfaces are connected to different peripheral modules. AXI (Advanced eXtensible Interface) is a high-performance, low-latency bus interface standard for connecting processors and peripherals. Integrating multiple peripheral interfaces on the second network on chip into a first AXI bus interface and a second AXI bus interface can simplify the communication protocol. Specifically, first identify all peripheral interfaces on the second network on chip (NOC1). Analyze the function, data transmission rate, protocol type, etc. of each peripheral interface to determine how they are integrated into the AXI bus interface. According to the AXI bus standard, design the first AXI bus interface and the second AXI bus interface, which may include read (Read) and write (Write) channels, and support multi-channel parallel transmission. According to the number and type of peripheral interfaces, determine how many AXI bus interfaces are required. The first AXI bus and the second AXI bus represent buses connected to the first AXI bus interface and the second AXI bus interface, respectively, and are responsible for transmitting data between the two networks on chip to ensure effective communication between the master device and the slave device. The first AXI bus interface and the second AXI bus interface are defined as mutually inverse master-slave interfaces. Specifically, the master interface (the first AXI bus interface) is responsible for initiating access requests to the peripheral modules in the second on-chip network, that is, the master interface can actively control the data transmission process. The slave interface (the second AXI bus interface) is responsible for responding to requests from the master interface, processing these requests and returning corresponding data. The subordinate relationship between the first AXI bus interface and the second AXI bus interface ensures the orderly transmission of data.

[0023] The present disclosure effectively modularizes the complex logic structure by splitting the on-chip network of the SOC chip into at least two on-chip networks (i.e., the first on-chip network and the second on-chip network), so that each on-chip network can independently process its corresponding peripheral module, thereby avoiding the situation of processing too many logic resources on a single FPGA, reducing the resource occupation of the main FPGA, and improving the possibility of timing convergence. Secondly, the present disclosure integrates multiple peripheral interfaces on the second on-chip network into the first AXI bus and the second AXI bus interface, and interconnects the first on-chip network and the second on-chip network through these AXI bus interfaces, which not only reduces the number of interconnection interfaces between FPGAs, reduces the difficulty of logic cutting and reconnection, but also improves the overall performance and efficiency of the system. In summary, the cutting method disclosed in the present disclosure effectively overcomes the problems of resource shortage and timing convergence difficulties caused by complex SoC design in the related art, provides a more simple and efficient FPGA prototype verification technology solution, significantly improves the performance of multi-chip FPGA collaborative verification, shortens the chip verification cycle, and makes the on-chip system easier to expand.

[0024] Exemplarily, splitting the on-chip network of the SOC chip into at least two on-chip networks includes: determining the peripheral interfaces that need to be split in the on-chip network of the SOC chip; splitting the on-chip network of the SOC chip into the first on-chip network and the second on-chip network according to the peripheral interfaces that need to be split in the on-chip network of the SOC chip; respectively defining the bus used by each peripheral interface of the first on-chip network and the second on-chip network, the mounted peripheral modules, and the address space of each peripheral module; mapping the address space of each peripheral module mounted on the second on-chip network to the first AXI bus and the second AXI bus through the second on-chip network.

[0025] In the specific implementation steps of the split, first, the on-chip network of the SOC chip is comprehensively analyzed to identify all peripheral interfaces, determine the functional requirements, data transmission rate and communication protocol of each peripheral interface, and analyze the dependencies between them to ensure that the peripheral interfaces can be reasonably allocated during the split to avoid unnecessary dependencies between different on-chip networks. As mentioned above, the present disclosure can use algorithmic tools (such as graph theory algorithms, clustering algorithms, etc.) to determine the on-chip network parts that need to be split in the SOC chip.

[0026] Then, according to the identified peripheral interfaces, the on-chip network of the SOC chip is split into at least two parts, such as NOC0 and NOC1. Each on-chip network will contain a set of interconnected nodes, which can be processor cores, storage units, or peripheral interfaces. Each on-chip network (NOC0 and NOC1) has an independent interconnection structure, including hardware components such as routers and switches, so that they can operate independently. Define the peripheral interface for each on-chip network, including communication protocols (such as AXI, APB, etc.), data formats, and transmission rates. These definitions will ensure that peripheral modules can interact correctly with the on-chip network. Determine the peripheral modules mounted on each on-chip network. For example, NOC0 can be connected to peripheral modules such as DDR4, QSPI, etc., while NOC1 can be connected to peripheral modules such as ROM, VGA, etc.

[0027] Finally, allocate address space for each peripheral module to ensure that their addresses in the on-chip network do not conflict. The address space of each peripheral module needs to be optimized according to the on-chip system design requirements to ensure access efficiency. The address space of each peripheral module mounted on the second on-chip network (NOC1) is mapped to the first AXI bus and the second AXI bus through the second on-chip network. According to the mapping relationship, configure the address mapping table of the AXI bus interface to ensure that the processor or other master device can correctly access the peripheral modules on NOC1 through the AXI bus.

[0028] Through the above steps, the on-chip network of the SOC chip is effectively split into at least two on-chip networks (including NOC0 and NOC1), and the peripheral interfaces, mounted peripheral modules and address spaces of each on-chip network are defined and configured in detail. Finally, effective data transmission and access are achieved through the first AXI bus interface and the second AXI bus interface. This splitting method not only improves the utilization efficiency of resources, but also simplifies the design and verification process.

[0029] Exemplarily, interconnecting the first on-chip network and the second on-chip network through a first AXI bus and a second AXI bus includes: configuring an AXI conversion interface on the first AXI bus and the second AXI bus, respectively, and the AXI conversion interface is used to convert the AXI bus interface into an AXI stream interface; between the AXI conversion interface and the first AXI bus interface, and between the AXI conversion interface and the second AXI bus interface, respectively, a high-speed physical layer interface is configured, and the high-speed physical layer interface transmits data from the AXI stream interface based on the Aurora protocol.

[0030] Figure 4 is another on-chip network system architecture diagram provided by an embodiment of the present disclosure, such as Figure 4 As shown, the first network on chip (NOC0) and the second network on chip (NOC1) are interconnected through the first AXI bus and the second AXI bus. Specifically, the first AXI bus and the second AXI bus can support read (Read) and write (Write) operations, allowing data to be transmitted bidirectionally between the two networks on chip. The AXI conversion interface is configured on the first AXI bus and the second AXI bus, respectively, for converting the AXI bus interface into an AXI stream interface, and the AXI stream interface is an interface for high-throughput data transmission, suitable for processing data streams. Between the AXI bus interface and the AXI stream interface, an AXI conversion interface is configured, which is responsible for converting the request from the AXI bus into the AXI stream format, so that the data can maintain consistency and efficiency in high-speed transmission. Between the AXI conversion interface and the first AXI bus interface, and between the AXI conversion interface and the second AXI bus interface, a high-speed physical layer interface is configured, which is responsible for converting the data of the AXI stream interface into a format suitable for the Aurora protocol for transmission at the physical layer.

[0031] When the first network on chip needs to send data to the second network on chip, the data first enters the AXI conversion interface through the first AXI bus interface. The AXI conversion interface converts the data into the AXI stream format and sends it to the high-speed physical layer interface. The high-speed physical layer interface converts the AXI stream data into the Aurora protocol format and transmits the data to the second network on chip through a physical connection (such as optical fiber or high-speed cable). The second network on chip receives the data stream from the Aurora protocol and processes it through the corresponding AXI stream interface. The data is converted back to the AXI bus format in the second network on chip so that it can interact with other peripheral modules on the second network on chip. During the entire data transmission process, the configuration of the AXI conversion interface and the high-speed physical layer interface ensures the consistency and integrity of the data and avoids data loss or errors that may occur during the format conversion process. By using the AXI stream interface and the Aurora protocol, high-throughput data transmission is achieved, which significantly improves the data exchange efficiency between the first network on chip and the second network on chip and reduces latency.

[0032] By interconnecting the first network on chip (NOC0) and the second network on chip (NOC1) through the first AXI bus and the second AXI bus interface, and configuring the AXI conversion interface and the high-speed physical layer interface, efficient and stable data transmission can be achieved. This not only improves the overall performance of the system, but also ensures data consistency and transmission efficiency between different FPGAs, providing strong support for the prototype verification of SOC chips.

[0033] Exemplarily, interconnecting the first on-chip network and the second on-chip network through the first AXI bus and the second AXI bus includes: interconnecting the first on-chip network and the second on-chip network through the first AXI bus and the second AXI bus, wherein the first AXI bus is configured as a master bus and the second AXI bus is configured as a slave bus.

[0034] In the disclosed embodiment, the first AXI bus interface and the second AXI bus interface are used to connect the first network on chip and the second network on chip. The first AXI bus accessed by the first AXI bus interface is configured as a master bus, where the master bus refers to the first AXI bus as the leader of control and data transmission. The master bus is responsible for initiating data transmission requests and controlling the flow of data. In the AXI protocol, a master device (such as a processor or a main controller) issues read and write requests through the master bus and controls the transmission of data. The second AXI bus accessed by the second AXI bus interface is configured as a slave bus, where the slave bus refers to the second AXI bus as a passive receiver, responding to requests from the master bus, used to connect peripherals or other modules, receiving data requests issued by the master bus, and providing corresponding data according to the request. The first network on chip and the second network on chip are interconnected through the AXI bus interface to form a complete data transmission channel, so that the master device on the first network on chip can effectively communicate with the peripheral device on the second network on chip. Through this master-slave relationship, data read and write operations can be realized. Under the above configuration, when the master device of the first network on chip needs to access the peripheral device of the second network on chip, it sends a request through the first AXI bus, and the slave device (NOC1) of the second AXI bus responds to the request and performs corresponding data transmission.

[0035] Exemplarily, the method also includes: in response to a communication instruction from a master device, determining an address space of the master device and an address space of a slave device, the slave device being the recipient of the communication instruction; judging the network on chip mounted on the master device and the network on chip mounted on the slave device according to the address space of the master device and the address space of the slave device; when it is determined that the master device is mounted on the first network on chip and the slave device is mounted on the second network on chip, sending the communication instruction to the slave device via the first AXI bus, and receiving a response result of the communication instruction returned by the slave device via the first AXI bus; when it is determined that the master device is mounted on the second network on chip and the slave device is mounted on the first network on chip, sending the communication instruction to the slave device via the second AXI bus, and receiving a response result of the communication instruction returned by the slave device via the second AXI bus.

[0036] When the master device issues a communication instruction, it responds to the instruction. The communication instruction includes a request to read or write data. First, determine the address space of the master device and the address space of the slave device. The address space refers to the memory address range available for the device in the system. The address space of the master device and the slave device must be correctly configured to ensure effective communication. The slave device is the object that receives the communication instruction sent by the master device, which can be a peripheral or other module. According to the address space of the master device and the slave device, determine which on-chip network the master device and the slave device are mounted on, which may be the first on-chip network or the second on-chip network.

[0037] When it is determined that the master device is mounted on the first on-chip network (NOC0) and the slave device is mounted on the second on-chip network (NOC1), the master device sends a communication instruction to the slave device through the first AXI bus as the main bus. Afterwards, the master device also receives the response result returned by the slave device through the first AXI bus. In this case, the main bus is responsible for the communication between the master device and the slave device.

[0038] If the master device is mounted on the second on-chip network (NOC1) and the slave device is mounted on the first on-chip network (NOC0), the master device needs to send communication instructions to the slave device through the second AXI bus as the slave bus, and receive the response result through the second AXI bus. In this case, the slave bus is responsible for the communication between the master and the slave. In both cases, the sending and responding process of communication instructions ensures the correct transmission of data. After the master device issues a request, the slave device performs the corresponding operation according to the request and returns the result to the master device.

[0039] In the disclosed embodiments, under the AXI bus protocol, the communication process between the master device and the slave device includes how to respond to communication instructions, determine the address space, judge the mounting status of the on-chip network, and transmit data through the master bus or the slave bus in different situations, thereby ensuring effective communication between the master device and the slave device and optimizing data reading and writing operations.

[0040] Exemplarily, the method also includes: merging the first network on chip and the second network on chip into a merged network on chip, and replacing the network on chip of the SOC chip with the merged network on chip; performing consistency simulation verification on the merged network on chip, checking the response time, data integrity and data correctness of each peripheral module mounted on the merged network on chip; and when the merged network on chip passes the consistency simulation verification, determining that the functions of the first network on chip and the second network on chip are consistent with those of the network on chip of the SOC chip.

[0041] The two split on-chip networks (NOC0 and NOC1) mentioned above are integrated into a new merged on-chip network to facilitate subsequent verification and testing to ensure that the on-chip network of the entire SOC chip can work properly. The merged on-chip network will replace the on-chip network in the original SOC chip. That is, during the verification process, the merged network structure will be used for functional testing and performance evaluation.

[0042] After the merged on-chip network is created and replaced, consistency simulation verification is performed to ensure that the merged network is functionally consistent with the on-chip network of the original SOC chip. During the consistency simulation verification process, the performance indicators of each peripheral module mounted in the merged on-chip network are checked, including response time, data integrity, and data correctness. Specifically, the response time is the response speed of the peripheral module to the request of the master device. Data integrity is to ensure that the data is not lost or damaged during the data transmission process. Data correctness is to ensure that the received data is consistent with the sent data and there are no errors. If the merged on-chip network passes the consistency simulation verification, it means that it meets the design requirements in terms of function and performance. Finally, it is confirmed that the merged on-chip network is functionally consistent with the original SOC chip on-chip network. That is, despite the splitting and merging, the overall function of the system is not affected and can perform the expected operations normally.

[0043] The present disclosure combines the first on-chip network and the second on-chip network into a combined on-chip network, and performs consistency simulation verification on the combined on-chip network. By checking the response time, data integrity and data correctness of the peripheral modules, it is ensured that the combined network is functionally consistent with the on-chip network of the original SOC chip.

[0044] Exemplarily, the AXI conversion interface includes an asynchronous clock cross-domain module; the method includes: converting the clock domains of the first network on chip and the second network on chip through the asynchronous clock cross-domain module, and the clock domains of the first network on chip and the second network on chip are asynchronous.

[0045] An asynchronous clock cross-domain module is configured in the AXI conversion interface of the embodiment of the present disclosure, and its function is to process signals from different clock domains. Since the clock domains of the first network on chip and the second network on chip are asynchronous, it means that their clock signals do not share the same clock source, and there may be differences in frequency and phase. The asynchronous clock cross-domain module can effectively manage the signal transmission between such clock domains, and ensure the stable and reliable transmission of data between different clock domains. When the data is transmitted from the first network on chip to the second network on chip, the asynchronous clock cross-domain module processes the signal to adapt to the clock domain of the target network on chip. Specifically, in the asynchronous clock cross-domain module, the signal is sampled at the edge of the receiving clock, and by using dual triggers or FIFO (first in, first out) buffer technology, it is ensured that the data will not be lost or errors will occur during the clock domain conversion. The processed data will be safely transmitted to the target network on chip. Since the clock domain is asynchronous, directly transmitting the signal from one clock domain to another clock domain may cause data inconsistency, loss or error. Therefore, the asynchronous clock cross-domain module can effectively solve these problems, process data interaction from different networks on chip, and avoid potential problems caused by clock asynchrony.

[0046] Exemplarily, the method also includes: during the on-chip network splitting process of the SOC chip, determining the communication mode and data flow of the peripheral modules connected to the first on-chip network and the second on-chip network respectively based on a machine learning algorithm, and dynamically optimizing the division of the first on-chip network and the second on-chip network.

[0047] In the traditional SOC chip on-chip network cutting method, the division of the on-chip network is usually static, based on the designer's experience and the preset peripheral module connection method, which may cause bandwidth bottlenecks or delay problems in some on-chip networks during use, especially in complex systems, where the communication mode between peripheral modules may change with the load changes during operation. The present disclosure proposes an improved cutting method, which introduces a machine learning algorithm to analyze the communication mode and data flow of the peripheral modules, dynamically optimize the division of the on-chip network, and can adapt to the load changes of the system in real time, thereby improving the overall performance of the on-chip network.

[0048] During the operation of the SOC chip, the communication frequency, data flow, and delay between each peripheral module are monitored and recorded. These data will be used as input for the machine learning algorithm. Using the collected data, the machine learning model configured based on the machine learning algorithm is trained to identify the communication mode and data flow characteristics between the peripheral modules. Optionally, supervised learning or unsupervised learning methods can be used to select appropriate machine learning algorithms (such as decision trees, random forests, neural networks, etc.) according to specific needs. After the training is completed, the machine learning model can predict which peripheral modules have higher communication requirements under different load conditions. Based on the prediction of the machine learning model, the division of the first on-chip network and the second on-chip network is dynamically adjusted to achieve higher bandwidth utilization. For example, if the communication frequency of a peripheral module increases significantly within a specific time period, it is divided into a network on chip with higher bandwidth, and vice versa. During the operation of the SOC chip, the communication of the peripheral modules is continuously monitored, and the real-time data is fed back to the machine learning model for online learning and adjustment, which can ensure that the division of the on-chip network always adapts to the current system requirements.

[0049] The disclosed embodiment provides a method for cutting network on chip based on machine learning, which aims to improve the bandwidth utilization of SOC chips and reduce latency by dynamically optimizing the division of network on chip. It not only enhances the adaptive ability of the system, but also provides a new solution for the performance optimization of complex systems.

[0050] See also Figure 3 The embodiment of the present disclosure provides an on-chip network system, which is used to execute a method for cutting an on-chip network. The system includes: at least two on-chip networks, the at least two on-chip networks include a first on-chip network and a second on-chip network, the first on-chip network and the second on-chip network respectively mount their own peripheral modules through peripheral interfaces; the first on-chip network and the second on-chip network are interconnected through a first AXI bus and a second AXI bus, the first AXI bus interface and the second AXI bus interface are mutually inverse master-slave interfaces, and the first AXI bus and the second AXI bus are buses to which the first AXI bus interface and the second AXI bus interface are respectively connected.

[0051] In the disclosed embodiment, the on-chip network system includes at least two on-chip networks, namely a first on-chip network and a second on-chip network. The first on-chip network and the second on-chip network are independent networks, which are responsible for different functions or tasks respectively. The first on-chip network or the second on-chip network is responsible for communicating with the peripheral modules mounted thereon, and the peripheral modules can be various functional modules, such as memory, input and output devices, processors, etc. Each on-chip network is connected to the peripheral modules mounted thereon through a peripheral interface, and the peripheral interface is used to transmit data and control signals to ensure effective communication between the on-chip network and the peripherals. The peripheral interface can be a standardized interface, such as AXI, I2C, SPI, etc., depending on the type and requirements of the peripherals.

[0052] The first AXI bus and the second AXI bus represent buses connected to the first AXI bus interface and the second AXI bus interface, respectively, and are responsible for transmitting data between the two on-chip networks to ensure effective communication between the master device and the slave device. The first AXI bus interface and the second AXI bus interface are defined as mutually inverse master-slave interfaces. Specifically, the master interface (the first AXI bus interface) is responsible for initiating access requests to the peripheral modules in the second on-chip network, that is, the master interface can actively control the data transmission process. The slave interface (the second AXI bus interface) is responsible for responding to requests from the master interface, processing these requests and returning the corresponding data. The subordinate relationship between the first AXI bus interface and the second AXI bus interface ensures the orderly transmission of data.

[0053] Exemplarily, an AXI conversion interface is configured on the first AXI bus and the second AXI bus, respectively, and the AXI conversion interface is used to convert the AXI bus interface into an AXI stream interface; a high-speed physical layer interface is configured between the AXI conversion interface and the first AXI bus interface, and between the AXI conversion interface and the second AXI bus interface, respectively, and the high-speed physical layer interface transmits data from the AXI stream interface based on the Aurora protocol.

[0054] like Figure 4As shown, the first network on chip (NOC0) and the second network on chip (NOC1) are interconnected through the first AXI bus and the second AXI bus interface. Specifically, the first AXI bus and the second AXI bus interface are defined to connect the first network on chip and the second network on chip. Each AXI bus interface can support read (Read) and write (Write) operations, allowing data to be transmitted bidirectionally between the two networks on chip. The main function of the AXI conversion interface is to convert the AXI bus interface into an AXI stream interface, which is an interface for high-throughput data transmission and is suitable for data stream processing. The AXI conversion interface is used to convert the AXI bus interface into an AXI stream interface, which is an interface for high-throughput data transmission and is suitable for data stream processing. Between the AXI bus interface and the AXI stream interface, an AXI conversion interface is configured to convert the request from the AXI bus into the AXI stream format, so that the data can maintain consistency and efficiency in high-speed transmission. Between the AXI conversion interface and the AXI stream interface, a high-speed physical layer interface is configured to convert the data of the AXI stream interface into a format suitable for the Aurora protocol for transmission at the physical layer.

[0055] When the first network-on-chip needs to send data to the second network-on-chip, the data first enters the AXI conversion interface through the AXI bus interface. The AXI conversion interface converts the data into the AXI stream format and sends it to the high-speed physical layer interface. The high-speed physical layer interface converts the AXI stream data into the Aurora protocol format and transmits the data to the second network-on-chip through a physical connection (such as optical fiber or high-speed cable). The second network-on-chip receives the data stream from the Aurora protocol and processes it through the corresponding interface (such as the AXI stream interface). The data is converted back to the AXI bus format in the second network-on-chip so that it can interact with other peripheral modules on the second network-on-chip. During the entire data transmission process, the configuration of the AXI conversion interface and the high-speed physical layer interface ensures the consistency and integrity of the data and avoids data loss or errors that may occur during the format conversion process. By using the AXI stream interface and the Aurora protocol, high-throughput data transmission is achieved, which significantly improves the data exchange efficiency between the first network-on-chip and the second network-on-chip and reduces latency.

[0056] The first network on chip (NOC0) and the second network on chip (NOC1) are interconnected through the first AXI bus and the second AXI bus interface, and the AXI conversion interface and the high-speed physical layer interface are configured to achieve efficient and stable data transmission. This not only improves the overall performance of the system, but also ensures data consistency and transmission efficiency between different FPGAs, providing strong support for the prototype verification of SOC chips.

[0057] Exemplarily, the first AXI bus is configured as a master bus, and the second AXI bus is configured as a slave bus; the address space of each peripheral module mounted on the second on-chip network is mapped to the first AXI bus and the second AXI bus through the second on-chip network; in response to a communication instruction from a master device, the address space of the master device and the address space of the slave device are determined, and the slave device is the recipient of the communication instruction; according to the address space of the master device and the address space of the slave device, the on-chip network mounted on the master device and the on-chip network mounted on the slave device are mapped to the first AXI bus and the second AXI bus; The method comprises the steps of: determining whether the master device is mounted on the first network on chip and the slave device is mounted on the second network on chip, sending the communication instruction to the slave device through the first AXI bus, and receiving a response result of the communication instruction returned by the slave device through the first AXI bus; determining whether the master device is mounted on the second network on chip and the slave device is mounted on the first network on chip, sending the communication instruction to the slave device through the second AXI bus, and receiving a response result of the communication instruction returned by the slave device through the second AXI bus.

[0058] In the disclosed embodiment, the first AXI bus interface and the second AXI bus interface are used to connect the first network on chip and the second network on chip, respectively. The first AXI bus accessed by the first AXI bus interface is configured as a master bus, where the master bus refers to the first AXI bus as the leader of control and data transmission. The master bus is responsible for initiating data transmission requests and controlling the flow of data. In the AXI protocol, a master device (such as a processor or a main controller) issues read and write requests through the master bus and controls the transmission of data. The second AXI bus accessed by the second AXI bus interface is configured as a slave bus, where the slave bus refers to the second AXI bus as a passive receiver, responding to requests from the master bus, used to connect peripherals or other modules, receiving data requests issued by the master bus, and providing corresponding data according to the request. The first network on chip and the second network on chip are interconnected through the AXI bus interface to form a complete data transmission channel, so that the master device on NOC0 can effectively communicate with the peripherals on NOC1. Through this master-slave relationship, data read and write operations can be realized. Under the above configuration, when the master device of the first network on chip needs to access the peripheral device of the second network on chip, it sends a request through the first AXI bus, and the slave device (NOC1) of the second AXI bus responds to the request and performs corresponding data transmission.

[0059] When the master device issues a communication instruction, it responds to the instruction. The communication instruction includes a request to read or write data. First, determine the address space of the master device and the address space of the slave device. The address space refers to the memory address range available for the device in the system. The address space of the master device and the slave device must be correctly configured to ensure effective communication. The slave device is the object that receives the communication instruction sent by the master device, which can be a peripheral or other module. According to the address space of the master device and the slave device, determine which on-chip network the master device and the slave device are mounted on, which may be the first on-chip network or the second on-chip network.

[0060] When it is determined that the master device is mounted on the first on-chip network (NOC0) and the slave device is mounted on the second on-chip network (NOC1), the master device sends a communication instruction to the slave device through the first AXI bus as the main bus. Afterwards, the master device also receives the response result returned by the slave device through the first AXI bus. In this case, the main bus is responsible for the communication between the master device and the slave device.

[0061] If the master device is mounted on the second on-chip network (NOC1) and the slave device is mounted on the first on-chip network (NOC0), the master device needs to send communication instructions to the slave device through the second AXI bus as the slave bus, and receive the response result through the second AXI bus. In this case, the slave bus is responsible for the communication between the master and the slave. In both cases, the sending and responding process of communication instructions ensures the correct transmission of data. After the master device issues a request, the slave device performs the corresponding operation according to the request and returns the result to the master device.

[0062] In the disclosed embodiments, under the AXI bus protocol, the communication process between the master device and the slave device includes how to respond to communication instructions, determine the address space, judge the mounting status of the on-chip network, and transmit data through the master bus or the slave bus in different situations, thereby ensuring effective communication between the master device and the slave device and optimizing data reading and writing operations.

[0063] Exemplarily, the AXI conversion interface includes an asynchronous clock cross-domain module; through the asynchronous clock cross-domain module, the clock domains of the first network on chip and the second network on chip are converted, and the clock domains of the first network on chip and the second network on chip are asynchronous.

[0064] An asynchronous clock cross-domain module is configured in the AXI conversion interface of the embodiment of the present disclosure, and its function is to process signals from different clock domains. Since the clock domains of the first network on chip and the second network on chip are asynchronous, it means that their clock signals do not share the same clock source, and there may be differences in frequency and phase. The asynchronous clock cross-domain module can effectively manage the signal transmission between such clock domains, and ensure the stable and reliable transmission of data between different clock domains. When the data is transmitted from the first network on chip to the second network on chip, the asynchronous clock cross-domain module processes the signal to adapt to the clock domain of the target network on chip. Specifically, in the asynchronous clock cross-domain module, the signal is sampled at the edge of the receiving clock, and by using dual triggers or FIFO (first in, first out) buffer technology, it is ensured that the data will not be lost or errors will occur during the clock domain conversion. The processed data will be safely transmitted to the target network on chip. Since the clock domain is asynchronous, directly transmitting the signal from one clock domain to another clock domain may cause data inconsistency, loss or error. Therefore, the asynchronous clock cross-domain module can effectively solve these problems, process data interaction from different networks on chip, and avoid potential problems caused by clock asynchrony.

[0065] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, electronic devices, and computer-readable media. Therefore, the embodiments of the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present disclosure may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0066] The embodiments of the present disclosure are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing terminal device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded into a computer or other programmable data processing terminal device, so that a series of operation steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable terminal device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0067] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0068] Finally, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "include..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements. The above is a detailed introduction to a network-on-chip cutting method and system provided by the present disclosure. The principles and implementation methods of the present disclosure are explained in this article using specific examples. The description of the above embodiments is only used to help understand the method and its core idea of ​​the present disclosure; at the same time, for those of ordinary skill in the art, according to the idea of ​​the present disclosure, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

Claims

1. A method for cutting a network on chip, characterized in that: The method comprises: Splitting the on-chip network of the SOC chip into at least two on-chip networks, wherein the at least two on-chip networks include a first on-chip network and a second on-chip network, wherein the first on-chip network and the second on-chip network are respectively mounted with respective peripheral modules through peripheral interfaces; The multiple peripheral interfaces on the second network on chip are integrated into a first AXI bus interface and a second AXI bus interface, and the first network on chip and the second network on chip are interconnected through a first AXI bus and a second AXI bus, the first AXI bus interface and the second AXI bus interface are mutually inverse master-slave interfaces, and the first AXI bus and the second AXI bus are buses to which the first AXI bus interface and the second AXI bus interface are respectively connected.

2. The method according to claim 1, characterized in that The step of splitting the on-chip network of the SOC chip into at least two on-chip networks includes: In the on-chip network of the SOC chip, determining the peripheral interfaces that need to be split; Splitting the network on chip of the SOC chip into the first network on chip and the second network on chip according to the peripheral interfaces that need to be split in the network on chip of the SOC chip; Respectively define the bus used by each peripheral interface of the first network on chip and the second network on chip, the mounted peripheral modules, and the address space of each peripheral module; The address space of each peripheral module mounted on the second network on chip is mapped to the first AXI bus and the second AXI bus through the second network on chip.

3. The method according to claim 1, characterized in that The interconnecting the first network on chip and the second network on chip through a first AXI bus and a second AXI bus comprises: An AXI conversion interface is configured on the first AXI bus and the second AXI bus respectively, and the AXI conversion interface is used to convert the AXI bus interface into an AXI stream interface; A high-speed physical layer interface is configured between the AXI conversion interface and the first AXI bus interface, and between the AXI conversion interface and the second AXI bus interface, respectively. The high-speed physical layer interface transmits data from the AXI stream interface based on the Aurora protocol.

4. The method according to claim 1, characterized in that: The interconnecting the first network on chip and the second network on chip through a first AXI bus and a second AXI bus comprises: interconnecting the first network on chip and the second network on chip through the first AXI bus and the second AXI bus, wherein the first AXI bus is configured as a master bus and the second AXI bus is configured as a slave bus; The method further comprises: In response to a communication instruction from a master device, determining an address space of the master device and an address space of a slave device, the slave device being a recipient of the communication instruction; According to the address space where the master device is located and the address space where the slave device is located, judging the network on chip mounted by the master device and the network on chip mounted by the slave device; When it is determined that the master device is mounted on the first network on chip and the slave device is mounted on the second network on chip, the communication instruction is sent to the slave device through the first AXI bus, and a response result of the communication instruction returned by the slave device is received through the first AXI bus; When it is determined that the master device is mounted on the second network on chip and the slave device is mounted on the first network on chip, the communication instruction is sent to the slave device through the second AXI bus, and a response result of the communication instruction returned by the slave device is received through the second AXI bus.

5. The method according to claim 1, characterized in that The method further comprises: Merging the first network on chip and the second network on chip into a merged network on chip, and replacing the network on chip of the SOC chip with the merged network on chip; Performing consistency simulation verification on the merged on-chip network to check the response time, data integrity and data correctness of each peripheral module mounted on the merged on-chip network; When the merged on-chip network passes the consistency simulation verification, it is determined that the functions of the first on-chip network and the second on-chip network are consistent with the on-chip network of the SOC chip.

6. The method according to claim 3, characterized in that The AXI conversion interface includes an asynchronous clock cross-domain module; the method includes: The clock domains of the first network on chip and the second network on chip are converted by the asynchronous clock cross-domain module, and the clock domains of the first network on chip and the second network on chip are asynchronous.

7. A network-on-chip system, characterized in that: Applied to perform the method according to any one of claims 1 to 6, the system comprising: At least two on-chip networks, the at least two on-chip networks include a first on-chip network and a second on-chip network, the first on-chip network and the second on-chip network are respectively mounted with respective peripheral modules via peripheral interfaces; The first on-chip network and the second on-chip network are interconnected through a first AXI bus and a second AXI bus. The first AXI bus interface and the second AXI bus interface are mutually inverse master-slave interfaces. The first AXI bus and the second AXI bus are buses to which the first AXI bus interface and the second AXI bus interface are respectively connected.

8. The system according to claim 7, characterized in that An AXI conversion interface is configured on the first AXI bus and the second AXI bus respectively, and the AXI conversion interface is used to convert the AXI bus interface into an AXI stream interface; A high-speed physical layer interface is configured between the AXI conversion interface and the first AXI bus interface, and between the AXI conversion interface and the second AXI bus interface, respectively. The high-speed physical layer interface transmits data from the AXI stream interface based on the Aurora protocol.

9. The system according to claim 7, characterized in that The first AXI bus is configured as a master bus, and the second AXI bus is configured as a slave bus; the address space of each peripheral module mounted on the second on-chip network is mapped to the first AXI bus and the second AXI bus through the second on-chip network; In response to a communication instruction from a master device, determining an address space of the master device and an address space of a slave device, the slave device being a recipient of the communication instruction; According to the address space where the master device is located and the address space where the slave device is located, judging the network on chip mounted by the master device and the network on chip mounted by the slave device; When it is determined that the master device is mounted on the first network on chip and the slave device is mounted on the second network on chip, the communication instruction is sent to the slave device through the first AXI bus, and a response result of the communication instruction returned by the slave device is received through the first AXI bus; When it is determined that the master device is mounted on the second network on chip and the slave device is mounted on the first network on chip, the communication instruction is sent to the slave device through the second AXI bus, and a response result of the communication instruction returned by the slave device is received through the second AXI bus.

10. The system according to claim 8, characterized in that The AXI conversion interface includes an asynchronous clock cross-domain module; The clock domains of the first network on chip and the second network on chip are converted by the asynchronous clock cross-domain module, and the clock domains of the first network on chip and the second network on chip are asynchronous.

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