Methods and apparatus for generating circuit configuration files, storage media, and electronic devices.

Abstract

Embodiments of the present application provide a circuit configuration file generation method and device, a storage medium and an electronic device. The method comprises: generating a configuration requirement file based on an obtained circuit configuration requirement; traversing the configuration requirement file to determine M target circuit functions from the requirement configuration file; searching for a circuit template matching each target circuit function to obtain M circuit templates; calling each circuit template to generate a circuit configuration file corresponding to each target circuit function to obtain M circuit configuration files; and integrating the M circuit configuration files to obtain a target circuit configuration file. Through the present application, the problem that a control circuit cannot be flexibly generated in the related art can be solved, a circuit configuration file is generated based on a circuit configuration requirement, and the effect of flexibly generating a control circuit is achieved.

Description

Technical Field

[0001] This application relates to the field of computers, and more specifically, to a method and apparatus for generating circuit configuration files, a storage medium, and an electronic device. Background Technology

[0002] The Quad Serial Peripheral Interface (QSPI) is a high-speed serial communication interface typically used to connect flash memory and other serial peripherals requiring high bandwidth. QSPI controllers are commonly used to connect high-performance non-volatile flash memory (NOR Flash Memory). Common operating modes of QSPI controllers include direct read mode, indirect read / write mode, and polling read mode. In practical applications, only some of the QSPI controller's operating modes may be used, resulting in redundant modes. It's also possible that the QSPI controller simply doesn't have the required operating modes. Furthermore, while a single QSPI controller can only connect to one NOR Flash memory, situations may arise where multiple NOR Flash memories are needed, leading to a situation where the QSPI controller's control circuitry cannot meet the actual requirements. Summary of the Invention

[0003] This application provides a method and apparatus for generating circuit configuration files, a storage medium, and an electronic device, to at least solve the problem of the inability to flexibly generate control circuits in related technologies.

[0004] According to one embodiment of this application, a method for generating a circuit configuration file is provided. The method includes: generating a configuration requirement file based on acquired circuit configuration requirements, wherein the configuration requirement file includes N circuit functions required and the circuit configuration status of each circuit function, where N is a natural number greater than or equal to 1; traversing the configuration requirement file to determine M target circuit functions from the requirement file, wherein the circuit configuration status of the M target circuit functions is a allowed configuration status, where M is a natural number less than or equal to N; searching for a circuit template matching each target circuit function to obtain M circuit templates; calling each circuit template to generate a circuit configuration file corresponding to each target circuit function to obtain M circuit configuration files, wherein the circuit configuration files are used to configure the circuit implementing the target circuit function; and integrating the M circuit configuration files to obtain a target circuit configuration file, wherein the target circuit configuration file is used to configure the target circuit responding to the circuit configuration requirements.

[0005] In an exemplary embodiment, a configuration requirement file is generated based on the acquired circuit configuration requirements, including: obtaining the required circuit operating mode, circuit chip select information, and circuit clock information from the circuit configuration requirements, wherein the circuit operating mode is used to indicate the read / write method between the controller and external storage devices in the required circuit, the circuit chip select information is used to indicate the required number of external storage devices, and the circuit clock information is used to indicate the requirement for cross-clock domain signal conversion function; determining the circuit operating mode, the circuit chip select information, and the circuit clock information as N circuit functions, and determining the circuit configuration state of each circuit function; integrating the N circuit functions and the circuit configuration state of each circuit function to generate the configuration requirement file.

[0006] In one exemplary embodiment, traversing the configuration requirement file to determine M target circuit functions from the requirement file includes: traversing the circuit configuration state of each circuit function in the configuration requirement file to select circuit functions whose circuit configuration state is allowed to be configured from N circuit functions, thereby obtaining M target circuit functions.

[0007] In one exemplary embodiment, each of the aforementioned circuit templates is invoked to generate a circuit configuration file corresponding to each of the aforementioned target circuit functions, resulting in M ​​such circuit configuration files, including at least one of the following: If the M aforementioned target circuit functions include a conversion function, a conversion function circuit template is invoked to generate a conversion function circuit configuration file that implements the conversion function, wherein the conversion function circuit configuration file includes a description of the conversion of cross-clock domain signals of the required circuit, and the conversion function circuit configuration file is used to construct a circuit that implements the cross-clock domain signal conversion function; If the M aforementioned target circuit functions include a clock function, a clock generation function circuit template is invoked to generate a clock generation function that implements the clock function. The configuration file for the clock generation function circuit includes a description of how the core clock in the required circuit is divided according to the clock division coefficient in the clock configuration requirements to obtain the clock signal of the serial external memory. This configuration file is used to construct the circuit that implements the clock function. If the M target circuit functions include a polling read function, a first register configuration function circuit template is called to generate a first register configuration circuit file that implements the polling read function. This first register configuration circuit file includes a description of the first save operation for implementing the circuit polling read status information and the external storage device polling read status information. The circuit file is used to construct the circuit that implements the polling read function described above. If the M target circuit functions include a direct read function, the second register configuration function circuit template is called to generate a second register configuration circuit file that implements the direct read function. This second register configuration circuit file includes description information for the second save operation used to implement the circuit's direct read status information and the external storage device's direct read status information. This second register configuration circuit file is used to construct the circuit that implements the direct read function. If the M target circuit functions include an indirect read / write function, the third register configuration function circuit template is called to generate a third register configuration circuit file that implements the indirect read / write function. The third register configuration circuit file includes description information for implementing the third save operation of indirect read / write status information of the circuit and indirect read / write status information of the external storage device. The third register configuration circuit file is used to construct the circuit that implements the indirect read / write function. When the M target circuit functions include logic control functions, the logic control function circuit template is called to generate a logic control function circuit configuration file that implements the logic control function. The logic control function circuit configuration file includes description information for generating the chip select signal according to the chip select information in the target circuit function and the interface protocol of the serial external memory. The logic control function circuit configuration file is used to construct the circuit that implements the logic control function.

[0008] In one exemplary embodiment, each of the aforementioned circuit templates is invoked to generate a circuit configuration file corresponding to each of the aforementioned target circuit functions, resulting in M ​​such circuit configuration files, including at least one of the following: If the M aforementioned target circuit functions include a chip select signal function, a chip select signal function circuit template is invoked to generate a chip select signal function circuit configuration file implementing the aforementioned chip select signal function, wherein the aforementioned chip select signal function circuit configuration file generates a target chip select signal based on the aforementioned chip select signal, hardware chip select signal, and software chip select signal, and the aforementioned chip select signal function circuit template is used to construct a circuit implementing the aforementioned chip select signal function; If the M aforementioned target circuit functions include the aforementioned indirect read / write function, a transmit buffer function circuit template and a receive buffer function circuit template are invoked to generate a transmit buffer function circuit configuration file implementing the transmit buffer function and a receive buffer function circuit configuration file implementing the receive buffer function, wherein the aforementioned transmit buffer function circuit configuration file is used to buffer write data on the circuit bus, and the aforementioned receive buffer function circuit configuration file is used to buffer the total data of the circuit bus. For reading data from the line, the aforementioned transmit buffer function circuit template is used to construct a circuit that implements the aforementioned transmit buffer function, and the aforementioned receive buffer function circuit template is used to construct a circuit that implements the aforementioned receive buffer function. If the M target circuit functions include a transmit shift function, the transmit shift function circuit template is invoked to generate a transmit shift function circuit configuration file that implements the aforementioned transmit shift function. The transmit shift function circuit configuration file is used to convert the written data into the output signal of the serial interface according to the interface protocol of the aforementioned serial external memory. The transmit shift function circuit template is used to construct a circuit that implements the aforementioned transmit shift function. If the M target circuit functions include a receive shift function, the receive shift function circuit template is invoked to generate a receive shift function circuit configuration file that implements the aforementioned receive shift function. The receive shift function circuit configuration file is used to convert the input signal of the serial interface into the aforementioned read data according to the interface protocol of the aforementioned serial external memory. The receive shift function circuit template is used to construct a circuit that implements the aforementioned receive shift function.

[0009] In one exemplary embodiment, integrating M of the aforementioned circuit configuration files to obtain a target circuit configuration file includes: calling a top-level circuit template and reading M functional modules from the M aforementioned circuit configuration files; integrating the M aforementioned functional modules based on the integration rules in the top-level circuit template to obtain the aforementioned target circuit configuration file, wherein the aforementioned integration rules are used to describe the connection method between each of the aforementioned functional modules.

[0010] In an exemplary embodiment, after integrating M of the above-mentioned circuit configuration files to obtain a target circuit configuration file, the above method further includes: calling a constraint template file to generate a target constraint file for the target circuit based on the composition and connection method of the target circuit, wherein the constraint template file is used to describe the general constraint settings of the circuit, including the timing constraint settings, input-output constraint settings, and clock constraint settings of the target circuit, and the target constraint file is used to describe the timing constraints, input-output constraints, and clock constraints in the target circuit.

[0011] According to another embodiment of this application, a circuit configuration file generation apparatus is provided. The apparatus includes: a first generation module, configured to generate a configuration requirement file based on acquired circuit configuration requirements, wherein the configuration requirement file includes N required circuit functions and circuit configuration states for each of the circuit functions, wherein N is a natural number greater than or equal to 1; a first traversal module, configured to traverse the configuration requirement file to determine M target circuit functions from the configuration file, wherein the circuit configuration states of the M target circuit functions are all allowed configuration states, wherein M is a natural number less than or equal to N; a first search module, configured to search for a circuit template matching each target circuit function to obtain M circuit templates; a first generation module, configured to call each circuit template to generate a circuit configuration file corresponding to each target circuit function to obtain M circuit configuration files, wherein the circuit configuration files are used to configure a circuit that implements the target circuit function; and a first integration module, configured to integrate the M circuit configuration files to obtain a target circuit configuration file, wherein the target circuit configuration file is used to configure a target circuit that responds to the circuit configuration requirements.

[0012] In an exemplary embodiment, the first generation module includes: a first acquisition submodule, configured to acquire the required circuit operating mode, circuit chip select information, and circuit clock information from the circuit configuration requirements, wherein the circuit operating mode is used to indicate the read / write method between the controller and external storage device in the required circuit, the circuit chip select information is used to indicate the required number of external storage devices, and the circuit clock information is used to indicate the requirement for cross-clock domain signal conversion function; a first determination submodule, configured to determine the circuit operating mode, the circuit chip select information, and the circuit clock information into N circuit functions, and determine the circuit configuration state of each circuit function; and a first integration submodule, configured to integrate the N circuit functions and the circuit configuration state of each circuit function to generate the configuration requirement file.

[0013] In an exemplary embodiment, the first traversal module includes a first traversal submodule, configured to traverse the circuit configuration state of each circuit function in the configuration requirements file, so as to select the circuit configuration state as an allowed circuit function from N circuit functions, and obtain M target circuit functions.

[0014] In one exemplary embodiment, the first generation module includes at least one of the following: a first generation submodule, configured to, when the M target circuit functions include a conversion function, invoke a conversion function circuit template to generate a conversion function circuit configuration file implementing the conversion function, wherein the conversion function circuit configuration file includes conversion description information of cross-clock domain signals of the required circuit, and the conversion function circuit configuration file is used to construct a circuit implementing the cross-clock domain signal conversion function; a second generation submodule, configured to, when the M target circuit functions include a clock function, invoke a clock generation function circuit template to generate a clock generation function circuit configuration file implementing the clock function, wherein the clock generation function circuit configuration file includes description information of performing a frequency division operation on the core clock in the required circuit according to the clock frequency division coefficient in the clock configuration requirement to obtain the clock signal of the serial external memory, and the clock generation function circuit configuration file is used to construct a circuit implementing the clock function; a third generation submodule, configured to, when the M target circuit functions include a polling read function, invoke a first register configuration function circuit template to generate a first register configuration circuit file implementing the polling read function, wherein... The first register configuration circuit file includes description information for implementing the first save operation of the circuit polling read status information and the external storage device polling read status information. The first register configuration circuit file is used to construct the circuit that implements the polling read function. The fourth generation submodule is used to call the second register configuration function circuit template to generate the second register configuration circuit file that implements the direct read function when the M target circuit functions include the direct read function. The second register configuration circuit file includes description information for implementing the second save operation of the circuit direct read status information and the external storage device direct read status information. The second register configuration circuit file is used to construct the circuit that implements the direct read function. The fifth generation submodule is used to call the third register configuration function circuit template to generate the third register configuration circuit file that implements the indirect read and write function when the M target circuit functions include the indirect read and write function. The third register configuration circuit file includes description information for implementing the third save operation of the circuit indirect read and write status information and the external storage device indirect read and write status information. The third register configuration circuit file is used to construct the circuit that implements the indirect read and write function.The sixth generation submodule is used to, when the M target circuit functions include logic control functions, call the logic control function circuit template to generate a logic control function circuit configuration file to implement the logic control functions. The configuration file includes description information for generating chip select signals based on the chip select information in the target circuit functions and the interface protocol of the serial external memory. This configuration file is used to construct the circuit that implements the logic control functions.

[0015] In an exemplary embodiment, the first generation module includes at least one of the following: a seventh generation submodule, configured to, when the M target circuit functions include a chip select signal function, invoke a chip select signal function circuit template to generate a chip select signal function circuit configuration file implementing the chip select signal function, wherein the chip select signal function circuit configuration file generates a target chip select signal based on the chip select signal, the hardware chip select signal, and the software chip select signal, and the chip select signal function circuit template is used to construct a circuit implementing the chip select signal function; an eighth generation submodule, configured to, when the M target circuit functions include the indirect read / write function, invoke a transmit buffer function circuit template and a receive buffer function circuit template to generate a transmit buffer function circuit configuration file implementing the transmit buffer function and a receive buffer function circuit configuration file implementing the receive buffer function, wherein the transmit buffer function circuit configuration file is used to buffer write data on the circuit bus, the receive buffer function circuit configuration file is used to buffer read data on the circuit bus, and the transmit buffer function circuit template is used to... A circuit implementing the aforementioned transmit buffer function is constructed, and the aforementioned receive buffer function circuit template is used to construct the circuit implementing the aforementioned receive buffer function; a ninth generation submodule is used to call the transmit shift function circuit template to generate a transmit shift function circuit configuration file to implement the aforementioned transmit shift function when the transmit shift function is included among the M aforementioned target circuit functions, wherein the transmit shift function circuit configuration file is used to convert the aforementioned write data into the output signal of the serial interface according to the interface protocol of the aforementioned serial external memory, and the aforementioned transmit shift function circuit template is used to construct the circuit implementing the aforementioned transmit shift function; a tenth generation submodule is used to call the receive shift function circuit template to generate a receive shift function circuit configuration file to implement the aforementioned receive shift function when the receive shift function is included among the M aforementioned target circuit functions, wherein the receive shift function circuit configuration file is used to convert the input signal of the serial interface into the aforementioned read data according to the interface protocol of the aforementioned serial external memory, and the aforementioned receive shift function circuit template is used to construct the circuit implementing the aforementioned receive shift function.

[0016] In an exemplary embodiment, the first integration module includes: a first invocation submodule, configured to invoke a top-level circuit template and read M functional modules from M circuit configuration files; and a second integration submodule, configured to integrate the M functional modules based on integration rules in the top-level circuit template to obtain the target circuit configuration file, wherein the integration rules describe the connection method between each functional module.

[0017] In an exemplary embodiment, the apparatus further includes a second generation module, configured to integrate M circuit configuration files, obtain a target circuit configuration file, and then call a constraint template file to generate a target constraint file for the target circuit based on the composition and connection method of the target circuit. The constraint template file is used to describe general constraint settings for the circuit, including timing constraint settings, input / output constraint settings, and clock constraint settings for the target circuit. The target constraint file is used to describe the timing constraints, input / output constraints, and clock constraints in the target circuit.

[0018] According to yet another embodiment of this application, a computer-readable storage medium is also provided, wherein a computer program is stored in the computer-readable storage medium, and the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0019] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0020] According to yet another embodiment of this application, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0021] This application first generates a configuration requirement file based on the obtained circuit configuration requirements. Then, it determines the target circuit functions with allowed configuration states from the requirement configuration file. Next, it searches for a circuit template that matches each target circuit function and calls the circuit template to generate a circuit configuration file corresponding to each target circuit function, resulting in M ​​circuit configuration files. Finally, it integrates the M circuit configuration files to obtain the target circuit configuration file. Since this application can call the circuit template to generate the corresponding circuit configuration file according to the circuit configuration requirements, it can solve the problem of inflexible generation of control circuits in related technologies, realize the generation of circuit configuration files based on circuit configuration requirements, and achieve the effect of flexibly generating control circuits. Attached Figure Description

[0022] Figure 1This is a hardware structure block diagram of a server device for a method of generating a circuit configuration file according to an embodiment of this application.

[0023] Figure 2 This is a flowchart of a method for generating a circuit configuration file according to an embodiment of this application;

[0024] Figure 3 This is a circuit structure of a circuit configuration file generation method according to a specific embodiment of this application. Figure 1 ;

[0025] Figure 4 This is a circuit structure of a circuit configuration file generation method according to a specific embodiment of this application. Figure 2 ;

[0026] Figure 5 This is a circuit diagram of the chip select signal function according to a specific embodiment of this application;

[0027] Figure 6 This is a flowchart of a method for generating a circuit configuration file according to a specific embodiment of this application;

[0028] Figure 7 This is a structural block diagram of a circuit configuration file generation device according to an embodiment of this application. Detailed Implementation

[0029] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0031] The methods and embodiments provided in this application can be executed on a server device or a similar computing device. Taking running on a server device as an example, Figure 1 This is a hardware structure block diagram of a server device for a circuit configuration file generation method according to an embodiment of this application. For example... Figure 1 As shown, the server device may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The server device may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the server equipment described above. For example, the server equipment may also include components that are more... Figure 1The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0032] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to a circuit configuration file generation method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the aforementioned method. The memory 104 may include high-speed random access memory and non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to server devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0033] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the server device. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0034] This embodiment provides a method for generating a circuit configuration file. Figure 2 This is a flowchart of a method for generating a circuit configuration file according to an embodiment of this application, such as... Figure 2 As shown, the process includes the following steps:

[0035] Step S202: Based on the obtained circuit configuration requirements, generate a configuration requirement file, wherein the configuration requirement file includes N circuit functions required and the circuit configuration status of each circuit function, where N is a natural number greater than or equal to 1.

[0036] Step S204: Traverse the configuration requirement file to determine M target circuit functions from the requirement configuration file, wherein the circuit configuration status of the M target circuit functions is an allowed configuration status, and M is a natural number less than or equal to N.

[0037] Optionally, circuit configuration requirements include, but are not limited to, the operating mode of the QSPI control circuit, chip select information, circuit clock information, bus width, clock frequency, bus protocol, signal line definitions, and arbitration mechanism. As shown in Table 1, the circuit functions in configuration requirement file A include: clock conversion function, polling read function, direct read function, indirect read / write function, and chip select signal function. The circuit configuration status of clock conversion function, direct read function, and indirect read / write function is enabled; the circuit configuration status of chip select signal function is configured and the number of chip select signals is 3; the circuit configuration status of polling read function is disabled.

[0038] Table 1

[0039]

[0040]

[0041] Step S206: Find the circuit template that matches the function of each target circuit to obtain M circuit templates;

[0042] Step S208: Call each circuit template to generate a circuit configuration file corresponding to each target circuit function, resulting in M ​​circuit configuration files, wherein the circuit configuration files are used to configure the circuits that implement the target circuit functions;

[0043] Step S210: Integrate M circuit configuration files to obtain a target circuit configuration file, wherein the target circuit configuration file is used to configure the target circuit in response to the circuit configuration requirements.

[0044] Optionally, the circuit template is a rule file used to generate the target circuit function, including but not limited to the conversion function circuit template bus2kernel_remp.sv, the clock generation function circuit template clk_gen_temp.sv, the chip select signal function circuit template cs_gen_temp.sv, the logic control function circuit template ctrl_logic_temp.sv, the top-level circuit template qspi_top_temp.sv, the register configuration function circuit template reg_cfg_temp.sv, the receive buffer function circuit template rx_fifo_temp.sv, the receive shift function circuit template rx_shifter_temp.sv, the transmit buffer function circuit template tx_fifo_temp.sv, the transmit shift function circuit template tx_shifter_temp.sv, and the constraint template file constraint_temp.tcl.

[0045] Optionally, the explanation will take the target circuit for generating the QSPI controller as an example, such as... Figure 3 As shown, Figure 3This is a circuit structure of a circuit configuration file generation method according to a specific embodiment of this application. Figure 1 The QSPI controller generates corresponding circuit configuration files based on the target circuit functions allowed for configuration in the configuration requirements file. Circuit functions not allowed for configuration will not generate corresponding circuit configuration files. The QSPI controller also generates the corresponding number of chip select signals based on the number of chip select signals configured in the configuration requirements file. The QSPI controller can operate in three modes according to user requirements: Standard Serial Peripheral Interface (Standard SPI), Dual Serial Peripheral Interface (Dual SPI), and Quad Serial Peripheral Interface (QSPI). The output signals of the QSPI controller are the QSPI bus signals and the corresponding number of chip select signals: qspi_clk, qspi_oe[3:0], qspi_o[3:0], qspi_i[3:0], cs 0...cs n. All other signals are the same for each Flash memory, except for the cs signal; only Flash memories with a low cs signal can operate. When the QSPI controller operates in standard SPI mode, the output enable signal qspi_oe[0], input signal qspi_i[0], and output signal qspi_o[0] are valid, and the high-order bits of these three signals are invalid. When the QSPI controller operates in dual SPI mode, the output enable signal qspi_oe[1:0], input signal qspi_i[1:0], and output signal qspi_o[1:0] are valid, and the high-order bits of these three signals are invalid. When the QSPI controller operates in QSPI mode, the output enable signal qspi_oe[3:0], input signal qspi_i[3:0], and output signal qspi_o[3:0] are all valid. The generated QSPI controller can support standard SPI, dual SPI, and QSPI modes. Different Flash memories require time-multiplexed control buses.

[0046] In this embodiment, the entity executing the above steps can be a terminal, a server, a specific processor set in the terminal or server, or a processor or processing device set relatively independently of the terminal or server, but is not limited thereto.

[0047] Through the above steps, firstly, a configuration requirement file is generated based on the obtained circuit configuration requirements. Then, the target circuit functions with allowed configuration states are determined from the requirement file. Next, a circuit template matching each target circuit function is found, and the circuit template is called to generate a circuit configuration file corresponding to each target circuit function, resulting in M ​​circuit configuration files. Finally, the M circuit configuration files are integrated to obtain the target circuit configuration file. Since this application can call the circuit template to generate the corresponding circuit configuration file according to the circuit configuration requirements, it can solve the problem of inflexible generation of control circuits in related technologies, realize the generation of circuit configuration files based on circuit configuration requirements, and achieve the effect of flexibly generating control circuits.

[0048] In an exemplary embodiment, a configuration requirement file is generated based on the acquired circuit configuration requirements, including: obtaining the required circuit operating mode, circuit chip select information, and circuit clock information from the circuit configuration requirements, wherein the circuit operating mode is used to indicate the read / write method between the controller and external storage devices in the required circuit, the circuit chip select information is used to indicate the required number of external storage devices, and the circuit clock information is used to indicate the requirement for cross-clock domain signal conversion function; determining the circuit operating mode, the circuit chip select information, and the circuit clock information as N circuit functions, and determining the circuit configuration state of each circuit function; integrating the N circuit functions and the circuit configuration state of each circuit function to generate the configuration requirement file.

[0049] Optionally, the circuit operating modes include, but are not limited to, direct read mode, indirect read / write mode, and polling read mode. The chip select information indicates the number of chip select signals; one chip select signal can control one NOR Flash memory, and multiple chip select signals can enable one QSPI controller to connect to multiple NOR Flash memories. Circuit functions include, but are not limited to: conversion function, clock function, polling read function, direct read function, indirect read / write function, logic control function, chip select signal function, indirect read / write function, transmit shift function, receive shift function, transmit buffer function, and receive buffer function. For example, if the circuit configuration requirements include direct read mode, three chip select signals, and circuit clock information, then the circuit functions include conversion function, clock function, polling read function, direct read function, indirect read / write function, logic control function, chip select signal function, indirect read / write function, transmit shift function, and receive shift function. This embodiment generates configuration requirement files through a systematic approach, ensuring that the circuit design meets the expected performance and functional requirements, while improving the efficiency and quality of the design process.

[0050] In one exemplary embodiment, traversing the configuration requirement file to determine M target circuit functions from the requirement file includes: traversing the circuit configuration state of each circuit function in the configuration requirement file to select circuit functions whose circuit configuration state is allowed to be configured from N circuit functions, thereby obtaining M target circuit functions.

[0051] Optionally, as shown in Table 1, the circuit functions in configuration requirement file A include: clock conversion function, polling read function, direct read function, indirect read / write function, and chip select signal function. The circuit configuration status of clock conversion function, direct read function, and indirect read / write function is allowed configuration status; the circuit configuration status of chip select signal function is configured and the number of chip select signals is 3; the circuit configuration status of polling read function is not allowed configuration status. That is, the target circuit functions are clock conversion function, direct read function, indirect read / write function, and chip select signal function. This embodiment, by traversing the configuration requirement file and filtering the circuit configuration status of the circuit functions, accurately evaluates the configuration status of each circuit function, ensuring that the finally determined target circuit functions all meet the configuration requirements. This achieves the goal of flexibly determining the target circuit functions according to different configuration requirement files, adapting to different application scenarios and needs.

[0052] In one exemplary embodiment, each of the aforementioned circuit templates is invoked to generate a circuit configuration file corresponding to each of the aforementioned target circuit functions, resulting in M ​​such circuit configuration files, including at least one of the following: If the M aforementioned target circuit functions include a conversion function, a conversion function circuit template is invoked to generate a conversion function circuit configuration file that implements the conversion function, wherein the conversion function circuit configuration file includes a description of the conversion of cross-clock domain signals of the required circuit, and the conversion function circuit configuration file is used to construct a circuit that implements the cross-clock domain signal conversion function; If the M aforementioned target circuit functions include a clock function, a clock generation function circuit template is invoked to generate a clock generation function that implements the clock function. The configuration file for the clock generation function circuit includes a description of how the core clock in the required circuit is divided according to the clock division coefficient in the clock configuration requirements to obtain the clock signal of the serial external memory. This configuration file is used to construct the circuit that implements the clock function. If the M target circuit functions include a polling read function, a first register configuration function circuit template is called to generate a first register configuration circuit file that implements the polling read function. This first register configuration circuit file includes a description of the first save operation for implementing the circuit polling read status information and the external storage device polling read status information. The circuit file is used to construct the circuit that implements the polling read function described above. If the M target circuit functions include a direct read function, the second register configuration function circuit template is called to generate a second register configuration circuit file that implements the direct read function. This second register configuration circuit file includes description information for the second save operation used to implement the circuit's direct read status information and the external storage device's direct read status information. This second register configuration circuit file is used to construct the circuit that implements the direct read function. If the M target circuit functions include an indirect read / write function, the third register configuration function circuit template is called to generate a third register configuration circuit file that implements the indirect read / write function. The third register configuration circuit file includes description information for implementing the third save operation of indirect read / write status information of the circuit and indirect read / write status information of the external storage device. The third register configuration circuit file is used to construct the circuit that implements the indirect read / write function. When the M target circuit functions include logic control functions, the logic control function circuit template is called to generate a logic control function circuit configuration file that implements the logic control function. The logic control function circuit configuration file includes description information for generating the chip select signal according to the chip select information in the target circuit function and the interface protocol of the serial external memory. The logic control function circuit configuration file is used to construct the circuit that implements the logic control function.

[0053] Optionally, cross-clock domain signal conversion refers to handling signals from different clock domains in circuit design. Different clock domains mean that signals operate at different clock frequencies or phases. The purpose of cross-clock domain signal conversion is to ensure that signals do not cause metastability or data corruption when transferred from one clock domain to another. Since the bus clock and the kernel clock may differ, a conversion function is required to implement cross-clock domain signal conversion when designing the QSPI control circuit. The template corresponding to the conversion function is the conversion function circuit template bus2kernel_remp.sv, which generates the corresponding conversion function circuit configuration file bus2kernel.sv. If the target circuit function includes conversion functionality, a circuit configuration file implementing the conversion function circuit is generated; otherwise, it is not generated. The description information of cross-clock domain signal conversion includes, but is not limited to, register information for implementing cross-clock domain signal conversion, cross-clock domain communication methods, and cross-clock domain conversion methods. For example, using two or more levels of registers in the target clock domain through synchronization registers to double-buffer the signal and eliminate metastability problems, thereby achieving cross-clock domain signal conversion. For example, request and acknowledgment signals in a handshake protocol ensure secure data transmission between two clock domains, enabling cross-clock domain signal conversion. For example, edge detection, by detecting the rising or falling edge of a signal, can generate a new signal in the target clock domain, achieving cross-clock domain signal conversion. For example, gray codes can reduce the error rate during cross-clock domain signal conversion. The description information of cross-clock domain signal conversion in the conversion function circuit configuration file can be selected and combined according to specific application scenarios and design requirements to achieve effective cross-clock domain signal conversion.

[0054] Optionally, the clock function can divide the core clock according to the clock division coefficient value stored in the register configured on the bus. The resulting clock after division is the description information of the serial external memory clock signal, such as... Figure 4 The clock function corresponds to the clock generation function circuit template clk_gen_temp.sv, and the corresponding function circuit configuration file is clk_gen.sv. In any operating mode of the QSPI controller, a circuit configuration file implementing the clock function circuit will be generated.

[0055] Optionally, the register configuration function can store bus configuration information (such as bus width, clock frequency, bus protocol, signal line definitions, arbitration mechanism, etc.) in registers for circuit control. Key circuit states (such as synchronization state, reset state, wait state, stable state, metastable state, overflow / undercurrent state, error state, interrupt state, power state, etc.) and key Flash readback states (such as read-ready state, data transmission state, data alignment state, error detection state, data integrity state, erase state, programming state, protection state, idle state, critical data state, etc.) are stored in the register configuration function's circuit, and the bus can read this key state information. The template corresponding to the register configuration function is the register configuration function circuit template reg_cfg_temp.sV, and the corresponding register configuration circuit file is reg_cfg.sV. In a QSPI controller, each operating mode corresponds to a circuit configuration file that implements register configuration functionality. For example, if the QSPI controller requires a polling read mode, and the target circuit functionality includes polling read, the register configuration function circuit template `reg_cfg_temp.sV` is called to generate a first register configuration circuit file that implements polling read functionality. The polling read status information includes, but is not limited to, the status information of internal registers. A first save operation stores the key states generated by the circuit and the key states read back from Flash in the register configuration function circuit. Similarly, if the QSPI controller requires a direct read mode, and the target circuit functionality includes direct read functionality, the register configuration function circuit template `reg_cfg_temp.sV` is called to generate a second register configuration circuit file that implements direct read functionality. A second save operation stores the key states generated by the circuit and the key states read back from Flash in the register configuration function circuit. For example, the QSPI controller requires an indirect read / write mode. The target circuit function includes indirect read / write functionality. The register configuration function circuit template reg_cfg_temp.sv is called to generate a third register configuration circuit file that implements the direct read function. The third save operation saves the key states generated by the circuit and the key states read back from Flash in the register configuration function circuit.

[0056] Optionally, the interface protocol for the serial external memory includes, but is not limited to, standard SPI, dual SPI, and QSPI. The logic control function is used to generate the chip select signal CS and the output enable signal QSPI_EO according to the chip select information in the target circuit function and the requirements of the serial external memory interface protocol, such as... Figure 4As shown. The template corresponding to the logic control function is the logic control function circuit template ctrl_logic_temp.sv, and the corresponding logic control function circuit configuration file is ctrl_logic.sv. In any operating mode of the QSPI controller, a circuit configuration file implementing the logic control function will be generated. Optionally, the logic control function can also store data in the transmit buffer or read data from the receive buffer, such as... Figure 4 As shown.

[0057] This embodiment uses circuit templates to automatically generate specific circuit configuration files to achieve different circuit functions. This achieves the goal of quickly generating circuit configuration files that meet specific functions, reducing human error, and improving the accuracy and flexibility of circuit design.

[0058] In one exemplary embodiment, each of the aforementioned circuit templates is invoked to generate a circuit configuration file corresponding to each of the aforementioned target circuit functions, resulting in M ​​such circuit configuration files, including at least one of the following: If the M aforementioned target circuit functions include a chip select signal function, a chip select signal function circuit template is invoked to generate a chip select signal function circuit configuration file implementing the aforementioned chip select signal function, wherein the aforementioned chip select signal function circuit configuration file generates a target chip select signal based on the aforementioned chip select signal, hardware chip select signal, and software chip select signal, and the aforementioned chip select signal function circuit template is used to construct a circuit implementing the aforementioned chip select signal function; If the M aforementioned target circuit functions include the aforementioned indirect read / write function, a transmit buffer function circuit template and a receive buffer function circuit template are invoked to generate a transmit buffer function circuit configuration file implementing the transmit buffer function and a receive buffer function circuit configuration file implementing the receive buffer function, wherein the aforementioned transmit buffer function circuit configuration file is used to buffer write data on the circuit bus, and the aforementioned receive buffer function circuit configuration file is used to buffer the total data of the circuit bus. For reading data from the line, the aforementioned transmit buffer function circuit template is used to construct a circuit that implements the aforementioned transmit buffer function, and the aforementioned receive buffer function circuit template is used to construct a circuit that implements the aforementioned receive buffer function. If the M target circuit functions include a transmit shift function, the transmit shift function circuit template is invoked to generate a transmit shift function circuit configuration file that implements the aforementioned transmit shift function. The transmit shift function circuit configuration file is used to convert the written data into the output signal of the serial interface according to the interface protocol of the aforementioned serial external memory. The transmit shift function circuit template is used to construct a circuit that implements the aforementioned transmit shift function. If the M target circuit functions include a receive shift function, the receive shift function circuit template is invoked to generate a receive shift function circuit configuration file that implements the aforementioned receive shift function. The receive shift function circuit configuration file is used to convert the input signal of the serial interface into the aforementioned read data according to the interface protocol of the aforementioned serial external memory. The receive shift function circuit template is used to construct a circuit that implements the aforementioned receive shift function.

[0059] Optionally, such as Figure 5As shown, the chip select signal is the output of the logic control function. `hw channel sel` is the input signal, the hardware chip select signal, with a default value of 1. The bit width of the `hw channel sel` signal is the same as the number of Flash memory modules. The chip select signal for the corresponding Flash memory is only valid when a bit is 0. `cs register` is the software chip select signal register, located within the register configuration function. Its default value is 1, and its bit width is the same as the number of Flash memory modules. The chip select signal for the corresponding Flash memory is only valid when a bit is 0. `cs mode select` is the chip select signal mode selection register, used to select between the hardware and software chip select signals. This register is located within the register configuration function. When `cs mode select` is 0, the hardware chip select signal input is enabled; when `cs mode select` is 1, the software chip select signal register input is enabled. The default value is 1, meaning the software chip select signal register is enabled by default. The template corresponding to the chip select signal function is the chip select signal function circuit template Cs_gen_temp.sv, and the corresponding chip select signal function circuit configuration file is cs_gen.sv. In any working mode of the QSPI controller, a circuit configuration file that implements the chip select signal function will be generated.

[0060] Optionally, the transmit buffer function is used to buffer write data from the bus within the receive buffer function. The template for the transmit buffer function is the transmit buffer function circuit template tx_fifo_temp.sv, and the corresponding transmit buffer function circuit configuration file is tx_fifo.sv. In the indirect read / write mode of the QSPI controller, if the target circuit function includes indirect read / write functionality, a circuit configuration file implementing the transmit buffer function will be generated. The receive buffer function is used to buffer read data from the bus within the transmit buffer function. The template for the receive buffer function is the receive buffer function circuit template rx_fifo_temp.sv, and the corresponding receive buffer function circuit configuration file is rxfifo.sv. In the indirect read / write mode of the QSPI controller, if the target circuit function includes indirect read / write functionality, a circuit configuration file implementing the transmit buffer function will be generated.

[0061] Optionally, the transmit shift function converts the data in the transmit buffer into the output data signal qspi_o based on configuration information, such as the serial external memory interface protocol. The template for the transmit shift function is the transmit shift function circuit template tx_shifter_temp.sv, and the corresponding transmit shift function circuit configuration file is tx_shifter.sv. A circuit configuration file implementing the transmit shift function will be generated in any operating mode of the QSPI controller. The receive shift function stores the input data signal qspi_i into the receive buffer based on configuration information, such as the serial external memory interface protocol. The template for the receive shift function is the receive shift function circuit template rx_shifter_temp.sv, and the corresponding receive shift function circuit configuration file is rxshifter.sv. A circuit configuration file implementing the receive shift function will be generated in any operating mode of the QSPI controller.

[0062] This embodiment uses circuit templates to automatically generate specific circuit configuration files to achieve different circuit functions. This achieves the goal of quickly generating circuit configuration files that meet specific functions, reducing human error, and improving the accuracy and flexibility of circuit design.

[0063] In one exemplary embodiment, integrating M of the aforementioned circuit configuration files to obtain a target circuit configuration file includes: calling a top-level circuit template and reading M functional modules from the M aforementioned circuit configuration files; integrating the M aforementioned functional modules based on the integration rules in the top-level circuit template to obtain the aforementioned target circuit configuration file, wherein the aforementioned integration rules are used to describe the connection method between each of the aforementioned functional modules.

[0064] Optionally, the integration rules include, but are not limited to, descriptions of the connection methods between functional modules, such as data flow direction and control signal connection. For example, the circuit configuration file includes configuration files for conversion function circuits, clock generation function circuits, chip select signal function circuits, logic control function circuits, register configuration function circuits, receive buffer function circuits, receive shift function circuits, transmit buffer function circuits, and transmit shift function circuits. The top-level circuit template qspi_top_temp.sv reads the above circuit configuration files and extracts the conversion function module, clock generation function module, chip select signal function module, logic control function module, register configuration function module, receive buffer function module, receive shift function module, transmit buffer function module, and transmit shift function module. Then, based on the data flow direction and control signal connection methods between the functional modules, the above functional modules are integrated to obtain the target circuit configuration file, as shown in Figure 4. This embodiment obtains the target circuit configuration file through integrated circuit configuration files, realizing modular design, allowing each functional module to be designed independently, and achieving the goal of improving the flexibility and maintainability of control circuit design.

[0065] In an exemplary embodiment, after integrating M of the above-mentioned circuit configuration files to obtain a target circuit configuration file, the above method further includes: calling a constraint template file to generate a target constraint file for the target circuit based on the composition and connection method of the target circuit, wherein the constraint template file is used to describe the general constraint settings of the circuit, including the timing constraint settings, input-output constraint settings, and clock constraint settings of the target circuit, and the target constraint file is used to describe the timing constraints, input-output constraints, and clock constraints in the target circuit.

[0066] Optionally, timing constraint settings can define the maximum and minimum delays for data propagation in the circuit, ensuring data synchronization and clock stability in the control circuit. Input / output constraint settings can configure the electrical characteristics of input / output pins, such as drive strength and input sensitivity, to ensure signal quality and circuit compatibility with external systems. Clock constraint settings can configure the propagation delay and skew of the clock signal, ensuring the accuracy and stability of the system clock. The constraint template file `constraint_temp.tcl` is called, which contains general constraint settings for the circuit design. Using the target circuit configuration file as input, the constraint template file is called to generate the target constraint file. This embodiment ensures that the circuit design meets performance requirements through a precise constraint template file. Furthermore, using the constraint template file allows for the rapid generation of compliant constraint files, reducing the time and workload of manually setting constraints.

[0067] The present application will now be described in conjunction with specific embodiments:

[0068] This embodiment uses the control circuit for generating the QSPI controller as an example for illustration. Figure 6 As shown, Figure 6 This is a flowchart of a method for generating a circuit configuration file according to a specific embodiment of this application, including the following steps:

[0069] S602, Begin;

[0070] S604: Obtain the circuit configuration requirements, generate a configuration requirement file, and the tool reads the configuration requirement file.

[0071] S606: Determine whether the target circuit function includes a conversion function. If yes, proceed to S608; otherwise, proceed to S610.

[0072] S608, call the conversion function circuit template to generate the conversion function circuit configuration file that implements the conversion function;

[0073] S610 calls the clock generation function circuit template, register configuration function circuit template, and logic control function circuit template to generate the corresponding clock generation function circuit configuration file, register configuration circuit file, and logic control function circuit configuration file.

[0074] S612 calls the chip select signal function circuit template to generate the chip select signal function circuit configuration file;

[0075] S614: Determine whether the control circuit of the QSPI controller is in indirect read / write mode. If yes, proceed to S616; otherwise, proceed to S618.

[0076] S616, call the receive buffer function circuit template and the send buffer function circuit template corresponding to the receive buffer function circuit configuration file and the send buffer function circuit configuration file;

[0077] S618 calls the receive shift function circuit template and the transmit shift function circuit template to generate the corresponding transmit shift function circuit configuration file and receive shift function circuit configuration file;

[0078] S620 calls the top-level circuit template to generate the target circuit configuration file;

[0079] S622, call the constraint template file to generate the target constraint file;

[0080] S624, End.

[0081] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0082] This embodiment also provides a circuit configuration file generation apparatus for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0083] Figure 7 This is a structural block diagram of a circuit configuration file generation apparatus according to an embodiment of this application, such as... Figure 7 As shown, the device includes:

[0084] The first generation module 702 is used to generate a configuration requirement file based on the acquired circuit configuration requirements. The configuration requirement file includes N circuit functions required and the circuit configuration status of each circuit function. N is a natural number greater than or equal to 1.

[0085] The first traversal module 704 is used to traverse the above configuration requirement file to determine M target circuit functions from the above requirement configuration file, wherein the circuit configuration status of the M target circuit functions is an allowed configuration status, and M is a natural number less than or equal to N.

[0086] The first search module 706 is used to search for a circuit template that matches the function of each of the above target circuits, and obtain M circuit templates; the first generation module is used to call each of the above circuit templates to generate a circuit configuration file corresponding to each of the above target circuit functions, and obtain M circuit configuration files, wherein the circuit configuration files are used to configure the circuit that implements the function of the above target circuit.

[0087] The first integration module 708 is used to integrate M of the above-mentioned circuit configuration files to obtain a target circuit configuration file, wherein the above-mentioned target circuit configuration file is used to configure a target circuit that responds to the above-mentioned circuit configuration requirements.

[0088] In an exemplary embodiment, the first generation module includes: a first acquisition submodule, configured to acquire the required circuit operating mode, circuit chip select information, and circuit clock information from the circuit configuration requirements, wherein the circuit operating mode is used to indicate the read / write method between the controller and external storage device in the required circuit, the circuit chip select information is used to indicate the required number of external storage devices, and the circuit clock information is used to indicate the requirement for cross-clock domain signal conversion function; a first determination submodule, configured to determine the circuit operating mode, the circuit chip select information, and the circuit clock information into N circuit functions, and determine the circuit configuration state of each circuit function; and a first integration submodule, configured to integrate the N circuit functions and the circuit configuration state of each circuit function to generate the configuration requirement file.

[0089] In an exemplary embodiment, the first traversal module includes a first traversal submodule, configured to traverse the circuit configuration state of each circuit function in the configuration requirements file, so as to select the circuit configuration state as an allowed circuit function from N circuit functions, and obtain M target circuit functions.

[0090] In one exemplary embodiment, the first generation module includes at least one of the following: a first generation submodule, configured to, when the M target circuit functions include a conversion function, invoke a conversion function circuit template to generate a conversion function circuit configuration file implementing the conversion function, wherein the conversion function circuit configuration file includes conversion description information of cross-clock domain signals of the required circuit, and the conversion function circuit configuration file is used to construct a circuit implementing the cross-clock domain signal conversion function; a second generation submodule, configured to, when the M target circuit functions include a clock function, invoke a clock generation function circuit template to generate a clock generation function circuit configuration file implementing the clock function, wherein the clock generation function circuit configuration file includes description information of performing a frequency division operation on the core clock in the required circuit according to the clock frequency division coefficient in the clock configuration requirement to obtain the clock signal of the serial external memory, and the clock generation function circuit configuration file is used to construct a circuit implementing the clock function; a third generation submodule, configured to, when the M target circuit functions include a polling read function, invoke a first register configuration function circuit template to generate a first register configuration circuit file implementing the polling read function, wherein... The first register configuration circuit file includes description information for implementing the first save operation of the circuit polling read status information and the external storage device polling read status information. The first register configuration circuit file is used to construct the circuit that implements the polling read function. The fourth generation submodule is used to call the second register configuration function circuit template to generate the second register configuration circuit file that implements the direct read function when the M target circuit functions include the direct read function. The second register configuration circuit file includes description information for implementing the second save operation of the circuit direct read status information and the external storage device direct read status information. The second register configuration circuit file is used to construct the circuit that implements the direct read function. The fifth generation submodule is used to call the third register configuration function circuit template to generate the third register configuration circuit file that implements the indirect read and write function when the M target circuit functions include the indirect read and write function. The third register configuration circuit file includes description information for implementing the third save operation of the circuit indirect read and write status information and the external storage device indirect read and write status information. The third register configuration circuit file is used to construct the circuit that implements the indirect read and write function.The sixth generation submodule is used to, when the M target circuit functions include logic control functions, call the logic control function circuit template to generate a logic control function circuit configuration file to implement the logic control functions. The configuration file includes description information for generating chip select signals based on the chip select information in the target circuit functions and the interface protocol of the serial external memory. This configuration file is used to construct the circuit that implements the logic control functions.

[0091] In an exemplary embodiment, the first generation module includes at least one of the following: a seventh generation submodule, configured to, when the M target circuit functions include a chip select signal function, invoke a chip select signal function circuit template to generate a chip select signal function circuit configuration file implementing the chip select signal function, wherein the chip select signal function circuit configuration file generates a target chip select signal based on the chip select signal, the hardware chip select signal, and the software chip select signal, and the chip select signal function circuit template is used to construct a circuit implementing the chip select signal function; an eighth generation submodule, configured to, when the M target circuit functions include the indirect read / write function, invoke a transmit buffer function circuit template and a receive buffer function circuit template to generate a transmit buffer function circuit configuration file implementing the transmit buffer function and a receive buffer function circuit configuration file implementing the receive buffer function, wherein the transmit buffer function circuit configuration file is used to buffer write data on the circuit bus, the receive buffer function circuit configuration file is used to buffer read data on the circuit bus, and the transmit buffer function circuit template is used to... A circuit implementing the aforementioned transmit buffer function is constructed, and the aforementioned receive buffer function circuit template is used to construct the circuit implementing the aforementioned receive buffer function; a ninth generation submodule is used to call the transmit shift function circuit template to generate a transmit shift function circuit configuration file to implement the aforementioned transmit shift function when the transmit shift function is included among the M aforementioned target circuit functions, wherein the transmit shift function circuit configuration file is used to convert the aforementioned write data into the output signal of the serial interface according to the interface protocol of the aforementioned serial external memory, and the aforementioned transmit shift function circuit template is used to construct the circuit implementing the aforementioned transmit shift function; a tenth generation submodule is used to call the receive shift function circuit template to generate a receive shift function circuit configuration file to implement the aforementioned receive shift function when the receive shift function is included among the M aforementioned target circuit functions, wherein the receive shift function circuit configuration file is used to convert the input signal of the serial interface into the aforementioned read data according to the interface protocol of the aforementioned serial external memory, and the aforementioned receive shift function circuit template is used to construct the circuit implementing the aforementioned receive shift function.

[0092] In an exemplary embodiment, the first integration module includes: a first invocation submodule, configured to invoke a top-level circuit template and read M functional modules from M circuit configuration files; and a second integration submodule, configured to integrate the M functional modules based on integration rules in the top-level circuit template to obtain the target circuit configuration file, wherein the integration rules describe the connection method between each functional module.

[0093] In an exemplary embodiment, the apparatus further includes a second generation module, configured to integrate M circuit configuration files, obtain a target circuit configuration file, and then call a constraint template file to generate a target constraint file for the target circuit based on the composition and connection method of the target circuit. The constraint template file is used to describe general constraint settings for the circuit, including timing constraint settings, input / output constraint settings, and clock constraint settings for the target circuit. The target constraint file is used to describe the timing constraints, input / output constraints, and clock constraints in the target circuit.

[0094] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0095] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when run.

[0096] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0097] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0098] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0099] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0100] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0101] The embodiments described herein also provide a computer program that includes computer instructions stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the steps in any of the above method embodiments.

[0102] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0103] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0104] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method for generating circuit configuration files, comprising: generating a configuration requirement file based on an obtained circuit configuration requirement, wherein the configuration requirement file comprises N circuit functions and a circuit configuration state of each of the circuit functions, and N is a natural number greater than or equal to 1; traversing the configuration requirement file to determine M target circuit functions from the configuration requirement file, wherein the circuit configuration state of each of the M target circuit functions is an allowed configuration state, and M is a natural number less than or equal to N; searching for a circuit template matching each of the target circuit functions to obtain M circuit templates; calling each of the circuit templates to generate a circuit configuration file corresponding to each of the target circuit functions to obtain M circuit configuration files, wherein the circuit configuration file is used to configure a circuit implementing the target circuit function; and integrating the M circuit configuration files to obtain a target circuit configuration file, wherein the target circuit configuration file is used to configure a target circuit responding to the circuit configuration requirement. 2.The method of claim 1, wherein generating a configuration requirement file based on an obtained circuit configuration requirement comprises: obtaining a circuit operation mode, a circuit chip select information and a circuit clock information from the circuit configuration requirement, wherein the circuit operation mode is used to indicate a read-write mode between a controller and an external storage device in a required circuit, the circuit chip select information is used to indicate a required number of the external storage device, and the circuit clock information is used to indicate a requirement for a cross-clock domain signal conversion function; determining the circuit operation mode, the circuit chip select information and the circuit clock information as N circuit functions and determining a circuit configuration state of each of the circuit functions; and integrating the N circuit functions and the circuit configuration state of each of the circuit functions to generate the configuration requirement file. 3.The method of claim 1, wherein traversing the configuration requirement file to determine M target circuit functions from the configuration requirement file comprises: traversing the circuit configuration state of each of the circuit functions in the configuration requirement file to filter out circuit functions with an allowed configuration state from the N circuit functions to obtain the M target circuit functions. 4.The method of claim 1, wherein calling each of the circuit templates to generate a circuit configuration file corresponding to each of the target circuit functions to obtain M circuit configuration files comprises at least one of: in a case where the M target circuit functions include a conversion function, calling a conversion function circuit template to generate a conversion function circuit configuration file implementing the conversion function, wherein the conversion function circuit configuration file comprises conversion description information of a cross-clock domain signal of a required circuit, and the conversion function circuit configuration file is used to construct a circuit implementing the conversion function of the cross-clock domain signal. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ In a case where the M target circuit functions include a clock function, a clock generation function circuit template is invoked to generate a clock generation function circuit configuration file implementing the clock function, wherein the clock generation function circuit configuration file includes description information of performing frequency division on a kernel clock in a demand circuit according to a clock frequency division coefficient in a clock configuration demand to obtain a clock signal of a serial external memory, and the clock generation function circuit configuration file is used to construct a circuit implementing the clock function. In a case where the M target circuit functions include a polling read function, a first register configuration function circuit template is invoked to generate a first register configuration circuit file implementing the polling read function, wherein the first register configuration circuit file includes description information of implementing first saving operations of circuit polling read state information and external storage device polling read state information, and the first register configuration circuit file is used to construct a circuit implementing the polling read function. In a case where the M target circuit functions include a direct read function, a second register configuration function circuit template is invoked to generate a second register configuration circuit file implementing the direct read function, wherein the second register configuration circuit file includes description information of implementing second saving operations of circuit direct read state information and external storage device direct read state information, and the second register configuration circuit file is used to construct a circuit implementing the direct read function. In a case where the M target circuit functions include an indirect read-write function, a third register configuration function circuit template is invoked to generate a third register configuration circuit file implementing the indirect read-write function, wherein the third register configuration circuit file includes description information of implementing third saving operations of circuit indirect read-write state information and external storage device indirect read-write state information, and the third register configuration circuit file is used to construct a circuit implementing the indirect read-write function. In a case where the M target circuit functions include a logic control function, a logic control function circuit template is invoked to generate a logic control function circuit configuration file implementing the logic control function, wherein the logic control function circuit configuration file includes description information of generating a chip select signal according to chip select information in the target circuit function and an interface protocol of the serial external memory, and the logic control function circuit configuration file is used to construct a circuit implementing the logic control function.

5. The method of claim 4, wherein each of the circuit templates is invoked to generate a circuit configuration file corresponding to each of the target circuit functions, and M circuit configuration files are obtained, including at least one of the following: ​ In a case that the chip selection signal function is included in the M target circuit functions, a chip selection signal function circuit template is invoked to generate a chip selection signal function circuit configuration file for implementing the chip selection signal function, wherein the chip selection signal function circuit configuration file generates a target chip selection signal based on the chip selection signal, a hardware chip selection signal and a software chip selection signal, and the chip selection signal function circuit template is used to construct a circuit for implementing the chip selection signal function. In a case that the indirect read-write function is included in the M target circuit functions, a sending buffer function circuit template and a receiving buffer function circuit template are invoked to generate a sending buffer function circuit configuration file for implementing a sending buffer function and a receiving buffer function circuit configuration file for implementing a receiving buffer function, wherein the sending buffer function circuit configuration file is used to buffer write data of a circuit bus, the receiving buffer function circuit configuration file is used to buffer read data of the circuit bus, the sending buffer function circuit template is used to construct a circuit for implementing the sending buffer function, and the receiving buffer function circuit template is used to construct a circuit for implementing the receiving buffer function. In a case that the sending shift function is included in the M target circuit functions, a sending shift function circuit template is invoked to generate a sending shift function circuit configuration file for implementing the sending shift function, wherein the sending shift function circuit configuration file is used to convert the write data into an output signal of a serial interface according to an interface protocol of the serial external memory, and the sending shift function circuit template is used to construct a circuit for implementing the sending shift function. In a case that the receiving shift function is included in the M target circuit functions, a receiving shift function circuit template is invoked to generate a receiving shift function circuit configuration file for implementing the receiving shift function, wherein the receiving shift function circuit configuration file is used to convert an input signal of a serial interface into the read data according to the interface protocol of the serial external memory, and the receiving shift function circuit template is used to construct a circuit for implementing the receiving shift function.

6. The method of claim 1, wherein the M circuit configuration files are integrated to obtain a target circuit configuration file, including: invoking a top-level circuit template to read M functional modules in the M circuit configuration files; and integrating the M functional modules based on integration rules in the top-level circuit template to obtain the target circuit configuration file, wherein the integration rules are used to describe a connection manner between each of the functional modules.

7. The method of claim 1, wherein after the M circuit configuration files are integrated to obtain the target circuit configuration file, the method further includes: invoking a constraint template file to generate a target constraint file of the target circuit based on a composition and a connection manner of the target circuit, wherein the constraint template file is used to describe general constraint settings of a circuit, including timing constraint settings, input-output constraint settings and clock constraint settings of the target circuit, and the target constraint file is used to describe timing constraints, input-output constraints and clock constraints in the target circuit. ​ ​ 8. An apparatus for generating circuit configuration files, comprising: a first generating module configured to generate a configuration requirement file based on an obtained circuit configuration requirement, wherein the configuration requirement file comprises N circuit functions and circuit configuration states of each of the circuit functions, and N is a natural number greater than or equal to 1; a first traversing module configured to traverse the configuration requirement file to determine M target circuit functions from the configuration requirement file, wherein the circuit configuration states of the M target circuit functions are all allowed configuration states, and M is a natural number less than or equal to N; a first searching module configured to search for a circuit template matched with each of the target circuit functions to obtain M circuit templates; a first generating module configured to call each of the circuit templates to generate a circuit configuration file corresponding to each of the target circuit functions to obtain M circuit configuration files, wherein the circuit configuration file is used to configure a circuit to implement the target circuit function; a first integrating module configured to integrate the M circuit configuration files to obtain a target circuit configuration file, wherein the target circuit configuration file is used to configure a target circuit to respond to the circuit configuration requirement. A computer readable storage medium stores a computer program, wherein the computer program is executed by a processor to implement the steps of the method in any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that, The processor executes the computer program to implement the steps of the method in any one of claims 1 to 7.

10. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, ​

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