Signal processing circuit, drive circuit and display device

Abstract

This application provides a signal processing circuit, a driving circuit, and a display device. The gate driving circuit includes a first gate driving unit. The signal processing circuit is configured to receive a first enable signal, a first clock signal output by a power management chip, and a second clock signal. When the first enable signal is at a first level, the first clock signal is output to the first gate driving unit, and when the first enable signal is at a second level, the second clock signal is output to the first gate driving unit. The second level is different from the first level. Thus, by adding a signal processing circuit between the power management chip and the gate driving circuit, the first clock signal and the second clock signal are selectively output to the first gate driving unit via the signal processing circuit. The first gate driving unit outputs different gate driving signals under the action of the first clock signal and the second clock signal, which is beneficial for the gate driving circuit to output multiple gate driving signals in different sequences.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a signal processing circuit, a driving circuit, and a display device. Background Technology

[0002] Currently, display devices include a display panel, a gate driving circuit, and a source driver. When the display device is in operation, the gate driving circuit sequentially outputs multiple gate driving signals to multiple scan lines on the display panel to select the scan lines sequentially. For a selected scan line, the data signal output by the source driver is transmitted to the corresponding pixel via the data lines of the display panel. However, the sequential output of multiple gate driving signals by the gate driving circuit makes it difficult to meet the needs of the display panel for different scanning methods. Summary of the Invention

[0003] This application provides a signal processing circuit, a driving circuit, and a display device, which facilitates the gate driving circuit to output multiple gate driving signals in different sequences, thereby at least partially solving the above-mentioned technical problems.

[0004] To achieve the above objectives, according to a first aspect of the embodiments of this application, a signal processing circuit is provided. The signal processing circuit is connected between a power management chip and a gate driving circuit, the gate driving circuit including a first gate driving unit. The signal processing circuit is configured to receive a first enable signal, a first clock signal output by the power management chip, and a second clock signal, and to output the first clock signal to the first gate driving unit when the first enable signal is at a first level, and to output the second clock signal to the first gate driving unit when the first enable signal is at a second level; wherein the second level is different from the first level.

[0005] Optionally, the signal processing circuit includes a first output circuit and a second output circuit. The first output circuit is configured to output the first clock signal in response to the first enable signal. The second output circuit is configured to output the second clock signal in response to a second enable signal, the phase of the second enable signal being opposite to the phase of the first enable signal.

[0006] Optionally, the first output circuit includes a first transistor, the first transistor including a first terminal, a second terminal, and a gate, the first terminal of the first transistor being configured to receive the first clock signal, the second terminal of the first transistor being the output terminal of the first output circuit, and the gate of the first transistor being configured to receive the first enable signal; and / or,

[0007] The second output circuit includes a second transistor, which includes a first terminal, a second terminal, and a gate. The first terminal of the second transistor is configured to receive the second clock signal, the second terminal of the second transistor is the output terminal of the second output circuit, and the gate of the second transistor is configured to receive the second enable signal.

[0008] Optionally, the signal processing circuit further includes a first inverting circuit. The first inverting circuit is configured to receive the first enable signal and output the second enable signal generated by inverting the first enable signal to the second output circuit.

[0009] Optionally, the signal processing circuit further includes at least one of a first voltage clamping circuit and a second voltage clamping circuit. The first voltage clamping circuit is configured to receive the first enable signal and clamp the first enable signal at a first clamping level before outputting it to the first output circuit. The second voltage clamping circuit is configured to receive the second enable signal and clamp the second enable signal at a second clamping level before outputting it to the second output circuit.

[0010] Optionally, the first voltage clamping circuit includes a first clamping diode, and the second voltage clamping circuit includes a second clamping diode.

[0011] Optionally, the signal processing circuit further includes: a first output control circuit, including a first current limiting element and a first pull-down power signal terminal, wherein the current limiting element is connected between the output terminal of the first output circuit and the first pull-down power signal terminal, and between the output terminal of the second output circuit and the first pull-down power signal terminal; and / or,

[0012] The second output control circuit includes a first decoupling element and a ground terminal. The first decoupling element is connected between the output terminal of the first output circuit and the ground terminal, and between the output terminal of the second output circuit and the ground terminal.

[0013] Optionally, the gate driving circuit further includes a second gate driving unit, and the signal processing circuit is further configured to output the second clock signal to the second gate driving unit when the first enable signal is at a first level, and to output the first clock signal to the second gate driving unit when the first enable signal is at a second level.

[0014] Secondly, embodiments of this application provide a driving circuit. The driving circuit includes the signal processing circuit of the first aspect.

[0015] Thirdly, embodiments of this application provide a display device, which includes a driving circuit and a display panel as described in the second aspect.

[0016] In some embodiments of the signal processing circuit, driving circuit, and display device of this application, by adding a signal processing circuit between the power management chip and the gate driving circuit, the first clock signal and the second clock signal are selectively output to the first gate driving unit via the signal processing circuit. Thus, the first gate driving unit outputs different gate driving signals under the action of the first clock signal and the second clock signal, which facilitates the gate driving circuit to output multiple gate driving signals in different sequences, meeting the display device's requirements for different scanning modes. Attached Figure Description

[0017] Figure 1 A schematic diagram of a gate driving circuit in a display device provided in an embodiment of this application, wherein multiple gate driving signals are output in a first sequence;

[0018] Figure 2 A schematic diagram of a gate driving circuit in a display device provided in an embodiment of this application, wherein multiple gate driving signals are output in a second order;

[0019] Figure 3 A signal timing diagram for a display device provided in this application where the gate driving circuit outputs multiple gate driving signals in a first sequence;

[0020] Figure 4 A signal timing diagram for a display device provided in this application where the gate driving circuit outputs multiple gate driving signals in a second order;

[0021] Figure 5 Provided for the embodiments of this application Figure 1 A schematic diagram of the structure of the first signal processing circuit in the middle;

[0022] Figure 6 Provided for the embodiments of this application Figure 1 Another schematic diagram of the first signal processing circuit in the middle;

[0023] Figure 7 Provided for the embodiments of this application Figure 1 A schematic diagram of a second signal processing circuit in the middle;

[0024] Figure 8 Provided for the embodiments of this application Figure 1 Another schematic diagram of the second signal processing circuit.

[0025] Explanation of reference numerals in the attached figures:

[0026] EN, first enable signal; iEN, second enable signal;

[0027] CLK1, first clock signal; CLK2, second clock signal;

[0028] 10. Signal processing circuit;

[0029] 100. Signal switching circuit;

[0030] 10A, First signal processing circuit;

[0031] 101, First output circuit; M1, First transistor;

[0032] 102, Second output circuit; M2, Second transistor;

[0033] 103. First inverting circuit;

[0034] 104. First voltage clamping circuit; 1041. First clamping diode;

[0035] 105. Second voltage clamping circuit; 1051. Second clamping diode;

[0036] 106. First output control circuit; 1061. First current limiting element; 1062. First pull-down power signal terminal;

[0037] 107. Second output control circuit; 1071. First decoupling element; 1072. Ground terminal;

[0038] 10B. Second signal processing circuit;

[0039] 111, Third output circuit; M3, Third transistor;

[0040] 112. Fourth output circuit; M4. Fourth transistor;

[0041] 113. Second inverting circuit;

[0042] 114. Third voltage clamping circuit; 1141. Third clamping diode;

[0043] 115. Fourth voltage clamping circuit; 1151. Fourth clamping diode;

[0044] 116. Third output control circuit; 1161. Second current limiting element; 1162. Second pull-down power signal terminal;

[0045] 117. Fourth output control circuit; 1171. Second decoupling element;

[0046] 20. Power management chip;

[0047] 30. Gate driving circuit; 301. First gate driving unit; 302. Second gate driving unit;

[0048] 40. Timing controller;

[0049] 50. Display panel; 60. Display device; 70. Drive circuit. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0051] Figure 1 This is a schematic diagram of a gate driving circuit in a display device provided in an embodiment of the present application, in which multiple gate driving signals are output in a first sequence. Figure 2 This is a schematic diagram of a display device provided in this application where the gate driving circuit outputs multiple gate driving signals in a second order. Figure 3 This is a signal timing diagram of a display device provided in this application where the gate driving circuit outputs multiple gate driving signals in a first order. Figure 4 This is a signal timing diagram of a display device provided in this application where the gate driving circuit outputs multiple gate driving signals in a second order.

[0052] like Figure 1 and Figure 2 As shown, the signal processing circuit 10 is connected between the power management chip 20 and the gate drive circuit 30.

[0053] The power management chip 20 is configured to output clock signals CK1 to CKm. Clock signals CK1 to CKm include clock signals CK1 to CTi and clock signals CK(i+1) to CKm. i is an integer greater than 1. m is an integer greater than (i+1). Any two of clock signals CK1 to CKm can be the first clock signal CLK1 and the second clock signal CLK2, respectively.

[0054] In some embodiments, m can be any one of 4, 6, 8, 10, and 12.

[0055] The gate driving circuit 30 includes gate driving units GOA1 to GOA(n). Gate driving units GOA1 to GOA(n) include gate driving units GOA1 to GOAi and gate driving units GOA(i+1) to GOA(n). n is an integer greater than (i+1). Gate driving unit GOA1 is configured to output a gate driving signal G1. GOAi is configured to output a gate driving signal Gi. GOA(i+1) is configured to output a gate driving signal G(i+1). GOA(m) is configured to output a gate driving signal G(m). GOA(n) is configured to output a gate driving signal G(n). Any two of the gate driving units GOA1 to GOA(n) can be a first gate driving unit 301 and a second gate driving unit 302, respectively.

[0056] In some embodiments, each of the gate driving units GOA1 to GOA(n) may include an output unit (not shown) and an output control unit (not shown). The output control unit is configured to adjust the potential of the control node. The output unit is configured to output a received clock signal as a gate driving signal in response to the potential of the control node.

[0057] In one exemplary embodiment, the output unit may include an output transistor, the gate of which is connected to a control node, one of the source and drain of the output transistor receiving a clock signal, and the other of the source and drain of the output transistor being connected to the output terminal of the gate driving unit.

[0058] In one exemplary embodiment, the output control unit may include an output control transistor. One of the source and drain terminals and the gate of the output control transistor may receive a transmission signal, and the other of the source and drain terminals of the output control transistor is connected to a control node.

[0059] In some embodiments, each of the gate driving units GOA1 to GOA(n) may further include a pull-down sustaining unit. The pull-down sustaining unit may employ a conventional design, which will not be described in detail here.

[0060] like Figures 1 to 4 As shown, the signal processing circuit 10 is configured to receive a first enable signal EN, a first clock signal CLK1 output by the power management chip 20, and a second clock signal CLK2. When the first enable signal EN is at a first level, the first clock signal CLK1 is output to the first gate driving unit 301, and when the first enable signal EN is at a second level, the second clock signal CLK2 is output to the first gate driving unit 301. The second level is different from the first level.

[0061] In the signal processing circuit 10 provided in this embodiment, by adding a signal processing circuit 10 between the power management chip 20 and the gate driving circuit 30, the first clock signal CLK1 and the second clock signal CLK2 are selectively output to the first gate driving unit 301 via the signal processing circuit 10. Thus, the first gate driving unit 301 outputs different gate driving signals under the action of the first clock signal CLK1 and the second clock signal CLK2, which facilitates the gate driving circuit 30 to output multiple gate driving signals in different sequences, satisfying the requirements of the display device 60 for different scanning modes.

[0062] In some embodiments, such as Figures 1 to 4 As shown, the signal processing circuit 10 is also configured to output the second clock signal CLK2 to the second gate driving unit 302 when the first enable signal EN is at the first level, and to output the first clock signal CLK1 to the second gate driving unit 302 when the first enable signal EN is at the second level.

[0063] like Figure 1 As shown, in the signal processing circuit 10 provided in this embodiment, when the first enable signal EN is at a first level, the signal processing circuit 10 outputs the first clock signal CLK1 to the first gate driving unit 301 and the second clock signal CLK2 to the second gate driving unit 302. In this case, the gate driving circuit 30 outputs multiple gate driving signals in a first order. The process of the gate driving circuit 30 outputting multiple gate driving signals in the first order includes: the first gate driving unit 301 outputs the corresponding gate driving signal before the second gate driving unit 302.

[0064] like Figure 2 As shown, when the first enable signal EN is at the second level, the signal processing circuit 10 outputs the second clock signal CLK2 to the first gate driving unit 301 and the first clock signal CLK1 to the second gate driving unit 302. In this case, the gate driving circuit outputs multiple gate driving signals in a second order. The process of the gate driving circuit outputting multiple gate driving signals in a second order includes: the second gate driving unit 302 may output the corresponding gate driving signal before the first gate driving unit 301.

[0065] Therefore, in response to the first enable signal EN, the signal processing circuit 10 outputs the first clock signal CLK1 and the second clock signal CLK2 interchangeably to the first gate driving unit 301 and the second gate driving unit 302, so that the first gate driving unit 301 and the second gate driving unit 302 can output two gate driving signals in two different orders. Therefore, the gate driving circuit 30 can output multiple gate driving signals in two different orders.

[0066] It should be noted that when the gate driving circuit outputs multiple gate driving signals in a first order and a second order respectively, the display device can realize two different display modes. For example, when the gate driving circuit outputs multiple gate driving signals in a first order, the display device realizes the main frequency display mode; and when the gate driving circuit outputs multiple gate driving signals in a second order, the display device realizes the frequency multiplication display mode.

[0067] In one exemplary embodiment, the first clock signal CLK1 is CTi, and the second clock signal CLK2 is CK(i+1). Furthermore, the first gate driving unit 301 is the gate driving unit GOAi, and the second gate driving unit 302 is the gate driving unit GOA(i+1).

[0068] like Figure 1 and Figure 3 As shown, after the power management chip 20 outputs clock signals CTi and CK(i+1), the signal processing circuit 10 responds to the first level by outputting clock signal CTi to the gate driving unit GOAi and clock signal CK(i+1) to the gate driving unit GOA(i+1). When the gate driving unit GOAi outputs gate driving signal Gi under the action of clock signal CTi, the gate driving unit GOA(i+1) outputs gate driving signal G(i+1) under the action of clock signal CK(i+1). Since the high level of clock signal CTi is output before the high level of clock signal CK(i+1), the gate driving signal Gi is also output before the gate driving signal G(i+1).

[0069] like Figure 2 and Figure 4 As shown, after the power management chip 20 outputs clock signals CTi and CK(i+1), the signal processing circuit 10 responds to the second level by outputting clock signal CTi to the gate driving unit GOA(i+1). When clock signal CK(i+1) is output to the gate driving unit GOAi, the gate driving unit GOAi outputs gate driving signal Gi under the action of clock signal CK(i+1), and the gate driving unit GOA(i+1) outputs gate driving signal G(i+1) under the action of clock signal CTi. Since clock signal CTi is output before clock signal CK(i+1), gate driving signal G(i+1) is also output before gate driving signal Gi.

[0070] It should be noted that, for Figure 1 and Figure 2The gate drive circuit outputs multiple gate drive signals. Since the high level of clock signal CK1 is output before the high level of clock signals CK(i) and CK(i+1), the gate drive signal G(1) is output before the gate drive signals Gi and G(i+1). Furthermore, since the high level of clock signal CKm is output after the high level of clock signals CK(i) and CK(i+1), the gate drive signal Gm is output after the gate drive signals Gi and G(i+1).

[0071] The first enable signal EN can be output from the output port of the timing controller 40. The output port includes, but is not limited to, a general purpose input output (GPIO) port. In some embodiments, the first level can be a high level of the first enable signal EN, and the second level can be a low level of the first enable signal EN.

[0072] Figure 5 This is a schematic diagram of a first signal processing circuit provided in an embodiment of this application. Figure 6 This is another schematic diagram of the structure of the first signal processing circuit provided in the embodiments of this application.

[0073] In some embodiments, such as Figure 1 , Figure 2 as well as Figure 5 As shown, the signal processing circuit 10 includes a first signal processing circuit 10A. The first signal processing circuit 10A includes a first output circuit 101 and a second output circuit 102. The first output circuit 101 is configured to output a first clock signal CLK1 in response to a first enable signal EN. The second output circuit 102 is configured to output a second clock signal CLK2 in response to a second enable signal iEN. The phase of the second enable signal iEN is opposite to the phase of the first enable signal EN. Thus, the first output circuit 101 and the second output circuit 102 respond to two enable signals with opposite phases to selectively output one of the first clock signal CLK1 and the second clock signal CLK2.

[0074] Specifically, when the first enable signal EN is at the first level, the second enable signal iEN is at the third level. The phase of the third level can be the same as the phase of the second level, and the phase of the third level can be opposite to the phase of the first level. When the first enable signal EN is at the second level, the second enable signal iEN is at the fourth level, and the phase of the fourth level is opposite to the phase of the third level.

[0075] In some embodiments, such as Figure 6As shown, the first output circuit 101 includes a first transistor M1. The first transistor M1 includes a first terminal, a second terminal, and a gate. The first terminal of the first transistor M1 is configured to receive a first clock signal CLK1. The second terminal of the first transistor M1 is the output terminal of the first output circuit 101. The gate of the first transistor M1 is configured to receive a first enable signal EN. Thus, the first enable signal EN controls the on / off state of the first transistor M1, thereby controlling whether the first clock signal CLK1 is output.

[0076] In some embodiments, such as Figure 6 As shown, the second output circuit 102 includes a second transistor M2. The second transistor M2 includes a first terminal, a second terminal, and a gate. The first terminal of the second transistor M2 is configured to receive a second clock signal CLK2. The second terminal of the second transistor M2 is the output terminal of the second output circuit 102. The gate of the second transistor M2 is configured to receive a second enable signal iEN. Thus, the second enable signal iEN controls the on / off state of the second transistor M2, thereby controlling whether the first clock signal CLK1 is output.

[0077] For the first signal processing circuit 10A, when the first enable signal EN is at the first level, the first transistor M1 is turned on and the second transistor M2 is turned off, and the first clock signal CLK1 is output to the first gate driving unit 301 through the first transistor M1. Similarly, when the first enable signal EN is at the second level, the first transistor M1 is turned off and the second transistor M2 is turned on, and the second clock signal CLK2 is output to the first gate driving unit 301 through the second transistor M2.

[0078] In some embodiments, the first transistor M1 and the second transistor M2 can be the same to ensure that the conduction characteristics of the first transistor M1 and the second transistor M2 are the same, and to ensure that the time when the first clock signal CLK1 is output through the first transistor M1 is the same or close to the same as the time when the second clock signal CLK2 is output through the second transistor M2, thereby reducing the risk that the gate drive circuit 30 will output an abnormal gate drive signal due to a large time difference between the output of the first clock signal CLK1 and the second clock signal CLK2.

[0079] In some embodiments, the first transistor M1 and the second transistor M2 can both be field-effect transistors (FETs). The FETs can be selected from either N-type metal-oxide-semiconductor (MMOS) FETs or P-type MMOS FETs.

[0080] In one example embodiment, the first transistor M1 and the second transistor M2 can both be N-type metal-oxide-semiconductor field-effect transistors.

[0081] In some embodiments, such as Figure 5and Figure 6 As shown, the signal processing circuit 10 further includes a first inverting circuit 103. The first inverting circuit 103 is configured to receive a first enable signal EN and output a second enable signal iEN generated by inverting the first enable signal EN to the second output circuit 102. Thus, the second enable signal iEN is obtained by inverting the first enable signal EN.

[0082] In some embodiments, the input terminal of the first inverter circuit 103 receives a first enable signal EN, and the output terminal of the first inverter circuit 103 is connected to the gate of the second transistor M2. In some embodiments, the first inverter circuit 103 may include a CMOS inverter, but is not limited thereto.

[0083] In some embodiments, such as Figure 5 As shown, the signal processing circuit 10 may further include at least one of a first voltage clamping circuit 104 and a second voltage clamping circuit 105. The first voltage clamping circuit 104 is configured to receive a first enable signal EN and clamp the first enable signal EN to a first clamping level before outputting it to the first output circuit 101. The second voltage clamping circuit 105 is configured to receive a second enable signal iEN and clamp the second enable signal iEN to a second clamping level before outputting it to the second output circuit 102. Thus, the first voltage clamping circuit 104 can clamp the first enable signal EN to a first clamping level to ensure that the first enable signal EN input to the first output circuit 101 is stable, thereby ensuring that the first output circuit 101 can stably output the first clock signal CLK1. Similarly, the second voltage clamping circuit 105 can clamp the second enable signal iEN to a second clamping level to ensure that the second enable signal iEN input to the second output circuit 102 is stable, thereby ensuring that the second output circuit 102 can stably output the second clock signal CLK2.

[0084] In some embodiments, such as Figure 6 As shown, the first voltage clamping circuit 104 includes a first clamping diode 1041, and the second voltage clamping circuit 105 includes a second clamping diode 1051. Since both the first clock signal CLK1 and the second clock signal CLK2 are high-frequency AC signals, using the first clamping diode 1041 and the second clamping diode 1051 for clamping reduces the risk of damage to the two clamping diodes under the influence of high-frequency AC signals. Furthermore, the first clamping diode 1041 and the second clamping diode 1051 can precisely limit the voltage to the first clamping level and the second clamping level. In addition, in the clamped state, the first clamping diode 1041 and the second clamping diode 1051 do not consume additional power, reducing the power consumption of the signal processing circuit.

[0085] In one exemplary embodiment, such as Figure 6 As shown, the cathode of the first clamping diode 1041 is connected to the timing controller 40 to receive the first enable signal EN. The anode of the first clamping diode 1041 is connected to the gate of the first transistor M1. The cathode of the second clamping diode 1051 is connected to the output terminal of the first inverter circuit 103, and the anode of the second clamping diode 1051 is connected to the gate of the second transistor M2.

[0086] In some embodiments, the first clamping diode 1041 and the second clamping diode 1051 can be the same. In this way, the first enable signal EN is the same level after being clamped by the first clamping diode 1041 when it is the first level, and the same level after being clamped by the second clamping diode 1051 when it is the third level when it is the second enable signal iEN. This is beneficial because the first output circuit and the second output circuit can be controlled to output the corresponding clock signal under the same clamping level.

[0087] In some embodiments, such as Figure 5 As shown, the signal processing circuit 10 also includes a first output control circuit 106. The first output control circuit 106 pulls down the low level of the clock signal output by the first output circuit 101 or the second output circuit 102 to a preset low level, so as to ensure that the low level of the clock signal output by the first signal processing circuit 10A remains basically unchanged.

[0088] In some embodiments, such as Figure 6 As shown, the first output control circuit 106 includes a first current limiting element 1061 and a first pull-down power signal terminal 1062. The first current limiting element 1061 is connected between the output terminal of the first output circuit 101 and the first pull-down power signal terminal 1062, and between the output terminal of the second output circuit 102 and the first pull-down power signal terminal 1062.

[0089] In some embodiments, the first current limiting element 1061 may include, but is not limited to, the first resistor, to ensure that the first current limiting element 1061 plays a current limiting role and reduce the risk of component burnout in the signal processing circuit 10.

[0090] In some embodiments, the resistance value of the first resistor can be from 1kΩ to 30kΩ to ensure that the first resistor functions as a current limiter. For example, the resistance value of the first resistor can be 10kΩ.

[0091] In some embodiments, the preset low level input to the first pull-down power signal terminal 1062 can be the same as the low level of the first clock signal CLK1 and the second clock signal CLK2, so as to ensure that the low level of the clock signal output by the first signal processing circuit 10A remains basically unchanged.

[0092] In some embodiments, such as Figure 5As shown, the first signal processing circuit 10A also includes a second output control circuit 107. The second output control circuit 107 is used to improve the output delay problem of the first output circuit 101 and the second output circuit 102, and to reduce the loss of the first clock signal CLK1 output by the first output circuit 101 and the second clock signal CLK2 output by the second output circuit 102 during transmission.

[0093] In some embodiments, such as Figure 6 As shown, the second output control circuit 107 includes a first decoupling element 1071 and a ground terminal 1072. The first decoupling element 1071 is connected between the output terminal of the first output circuit 101 and the ground terminal 1072, and between the output terminal of the second output circuit 102 and the ground terminal 1072. Thus, the first decoupling element 1071 helps ensure that the first output circuit 101 smoothly outputs the first clock signal CLK1, and ensures that the second output circuit 102 smoothly outputs the second clock signal CLK2, thus ensuring the stability of the first clock signal CLK1 or the second clock signal CLK2.

[0094] In some embodiments, the first decoupling element 1071 may include a first capacitor. One electrode of the first capacitor is connected to a ground terminal 1072, and the other electrode of the first capacitor may be connected to the output terminal of the first output circuit 101 and the output terminal of the second output circuit 102.

[0095] Figure 7 This is a schematic diagram of a second signal processing circuit provided in an embodiment of this application. Figure 8 This is another schematic diagram of the structure of the second signal processing circuit provided in the embodiments of this application.

[0096] In some embodiments, such as Figure 1 , Figure 2 as well as Figure 7 As shown, the signal processing circuit 10 further includes a second signal processing circuit 10B. When the first signal processing circuit 10A outputs a first clock signal CLK1 in response to a first enable signal, the second signal processing circuit 10B outputs a second clock signal CLK2 in response to the first enable signal. When the first signal processing circuit 10A outputs the second clock signal CLK2 in response to the first enable signal, the second signal processing circuit 10B outputs the first clock signal CLK1 in response to the first enable signal. One first signal processing circuit 10A and one second signal processing circuit 10B constitute a signal switching circuit 100. For each signal switching circuit 100, the first clock signal CLK1 and the second clock signal CLK2 can be interchangeably output to two different gate driving units.

[0097] It is understood that the signal processing circuit 10 may include two or more signal switching circuits 100, each of which can switchably output two different clock signals to two different gate driving units.

[0098] In some embodiments, such as Figure 1 , Figure 2 as well as Figure 7 As shown, the second signal processing circuit 10B includes a third output circuit 111 and a fourth output circuit 112. The third output circuit 111 is configured to output a second clock signal CLK2 in response to a first enable signal EN. The fourth output circuit 112 is configured to output a first clock signal CLK1 in response to a second enable signal EN. Thus, the third output circuit 111 and the fourth output circuit 112 respond to two enable signals with opposite phases to selectively output the other of the first clock signal CLK1 and the second clock signal CLK2.

[0099] In some embodiments, such as Figure 8 As shown, the third output circuit 111 includes a third transistor M3. The third transistor M3 includes a first terminal, a second terminal, and a gate. The first terminal of the third transistor M3 is configured to receive the second clock signal CLK2. The second terminal of the third transistor M3 is the output terminal of the third output circuit 111. The gate of the third transistor M3 is configured to receive a first enable signal EN. Thus, the first enable signal EN controls the on / off state of the third transistor M3, thereby controlling whether the second clock signal CLK2 is output.

[0100] In some embodiments, such as Figure 8 As shown, the fourth output circuit 112 includes a fourth transistor M4. The fourth transistor M4 includes a first terminal, a second terminal, and a gate. The first terminal of the fourth transistor M4 is configured to receive a first clock signal CLK1. The second terminal of the fourth transistor M4 is the output terminal of the fourth output circuit 112. The gate of the fourth transistor M4 is configured to receive a second enable signal iEN. Thus, the second enable signal iEN controls the on / off state of the fourth transistor M4, thereby controlling whether the second clock signal CLK2 is output.

[0101] For the second signal processing circuit 10B, when the first enable signal EN is at the first level, the third transistor M3 is turned on and the fourth transistor M4 is turned off, and the second clock signal CLK2 is output to the second gate driving unit 302 through the third transistor M3. Similarly, when the first enable signal EN is at the second level, the third transistor M3 is turned off and the fourth transistor M4 is turned on, and the first clock signal CLK1 is output to the second gate driving unit 302 through the fourth transistor M4.

[0102] In some embodiments, the third transistor M3 and the fourth transistor M4 can be the same to ensure that the conduction characteristics of the third transistor M3 and the fourth transistor M4 are the same, and to ensure that the time when the second clock signal CLK2 is output through the third transistor M3 is the same as or close to the same as the time when the first clock signal CLK1 is output through the fourth transistor M4. This reduces the risk that the gate drive circuit 30 will output an abnormal gate drive signal due to a large time difference between the output of the second clock signal CLK2 and the first clock signal CLK1.

[0103] In some embodiments, the third transistor M3 may be the same as the second transistor M2 to ensure that the conduction characteristics of the third transistor M3 and the second transistor M2 are the same, and to ensure that the second clock signal CLK2 is output at the same or similar time through the third transistor M3 and the second transistor M2.

[0104] In some embodiments, the fourth transistor M4 may be the same as the first transistor M1 to ensure that the fourth transistor M4 and the first transistor M1 have the same conduction characteristics, and to ensure that the first clock signal CLK1 is output at the same or similar time through the first transistor M1 and the fourth transistor M4.

[0105] In some embodiments, the third transistor M3 and the fourth transistor M4 can both be field-effect transistors (FETs). The FETs can be selected from either N-type metal-oxide-semiconductor (MMOS) FETs or P-type MMOS FETs.

[0106] In one example embodiment, the third transistor M3 and the fourth transistor M4 can both be N-type metal-oxide-semiconductor field-effect transistors.

[0107] In some embodiments, such as Figure 7 As shown, the second signal processing circuit 10B further includes a second inverting circuit 113. The second inverting circuit 113 is configured to receive a first enable signal EN and output a second enable signal iEN generated by inverting the first enable signal EN to the fourth output circuit 112. Thus, the second enable signal iEN is obtained by inverting the first enable signal EN.

[0108] In some embodiments, the design of the second inverter circuit 113 may be the same as that of the first inverter circuit 103. The second inverter circuit 113 may include a CMOS inverter, but is not limited thereto.

[0109] In some embodiments, such as Figure 7As shown, the second signal processing circuit 10B may further include at least one of a third voltage clamping circuit 114 and a fourth voltage clamping circuit 115. The third voltage clamping circuit 114 is configured to receive a first enable signal EN, clamp the first enable signal EN at a third clamping level, and then output it to the third output circuit 111. The fourth voltage clamping circuit 115 is configured to receive a second enable signal iEN, clamp the second enable signal iEN at a fourth clamping level, and then output it to the fourth output circuit 112. Thus, the third voltage clamping circuit 114 can clamp the first enable signal EN to the third clamping level to ensure that the first enable signal EN input to the third output circuit 111 is stable, thereby ensuring that the third output circuit 111 can stably output the second clock signal CLK2. Similarly, the fourth voltage clamping circuit 115 can clamp the second enable signal iEN to the fourth clamping level to ensure that the second enable signal iEN input to the fourth output circuit 112 is stable, thereby ensuring that the fourth output circuit 112 can stably output the first clock signal CLK1.

[0110] In some embodiments, such as Figure 8 As shown, the third voltage clamping circuit 114 includes a third clamping diode 1141, and the fourth voltage clamping circuit 115 includes a fourth clamping diode 1151. Since both the first clock signal CLK1 and the second clock signal CLK2 are high-frequency AC signals, using the third clamping diode 1141 and the fourth clamping diode 1151 for clamping reduces the risk of damage to the two clamping diodes under the influence of high-frequency AC signals. Furthermore, the third clamping diode 1141 and the fourth clamping diode 1151 can precisely limit the voltage to the third clamping level and the fourth clamping level, respectively. In addition, in the clamped state, the third clamping diode 1141 and the fourth clamping diode 1151 do not consume additional power.

[0111] In some embodiments, the third clamping diode 1141 and the fourth clamping diode 1151 can be the same. Thus, the first enable signal EN, when clamped by the third clamping diode 1141, is at a first level, and its level is the same as or nearly the same as the second enable signal iEN, when clamped by the fourth clamping diode 1151, at a third level. This allows the third and fourth output circuits to be controlled by the same clamping level to output corresponding clock signals.

[0112] In some embodiments, the third clamping diode 1141 can be the same as the first clamping diode 1041. Thus, the first enable signal EN, after being clamped by both the third clamping diode 1141 and the first clamping diode 1041, has the same or nearly the same level. This facilitates the synchronous output of the corresponding clock signals by the first output circuit 101 and the third output circuit 111, and consequently, the synchronous output of the corresponding clock signals by the first signal processing circuit and the second signal processing circuit.

[0113] In some embodiments, the fourth clamping diode 1151 and the second clamping diode 1051 can be the same. The second enable signal iEN is clamped by the second clamping diode 1051 and the fourth clamping diode 1151, respectively, and the level is the same or tends to be the same. This is beneficial for the second output circuit 102 and the fourth output circuit 112 to output the corresponding clock signal synchronously, and thus it is beneficial for the first signal processing circuit and the second signal processing circuit to output the corresponding clock signal synchronously.

[0114] In some embodiments, such as Figure 7 As shown, the signal processing circuit 10 also includes a third output control circuit 116. The third output control circuit 116 pulls down the low level of the clock signal output by the third output circuit 111 or the fourth output circuit 112 to a preset low level, so as to ensure that the second signal processing circuit 10B stably outputs a low level of the clock signal.

[0115] In some embodiments, such as Figure 8 As shown, the third output control circuit 116 includes a second current limiting element 1161 and a second pull-down power signal terminal 1162. The second current limiting element 1161 is connected between the output terminal of the third output circuit 111 and the second pull-down power signal terminal 1162, and between the output terminal of the third output circuit 111 and the second pull-down power signal terminal 1162.

[0116] In some embodiments, the second pull-down power signal terminal 1162 may be the same as the first pull-down power signal terminal 1062. In some embodiments, the signal input to the second pull-down power signal terminal 1162 may be the same as the low level of the first clock signal CLK1 and the second clock signal CLK2.

[0117] In some embodiments, the second current limiting element 1161 may include, but is not limited to, a second resistor, to ensure that the first current limiting element 1061 performs its current limiting function and reduce the risk of component burnout in the signal processing circuit 10.

[0118] In some embodiments, the second resistor can be the same as the first resistor to ensure that the first resistor and the second resistor have the same current-limiting effect.

[0119] In some embodiments, the resistance value of the second resistor can be from 1kΩ to 30kΩ to ensure that the second resistor functions as a current limiter. For example, the resistance value of the second resistor can be 10kΩ.

[0120] In some embodiments, such as Figure 7 As shown, the second signal processing circuit 10B also includes a fourth output control circuit 117. The fourth output control circuit 117 is used to improve the output delay problem of the third output circuit 111 and the fourth output circuit 112, and reduce the loss of the clock signals output by the third output circuit 111 and the fourth output circuit 112 during transmission.

[0121] In some embodiments, such as Figure 8 As shown, the fourth output control circuit 117 includes a second decoupling element 1171 and a ground terminal 1072. The second decoupling element 1171 is connected between the output terminal of the third output circuit 111 and the ground terminal 1072, and between the output terminal of the fourth output circuit 112 and the ground terminal 1072. Thus, the second decoupling element 1171 helps ensure that the third output circuit 111 smoothly outputs the first clock signal CLK1, and ensures that the fourth output circuit 112 smoothly outputs the second clock signal CLK2, thus ensuring the stability of the first clock signal CLK1 or the second clock signal CLK2.

[0122] In some embodiments, the second decoupling element 1171 may include a second capacitor. One electrode of the second capacitor is connected to the ground terminal 1072, and the other electrode of the second capacitor may be connected to the output terminal of the third output circuit 111 and the output terminal of the fourth output circuit 112.

[0123] Based on the same inventive concept, such as Figure 1 and Figure 2 As shown in the figure, this application embodiment also provides a driving circuit 70. The driving circuit 70 includes a signal processing circuit 10, a power management chip 20, a timing controller 40, and a gate driving circuit 30.

[0124] In addition to outputting clock signals CK1 to CKm, power management chip 20 can also output start signals, etc. Timing controller 40 is configured to output the first enable signal EN.

[0125] Based on the same inventive concept, such as Figure 1 and Figure 2 As shown, this application embodiment also provides a display device 60. The display device 60 can be any one of a liquid crystal display device, an organic light-emitting diode display device, a micro light-emitting diode display device, and a sub-millimeter light-emitting diode display device. The display device 60 includes the above-described driving circuit and a display panel 50.

[0126] like Figure 1 and Figure 2 As shown, the gate drive circuit 30 can be integrated onto the display panel 50 to improve the integration of the display panel 50 and simplify the manufacturing process of the display device 60.

[0127] In some embodiments, the signal processing circuit 10 may also be integrated on the display panel 50 to improve the integration of the display panel 50 and simplify the manufacturing process of the display device 60.

[0128] In some embodiments, the display device 60 may further include a circuit board (not shown). The power management chip 20 and the timing controller 40 may both be located on the circuit board. In some embodiments, the circuit board may include, but is not limited to, a printed circuit board.

[0129] In some embodiments, the signal processing circuit 10 is located on a circuit board to reduce the difficulty of forming the signal processing circuit 10.

[0130] In summary, in the signal processing circuit, driving circuit, and display device of some embodiments of this application, by adding a signal processing circuit between the power management chip and the gate driving circuit, the first clock signal and the second clock signal are selectively output to the first gate driving unit via the signal processing circuit. Thus, the first gate driving unit outputs different gate driving signals under the action of the first clock signal and the second clock signal respectively, which is beneficial for the gate driving circuit to output multiple gate driving signals in different sequences, meeting the display device's requirements for different scanning modes.

[0131] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A signal processing circuit, characterized in that, The signal processing circuit is connected between the power management chip and the gate driving circuit, and the gate driving circuit includes a first gate driving unit and a second gate driving unit. The signal processing circuit is configured to receive a first enable signal, a first clock signal output by the power management chip, and a second clock signal. The signal processing circuit includes a first output circuit and a second output circuit. The first output circuit is configured to output the first clock signal in response to the first enable signal, and the second output circuit is configured to output the second clock signal in response to the second enable signal. The phase of the second enable signal is opposite to the phase of the first enable signal. When the first enable signal is at a first level, the signal processing circuit outputs the first clock signal to the first gate driving unit and the second clock signal to the second gate driving unit. The gate driving circuit outputs a plurality of gate driving signals in a first order, the first order including: the first gate driving unit outputs the corresponding gate driving signal before the second gate driving unit. When the first enable signal is at the second level, the signal processing circuit outputs the second clock signal to the first gate driving unit and outputs the first clock signal to the second gate driving unit. The gate driving circuit outputs a plurality of gate driving signals in a second order, the second order including: the second gate driving unit outputs the corresponding gate driving signal before the first gate driving unit. The second level is different from the first level.

2. The signal processing circuit according to claim 1, characterized in that, The first output circuit includes a first transistor, which includes a first terminal, a second terminal, and a gate. The first terminal of the first transistor is configured to receive the first clock signal, the second terminal of the first transistor is the output terminal of the first output circuit, and the gate of the first transistor is configured to receive the first enable signal. And / or, The second output circuit includes a second transistor, which includes a first terminal, a second terminal, and a gate. The first terminal of the second transistor is configured to receive the second clock signal, the second terminal of the second transistor is the output terminal of the second output circuit, and the gate of the second transistor is configured to receive the second enable signal.

3. The signal processing circuit according to claim 1, characterized in that, Also includes: A first inverting circuit is configured to receive the first enable signal and output the second enable signal generated by inverting the first enable signal to the second output circuit.

4. The signal processing circuit according to claim 1, characterized in that, It also includes at least one of a first voltage clamping circuit and a second voltage clamping circuit; the first voltage clamping circuit is configured to receive the first enable signal and clamp the first enable signal at a first clamping level before outputting it to the first output circuit; The second voltage clamping circuit is configured to receive the second enable signal and clamp the second enable signal at a second clamping level before outputting it to the second output circuit.

5. The signal processing circuit according to claim 4, characterized in that, The first voltage clamping circuit includes a first clamping diode, and the second voltage clamping circuit includes a second clamping diode.

6. The signal processing circuit according to any one of claims 1 to 5, characterized in that, Also includes: A first output control circuit includes a first current-limiting element and a first pull-down power signal terminal. The first current-limiting element is connected between the output terminal of the first output circuit and the first pull-down power signal terminal, and between the output terminal of the second output circuit and the first pull-down power signal terminal; and / or The second output control circuit includes a first decoupling element and a ground terminal. The first decoupling element is connected between the output terminal of the first output circuit and the ground terminal, and between the output terminal of the second output circuit and the ground terminal.

7. A driving circuit, characterized in that, Includes the signal processing circuit as described in any one of claims 1 to 6.

8. A display device, characterized in that, It includes the driving circuit and display panel as described in claim 7.

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