Light-emitting device, photoelectric conversion device, and electronic apparatus

Abstract

The invention provides a light-emitting device, a photoelectric conversion device, and an electronic apparatus. The light emitting device includes: a first pixel circuit and a second pixel circuit; a signal line configured to supply a pixel signal to the first pixel circuit and the second pixel circuit; and a first transistor connected to the signal line. Each of the first pixel circuit and the second pixel circuit includes: a light emitting element; a second transistor disposed on a path through which a current for causing the light emitting element to emit light flows; and a third transistor connected to a control terminal of the second transistor. A third transistor of each of the first pixel circuit and the second pixel circuit is connected to the signal line via the first transistor.

Description

Technical Field

[0001] The present invention relates to a light emitting device, a photoelectric conversion device and an electronic device. Background Art

[0002] An active matrix display device in which a driving transistor for controlling the current flowing to a light-emitting element is arranged in a pixel circuit is under development. In the display device described in Japanese Patent Laid-Open No. 2010-145579, each of a plurality of pixel circuits forming a pixel column is connected to a signal line. As the number of transistors connected to the signal line increases, the load capacitance of the signal line also increases. If the load capacitance of the signal line is large, the potential settling time of the signal line increases, and it becomes difficult to write a signal in the pixel circuit at high speed and accurately. Summary of the invention

[0003] Some aspects of the present disclosure reduce the load capacitance of the signal line. According to some embodiments, a light-emitting device is provided, including: a first pixel circuit and a second pixel circuit; a signal line configured to supply a pixel signal to the first pixel circuit and the second pixel circuit; and a first transistor connected to the signal line, wherein the first pixel circuit and the second pixel circuit each include: a light-emitting element, a second transistor arranged on a path for a current to flow for causing the light-emitting element to emit light, and a third transistor connected to a control terminal of the second transistor, and the third transistor of each of the first pixel circuit and the second pixel circuit is connected to the signal line via the first transistor.

[0004] Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram for explaining an example of the arrangement of the light emitting device according to the first embodiment;

[0006] Figure 2 is a circuit diagram for explaining an example of the arrangement of a pixel circuit according to the first embodiment;

[0007] Figure 3 is a timing chart for explaining an example of the operation of the light emitting device according to the first embodiment;

[0008] Figure 4 is a timing chart for explaining another example of the operation of the light emitting device according to the first embodiment;

[0009] Figure 5 is a circuit diagram for explaining an example of the arrangement of a pixel circuit according to the second embodiment;

[0010] Figure 6 is a timing chart for explaining an example of the operation of the light emitting device according to the second embodiment;

[0011] Figure 7 is a block diagram for explaining an example of the arrangement of a light emitting device according to a third embodiment;

[0012] Figure 8 is a timing chart for explaining an example of the operation of the light emitting device according to the third embodiment;

[0013] Fig. 9 is a circuit diagram for explaining an example of the arrangement of a pixel circuit according to a fourth embodiment;

[0014] Fig.10 is a timing chart for explaining an example of the operation of the light emitting device according to the fourth embodiment;

[0015] Fig.11 is a diagram showing an example of a display device using the light emitting device according to the embodiment;

[0016] Fig. 12A is a diagram showing an example of a photoelectric conversion device using the light emitting device according to the embodiment;

[0017] Fig. 12B is a diagram showing an example of an electronic device using the light emitting device according to the embodiment;

[0018] Fig.13A and Fig. 13B are diagrams each showing an example of a display device using the light emitting device according to the embodiment;

[0019] Fig.14A is a diagram showing an example of a lighting device using the light emitting device according to the embodiment;

[0020] Fig. 14B is a diagram showing an example of a moving object using the light emitting device according to the embodiment; and

[0021] Fig.15A and Fig. 15B 2 are diagrams each showing an example of a wearable device using the light emitting device according to the embodiment. DETAILED DESCRIPTION

[0022] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments are not intended to limit the scope of the claimed invention. A plurality of features are described in the embodiments, but are not limited to an invention requiring all such features, and a plurality of such features may be appropriately combined. In addition, in the accompanying drawings, the same reference numerals are given to the same or similar structures, and redundant descriptions thereof are omitted.

[0023] <First embodiment>

[0024] refer to Figure 1 , an example of the arrangement of the light emitting device 100 according to the first embodiment will be described. As will be described later, the light emitting device 100 can be used in a display device. For example, the light emitting device 100 can be used in a flat (or flat panel) display device.

[0025] The light emitting device 100 may include a plurality of pixel circuits 101, a vertical scanning circuit 103, a signal output circuit 104, and a control circuit 105. The plurality of pixel circuits 101 are two-dimensionally arranged in a pixel array section 102 (that is, in a manner of forming a plurality of pixel rows and a plurality of pixel columns). The pixel rows may be Figure 1 A row is formed by a plurality of pixels arranged in a row direction (horizontal direction). A pixel column can be Figure 1 In the example, a column is formed by a plurality of pixels arranged in a column direction (vertical direction). A plurality of pixel circuits 101 may be arranged one-dimensionally. Figure 1 In the example shown, a plurality of pixel circuits 101 are arranged in 2m rows and n columns (m and n are integers of 1 or greater). For one pixel column, the i-th pixel circuit 101 from the signal output circuit 104 is referred to as a pixel circuit 101_i (i is an integer from 1 to 2m). The pixel circuit 101 may be referred to as a pixel for short. Figure 1 In order to simplify the description, a case where the number of pixel rows included in the pixel array section 102 is an even number will be described. Alternatively, the number of pixel rows included in the pixel array section 102 may be an odd number.

[0026] A plurality of pixel circuits 101 included in each pixel column form a pixel block 108. Figure 1 In the example in which each pixel block 108 is formed by two adjacent pixel circuits 101 arranged in the column direction (that is, the extension direction of the signal line 107) will be described. For one pixel column, the i-th pixel block 108 from the signal output circuit 104 is referred to as pixel block 108_i (i is an integer from 1 to m). Each pixel block 108 may be formed by three or more than three pixel circuits 101. The pixel circuits 101 included in the same pixel block 108 may be continuous or may not be continuous. For example, the pixel circuits 101 in the first row and the pixel circuits 101 in the third row may form a pixel block 108, and the pixel circuits 101 in the second row may not be included in the pixel block 108. In addition, one pixel block 108 may include pixel circuits 101 included in different pixel columns.

[0027] The number of pixel circuits 101 included in the pixel block 108 may be the same or different in the entire pixel array section 102. For example, the number of pixel circuits 101 included in the pixel block 108 may be changed for each region of the pixel array section 102. In addition, pixel circuits 101 that do not form the pixel block 108 may be included in the pixel array section 102. For example, the pixel block 108 may be arranged only in some regions of the pixel array section 102.

[0028] In the pixel array section 102, m scan lines 106_1 to 106_m are arranged, each extending in the row direction. In the following description, the plurality of scan lines 106_1 to 106_m are collectively referred to as scan lines 106. The description of the scan line 106 may apply to any scan line in one or more scan lines 106_1 to 106_m. The scan line 106 may represent any scan line in one or more scan lines 106-1 to 106-m, or a specific scan line determined by the context. This also applies to other constituent elements collectively referred to below. As will be described later, a scan line 106 may be divided into a plurality of scan lines. Each scan line 106 connects the vertical scanning circuit 103 with each pixel block in the plurality of pixel blocks 108 included in the corresponding row. The vertical scanning circuit 103 supplies a scanning signal to each pixel block 108 via a scanning line 106, thereby switching each of the plurality of transistors included in each pixel block 108 between ON (conduction) (that is, a conducting state) and OFF (disconnection) (that is, a non-conducting state). The operation of the vertical scanning circuit 103 is controlled by a control circuit 105.

[0029] In the pixel array section 102, n signal lines 107_1 to 107_n are arranged, each extending in the column direction. In the following description, the plurality of signal lines 107_1 to 107_n are collectively referred to as signal lines 107. Each signal line 107 connects the signal output circuit 104 to each pixel block in the plurality of pixel blocks 108 included in the corresponding column. The signal output circuit 104 supplies the pixel signal to each pixel circuit 101 included in each pixel block 108 via the signal line 107. The pixel signal may have a signal potential Vsig corresponding to the brightness information. The pixel signal may be referred to as an image signal when the light-emitting device 100 displays an image, and may be referred to as a video signal when the light-emitting device 100 displays a video. The operation of the signal output circuit 104 is controlled by the control circuit 105.

[0030] refer to Figure 2, an example of the arrangement of the pixel block 108 will be described. The pixel block 108 is formed by two pixel circuits 101a and 101b adjacent to each other in the column direction, and a block transistor 210. The pixel circuit 101a and the pixel circuit 101b may have the same arrangement or different arrangements. Each pixel circuit in the two pixel circuits 101a and 101b may be connected to Figure 1 For example, the pixel circuit 101a may correspond to the pixel circuit 101 included in the odd pixel row, and the pixel circuit 101b may correspond to the pixel circuit 101 included in the even pixel row. The following description of the pixel circuit 101 is applicable to each of the two pixel circuits 101a and 101b.

[0031] The scan line 106 arranged for the pixel block 108 is divided into two write scan lines 209a and 209b and one block scan line 211. The write scan line 209a is arranged for each odd pixel row. The write scan line 209b is arranged for each even pixel row. The block scan line 211 is arranged for each row of the pixel block 108. The vertical scanning circuit 103 can also be divided corresponding to the two write scan lines 209a and 209b and the one block scan line 211.

[0032] The pixel circuit 101 may include a light-emitting element 201, a driving transistor 202, a writing transistor 203, and a capacitor 204. The light-emitting element 201 may be a current-driven electro-optical element whose light-emitting brightness changes according to the amount of current flowing through the light-emitting element 201. The light-emitting element 201 may be, for example, a light-emitting diode (LED) or an organic electroluminescent (EL) element. The light-emitting element 201 may include an anode and a cathode. The cathode of the light-emitting element 201 is connected to a power line 206. The power line 206 is arranged in common for a plurality of pixel circuits 101. A power supply potential VSS is supplied to the power line 206. Figure 2 In the example shown, all transistors included in the pixel circuit 101 are p-channel transistors. Alternatively, a part or all of the transistors included in the pixel circuit 101 may be n-channel transistors.

[0033] The driving transistor 202 is a transistor configured to adjust the amount of current flowing through the light emitting element 201. The current flowing through the light emitting element 201 may also be referred to as a driving current. Since the light emitting element 201 emits light when the driving current flows through the light emitting element 201, the driving current is a current that causes the light emitting element 201 to emit light. The driving transistor 202 is arranged on a path where the driving current flows (in Figure 2 In the example shown, on a path from the power supply line 205 through the driving transistor 202 and the light emitting element 201 to the power supply line 206). Figure 2In the example shown, one of the two main terminals of the driving transistor 202 (e.g., the drain) is connected to the anode of the light emitting element 201. The other of the two main terminals of the driving transistor 202 (e.g., the source) is connected to the power supply line 205. The power supply line 205 is arranged in common for a plurality of pixel circuits 101. A power supply potential VDD is supplied to the power supply line 205. The power supply potential VDD supplied to the power supply line 205 may be higher than the potential VSS supplied to the power supply line 206.

[0034] The write transistor 203 is a transistor configured to switch whether to write a pixel signal supplied from the signal output circuit 104 to the pixel circuit 101 via the signal line 107 in the gate of the drive transistor 202. The gate of the drive transistor 202 serves as a control terminal of the drive transistor 202. This also applies to the gates of other transistors in this specification. The write transistor 203 is arranged on a path connecting the signal line 107 and the gate of the drive transistor 202. The gate of the write transistor 203 of the pixel circuit 101a is connected to the write scan line 209a. The gate of the write transistor 203 of the pixel circuit 101b is connected to the write scan line 209b. One of the two main terminals of the write transistor 203 (e.g., the source) is connected to the signal line 107 via the block transistor 210. The other of the two main terminals of the write transistor 203 (e.g., the drain) is connected to the gate of the drive transistor 202.

[0035] The capacitor 204 is a capacitor configured to hold the gate-source voltage of the drive transistor 202. The capacitor 204 connects the gate of the drive transistor 202 and the source of the drive transistor 202.

[0036] As explained above, in Figure 2 In the circuit arrangement shown, the gate of the drive transistor 202, one main terminal (e.g., drain) of the write transistor 203, and one electrode of the capacitor 204 are connected to the same node 207. One main terminal (e.g., source) of the drive transistor 202, one electrode of the capacitor 204, and the power supply line 205 are connected to the same node 208.

[0037] One of the two main terminals of the block transistor 210 (e.g., source) is connected to the signal line 107. The other of the two main terminals of the block transistor 210 (e.g., drain) is connected to one of the main electrodes (e.g., source) of the write transistor 203 of the pixel circuit 101a. In addition, the other of the two main terminals of the block transistor 210 (e.g., drain) is also connected to one of the main electrodes (e.g., source) of the write transistor 203 of the pixel circuit 101b. The gate of the block transistor 210 is connected to the block scan line 211.

[0038] When the block transistor 210 is ON and the write transistor 203 of the pixel circuit 101a is ON, the pixel signal supplied via the signal line 107 is written into the capacitor 204 of the pixel circuit 101a. On the other hand, when the block transistor 210 is ON but the write transistor 203 of the pixel circuit 101a is OFF, the pixel signal supplied via the signal line 107 is not written into the capacitor 204 of the pixel circuit 101a. This also applies to the writing of the pixel signal in the capacitor 204 of the pixel circuit 101b.

[0039] In the main terminal (for example, source) of the transistor connected to the signal line 107, there is parasitic capacitance to the back gate and the like. Figure 1 and Figure 2 In the light emitting device 100, the number of transistors (more specifically, the source thereof) connected to one signal line 107 is half the number of pixel rows (for example, 2m) (that is, m as the number of block transistors 210). As a result, the load capacitance of the signal line 107 is reduced compared to the case where the write transistor 203 (more specifically, the source thereof) of each pixel circuit 101 is directly connected to the signal line 107. Therefore, the potential settling time of the signal line 107 is reduced, and the signal can be written in the pixel circuit 101 at high speed and accurately.

[0040] The capacitance of the block transistor 210 may be smaller than the capacitance of the write transistor 203 of each pixel circuit in the pixel circuit 101a and the pixel circuit 101b. In this case, the load capacitance of the signal line 107 may be further reduced. The thickness of the gate insulating film of the block transistor 210 may be greater than the thickness of the gate insulating film of the write transistor 203 of each pixel circuit in the pixel circuit 101a and the pixel circuit 101b. The area of ​​the substrate surface occupied by the block transistor 210 may be smaller than the area of ​​the substrate surface occupied by the write transistor 203 of each pixel circuit in the pixel circuit 101a and the pixel circuit 101b. The area of ​​the substrate surface occupied by the transistor may be the total area of ​​two impurity regions serving as the source and gate of the transistor, respectively, and a region in which a channel is formed, in a plan view relative to the substrate surface.

[0041] refer to Figure 3 , an example of the operation of the light emitting device 100 will be described. This operation can be performed when the control circuit 105 controls the vertical scanning circuit 103 to change the potential of the scanning line 106 and controls the signal output circuit 104 to change the potential of the signal line 107. Figure 3The timing diagram shows changes in the potential of the signal line 107, the write scan lines 209_1 to 209_4, and the block scan lines 211_1 and 211_2. The write scan line 209_i (i is an integer of 1 or more) is arranged from the signal output circuit 104 for the i-th pixel row. The block scan line 211_i (i is an integer of 1 or more) is arranged from the signal output circuit 104 for the row of the i-th pixel block 108_i. The write transistor 203 of the pixel circuit 101_2i-1 included in the (2i-1)-th pixel row and the write transistor 203 of the pixel circuit 101_2i included in the (2i)-th pixel row are connected to the block transistor 210 included in the pixel block 108_i. For example, the write transistor 203 of the pixel circuit 101_1 included in the first pixel row and the write transistor 203 of the pixel circuit 101_2 included in the second pixel row are connected to the block transistor 210 included in the pixel block 108_1. In the following description, an operation for a specific pixel column included in the pixel array section 102 will be described. Similar operations are performed for other pixel columns included in the pixel array section 102.

[0042] because Figure 2 All transistors included in the illustrated pixel block 108 are p-type transistors, and thus each of these transistors becomes conductive when a low-level signal is supplied to the gate, and becomes off when a high-level signal is supplied to the gate. Figure 2 Some or all of the transistors included in the illustrated pixel block 108 may be n-type transistors.

[0043] exist Figure 3 In the example shown, one frame time period ends at time t1, and the next frame time period starts from time t1. The frame time period may be a time period during which the control circuit 105 controls the light emitting state of the light emitting element 201 of each pixel circuit in all pixel circuits 101 included in the pixel array section 102 to represent one frame. One frame time period includes a plurality of horizontal time periods. The horizontal time period may be a time period during which the control circuit 105 controls the light emitting state of the light emitting element 201 of each pixel circuit in all pixel circuits 101 included in one pixel row to represent one row of one frame. The time from the beginning of the frame time period (e.g., t1) until the switching of the potential may be a preset value.

[0044] At the time immediately before the time t1, a high-level signal is supplied to each of the write scan line 209 and the block scan line 211. Therefore, the write transistor 203 included in each pixel circuit 101 and the block transistor 210 included in each pixel block 108 are OFF.

[0045] At time t1, the signal output circuit 104 switches the value of the pixel signal supplied to the signal line 107 to the signal potential Vsig_1. The signal potential Vsig_1 has a value corresponding to the brightness of the light to be emitted by the light emitting element 201 of the pixel circuit 101_1. The potential of the signal line 107 settles at the signal potential Vsig_1 according to a time constant corresponding to the load of the signal line 107.

[0046] At time t2, the vertical scanning circuit 103 switches the potential of the write scanning line 209_1 and the potential of the block scanning line 211_1 from a high level to a low level. As a result, the write transistor 203 of the pixel circuit 101_1 and the block transistor 210 included in the pixel block 108_1 become conductive. Thus, the signal potential Vsig_1 is written into the capacitor element 204 of the pixel circuit 101_1, and the light-emitting element 201 of the pixel circuit 101_1 emits light with a brightness corresponding to the signal potential Vsig_1. Since the write transistor 203 of the pixel circuit 101_2 is OFF, the signal potential Vsig_1 is not written into the capacitor element 204 of the pixel circuit 101_2.

[0047] At time t3, the vertical scanning circuit 103 switches the potential of the write scanning line 209_1 and the potential of the block scanning line 211_1 from a low level to a high level. As a result, the write transistor 203 of the pixel circuit 101_1 and the block transistor 210 included in the pixel block 108_1 become off. After that, the capacitor 204 of the pixel circuit 101_1 continues to hold the signal potential Vsig_1.

[0048] At time t4, the signal output circuit 104 switches the value of the pixel signal supplied to the signal line 107 to the signal potential Vsig_2. The signal potential Vsig_2 has a value corresponding to the brightness of the light to be emitted by the light emitting element 201 of the pixel circuit 101_2. The potential of the signal line 107 settles at the signal potential Vsig_2 according to a time constant corresponding to the load of the signal line 107.

[0049] At time t5, the vertical scanning circuit 103 switches the potential of the write scanning line 209_2 and the potential of the block scanning line 211_1 from a high level to a low level. As a result, the write transistor 203 of the pixel circuit 101_2 and the block transistor 210 included in the pixel block 108_1 become conductive. Thus, the signal potential Vsig_2 is written into the capacitor element 204 of the pixel circuit 101_2, and the light-emitting element 201 of the pixel circuit 101_2 emits light with a brightness corresponding to the signal potential Vsig_2. Since the write transistor 203 of the pixel circuit 101_1 is OFF, the signal potential Vsig_2 is not written into the capacitor element 204 of the pixel circuit 101_1.

[0050] At time t6, the vertical scanning circuit 103 switches the potential of the write scanning line 209_2 and the potential of the block scanning line 211_1 from a low level to a high level. As a result, the write transistor 203 of the pixel circuit 101_2 and the block transistor 210 included in the pixel block 108_1 become off. After that, the capacitor 204 of the pixel circuit 101_2 continues to maintain the signal potential Vsig_2.

[0051] When the control circuit 105 performs an operation similar to the operation performed from time t1 to time t4 for the block scan line 211_2 from time t7 to time t10, the signal potential Vsig_3 is written in the capacitor element 204 of the pixel circuit 101_3. When the control circuit 105 performs an operation similar to the operation performed from time t4 to time t7 for the block scan line 211_2 from time t11 to time t13, the signal potential Vsig_4 is written in the capacitor element 204 of the pixel circuit 101_4. Similarly, in the fifth pixel row to the last pixel row, the signal potential is written in the capacitor element 204 of the pixel circuit 101. When the processing ends for the last pixel row, one frame period ends.

[0052] exist Figure 3 In the illustrated operation, the pixel rows included in the pixel array section 102 are scanned for each row. Alternatively, the pixel rows included in the pixel array section 102 may be scanned for a plurality of rows. Furthermore, as in interlaced driving, a combination of pixel rows that changes for each frame may be scanned.

[0053] exist Figure 3 In the operation shown, the write transistor 203 and the block transistor 210 are turned on at the same time, and turned off at the same time. The operation using the vertical scanning circuit 103 is not limited to this. For example, the vertical scanning circuit 103 can write a pixel signal in the gate of the drive transistor 202 of the pixel circuit 101a by overlapping the time period when the block transistor 210 is ON and the time period when the write transistor 203 of the pixel circuit 101a is ON. As described above, during the time period when both the block transistor 210 and the write transistor 203 of the pixel circuit 101a are ON, the vertical scanning circuit 103 keeps the write transistor 203 of the pixel circuit 101b OFF. Thus, the pixel signal to be written in the pixel circuit 101a can be suppressed from being written in the pixel circuit 101b. Writing a pixel signal in the gate of the drive transistor 202 of the pixel circuit 101b can be similar to writing a pixel signal in the gate of the drive transistor 202 of the pixel circuit 101a as described above.

[0054] From the state where both the block transistor 210 and the write transistor 203 of the pixel circuit 101a are ON, the vertical scanning circuit 103 can turn off the block transistor 210 after turning off the write transistor 203 of the pixel circuit 101a. In other words, from the state where both the block transistor 210 and the write transistor 203 of the pixel circuit 101a are turned on, the vertical scanning circuit 103 can turn off the write transistor 203 of the pixel circuit 101a while keeping the block transistor 210 ON. Thus, it is possible to suppress the degradation of signal accuracy due to the influence of field penetration when turning off the write transistor 203 and field penetration when turning off the block transistor 210. The timing of turning off the write transistor 203 of the pixel circuit 101b can be similar to the timing of turning off the write transistor 203 of the above-mentioned pixel circuit 101a.

[0055] refer to Figure 4 , another example of the operation of the light emitting device 100 will be described. Figure 4 The operations shown are similar to Figure 3 The operation shown differs in the timing of switching the signals supplied to the block scan lines 211_1 and 211_2. The rest can be the same as Figure 3 The same as shown in the operation.

[0056] The vertical scanning circuit 103 switches the potential of the block scanning line 211_1 from a high level to a low level at time t1, and switches it from a low level to a high level at time t7. Thus, from time t1 to time t7, the block transistor 210 included in the pixel block 108_1 becomes conductive. Therefore, when the vertical scanning circuit 103 switches the potential of the write scanning line 209_1 from a high level to a low level at time t2, the signal potential Vsig_1 is written into the capacitor element 204 of the pixel circuit 101_1. Then, when the vertical scanning circuit 103 switches the potential of the write scanning line 209_2 from a high level to a low level at time t5, the signal potential Vsig_2 is written into the capacitor element 204 of the pixel circuit 101_2.

[0057] When the control circuit 105 performs an operation similar to the operation performed from time t1 to time t4 for the block scan line 211_2 from time t7 to time t10, the signal potential Vsig_3 is written in the capacitor element 204 of the pixel circuit 101_3. When the control circuit 105 performs an operation similar to the operation performed from time t4 to time t7 for the block scan line 211_2 from time t11 to time t13, the signal potential Vsig_4 is written in the capacitor element 204 of the pixel circuit 101_4. Similarly, in the fifth pixel row to the last pixel row, the signal potential is written in the capacitor element 204 of the pixel circuit 101. When the processing ends to the last pixel row, one frame period ends.

[0058] <Second embodiment>

[0059] refer to Figure 5 , an example of the arrangement of the light emitting device 100 according to the second embodiment will be described. The light emitting device 100 according to the second embodiment is different from the light emitting device 100 according to the first embodiment in that the pixel circuit 101 further includes a light emission control transistor 501 and a capacitor 502, and the scan line 106 further includes light emission scan lines 503a and 503b. The rest may be the same as in the first embodiment.

[0060] The light emission control transistor 501 is a transistor configured to switch whether or not to cause the light emitting element 201 to emit light. Figure 5 In the example shown, the light emission control transistor 501 is a p-type transistor. Alternatively, the light emission control transistor 501 may be an n-type transistor. The light emission control transistor 501 is arranged on a path where a driving current flows. Figure 5 In the example shown, the light emission control transistor 501 is arranged on a path connecting the source of the driving transistor 202 and the power supply line 205. More specifically, one of the two main terminals of the light emission control transistor 501 (e.g., the drain) is connected to the source of the driving transistor 202. The other of the two main terminals of the light emission control transistor 501 (e.g., the source) is connected to the power supply line 205. The gate of the light emission control transistor 501 of the pixel circuit 101a is connected to the light emission control line 503a. The gate of the light emission control transistor 501 of the pixel circuit 101b is connected to the light emission scanning line 503b.

[0061] The capacitor 502 connects the source of the light emission control transistor 501 and the drain of the light emission control transistor 501. The light emission scanning line 503a is arranged for each odd-numbered pixel row, and the light emission scanning line 503b is arranged for each even-numbered pixel row.

[0062] refer to Figure 6, an example of the operation of the light emitting device 100 according to the second embodiment will be described. This operation can be performed when the control circuit 105 controls the vertical scanning circuit 103 to change the potential of the scanning line 106 and controls the signal output circuit 104 to change the potential of the signal line 107. Figure 3 In addition to the timing diagram, Figure 6 The timing diagram also shows changes in the potential of the light emitting scan lines 503_1 to 503_4. The light emitting scan line 503_i (i is an integer of 1 or more) is arranged for the i-th pixel row from the signal output circuit 104. In the following description, an operation for a specific pixel column included in the pixel array section 102 will be described. Similar operations are performed for other pixel columns included in the pixel array section 102.

[0063] At a time immediately before time t1, a high-level signal is supplied to each of the write scan line 209 and the block scan line 211. Therefore, the write transistor 203 included in each pixel circuit 101 and the block transistor 210 included in each pixel block 108 are OFF. At a time immediately before time t1, a low-level signal is supplied to each light emission scan line 503. Therefore, the light emission control transistor 501 included in each pixel circuit 101 is ON.

[0064] At time t1, the signal output circuit 104 switches the value of the pixel signal supplied to the signal line 107 to the reference potential Vref. The reference potential Vref may have a value that is independent of the brightness signal. The potential of the signal line 107 settles at the reference potential Vref according to a time constant corresponding to the load of the signal line 107. In addition, at time t1, the vertical scanning circuit 103 switches the potential of the light emission scanning line 503_1 from a low level to a high level. As a result, the light emission control transistor 501 of the pixel circuit 101_1 becomes off.

[0065] At time t2, the vertical scanning circuit 103 switches the potential of the write scanning line 209_1 and the potential of the block scanning line 211_1 from a high level to a low level. As a result, the write transistor 203 of the pixel circuit 101_1 and the block transistor 210 included in the pixel block 108_1 become conductive. Thus, the potential of the gate of the driving transistor 202 of the pixel circuit 101_1 is set to the reference potential Vref. However, since the light emission control transistor 501 of the pixel circuit 101_1 is OFF, the driving current does not flow.

[0066] During the time period from time t3 to time t4, the vertical scanning circuit 103 temporarily turns on the light emission control transistor 501 of the pixel circuit 101_1. Thus, the source of the driving transistor 202 of the pixel circuit 101_1 is connected to the power line 205, and the driving current flows. When the light emission control transistor 501 is turned off, the potential of the source of the driving transistor 202 decreases with the passage of time. The decrease ends when the gate-source voltage of the driving transistor 202 reaches approximately the threshold voltage of the driving transistor 202. Thus, the threshold voltage of the driving transistor 202 is maintained in the capacitor 204.

[0067] The control circuit 105 performs the same operation from time t4 to time t7. Figure 3 In the operation similar to the operation from time t1 to time t4 in FIG. 1 , the signal potential Vsig_1 is written into the capacitor 204 of the pixel circuit 101_1. In the period from time t4 to time t7, the light emission control transistor 501 of the pixel circuit 101_1 remains OFF. Therefore, the light emitting element 201 of the pixel circuit 101_1 does not emit light.

[0068] At time t7, the signal output circuit 104 switches the value of the pixel signal supplied to the signal line 107 to the reference potential Vref. The potential of the signal line 107 is static at the signal potential Vref according to the time constant corresponding to the load of the signal line 107. In addition, at time t7, the vertical scanning circuit 103 switches the potential of the light-emitting scanning line 503_1 from a high level to a low level. As a result, the light-emitting control transistor 501 of the pixel circuit 101_1 becomes turned on. Thus, the light-emitting element 201 of the pixel circuit 101_1 emits light with a brightness corresponding to the signal potential Vsig_1. In addition, at time t7, the vertical scanning circuit 103 switches the potential of the light-emitting scanning line 503_2 from a low level to a high level. As a result, the light-emitting control transistor 501 of the pixel circuit 101_2 becomes turned off.

[0069] At time t8, the vertical scanning circuit 103 switches the potential of the write scanning line 209_2 and the potential of the block scanning line 211_1 from a high level to a low level. As a result, the write transistor 203 of the pixel circuit 101_2 and the block transistor 210 included in the pixel block 108_1 become conductive. Thus, the potential of the gate of the driving transistor 202 of the pixel circuit 101_2 is set to the reference potential Vref. However, since the light emission control transistor 501 of the pixel circuit 101_2 is OFF, the driving current does not flow.

[0070] During the time period from time t8 to time t9, the vertical scanning circuit 103 temporarily turns on the light emission control transistor 501 of the pixel circuit 101_2. Thus, the source of the driving transistor 202 of the pixel circuit 101_2 is connected to the power line 205, and the driving current flows. When the light emission control transistor 501 is turned off, the potential of the source of the driving transistor 202 decreases over time. The decrease ends when the gate-source voltage of the driving transistor 202 approximately reaches the threshold voltage of the driving transistor 202. Thus, the threshold voltage of the driving transistor 202 is maintained in the capacitor 204.

[0071] The control circuit 105 performs the same operation from time t10 to time t13. Figure 3 In the operation similar to the operation from time t4 to time t7 in FIG. 1 , the signal potential Vsig_2 is written into the capacitor 204 of the pixel circuit 101_2. During the period from time t10 to time t13, the light emission control transistor 501 of the pixel circuit 101_2 remains OFF. Therefore, the light emitting element 201 of the pixel circuit 101_2 does not emit light.

[0072] When the control circuit 105 performs an operation similar to the operation performed from time t1 to time t7 for the block scan line 211_2 from time t13 to time t19, the signal potential Vsig_3 is written in the capacitor element 204 of the pixel circuit 101_3. When the control circuit 105 performs an operation similar to the operation performed from time t10 to time t16 for the block scan line 211_2 from time t19 to time t25, the signal potential Vsig_4 is written in the capacitor element 204 of the pixel circuit 101_4. Similarly, in the fifth pixel row to the last pixel row, the signal potential is written in the capacitor element 204 of the pixel circuit 101. When the processing ends for the last pixel row, one frame period ends.

[0073] according to Figure 6 According to the operation shown in FIG. 1 , the driving current flowing to the light emitting element 201 of the pixel circuit 101_1 from time t7 is set to a value which is based on the signal potential Vsig_1 and the capacitance ratio between the capacitor 204 and the capacitor 502, but has a reduced dependency on the threshold voltage of the driving transistor 202. As a result, the variation in the luminance of the light emitting element 201 caused by the variation in the threshold voltage between the driving transistors 202 of the plurality of pixel circuits 101 is reduced. Therefore, the quality of the image displayed by the light emitting device 100 is further improved.

[0074] Furthermore, in the second embodiment, as in the first embodiment, the load capacitance of the signal line 107 is reduced. Figure 4As in the above-described modification example, during the period of time in which the write transistors 203 of the pixel circuits 101 in one pixel block 108 are scanned, the block transistors 210 in the pixel block 108 may be kept ON.

[0075] <Third embodiment>

[0076] refer to Figure 7 and Figure 8 , an example of the arrangement of the light emitting device 100 according to the third embodiment will be described. The light emitting device 100 according to the third embodiment is different from the light emitting device 100 according to the first embodiment in that the pixel array section 102 is divided into a low-resolution area 701 and a high-resolution area 702, and the driving method is changed between these areas. The rest may be the same as in the first embodiment. The differences between the first embodiment and the third embodiment may be applied to the second embodiment.

[0077] refer to Figure 7 , an example of the arrangement of the light emitting device 100 according to the third embodiment will be described. The hardware arrangement of the light emitting device 100 according to the third embodiment is the same as that of the light emitting device 100 according to the first embodiment, but the operation of the vertical scanning circuit 103 is changed. The light emission brightness is controlled for each pixel circuit 101 in the high-resolution area 702, and the light emission brightness is controlled for each pixel block 108 in the low-resolution area 701. More specifically, in order to display one image, in the high-resolution area 702, one pixel circuit 101 emits light according to one pixel signal, and in the low-resolution area 701, two pixel circuits 101 included in one pixel block 108 emit light according to one pixel signal. As a result, in the high-resolution area 702, an image is displayed with a higher resolution than in the low-resolution area 701.

[0078] exist Figure 7 In the example shown, the low-resolution region 701 is divided into two parts to sandwich the high-resolution region 702. The layout of the low-resolution region 701 and the high-resolution region 702 is not limited to Figure 7 The high-resolution region 702 may be divided into two or more parts, or the low-resolution region 701 may include only one part. In addition, the number of pixel blocks 108 included in each of the low-resolution region 701 and the high-resolution region 702 is not limited to Figure 7 The example shown. Figure 7In the example shown, the pixel array section 102 is divided in the column direction, and the boundary between the low-resolution region 701 and the high-resolution region 702 extends in the row direction. Alternatively or additionally, the pixel array section 102 may be divided in the row direction, and the boundary between the low-resolution region 701 and the high-resolution region 702 may extend in the column direction. In this case, separate scan lines 106 may be arranged for the low-resolution region 701 and the high-resolution region 702, respectively.

[0079] refer to Figure 8 , an example of the operation of the light emitting device 100 will be described. Figure 8 The timing diagram shows changes in the potential of the signal line 107, the write scan lines 209_1 to 209_6, and the block scan lines 211_1 to 211_3. The write scan lines 209_1 to 209_4 supply scan signals to the pixel circuits 101 included in the low-resolution area 701. The write scan lines 209_5 and 209_6 supply scan signals to the pixel circuits 101 included in the high-resolution area 702. The block scan lines 211_1 and 211_2 supply scan signals to the pixel blocks 108 included in the low-resolution area 701. The block scan line 211_3 supplies scan signals to the pixel blocks 108 included in the high-resolution area 702. In the following description, operations for a specific pixel column included in the pixel array section 102 will be described. Similar operations are performed for other pixel columns included in the pixel array section 102.

[0080] At the time immediately before the time t1, a high-level signal is supplied to each of the write scan line 209 and the block scan line 211. Therefore, the write transistor 203 included in each pixel circuit 101 and the block transistor 210 included in each pixel block 108 are OFF.

[0081] Since the first pixel row is included in the low-resolution region 701, the vertical scanning circuit 103 performs an operation for scanning the low-resolution region 701 from time t1. In the operation for scanning the low-resolution region 701, light emission is controlled for each pixel block 108. The operation for scanning the low-resolution region 701 will be specifically described below.

[0082] At time t1, the signal output circuit 104 switches the value of the pixel signal supplied to the signal line 107 to the signal potential Vsig_1. The signal potential Vsig_1 has a value corresponding to the brightness of light to be emitted by the light emitting element 201 of the pixel circuit 101_1 and the light emitting element 201 of the pixel circuit 101_2 included in the second pixel row. The potential of the signal line 107 settles at the signal potential Vsig_1 according to a time constant corresponding to the load of the signal line 107.

[0083] At time t2, the vertical scanning circuit 103 switches the potential of the write scanning line 209_1, the potential of the write scanning line 209_2, and the potential of the block scanning line 211_1 from a high level to a low level. As a result, the write transistor 203 of the pixel circuit 101_1, the write transistor 203 of the pixel circuit 101_2 included in the second pixel row, and the block transistor 210 included in the pixel block 108_1 become conductive. Thus, the signal potential Vsig_1 is written into the capacitor element 204 of the pixel circuit 101_1 and the capacitor element 204 of the pixel circuit 101_2, and the light-emitting element 201 of the pixel circuit 101_1 and the light-emitting element 201 of the pixel circuit 101_2 emit light with a brightness corresponding to the signal potential Vsig_1.

[0084] At time t3, the vertical scanning circuit 103 switches the potential of the write scanning line 209_1, the potential of the write scanning line 209_2, and the potential of the block scanning line 211_1 from a low level to a high level. As a result, the write transistor 203 of the pixel circuit 101_1, the write transistor 203 of the pixel circuit 101_2, and the block transistor 210 included in the pixel block 108_1 become turned off. After that, the capacitor element 204 of the pixel circuit 101_1 and the capacitor element 204 of the pixel circuit 101_2 continue to maintain the signal potential Vsig_1.

[0085] At time t4, the signal output circuit 104 switches the value of the pixel signal supplied to the signal line 107 to the signal potential Vsig_2. The signal potential Vsig_2 has a value corresponding to the brightness of light to be emitted by the light emitting element 201 of the pixel circuit 101_3 included in the third pixel row and the light emitting element 201 of the pixel circuit 101_4 included in the fourth pixel row. The potential of the signal line 107 settles at the signal potential Vsig_2 according to a time constant corresponding to the load of the signal line 107.

[0086] The operation performed from time t5 to time t6 is similar to the operation performed from time t2 to time t3. By the operation performed from time t5 to time t6, the light emitting element 201 of the pixel circuit 101_3 and the light emitting element 201 of the pixel circuit 101_4 emit light at a brightness corresponding to the signal potential Vsig_2.

[0087] Since the third pixel row is included in the high-resolution area 702, the vertical scanning circuit 103 performs an operation for scanning the high-resolution area 702 from time t7. Through the operation for scanning the high-resolution area 702, light emission of each of the two pixel circuits 101 included in each pixel block 108 is individually controlled as in the first embodiment. Subsequently, the vertical scanning circuit 103 performs a corresponding scanning method according to whether the pixel block 108 is in the low-resolution area 701 or the high-resolution area 702 until the last pixel row. When the processing for the last pixel row ends, one frame period ends.

[0088] As has been explained above, in the third embodiment, for the pixel block 108 included in the low-resolution area 701, the vertical scanning circuit 103 overlaps the time period in which the write transistor 203 of the pixel circuit 101a is ON, the time period in which the write transistor 203 of the pixel circuit 101b is ON, and the time period in which the block transistor 210 is ON, thereby writing the signal potential Vsig to each of the control terminal of the drive transistor 202 of the pixel circuit 101a and the control terminal of the drive transistor 202 of the pixel circuit 101b. In addition, in the third embodiment, as in the first embodiment, the load capacitance of the signal line 107 is reduced.

[0089] The control circuit 105 can dynamically change the layout of the low-resolution area 701 and the high-resolution area 702 in the pixel array section 102 (hereinafter referred to as the resolution layout). The control circuit 105 can set the resolution layout according to a preset setting, can set the resolution layout according to a user instruction, or can set the resolution layout according to the characteristics of the image to be displayed. The control circuit 105 can change the resolution layout for each frame. For example, in a given frame, pixel blocks 108_1 to 108_j and pixel blocks 108_k+1 to 108_m are included in the low-resolution area 701, and pixel blocks 108_j+1 to 108_k are included in the high-resolution area 702. In another frame, pixel blocks 108_1 to 108_j+2 and pixel blocks 108_k+3 to 108_m are included in the low-resolution area 701, and pixel blocks 108_j+3 to 108_k+2 are included in the high-resolution area 702.

[0090] In a part of the pixel block 108, the block transistor 210 may be omitted, and the signal line 107 and the write transistor 203 may be directly connected. For example, the block transistor 210 included in the low-resolution region 701 may be omitted, and the block transistor 210 may be included in the high-resolution region 702. Alternatively, the block transistor 210 included in the high-resolution region 702 may be omitted, and the block transistor 210 may be included in the low-resolution region 701.

[0091] The period of time during which the block transistor 210 in the low-resolution region 701 is ON is not limited to Figure 8 For example, the block transistor 210 of the pixel block 108_1 may remain ON during a time period overlapping with time t2 to time t3 (e.g., a time period from time t1 to time t4). Alternatively, in the low-resolution region 701, the write transistor 203 may always remain ON, and the pixel circuit 101 to which the signal potential Vsig is written may be selected by switching the block transistor 210 ON / OFF. The time period during which the block transistor 210 in the high-resolution region 702 is ON is not limited to Figure 8 For example, as in the modification of the first embodiment, the block transistor 210 may be kept ON.

[0092] <Fourth embodiment>

[0093] refer to Fig. 9 and Fig.10 , an example of the arrangement of the light emitting device 100 according to the fourth embodiment will be described. The light emitting device 100 according to the fourth embodiment is different from the light emitting device 100 according to the third embodiment in that, instead of the pixel block 108, Fig. 9 The pixel block 900 shown is included in the low-resolution area 701. The remaining parts may be the same as those in the third embodiment. The modification example described in the third embodiment is also applicable to the fourth embodiment.

[0094] refer to Fig. 9 , an example of the arrangement of the pixel block 900 will be described. The pixel block 900 is formed by two pixel circuits 901a and 901b adjacent to each other in the column direction, and a block transistor 210. The pixel circuit 901a and the pixel circuit 901b may have the same arrangement or different arrangements. The pixel circuits 901a and 901b will be collectively referred to as pixel circuits 901. The following description of the pixel circuit 901 is applicable to each pixel circuit in the two pixel circuits 901a and 901b.

[0095] The pixel circuit 901 is different from the pixel circuit 101 in that the write transistor 203 is not included. Therefore, the control terminal of the drive transistor 202 is connected to the block transistor 210 without passing through other terminals. That is, the control terminal of the drive transistor 202 of the pixel circuit 901a, the control terminal of the drive transistor 202 of the pixel circuit 901b, and one of the main terminals of the block transistor 210 (for example, the drain) are connected to the same node. The light emitting device 100 does not include a write scan line for the pixel circuits 901a and 901b.

[0096] refer to Fig.10 , an example of the operation of the light emitting device 100 will be described. Fig.10 The timing diagram shows changes in the potential of the signal line 107, the write scan lines 209_1 and 209_2, and the block scan lines 211_1 to 211_3. The write scan lines 209_1 and 209_2 supply scan signals to the pixel circuit 101 included in the high-resolution area 702. The block scan lines 211_1 and 211_2 supply scan signals to the pixel block 108 included in the low-resolution area 701. The block scan line 211_3 supplies scan signals to the pixel block 108 included in the high-resolution area 702. In the following description, operations for a specific pixel column included in the pixel array section 102 will be described. Similar operations are performed for other pixel columns included in the pixel array section 102.

[0097] At the time immediately before the time t1, a high-level signal is supplied to each of the write scan line 209 and the block scan line 211. Therefore, the write transistor 203 included in each pixel circuit 101 and the block transistor 210 included in each pixel block 108 are OFF.

[0098] Since the first pixel row is included in the low-resolution region 701, the vertical scanning circuit 103 performs an operation for scanning the low-resolution region 701 from time t1. In the operation for scanning the low-resolution region 701, light emission is controlled for each pixel block 108. The operation for scanning the low-resolution region 701 will be specifically described below.

[0099] At time t1, the signal output circuit 104 switches the value of the pixel signal supplied to the signal line 107 to the signal potential Vsig_1. The signal potential Vsig_1 has a value corresponding to the brightness of light to be emitted by the light emitting element 201 of the pixel circuit 101_1 and the light emitting element 201 of the pixel circuit 101_2 included in the second pixel row. The potential of the signal line 107 settles at the signal potential Vsig_1 according to a time constant corresponding to the load of the signal line 107.

[0100] At time t2, the vertical scanning circuit 103 switches the potential of the block scanning line 211_1 from a high level to a low level. As a result, the block transistor 210 included in the pixel block 108_1 becomes conductive. Thus, the signal potential Vsig_1 is written into the capacitor element 204 of the pixel circuit 101_1 and the capacitor element 204 of the pixel circuit 101_2, and the light-emitting element 201 of the pixel circuit 101_1 and the light-emitting element 201 of the pixel circuit 101_2 emit light with a brightness corresponding to the signal potential Vsig_1.

[0101] At time t3, the vertical scanning circuit 103 switches the potential of the block scanning line 211_1 from low level to high level. As a result, the block transistor 210 included in the pixel block 108_1 becomes off. Thereafter, the capacitor 204 of the pixel circuit 101_1 and the capacitor 204 of the pixel circuit 101_2 continue to hold the signal potential Vsig_1.

[0102] At time t4, the signal output circuit 104 switches the value of the pixel signal supplied to the signal line 107 to the signal potential Vsig_2. The signal potential Vsig_2 has a value corresponding to the brightness of light to be emitted by the light emitting element 201 of the pixel circuit 101_3 included in the third pixel row and the light emitting element 201 of the pixel circuit 101_4 included in the fourth pixel row. The potential of the signal line 107 settles at the signal potential Vsig_2 according to a time constant corresponding to the load of the signal line 107.

[0103] The operation performed from time t5 to time t6 is similar to the operation performed from time t2 to time t3. By the operation performed from time t5 to time t6, the light emitting element 201 of the pixel circuit 101_3 and the light emitting element 201 of the pixel circuit 101_4 emit light at a brightness corresponding to the signal potential Vsig_2.

[0104] Since the third pixel row is included in the high-resolution area 702, the vertical scanning circuit 103 performs an operation for scanning the high-resolution area 702 from time t7. Through the operation for scanning the high-resolution area 702, light emission of each of the two pixel circuits 101 included in each pixel block 108 is individually controlled as in the first embodiment. Subsequently, the vertical scanning circuit 103 performs a corresponding scanning method according to whether the pixel block 108 is in the low-resolution area 701 or the high-resolution area 702 until the last pixel row. When the processing for the last pixel row ends, one frame period ends.

[0105] As has been explained above, in the fourth embodiment, for the pixel block 108 included in the low-resolution area 701, the vertical scanning circuit 103 turns on the block transistor 210 to write the signal potential Vsig into each of the control terminal of the drive transistor 202 of the pixel circuit 101a and the control terminal of the drive transistor 202 of the pixel circuit 101b. In addition, in the fourth embodiment, as in the first embodiment, the load capacitance of the signal line 107 is reduced.

[0106] The control circuit 105 can dynamically change the resolution layout. More specifically, the control circuit 105 can set whether the portion of the pixel array section 102 including the pixel block 900 is included in the low-resolution region 701 or the high-resolution region 702 .

[0107] <Other Examples>

[0108] Fig.11 1100 is a schematic diagram showing an example of a display device of the present embodiment. The display device 1100 may include a touch panel 1103, a display panel 1105, a frame 1106, a circuit board 1107, and a battery 1108 between an upper cover 1101 and a lower cover 1109. The touch panel 1103 and the display panel 1105 are connected to flexible printed circuits FPC 1102 and 1104, respectively. A transistor is printed on the circuit board 1107. If the display device is not a portable device, the battery 1108 may not be provided, or even if the display device is a portable device, the battery 1108 may be provided in other positions.

[0109] The display device according to the present embodiment may include red, green and blue color filters. The red, green and blue color filters may be arranged in a delta (triangle) array.

[0110] The display device according to the present embodiment can also be used for a display unit of a portable terminal. In this case, the display unit can have both a display function and an operation function. Examples of portable terminals are portable phones such as smart phones, tablet computers, and head-mounted displays.

[0111] The display device according to this embodiment can be used for the display unit of a camera device, which includes an optical unit having a plurality of lenses and an image sensor for receiving light that has passed through the optical unit. The camera device may include a display unit for displaying information acquired by the image sensor. In addition, the display unit may be a display unit exposed outside the camera device, or a display unit arranged in a viewfinder. The camera device may be a digital camera or a digital video camera.

[0112] Fig. 12A 1 is a schematic diagram showing an example of an image pickup device according to the present embodiment. The image pickup device 1200 may include a viewfinder 1201, a rear display 1202, an operation unit 1203, and a housing 1204. The viewfinder 1201 may include a display device according to the present embodiment. In this case, the display device may display not only an image to be captured but also environmental information and an image pickup instruction, etc. Examples of environmental information are the intensity and direction of external light, the moving speed of a subject, and the possibility that a subject is covered by an obstacle.

[0113] The timing suitable for video recording is a very short time, so it is preferable to display information as quickly as possible. Therefore, it is preferable to use a display device using the organic light-emitting element of the present invention. This is because the organic light-emitting element has a high response speed. A display device using an organic light-emitting element can be more preferably used for a device requiring a high display speed than a liquid crystal display device.

[0114] The camera 1200 includes an optical unit (not shown). The optical unit includes a plurality of lenses, and forms an image on an image sensor housed in the housing 1204. The focus of the plurality of lenses can be adjusted by adjusting the relative positions. This operation can also be performed automatically. The camera may be referred to as a photoelectric conversion device. Instead of sequentially capturing images, the photoelectric conversion device may include a method of detecting a difference from a previous image, or a method of extracting an image from an image that is always recorded, etc., as a camera method.

[0115] Fig. 12B 12 is a schematic diagram showing an example of an electronic device of the present embodiment. The electronic device 1250 includes a display unit 1251, an operation unit 1252, and a housing 1253. The housing 1253 can accommodate a circuit, a printed circuit board including the circuit, a battery, and a communication unit. The operation unit 1252 can be a button or a touch panel type reaction unit. The operation unit can also be a biometric authentication unit for unlocking by authenticating a fingerprint. An electronic device including a communication unit can also be considered a communication device. The electronic device can also have a camera function by including a lens and an image sensor. The image captured by the camera function is displayed on the display unit. Examples of electronic devices are smart phones and laptop computers.

[0116] Fig.13A and Fig. 13B is a schematic diagram showing an example of the display device according to the present embodiment. Fig.13A A display device such as a TV monitor or a PC monitor is shown. The display device 1300 includes a frame 1301 and a display unit 1302. The light emitting device according to the present embodiment can be used in the display unit 1302.

[0117] The display device 1300 includes a support frame 1301 and a base 1303 of a display unit 1302. The base 1303 is not limited to Fig.13A The form shown. The underside of the frame 1301 can also be used as a base.

[0118] In addition, the frame 1301 and the display unit 1302 may be curved, and the curvature radius may be 5000 mm (inclusive) to 6000 mm (inclusive).

[0119] Fig. 13B is a schematic diagram showing other examples of the display device according to the present embodiment. Fig. 13B The display device 1350 shown is configured to be foldable, that is, the display device 1350 is a so-called foldable display device. The display device 1350 includes a first display unit 1351, a second display unit 1352, a housing 1353, and a bending point 1354. The first display unit 1351 and the second display unit 1352 may each include a light-emitting device according to the present embodiment. The first display unit 1351 and the second display unit 1352 may also be a seamless display device. The first display unit 1351 and the second display unit 1352 may be separated by a bending point. The first display unit 1351 and the second display unit 1352 may display different images, and may display one image together.

[0120] Fig.14A 14 is a schematic diagram showing an example of a lighting device according to the present embodiment. The lighting device 1400 may include a housing 1401, a light source 1402, a circuit board 1403, an optical film 1404, and a light diffusion unit 1405. The light source may include an organic light emitting element according to the present embodiment. The optical film may be a film that improves the color rendering of the light source. When performing lighting, etc., the light diffusion unit may project the light of the light source over a wide range by effectively diffusing the light. The optical film and the light diffusion unit may be disposed on the illumination light exit side. As required, the lighting device may also include a cover on the outermost portion.

[0121] The lighting device is, for example, a device for illuminating the interior of a room. The lighting device may emit white light, natural white light, or light of other colors from blue to red. The lighting device may include a light control circuit for controlling these light components. The lighting device may include an organic light emitting element according to the present invention and a power supply circuit connected to the organic light emitting element. The power supply circuit is a circuit for converting an AC voltage into a DC voltage. The color temperature of white is 4200K, and the color temperature of natural white is 5000K. The lighting device may also include a color filter.

[0122] In addition, the lighting device according to the present embodiment may include a heat dissipation unit. The heat dissipation unit dissipates internal heat of the device to the outside of the device, and examples thereof are metals having high specific heat, and liquid silicon.

[0123] Fig. 14B 1450 is a schematic diagram of a car as an example of a moving body according to the present embodiment. The car has a tail light as an example of a lighting device. The car 1450 has a tail light 1451, and may have a form in which the tail light is lit when a brake operation or the like is performed.

[0124] The taillight 1451 may include an organic light emitting element according to the present embodiment. The taillight may include a protective member for protecting the organic EL element. The material of the protective member is not limited as long as the material is a transparent material having a high strength to a certain extent, and is preferably polycarbonate or the like. Furan dicarboxylic acid derivatives or acrylonitrile derivatives or the like may be mixed in polycarbonate.

[0125] The car 1450 may include a body 1453 and a window 1452 attached to the body 1453. The window may be a transparent display as long as it is not a window for checking the front or rear of the car. The transparent display may include an organic light emitting element according to the present embodiment. In this case, the constituent material of the electrode and the like of the organic light emitting element is formed of a transparent member.

[0126] The mobile body according to the present embodiment includes a driving unit such as an engine or a motor, and a moving part such as a wheel, a propeller or a tire. For example, the mobile body may be a car, a ship, an airplane, a drone, a bicycle or a railway vehicle. The mobile body may include a main body and a lighting fixture provided on the main body. The lighting fixture may emit light for notifying the position of the main body. The lighting fixture includes an organic light emitting element according to the present embodiment.

[0127] Will refer to Fig.15A and Fig. 15B The following is an example of an application of the display device according to each of the above embodiments. The display device can be applied to a system that can be worn as a wearable device (such as smart glasses, HMD, or smart contact lenses). The imaging display device used in such an application example includes an imaging device capable of photoelectrically converting visible light and a display device capable of emitting visible light.

[0128] Will refer to Fig.15A A pair of glasses 1500 (smart glasses) according to an application example is described. A camera device 1502 such as a CMOS sensor or a SPAD is provided on the front side of a lens 1501 of the glasses 1500. In addition, a display device of each of the above embodiments is provided on the back side of the lens 1501.

[0129] The glasses 1500 further include a control device 1503. The control device 1503 serves as a power source for supplying power to the camera 1502 and the display device according to each embodiment. In addition, the control device 1503 controls the operation of the camera 1502 and the display device. An optical system configured to converge light to the camera 1502 is formed on the lens 1501.

[0130] Will refer to Fig. 15B15 to illustrate glasses 1550 (smart glasses) according to an application example. Glasses 1550 include a control device 1552. A camera corresponding to the camera 1502 and a display device are mounted on the control device 1552. An optical system configured to project light emitted from the display device in the control device 1552 is formed in the lens 1551, and an image is projected to the lens 1551. The control device 1552 serves as a power supply for supplying power to the camera and the display device, and controls the operation of the camera and the display device. The control device may include a line of sight detection unit for detecting the line of sight of the wearer. The line of sight may be detected using infrared rays. The infrared emitting unit emits infrared rays to the eyeball of the user who is looking at the displayed image. The camera unit including a light receiving element detects the reflected light of the emitted infrared rays from the eyeball, thereby obtaining a captured image of the eyeball. A reducing unit for reducing light from the infrared emitting unit to the display unit in a plan view is provided, thereby reducing degradation of image quality.

[0131] The user's line of sight toward the displayed image is detected from a captured image of the eyeball obtained by capturing infrared rays. Any known method can be applied to line of sight detection using a captured image of the eyeball. As an example, a line of sight detection method based on a Purkinje image obtained by reflecting irradiated light from the cornea can be used.

[0132] More specifically, a gaze detection process based on pupil center corneal reflection is performed. Using pupil center corneal reflection, a gaze vector representing the direction (rotation angle) of the eyeball is calculated based on an image of the pupil included in a captured image of the eyeball and a Purkinje image, thereby detecting the user's gaze.

[0133] The display device according to the embodiment of the present invention may include an imaging device including a light receiving element, and may control a display image on the display device based on line of sight information of a user from the imaging device.

[0134] More specifically, the display device determines the first display area that the user is looking at and the second display area other than the first display area based on the line of sight information. The first display area and the second display area may be determined by the control device of the display device, or the first display area and the second display area determined by an external control device may be received. In the display area of ​​the display device, the display resolution of the first display area may be controlled to be higher than the display resolution of the second display area. That is, the resolution of the second display area may be lower than the resolution of the first display area.

[0135] In addition, the display area includes a first display area and a second display area different from the first display area, and a higher priority area is determined from the first display area and the second display area based on the line of sight information. The first display area and the second display area may be determined by the control device of the display device, or the first display area and the second display area determined by an external control device may be received. The resolution of the higher priority area may be controlled to be higher than the resolution of the area other than the higher priority area. That is, the resolution of the relatively lower priority area may be low.

[0136] Note that AI can be used to decide the first display area or an area with a higher priority. AI can be a model configured to use an image of the eyeball and the actual viewing direction of the eyeball in the image as supervision data to estimate the angle of sight and the distance relative to the target in front of the sight from the image of the eyeball. The AI ​​program can be maintained by a display device, a camera device, or an external device. If the external device maintains the AI ​​program, the AI ​​program can be sent to the display device through communication.

[0137] In the case of display control based on line of sight detection, it may be preferred to apply smart glasses that also include a camera configured to capture external information. The smart glasses can display the captured external information in real time.

[0138] While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims

1. A light emitting device, comprising: a first pixel circuit and a second pixel circuit; a signal line configured to supply a pixel signal to the first pixel circuit and the second pixel circuit; as well as a first transistor connected to the signal line, Wherein, the first pixel circuit and the second pixel circuit each include: Light emitting element, a second transistor disposed on a path through which a current for causing the light emitting element to emit light flows, and a third transistor connected to the control terminal of the second transistor, and The third transistor of each of the first pixel circuit and the second pixel circuit is connected to the signal line via the first transistor.

2. The light emitting device according to claim 1, wherein: The first pixel circuit and the second pixel circuit are arranged in the extending direction of the signal line. 3 . The light emitting device according to claim 1 , further comprising a scanning circuit configured to switch each of the first transistor, each transistor of the first pixel circuit, and each transistor of the second pixel circuit between on and off.

4. The light emitting device according to claim 3, wherein: The scanning circuit: writing the pixel signal into the control terminal of the second transistor of the first pixel circuit by overlapping a time period during which the first transistor is turned on and a time period during which the third transistor of the first pixel circuit is turned on, and The pixel signal is written into the control terminal of the second transistor of the second pixel circuit by overlapping a period during which the first transistor is turned on and a period during which the third transistor of the second pixel circuit is turned on.

5. The light emitting device according to claim 3, wherein: The scanning circuit: keeping the third transistor of the second pixel circuit off while both the first transistor and the third transistor of the first pixel circuit are on, and While both the first transistor and the third transistor of the second pixel circuit are turned on, the third transistor of the first pixel circuit is kept turned off.

6. The light emitting device according to claim 3, wherein: The scanning circuit: Starting from a state where both the first transistor and the third transistor of the first pixel circuit are turned on, while keeping the first transistor turned on, the third transistor of the first pixel circuit is turned off, and From a state where both the first transistor and the third transistor of the second pixel circuit are turned on, the third transistor of the second pixel circuit is turned off while the first transistor is kept turned on.

7. The light emitting device according to claim 3, further comprising: a third pixel circuit and a fourth pixel circuit to which a pixel signal is supplied from the signal line; as well as a fourth transistor connected to the signal line, Wherein, the third pixel circuit and the fourth pixel circuit each include: a second light emitting element, a fifth transistor disposed on a path through which a current for causing the second light emitting element to emit light flows, and a sixth transistor connected to the control terminal of the fifth transistor, The sixth transistor of each of the third pixel circuit and the fourth pixel circuit is connected to the signal line via the fourth transistor, and The scanning circuit writes the pixel signal into each of the control terminals of the fifth transistor of the third pixel circuit and the fifth transistor of the fourth pixel circuit by overlapping the time period when the fourth transistor is turned on, the time period when the sixth transistor of the third pixel circuit is turned on, and the time period when the sixth transistor of the fourth pixel circuit is turned on.

8. The light emitting device according to claim 3, further comprising: a fifth pixel circuit and a sixth pixel circuit to which pixel signals are supplied from the signal line; as well as a seventh transistor connected to the signal line, Wherein, the fifth pixel circuit and the sixth pixel circuit each include: a third light emitting element, and an eighth transistor disposed on a path through which a current for causing the third light emitting element to emit light flows, The control terminal of the eighth transistor of each of the fifth pixel circuit and the sixth pixel circuit is connected to the seventh transistor without passing through other transistors, and The scanning circuit writes the pixel signal into each of a control terminal of the eighth transistor of the fifth pixel circuit and a control terminal of the eighth transistor of the sixth pixel circuit by turning on the seventh transistor.

9. The light emitting device according to claim 1, wherein: The capacitance of the first transistor is smaller than the capacitance of the third transistor of each of the first pixel circuit and the second pixel circuit.

10. The light emitting device according to claim 1, wherein: The thickness of the gate insulating film of the first transistor is greater than the thickness of the gate insulating film of the third transistor of each of the first pixel circuit and the second pixel circuit.

11. The light emitting device according to claim 1, wherein: An area of ​​a substrate surface occupied by the first transistor is smaller than an area of ​​a substrate surface occupied by a third transistor of each of the first pixel circuit and the second pixel circuit.

12. A photoelectric conversion device comprising: an optical unit including a plurality of lenses; an image sensor configured to receive light having passed through the optical unit; and a display unit configured to display the image captured by the image sensor, Wherein, the display unit comprises the light emitting device according to any one of claims 1 to 11.

13. An electronic device, comprising: A display unit comprising a light emitting device according to any one of claims 1 to 11; a housing provided with the display unit; and a communication unit which is provided in the housing and configured to perform external communication.

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