Display driving method, display driving circuit, display panel

Abstract

The application discloses a display driving method, a display driving circuit and a display panel. The pulse width of a first sub-area scanning driving signal corresponding to a second display area and the pulse width of a second sub-area scanning driving signal corresponding to a first display area are set according to the second display area and the first display area, so that the pulse width of the second sub-area scanning driving signal is greater than the pulse width of the first sub-area scanning driving signal. The positive bias stability test time of a transistor in a pixel driving unit in the first display area is increased, so that the difference between the pressure tests of the transistors in the first display area and the second display area is reduced, that is, the problem of the threshold voltage positive bias of the transistor in the high-frequency area after a long-time reliability test is compensated, and the purpose of solving the dark display of the high-brushing area is achieved.

Description

Technical Field

[0001] This application relates to the field of display panel technology, specifically to a display driving method, a display driving circuit, and a display panel. Background Technology

[0002] With the improvement of people's living standards, electronic products play an important role in people's lives. Display panels are an important component of electronic products, so the demand for display panels is increasing. Currently, the active-matrix organic light-emitting diode (AMOLED) or low-temperature polycrystalline oxide (LTPO) 3.0 localized refresh display technology on the market can realize the function of displaying different refresh rates in multiple areas of the mobile phone. For example, the mobile phone can simultaneously watch videos (requiring a high refresh rate display) and read text (requiring a low refresh rate display). It also has the advantage of saving power, that is, the power consumption of the low refresh rate area is reduced.

[0003] In related technologies, the display effect is poor because the turn-on frequency of the indium gallium zinc oxide (IGZO) transistors in the low refresh rate display area and the high refresh rate display area of ​​LTPO3.0 is inconsistent. Summary of the Invention

[0004] In view of the above problems, this application provides a display driving method, a display driving circuit, and a display panel, aiming to solve the problem that the display screen in the second display area of ​​the display panel is too dark after a long period of reliability testing.

[0005] A first aspect of this application provides a display driving method applied to a display panel, the display driving method comprising:

[0006] A first display area and a second display area of ​​the display panel are determined; wherein the refresh rate of the first display area is less than the refresh rate of the second display area;

[0007] Based on the first display area and the second display area, the pulse width of the first partition scan drive signal corresponding to the second display area and the pulse width of the second partition scan drive signal corresponding to the first display area are set; wherein, the pulse width of the second partition scan drive signal is greater than the pulse width of the first partition scan drive signal;

[0008] The pixel driving unit in the first display area is controlled to generate a corresponding pixel driving signal according to the second partition scan driving signal and data signal, so as to drive the display pixels in the first display area to light up at a preset refresh rate.

[0009] In some embodiments, the display driving method further includes:

[0010] Obtain the reliability test time of the display panel;

[0011] The pulse widths of the first partition scan drive signal and the second partition scan drive signal are determined based on the reliability test time.

[0012] In some embodiments, the reliability test time is positively correlated with the pulse width of the second partition scan drive signal.

[0013] In some embodiments, the display driving method further includes:

[0014] Based on the time from the first time the display panel is lit up to the current time of use, the corresponding target pulse width is determined from the preset time pulse width relationship table;

[0015] Set the pulse width of the second partition scan drive signal to the target pulse width.

[0016] In some embodiments, the time from the first illumination of the display panel to its current use is positively correlated with the target pulse width.

[0017] In some embodiments, the display driving method further includes:

[0018] Obtain the absolute value of the difference between the screen refresh rates of the first display area and the second display area;

[0019] The pulse width of the second partition scan drive signal is determined based on the absolute value of the difference in the screen refresh rates.

[0020] In some embodiments, the difference in screen refresh rates is positively correlated with the pulse width of the second partition scan drive signal.

[0021] A second aspect of this application also provides a display driving circuit applied to a display panel, the display panel including a plurality of display pixels; the display driving circuit includes a plurality of pixel driving units and a main control circuit, the main control circuit being used to execute the display driving method as described in any of the above embodiments;

[0022] The plurality of pixel driving units are used to drive the plurality of display pixels to light up respectively.

[0023] In some embodiments, the display driving circuit further includes a plurality of scan driving modules, and the plurality of gate scan lines are respectively connected to the plurality of scan driving modules;

[0024] The scanning drive module is controlled by the main control circuit to provide gate scan drive signals to multiple gate scan lines, and the multiple pixel drive units are respectively connected to the corresponding gate scan lines;

[0025] Each pixel driving unit is used to drive the corresponding display pixel to light up according to the received gate scan driving signal and data signal.

[0026] A third aspect of this application also provides a display panel, the display panel including the display driving circuit as described in any of the above embodiments.

[0027] The beneficial effects of this application embodiment are as follows: The pulse width of the first partition scanning drive signal corresponding to the second display area and the pulse width of the second partition scanning drive signal corresponding to the first display area are set according to the second display area and the first display area, so that the pulse width of the second partition scanning drive signal is greater than the pulse width of the first partition scanning drive signal. By increasing the positive bias voltage stability test time of the transistor in the pixel driving unit in the first display area, the difference in stress test of the transistor in the first display area and the second display area is reduced, that is, the problem of the threshold voltage positive bias of the transistor in the high frequency area after long-term reliability test is compensated, thereby achieving the purpose of solving the problem of the high refresh rate area display being too dark.

[0028] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0029] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiments below. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0030] Figure 1 This is a first schematic diagram of a display driving method provided in an embodiment of this application;

[0031] Figure 2 A waveform diagram of the second display area and the second partition scanning drive signal within the first display area provided in the embodiments of this application;

[0032] Figure 3This is a second schematic diagram of the display driving method provided in the embodiments of this application;

[0033] Figure 4 This is a third schematic diagram of the display driving method provided in the embodiments of this application;

[0034] Figure 5 This is a fourth schematic diagram of the display driving method provided in the embodiments of this application;

[0035] Figure 6 A schematic diagram of a display driving circuit provided in an embodiment of this application;

[0036] Figure 7 A schematic diagram of a pixel driving unit provided in an embodiment of this application;

[0037] Figure 8 This is a schematic diagram of the driving timing of the pixel driving unit of the 8T1C pixel architecture provided in the embodiments of this application. Detailed Implementation

[0038] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0040] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0041] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The phrase "second connection port" at various locations in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0042] In related technologies, due to the inconsistent turn-on frequencies of the indium gallium zinc oxide (IGZO) transistors in the first and second display areas of the LTPO3.0, the degree of forward bias stability testing (PBS) of the IGZO transistors differs. After long-term reliability testing (RA testing), the threshold voltage of the IGZO in the high-frequency region is forward biased, resulting in a problem of dim display.

[0043] To address the aforementioned technical problems, this application provides a display driving method, see below. Figure 1 As shown, the display driving method in this embodiment includes steps S100 to S300.

[0044] In step S100, the first display area and the second display area of ​​the display panel are determined.

[0045] In this embodiment, the refresh rate of the first display area is lower than that of the second display area; the first display area refers to the area of ​​the display panel that uses a lower refresh rate, and the second display area refers to the area of ​​the display panel that uses a higher refresh rate. When displaying an image, the display panel can display some areas at a lower refresh rate according to user needs or image display requirements. For example, in areas where only text needs to be displayed, the refresh rate of that area can be reduced to reduce display power consumption.

[0046] In some embodiments, the refresh rate of the first display area may be less than 30Hz.

[0047] In some embodiments, the refresh rate of the first display area can be 1Hz.

[0048] In some embodiments, the refresh rate of the second display area may be greater than 100Hz.

[0049] In some embodiments, the refresh rate of the second display area can be 120Hz or 144Hz.

[0050] In step S200, based on the first display area and the second display area, the pulse width of the first partition scan drive signal corresponding to the second display area and the pulse width of the second partition scan drive signal corresponding to the first display area are set.

[0051] In this embodiment, when the partition refresh function of the display panel is enabled, the refresh rates of the display images in different areas may be inconsistent. For example, the refresh rates of the display images in the upper, middle, and lower areas of the display panel may be 1Hz, 120Hz, and 1Hz, respectively. Because the turn-on frequencies of the indium gallium zinc oxide (IGZO) transistors in the first and second display areas are inconsistent, the forward bias stability test (PBS) of the IGZO transistors differs. After long-term reliability testing (RA testing), the threshold voltage of the IGZO in the high-frequency area is forward biased, resulting in a dim display. In this embodiment, by setting the pulse width of the second partition scan drive signal to be greater than the pulse width of the first partition scan drive signal, the forward bias stability test time of the transistors in the pixel drive unit in the first display area is increased. This reduces the difference in stress testing between the transistors in the first and second display areas, compensating for the problem of the threshold voltage being forward biased in the high-frequency area after long-term reliability testing, thus solving the problem of a dim display in the high refresh rate area.

[0052] In step S300, the pixel driving unit in the first display area is controlled to generate a corresponding pixel driving signal according to the second partition scan driving signal and the data signal, so as to drive the display pixels in the first display area to light up at a preset refresh rate.

[0053] In this embodiment, the display panel includes multiple display pixels, which can be arranged in an array. Each display pixel is driven by a corresponding pixel driving unit. The pixel driving unit can generate a corresponding pixel driving signal based on the received gate scan driving signal and the corresponding partition scan driving signal, thereby driving the display pixels in the first display area and the second display area to light up according to their set display refresh rate. In the first display area, the pixel driving unit can generate a corresponding pixel driving signal based on the received gate scan driving signal and the second partition scan driving signal to drive the display pixels in the first display area to light up. In the second display area, the pixel driving unit can generate a corresponding pixel driving signal based on the received gate scan driving signal and the first partition scan driving signal to drive the display pixels in the second display area to light up. When the multiple display pixels in the second display area and the first display area are driven to light up, they can display corresponding images.

[0054] In some embodiments, the pixel driving unit can be an 8T1C pixel architecture, and the partition driving transistor in the 8T1C pixel architecture can be an IGZO transistor. The partition driving transistor determines the display refresh rate of the display pixel corresponding to its pixel driving unit according to the received partition scan driving signal. In this way, the main control circuit controls the corresponding pixel driving unit to generate a pixel driving signal with a low duty cycle according to the first display area, thereby achieving the effect of reducing the display refresh rate of the first display area.

[0055] Combination Figure 2 As shown, taking a second display area with a refresh rate of 120Hz and a first display area with a refresh rate of 1Hz as an example, N1 represents the gate voltage of the partition driving transistor in the pixel driving unit. The gate of the partition driving transistor is used to receive the corresponding partition scan driving signal SN2. In the second display area, the pulse width of the first partition scan driving signal is t1, and the pulse width of the second partition scan driving signal is t2. Under the control of the corresponding partition scan driving signal, the partition driving transistor is in a PBS and NBS cycle state. By setting the pulse width t2 of the second partition scan driving signal to be greater than the pulse width t1 of the first partition scan driving signal, the PBS time of the partition driving transistor in the first display area can be increased, thereby reducing the difference in stress test between the transistors in the first and second display areas. That is, compensating for the problem of the threshold voltage positive bias of the transistor in the high-frequency area after long-term reliability testing, thus achieving the purpose of solving the problem of the high refresh rate area display being too dark.

[0056] In some embodiments, see Figure 3 As shown, the display driving method in this embodiment further includes steps S410 and S420.

[0057] In step S410, the reliability test time of the display panel is obtained.

[0058] In step S420, the pulse widths of the first partition scan drive signal and the second partition scan drive signal are determined based on the reliability test time.

[0059] In this embodiment, since the RA reliability test simulates the aging and degradation experiment of the display panel under long-term use, for example, the service life of a mobile phone and the RA time can be obtained from previous tests, such as one year of display panel use being approximately equal to 60 hours of RA testing, and two years of display panel use being approximately equal to 120 hours of RA testing, the reliability test time of the display panel is positively correlated with the service life of the display panel. The longer the reliability test time of the display panel, the higher the degree of compensation for the forward bias of the threshold voltage of the IGZO transistor in the second display area, and the more the PBS time of the IGZO transistor in the first display area needs to be increased. Therefore, the pulse width of the second partition scan drive signal received by the partition scan transistor (e.g., IGZO transistor) in the first display area needs to be larger. It should be noted that the service life of the display panel in this application can be the time from the first time the display panel is lit up to the current time of use. Therefore, the high-level pulse width of the second partition scan drive signal can be obtained based on the actual reliability test time of the display panel. For example, when the RA test is 60H, setting the pulse width of the second partition scan drive signal to t2 can improve the problem of the high refresh rate area being too dark. When the RA test is 120H, setting the pulse width of the second partition scan drive signal to t3 can improve the problem of the high refresh rate area being too dark.

[0060] In some embodiments, the reliability test time is positively correlated with the pulse width of the second partition scan drive signal.

[0061] In this embodiment, the reliability test time of the display panel is positively correlated with the usage time of the display panel. The longer the reliability test time of the display panel, the higher the degree of compensation for the forward bias of the threshold voltage of the IGZO transistor in the second display area. Therefore, the required PBS time of the IGZO transistor in the first display area needs to be increased, and consequently, the pulse width of the second partition scan drive signal received by the partition scan transistor (e.g., the IGZO transistor) in the first display area needs to be larger. Thus, the high-level pulse width of the second partition scan drive signal can be obtained based on the actual reliability test time of the display panel.

[0062] As shown in Table 1, the RA test time is used to characterize the corresponding years of mobile phone use. For example, when the RA test is 0H, the pulse width of the second partition scan drive signal is set to t1; when the RA test is 60H, the pulse width of the second partition scan drive signal is set to t2, which can improve the problem of the high refresh rate area being too dark; when the RA test is 120H, the pulse width of the second partition scan drive signal is set to t3, which can improve the problem of the high refresh rate area being too dark; when the RA test is 240H, the pulse width of the second partition scan drive signal is set to t4, which can improve the problem of the high refresh rate area being too dark; when the RA test is 500H, the pulse width of the second partition scan drive signal is set to t5, which can improve the problem of the high refresh rate area being too dark; when the RA test is 1000H, the pulse width of the second partition scan drive signal is set to t6, which can improve the problem of the high refresh rate area being too dark, and so on.

[0063] Table 1:

[0064] Mobile phone usage years / year RA Time / Hour (H) SN2 high-level pulse width 0 0 t1 1 60 t2 2 120 t3 3 240 t4 4 500 t5 5 1000 t6

[0065] In some embodiments, t6>t5>t4>t3>t2>t1.

[0066] In some embodiments, see Figure 4 As shown, the display driving method in this embodiment further includes steps S510 and S520.

[0067] In step S510, the target pulse width is determined from a preset time pulse width relationship table based on the time from the first time the display panel is lit up to the current time of use.

[0068] In step S520, the pulse width of the second partition scan drive signal is set to the target pulse width.

[0069] In this embodiment, the reliability test time of the display panel is positively correlated with the usage time of the display panel. A time pulse width relationship table can be established based on the actual usage and debugging time of the display panel during RA testing. For example, 60 hours of RA testing is equivalent to one year of use of the display panel, 120 hours of RA testing is equivalent to two years of use, and so on. In actual use, the usage time of the display panel is obtained, and the corresponding target pulse width is determined from the preset time pulse width relationship table. Then, the pulse width of the second partition scan drive signal is set to the target pulse width, thereby reducing the difference in stress testing of transistors in the first and second display areas. This compensates for the problem of positive bias of the threshold voltage of transistors in the high-frequency area after long-term reliability testing, thus achieving the goal of solving the problem of dim display in the high refresh rate area.

[0070] In some embodiments, in steps S510 and S520, when the usage time of the display panel reaches a preset time node, the corresponding target pulse width is determined from the preset time pulse width relationship table according to the usage time of the display panel, and then the pulse width of the second partition scan drive signal is set as the target pulse width.

[0071] In some embodiments, the preset time node for setting the pulse width of the second partition scan drive signal can be a linear node, that is, the interval time between adjacent time nodes is the same.

[0072] In some embodiments, the usage time of the display panel is positively correlated with the target pulse width.

[0073] In this embodiment, the longer the display panel is used, the higher the degree of forward bias compensation of the threshold voltage of the IGZO transistor in the second display area becomes. Therefore, the required PBS (Back-Side Buffer) time of the IGZO transistor in the first display area needs to be increased. Consequently, the pulse width of the second partition scan drive signal received by the partition scan transistor (e.g., the IGZO transistor) in the first display area needs to be larger. During the use of the display panel, as the usage time gradually increases, the high-level pulse width of the second partition scan drive signal can be obtained from a preset time pulse width relationship table based on the usage time of the display panel. This allows for the selection of a suitable target pulse width to adjust the high-level pulse width of the second partition scan drive signal, thereby improving the problem of a dark display in the high refresh rate area.

[0074] In some embodiments, see Figure 5 As shown, the display driving method in this embodiment further includes steps S610 and S620.

[0075] In step S610, the absolute value of the difference between the screen refresh rates of the first display area and the second display area is obtained.

[0076] In step S620, the pulse width of the second partition scan drive signal is determined based on the absolute value of the difference in the screen refresh rates.

[0077] In this embodiment, the first display area refers to the area of ​​the display panel that uses a lower refresh rate, and the second display area refers to the area of ​​the display panel that uses a higher refresh rate. Because the second display area has a higher refresh rate, after a long period of RA testing, the threshold voltage of the IGZO transistors in the second display area becomes positively biased. The degree of this positive bias is related to the absolute value of the difference between the refresh rates of the first and second display areas. By setting the pulse width of the second partition scan drive signal in the first display area to be greater than the pulse width of the first partition scan drive signal in the second display area, the positive bias voltage stability test time of the transistors in the pixel drive unit in the first display area is increased. Furthermore, the positive bias voltage stability test time of the transistors in the pixel drive unit in the first display area can be set to be related to the refresh rate of the first display area. Thus, by adjusting the pulse width of the second partition scan drive signal in the first display area according to the absolute value of the difference between the refresh rates of the first and second display areas, the difference in stress testing between the transistors in the first and second display areas is reduced. This compensates for the problem of the threshold voltage being positively biased in the high-frequency region transistors after a long period of reliability testing, thereby solving the problem of the high refresh rate region displaying too darkly.

[0078] In some embodiments, the absolute value of the difference in screen refresh rates is positively correlated with the pulse width of the second partition scan drive signal.

[0079] In this embodiment, the greater the absolute value of the difference between the refresh rates of the first display area and the second display area, the greater the difference in the stress test of the transistors in the first display area and the second display area. Therefore, the pulse width of the second partition scan drive signal is larger. In this way, the problem of the threshold voltage of the transistor in the high-frequency area being positively biased after a long-term reliability test can be compensated, thereby achieving the purpose of solving the problem of the high refresh rate area being dark.

[0080] In some embodiments, the display driving method in this embodiment further includes: generating a corresponding partition scan driving signal according to the first display area, so as to control the corresponding pixel driving unit to reduce the duty cycle of the pixel driving signal.

[0081] In this embodiment, the scanning area where the display refresh rate needs to be reduced is determined by the first display area, thereby generating a corresponding partitioned scanning drive signal. The partitioned scanning drive signal is used to control the corresponding pixel driving unit to reduce the duty cycle of the pixel driving signal, thereby reducing the on / off duty cycle of the pixels in the corresponding area, thereby performing partitioned display on the display panel and reducing the display refresh rate in the first display area.

[0082] This application embodiment also provides a display driving circuit applied to a display panel, the display panel including multiple display pixels, see [link]. Figure 6As shown, the display driving circuit in this embodiment includes a plurality of pixel driving units 530 and a main control circuit 510. The main control circuit 510 is used to execute the display driving method as described in any of the above embodiments; the plurality of pixel driving units 530 are used to drive a plurality of display pixels to light up respectively.

[0083] In this embodiment, multiple display pixels can be arranged in an array. Each display pixel is driven by a corresponding pixel driving unit 530. The pixel driving unit 530 can generate a pixel driving signal according to the received gate scan driving signal, thereby driving the corresponding display pixel to light up. When multiple display pixels are driven to light up, they can display the corresponding image. The main control circuit 510 can control the corresponding pixel driving unit 530 to generate a pixel driving signal with a low duty cycle according to the first display area, thereby reducing the refresh rate of the display screen in the first display area.

[0084] In some embodiments, combined with Figure 6 As shown, the partition scan drive signal can also be ANDed with the scan drive signal output by the scan drive module 520 to adjust the duty cycle of the scan drive signal output to the gate scan line 501, thereby controlling the corresponding pixel drive unit to reduce the duty cycle of the pixel drive signal and realizing the partition refresh display of the display panel.

[0085] In some embodiments, the main control circuit 510 can provide the scanning drive module 520 with corresponding partition scanning drive signals according to the content to be displayed on the display panel, thereby adjusting the refresh rate of the display screen accordingly. For example, based on the coordinates of the display screen and the refresh rate requirements, by providing corresponding partition scanning drive signals to the display driving method, the refresh rate of the display screen can be set according to frequency distributions such as 60Hz-120Hz-60Hz, 30Hz-120Hz-30Hz, 1Hz-120Hz-1Hz, etc. Specifically, in implementing the function of displaying different refresh rates in multiple areas of the mobile phone, if the mobile phone is simultaneously watching videos (requiring high refresh rate display) and reading text (requiring low refresh rate display), the refresh rate of the text display area in the display screen can be set to a low refresh rate (e.g., 1Hz, 30Hz, etc.) to reduce the power consumption of the display panel without affecting the display effect.

[0086] In some embodiments, combined with Figure 6As shown, the display driving circuit also includes multiple scan driving modules 520, and multiple gate scan lines 501 are respectively connected to multiple scan driving modules 520; the main control circuit 510 outputs corresponding scan control signals (SWN, SWN+1) to the scan driving modules 520, and the scan driving modules 520 are controlled by the main control circuit 510 to provide gate scan driving signals to multiple gate scan lines 501. Multiple pixel driving units 530 are respectively connected to the corresponding gate scan lines 501; each pixel driving unit 530 is used to drive the corresponding display pixel to light up according to the received gate scan driving signal and data signal.

[0087] In this embodiment, combined with Figure 6 As shown, the display panel may include N+1 rows of display pixels, each row of display pixels corresponds to a gate scan line 501, each gate scan line 501 is connected to a corresponding scan drive module 520, the main control circuit 510 provides a scan control signal SWN to the Nth scan drive module 520, the main control circuit 510 provides a scan control signal SWN+1 to the N+1th scan drive module 520, and the N+1 scan drive modules 520 provide gate scan drive signals to multiple gate scan lines 501 according to the corresponding scan control signals.

[0088] In some embodiments, the main control circuit 510 can also control the scan drive module 520 to provide partition scan drive signals to the corresponding pixel drive unit 530, thereby adjusting the display refresh rate of the display area of ​​the display panel.

[0089] In some embodiments, see Figure 7 As shown, the pixel driving unit 530 includes: a first driving transistor T1, a second switching transistor T2, a partition driving transistor T3, a scan driving transistor T4, a fifth switching transistor T5, a sixth switching transistor T6, and a storage capacitor Cst.

[0090] In this embodiment, the first terminal of the second switch transistor T2 is used to receive the display data signal Data, and the control terminal of the second switch transistor T2 is used to receive the first data control signal SP1; the control terminal of the scan drive transistor T4 is used to receive the gate scan drive signal SN1, and the control terminal of the partition drive transistor T3 is used to receive the partition scan drive signal SN2.

[0091] In some embodiments, the partition scan drive signal SN2 can be provided by a level conversion circuit to achieve partition refresh control of the pixel drive unit 530.

[0092] The control terminal of the fifth switch transistor T5 and the controller terminal of the sixth switch transistor T6 are connected together to receive the light emission control signal EM. The control terminal of the seventh switch transistor T7 and the control terminal of the eighth switch transistor T8 are connected together to receive the second data control signal SP2. The first terminal of the fifth switch transistor T5 and the first terminal of the storage capacitor Cst are connected together to the first power supply terminal ELVDD. The second terminal of the second switch transistor T2, the second terminal of the fifth switch transistor T5, and the first terminal of the first driving transistor T1 are connected together. The second terminal of the storage capacitor Cst, the control terminal of the first driving transistor T1, and the first terminal of the partition driving transistor T3 are connected together. The second terminal of the partition driving transistor T3, the first terminal of the scan driving transistor T4, the second terminal of the first driving transistor T1, the first terminal of the sixth switch transistor T6, and the first terminal of the eighth switch transistor T8 are connected together. The second terminal of the scan driving transistor T4 is connected to the first reference signal terminal Vrefn1.

[0093] The second terminal of the sixth switch transistor T6 and the first terminal of the seventh switch transistor T7 are connected to the positive terminal of the display pixel, and the negative terminal of the display pixel is connected to the reference ground. The second terminal of the seventh switch transistor T7 is connected to the second reference signal terminal Vrefn2, and the second terminal of the eighth switch transistor T8 is connected to the third reference signal terminal Vrefp.

[0094] In some embodiments, the second switch T2, the seventh switch T7, the eighth switch T8, the fifth switch T5, and the sixth switch T6 are N-type MOS transistors; the partition drive transistor T3 and the scan drive transistor T4 are P-type MOS transistors.

[0095] In some embodiments, the partition driving transistor T3 and the scan driving transistor T4 are IGZO transistors.

[0096] The timing sequence of the first data control signal SP1, the second data control signal SP2, the light emission control signal EM, the partition scan drive signal SN2, and the gate scan drive signal SN1 in the pixel driving unit within the first display area is as follows: Figure 8 As shown, combined with Figure 2 , Figure 7 as well as Figure 8As shown, taking a second display area with a refresh rate of 120Hz and a first display area with a refresh rate of 1Hz as an example, N1 represents the gate voltage of the partition driving transistor in the pixel driving unit. The gate of the partition driving transistor is used to receive the corresponding partition scan driving signal SN2. In the second display area, the pulse width of the first partition scan driving signal is t1, and the pulse width of the second partition scan driving signal is t2. Under the control of the corresponding partition scan driving signal, the partition driving transistor T3 is in a PBS and NBS cycle state. By setting the pulse width t2 of the second partition scan driving signal to be greater than the pulse width t1 of the first partition scan driving signal, the PBS time of the partition driving transistor T3 in the first display area can be increased, thereby reducing the difference in stress test between the transistors in the first and second display areas. That is, compensating for the problem of the threshold voltage positive bias of the transistor in the high-frequency area after long-term reliability testing, thus achieving the purpose of solving the problem of the high refresh rate area display being too dark.

[0097] In some embodiments, the main control circuit 510 is further configured to execute step S400 in the above embodiments. The main control circuit 510 generates a corresponding partition scanning drive signal according to the first display area, and controls the corresponding pixel driving unit to reduce the duty cycle of the pixel driving signal by the partition scanning drive signal, thereby achieving the purpose of reducing the switching duty cycle of the pixels in the corresponding area.

[0098] In some embodiments, the display driving circuit is used to drive the display panel, which may include multiple partition refresh areas. The main control circuit 510 in the display driving circuit can adjust the refresh rate of each partition refresh area by providing multiple partition scan driving signals to the pixel driving units in the multiple partition refresh areas, thereby realizing the partition refresh function of the display panel.

[0099] This application also provides a display panel, which includes a display driving circuit as described in any of the above embodiments.

[0100] In this embodiment, the display panel includes a display panel and a display driving circuit. The display panel includes multiple display pixels, and each display pixel includes at least one display pixel. When lit, the display pixels can emit a corresponding color, such as red, blue, or green light. Display pixels of the three colors can form a display pixel. In the display panel, the pulse width of the first partition scan driving signal corresponding to the second display area and the pulse width of the second partition scan driving signal corresponding to the first display area are set according to the second display area and the first display area, so that the pulse width of the second partition scan driving signal is greater than the pulse width of the first partition scan driving signal. By increasing the positive bias voltage stability test time of the transistors in the pixel driving unit in the first display area, the difference in stress test between the transistors in the first and second display areas is reduced, that is, the problem of the threshold voltage positive bias of the transistors in the high-frequency area after long-term reliability testing is compensated, thereby achieving the purpose of solving the problem of the high refresh rate area display being too dark.

[0101] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0102] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0103] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the electronic device embodiments described above are merely illustrative. For example, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0104] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0105] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0106] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A display driving method, characterized in that, The display driving method includes: A first display area and a second display area of ​​the display panel are determined; wherein the refresh rate of the first display area is less than the refresh rate of the second display area; Based on the first display area and the second display area, the pulse width of the first partition scan drive signal corresponding to the second display area and the pulse width of the second partition scan drive signal corresponding to the first display area are set; wherein, the pulse width of the second partition scan drive signal is greater than the pulse width of the first partition scan drive signal; The pixel driving unit in the first display area is controlled to generate a corresponding pixel driving signal according to the second partition scan driving signal and data signal, so as to drive the display pixels in the first display area to light up at a preset refresh rate; Obtain the reliability test time of the display panel; The pulse widths of the first partition scan drive signal and the second partition scan drive signal are determined based on the reliability test time.

2. The display driving method according to claim 1, characterized in that, The reliability test time is positively correlated with the pulse width of the second partition scan drive signal.

3. The display driving method according to claim 1, characterized in that, The display driving method further includes: Based on the time from the first time the display panel is lit up to the current time of use, the corresponding target pulse width is determined from the preset time pulse width relationship table; Set the pulse width of the second partition scan drive signal to the target pulse width.

4. The display driving method according to claim 3, characterized in that, The time from the first time the display panel is lit up to the current time of use is positively correlated with the target pulse width.

5. The display driving method according to any one of claims 1-4, characterized in that, The display driving method further includes: Obtain the absolute value of the difference between the screen refresh rates of the first display area and the second display area; The pulse width of the second partition scan drive signal is determined based on the absolute value of the difference in the screen refresh rates.

6. The display driving method according to claim 5, characterized in that, The difference in screen refresh rates is positively correlated with the pulse width of the second partition scan drive signal.

7. A display driving circuit, characterized in that, The display driving circuit includes multiple pixel driving units and a main control circuit, wherein the main control circuit is used to execute the display driving method as described in any one of claims 1-6; The plurality of pixel driving units are used to drive the plurality of display pixels to light up respectively.

8. The display driving circuit according to claim 7, characterized in that, The display driving circuit also includes multiple scan driving modules, and multiple gate scan lines are respectively connected to multiple scan driving modules; The scanning drive module is controlled by the main control circuit to provide gate scan drive signals to multiple gate scan lines, and the multiple pixel drive units are respectively connected to the corresponding gate scan lines; Each pixel driving unit is used to drive the corresponding display pixel to light up according to the received gate scan driving signal, partition scan driving signal and data signal.

9. A display panel, characterized in that, The display panel includes the display driving circuit as described in claim 7 or 8.

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