High-capacity low-ESR laminated solid aluminum capacitor and manufacturing method thereof

Abstract

The invention discloses a high-capacity low-ESR laminated solid aluminum capacitor and a manufacturing method thereof, the laminated solid aluminum capacitor comprises a shunt capacitor body, and the shunt capacitor body comprises a plurality of capacitor split bodies which are stacked up and down and connected in parallel; each capacitor split body comprises a plurality of capacitor chips, a conductive frame and a shell, the capacitor chips and the conductive frame are arranged in the shell, a plurality of stacked capacitor chips are arranged on both sides of the conductive frame, an anode pin and a cathode pin are respectively led out from both sides of the conductive frame towards the shell, and the anode pin and the cathode pin are connected with the conductive frame. The anode pins of the plurality of capacitor split bodies are connected in a conductive manner, and the cathode pins of the plurality of capacitor split bodies are connected in a conductive manner. According to the invention, the plurality of capacitor split bodies which are stacked up and down and connected in parallel are arranged, and the anode pin and the cathode pin of each capacitor split body are connected in a conducting manner, so that the capacity and the yield of the capacitor can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of aluminum electrolytic capacitors, and more specifically, to a large-capacity, low-ESR laminated solid aluminum capacitor and a manufacturing method thereof. Background Art

[0002] As one of the indispensable components in electronic circuits, the existing laminated solid aluminum capacitors are mainly composed of multi-layer capacitor units stacked on the front and back sides of a conductive connection frame. During the manufacturing process, the anode is fixed layer by layer by resistance welding, and the cathode is fixed by single-point conductive silver paste bonding. Then, the insulating material is packaged, and the positive and negative leads are left to pass through the insulating material to connect to the outside world. Then, the positive and negative leads outside the insulating material are bent to the bottom of the finished product for use with the chip pad. The laminated welding process directly affects the capacity, equivalent series resistance (ESR) and product yield of the finished capacitor.

[0003] With the continuous development of power supply, automotive electronics, industrial control and other fields, the demand will continue to increase. Therefore, how to improve the product yield of multilayer solid aluminum capacitors and reduce the equivalent series resistance (ESR) has become a technical problem that urgently needs to be solved.

[0004] Chinese invention patent 201711151480.1 discloses a stacked capacitor, including multiple stacked monomers, and positive and negative lead terminals electrically connected to the monomers, each monomer including a positive terminal, a negative terminal and a shielding rubber wire located between the positive terminal and the negative terminal; the negative terminals of each monomer are connected together and connected to the negative lead terminal; the positive terminals of each monomer are connected together and connected to the positive lead terminal, the negative terminal of each monomer includes a dielectric film, a solid electrolyte layer, a carbon paste layer and a silver paste layer sequentially coated on the surface of the positive foil, the outer surface of the multiple monomers is encapsulated with an insulating resin layer, and the stacked capacitor also includes an anti-sulfurization protection frame arranged near the negative lead terminal to prevent sulfur and sulfide in the air from contacting the silver paste layer. Although the above invention patent has a good anti-sulfurization effect, the polymer capacitor of this structure has a small capacity and a large equivalent series resistance, which cannot meet the requirements of a large current working environment.

[0005] Therefore, there is an urgent need to find a technical solution to further increase the capacity of polymer multilayer capacitors while reducing the equivalent series resistance of the capacitors. Summary of the invention

[0006] Based on this, it is necessary to provide a laminated solid aluminum capacitor with stable structure, large capacity and low ESR and a manufacturing method thereof to address the above technical problems.

[0007] In order to solve the above technical problems, the present invention provides a large-capacity low-ESR laminated solid aluminum capacitor and a manufacturing method thereof, which adopts the following technical solution:

[0008] The first aspect of the present invention proposes a large-capacity, low-ESR stacked solid-state capacitor, which includes a parallel capacitor body, wherein the parallel capacitor body includes a plurality of capacitor splits stacked in parallel; the capacitor splits include a plurality of capacitor chips, a conductive frame and a shell, wherein the capacitor chips and the conductive frame are arranged in the shell, and a plurality of stacked capacitor chips are arranged on both sides of the conductive frame, and the conductive frame leads out anode pins and cathode pins toward both sides of the shell respectively, and the anode pins of the plurality of capacitor splits are conductively connected, and the cathode pins of the plurality of capacitor splits are conductively connected.

[0009] Furthermore, the parallel capacitor body is an A-type parallel capacitor body, and the A-type parallel capacitor body includes an A-type first split and an A-type second split. The A-type first split and the A-type second split are stacked up and down in parallel, and the parallel connection between the A-type first split and the A-type second split is a contact parallel connection between pins.

[0010] Furthermore, the parallel capacitor body is a B-type parallel capacitor body, and the B-type parallel capacitor body includes a B-type first sub-body and a B-type second sub-body, and the B-type first sub-body and the B-type second sub-body are stacked up and down and connected in parallel through a connecting frame.

[0011] Furthermore, the connecting frame includes a first connecting frame and a second connecting frame which are C-shaped and buckled on the left and right sides of the B-type second split body.

[0012] Furthermore, the parallel capacitor body is an A-type parallel capacitor body, and the A-type parallel capacitor body includes an A-type third split, an A-type first split, and an A-type second split stacked up and down in parallel, and the A-type third split, the A-type first split, and the A-type second split are connected in parallel with pin-to-pin contact.

[0013] Furthermore, the parallel capacitor body is a B-type parallel capacitor body, and the B-type parallel capacitor body includes a B-type first split body, a B-type second split body and a B-type third split body stacked in sequence from top to bottom, and the B-type first split body, the B-type second split body and the B-type third split body are connected in parallel through a connecting frame.

[0014] Furthermore, the capacitor chip is provided with an anode region and a cathode region, and a plurality of silver paste dots are provided between the cathode regions of the capacitor chip and between the cathode region of the capacitor chip and the conductive frame.

[0015] Furthermore, the silver paste dots are arranged as four-point, six-point or nine-point dots.

[0016] Furthermore, an adhesive layer is provided between the capacitor parts.

[0017] A second aspect of the present invention provides a method for preparing a large-capacity, low-ESR laminated solid capacitor, comprising the following steps:

[0018] Step 1, cutting and punching the aluminum foil to separate the anode area and the cathode area through a silica gel strip (32);

[0019] Step 2, after the cathode area of ​​the aluminum foil is impregnated in the impregnation liquid, a polymer layer, a carbon layer and a silver layer are sequentially generated from the inside to the outside of the cathode area to form a complete capacitor chip (3);

[0020] Step 3, a plurality of capacitor chips (3) are stacked on the front and back sides of the conductive frame respectively, and the cathode areas of adjacent capacitor chips (3) and the cathode areas of the capacitor chips (3) and the conductive frame are bonded and fixed by a plurality of silver paste dots (34);

[0021] Step 4, laser welding the conductive frame on which the plurality of capacitor chips (3) are stacked in step 3;

[0022] Step 5: Packaging and aging to form a capacitor split body, and the conductive frame leads out the anode pin and the cathode pin on the left and right sides of the capacitor split body;

[0023] Step 6: After a number of capacitors are stacked up and down and fixed by an adhesive layer, the anode pins and cathode pins of each capacitor are connected in parallel by contact between the pins or by connecting the frames.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The large-capacity, low-ESR, laminated solid aluminum capacitor provided by the present invention is configured with a plurality of capacitor splits stacked in parallel, wherein the anode pins and cathode pins of each capacitor split are respectively connected and connected in parallel, thereby reducing the gap between the anode terminals of the patches, reducing the extrusion stress of the epoxy resin on the anode terminals during packaging, and adding adhesive between the two capacitors to improve the connection integrity. Compared with capacitor chips with the same number of layers but packaged in a single capacitor, the capacitor capacity and yield rate can be effectively improved.

[0026] The large-capacity, low-ESR laminated solid aluminum capacitor provided by the present invention sets multi-point silver paste points in the cathode area of ​​the capacitor chip to increase the contact area between the silver-immersed layers of each capacitor chip, improve conductivity, and effectively reduce ESR. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the solutions in the present application or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 This is a schematic structural diagram of a large-capacity, low-ESR multilayer solid-state capacitor according to Embodiment 1 of the present invention;

[0029] Figure 2 This is a schematic diagram of the structural decomposition of a large-capacity, low-ESR multilayer solid-state capacitor according to Embodiment 1 of the present invention;

[0030] Figure 3 This is a schematic structural diagram of a large-capacity, low-ESR multilayer solid-state capacitor according to Embodiment 2 of the present invention;

[0031] Figure 4 A schematic diagram of the structural decomposition of a large-capacity, low-ESR multilayer solid-state capacitor according to Embodiment 2 of the present invention;

[0032] Figure 5 This is a schematic diagram of the structural decomposition of a large-capacity, low-ESR multilayer solid capacitor according to Embodiment 7 of the present invention;

[0033] Figure 6 A schematic diagram of the structural decomposition of a large-capacity, low-ESR multilayer solid capacitor according to Embodiment 8 of the present invention;

[0034] Figure 7 A schematic diagram of the arrangement of a single silver paste point on the cathode region of a capacitor chip of a large-capacity, low-ESR multilayer solid-state capacitor proposed by the present invention;

[0035] Figure 8 A schematic diagram of the arrangement of four silver paste dots on the cathode area of ​​the capacitor chip of the large-capacity, low-ESR multilayer solid-state capacitor proposed by the present invention;

[0036] Fig. 9 A schematic diagram of the arrangement of six silver paste dots on the cathode area of ​​the capacitor chip of the large-capacity, low-ESR multilayer solid-state capacitor proposed by the present invention;

[0037] Fig.10 The figure is a schematic diagram of the arrangement of nine silver paste dots in the cathode area of ​​the capacitor chip of the large-capacity, low-ESR multilayer solid-state capacitor proposed by the present invention.

[0038] Description of reference numerals:

[0039] A-type parallel capacitor body 1, A-type first split body 11, A-type second split body 12, A-type first pin 111, A-type second pin 112, A-type third pin 121, A-type fourth pin 122, A-type first adhesive layer 123, capacitor chip 3, anode area 31, silicone layer 142, cathode area 33, silver paste dots 34;

[0040] B-type parallel capacitor body 2, B-type first split body 21, B-type second split body 22, B-type first pin 211, B-type second pin 212, B-type third pin 221, B-type fourth pin 222, B-type first adhesive layer 223, first connecting frame 23, second connecting frame 24;

[0041] A-type parallel capacitor body 1', A-type third split body 13, A-type fifth pin 131, A-type sixth pin 132, A-type second adhesive layer 113;

[0042] B-type parallel capacitor body 2 ′, B-type third split body 25 , B-type fifth pin 251 , B-type sixth pin 252 , B-type second adhesive layer 253 , third connecting frame 26 , and fourth connecting frame 27 . DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0044] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0045] In addition, the terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0046] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0047] Example 1

[0048] Please refer to Figures 1-2 The present embodiment provides a large-capacity low-ESR stacked solid-state capacitor, which includes an A-type parallel capacitor body 1, and the A-type parallel capacitor body 1 includes an A-type first split 11 and an A-type second split 12, the A-type first split 11 and the A-type second split 12 are stacked and connected in parallel, and the parallel connection between the A-type first split 11 and the A-type second split 12 is a contact parallel connection between pins. Specifically, the A-type first split 11 and the A-type second split 12 are respectively provided with an anode pin and a cathode pin, and the anode pins of the A-type first split 11 and the A-type second split 12 are welded and connected to each other, and the cathode pins of the first split 11 and the A-type second split 12 are welded and connected to each other.

[0049] Specifically, the A-type first split body 11 and the A-type second split body 12 both include a capacitor chip 3, a conductive frame and a shell. The capacitor chip 3 and the conductive frame are arranged in the shell. The capacitor chip 3 is divided into an anode area 31 and a cathode area 33 by a silicone strip 32. Furthermore, two stacked capacitor chips 3 are arranged on both sides of the conductive frame. The anode areas of the capacitor chips 3 and the anode areas of the capacitor chips 3 and the connecting frame are connected by laser welding. The cathode areas of the capacitor chips 3 and the cathode areas of the capacitor chips 3 and the conductive frame are connected by silver paste. Specifically, a plurality of silver paste dots 34 are arranged between the cathode areas of the capacitor chips 3 and between the cathode areas of the aluminum foil and the conductive frame. In this embodiment, Figure 8 As shown, the arrangement of the silver paste dots 34 is a four-dot arrangement, wherein four silver paste dots 34 are evenly spaced and arranged in two rows and two columns.

[0050] Furthermore, in the A-type first split body 11, after the conductive frame is connected to the anode area of ​​the capacitor chip 3, the A-type first pin 111 is led out from the left side of the shell, and the A-type first pin 111 is the anode pin. After the conductive frame is connected to the cathode area of ​​the capacitor chip 3, the A-type second pin 112 is led out from the right side of the shell, and the A-type second pin 112 is the cathode pin. The A-type first pin 111 and the A-type second pin 112 extend vertically downward toward the second split body 12.

[0051] Further, in the second split body 12, after the conductive frame is connected to the anode area of ​​the capacitor chip 3, the A-type third pin 121 is led out from the left side of the shell, and the A-type third pin 121 is the anode pin. After the conductive frame is connected to the cathode area of ​​the capacitor chip 3, the A-type fourth pin 122 is led out from the right side of the shell, and the A-type third pin 121 is the cathode pin. The A-type third pin 121 and the A-type fourth pin 122 extend vertically downward to protrude from the bottom of the shell of the A-type second split body 12 and then bend inward. When in use, the A-type third pin 121 and the A-type fourth pin 122 are welded to the external circuit board at the bent portion of the bottom of the shell.

[0052] Furthermore, an A-type first adhesive layer 123 is provided between the bottom surface of the shell of the A-type first split body 11 and the top surface of the shell of the A-type second split body 12 to fix them to each other. The A-type first pin 111 and the A-type second pin 112 are respectively conductively connected to the A-type third pin 121 and the A-type fourth pin 122 in the vertical direction after being led out from the left and right sides of the shell of the first split body 11. Specifically, the A-type first pin 111 is led out from the left side of the shell of the first split body 11 and covers and fits the outer surface of the A-type third pin 121 in the vertical direction, and a conductive connecting material is provided between the A-type first pin 111 and the A-type third pin 121. The A-type second pin 112 is led out from the right side of the shell of the first split body 11 and covers and fits the outer surface of the A-type fourth pin 122 in the vertical direction, and a conductive connecting material is provided between the A-type second pin 112 and the A-type fourth pin 122.

[0053] The method for preparing a large-capacity low-ESR laminated solid capacitor proposed in this embodiment comprises the following steps:

[0054] S1, cutting and punching the aluminum foil into aluminum foil sheets;

[0055] S2, welding the aluminum foil to the carrier strip, and applying isolation glue on the aluminum foil and drying it to divide the anode area and the cathode area. The isolation glue is a silica gel strip 32, and the isolation glue can prevent the high molecular polymer in the cathode area from climbing to the anode area and causing a short circuit of the product;

[0056] S3, impregnating the cathode area of ​​the aluminum foil sheet after step S2 in an impregnation liquid to repair the oxide film damaged during the punching process, wherein the impregnation liquid is an ammonium adipate solution;

[0057] S4, using chemical polymerization or dispersion impregnation on the aluminum foil after completing step S3, a high molecular polymer layer is generated on the cathode region of the aluminum foil, and then a carbon layer is impregnated outside the high molecular polymer layer to wrap it, and then a silver layer is impregnated outside the carbon layer to wrap it, so as to form a complete capacitor chip 3;

[0058] S5, stacking two capacitor chips 3 on the front and back sides of the conductive frame respectively by a fixing device, and bonding and fixing the cathode areas of the adjacent capacitor chips 3 and the cathode areas of the capacitor chips 3 and the conductive frame by four silver paste dots 34;

[0059] (1) S6, sending the conductive frame with four capacitor chips 3 stacked on it in S5 to a welding device for laser welding of the positive electrode area. The welding width is consistent with the width of the capacitor chip 3. The contact area between the anode area and the connection frame is increased by laser welding, and the burrs caused by multiple welding of the anode area are reduced.

[0060] S7, encapsulating the four capacitor chips 3 and the conductive frame welded in S6 with epoxy resin to form a capacitor with a shell, and then aging the capacitor;

[0061] S8, take a capacitor after S7 packaging aging, and bend the left and right lead ends of its connecting frame downward vertically to form an A-type first pin 111 and an A-type second pin 112. This capacitor is an A-type first split 11; take another capacitor after S7 packaging aging, bend the left and right lead ends of its connecting frame downward vertically to the bottom of the capacitor housing, and then bend them 90 degrees inside the housing to form an A-type third pin 121 and an A-type fourth pin 122. This capacitor is an A-type second split 12;

[0062] S9. The A-type first split body 11 and the A-type second split body 12 are connected in parallel up and down, and the shells are connected and fixed by the A-type first adhesive layer 123. The A-type first pin 111 and the A-type third pin 121 as well as the A-type second pin 112 and the A-type fourth pin 122 are aligned and coated with conductive connecting material to fix them, and then the A-type first split body 11 and the A-type second split body 12 are reflow-soldered to form a conductive connection to form a large-capacity low-ESR laminated solid aluminum capacitor.

[0063] Ten multilayer solid capacitors of Example 1 were taken for performance testing using a standard test method. The sample specification was 100 μF 25V, wherein the aluminum foil specification was 38VF. The test results are shown in Table 1 below.

[0064]

[0065] Example 2

[0066] Please refer to Figures 3-4 The present embodiment provides a large-capacity low-ESR stacked solid-state capacitor, which includes a B-type parallel capacitor body 2, wherein the B-type parallel capacitor body 1 includes a B-type first split body 21 and a B-type second split body 22, wherein the B-type first split body 21 and the B-type second split body 22 are stacked and connected in parallel, and specifically, the B-type first split body 21 and the B-type second split body 22 are respectively provided with an anode pin and a cathode pin, and the anode pins of the B-type first split body 21 and the B-type second split body 22 are conductively connected to each other, and the cathode pins of the B-type first split body 21 and the B-type second split body 22 are conductively connected to each other.

[0067] In this embodiment, the internal structures of the B-type first sub-body 21 and the B-type second sub-body 22 are the same as the internal structures of the A-type first sub-body 11 and the A-type second sub-body 12 in Embodiment 1.

[0068] Furthermore, in the B-type first split body 21, after the conductive frame is connected to the anode area of ​​the capacitor chip 3, a B-type first pin 211 is led out from the shell, and the B-type first pin 211 is the anode pin. After the conductive frame is connected to the cathode area of ​​the capacitor chip 3, a B-type second pin 212 is led out from the shell, and the B-type second pin 212 is the cathode pin. The B-type first pin 211 and the B-type second pin 212 are led out from the left and right sides of the shell of the B-type first split body 21 and extend vertically to the bottom of the shell protruding from the B-type first split body 21, and then bend toward the inside of the shell of the B-type first split body 21.

[0069] Further, in the B-type second split body 22, after the conductive frame is connected to the anode area of ​​the capacitor chip 3, the B-type third pin 221 is led out from the shell, and the B-type third pin 221 is the anode pin. After the conductive frame is connected to the cathode area of ​​the capacitor chip 3, the B-type fourth pin 222 is led out from the shell, and the B-type fourth pin 222 is the cathode pin. Specifically, the B-type third pin 221 and the B-type fourth pin 222 are led out from the left and right sides of the shell and extend vertically upward to the top of the shell protruding from the B-type second split body 22, and then bend toward the inside of the shell of the B-type second split body 22.

[0070] Furthermore, a B-type first adhesive layer 223 is provided between the bottom surface of the shell of the B-type first split body 21 and the top surface of the shell of the B-type second split body 22 to fix them to each other.

[0071] Furthermore, the B-type first sub-body 21 and the B-type second sub-body 22 are conductively connected via a connecting frame, and the connecting frame includes a C-shaped first connecting frame 23 and a second connecting frame 24 that are buckled on the left and right sides of the B-type second sub-body 22 .

[0072] Specifically, the upper surface and the lower surface of the top end of the first connecting frame 23 are respectively connected to the B-type first pin 211 and the B-type third pin 221 through conductive materials, and then extend downward to protrude from the bottom of the B-type second split 22 and then bend toward the inside of the B-type second split 22; the upper surface and the lower surface of the top end of the second connecting frame 24 are respectively connected to the B-type first pin 211 and the B-type third pin 221 through conductive materials, and then extend downward to protrude from the bottom of the B-type second split 22 and then bend toward the inside of the B-type second split 22.

[0073] The difference between the preparation method of the large-capacity low-ESR laminated solid capacitor proposed in this embodiment and the preparation method of Example 1 is that:

[0074] S8. Take a capacitor that has been aged by S7 packaging, bend the lead ends on both sides of its connecting frame vertically downward, and then bend its vertically extending end protruding from the bottom surface of the capacitor shell toward the inside of the capacitor to form a B-type first pin 211 and a B-type second pin 212. The capacitor is a B-type first split 21. Take another capacitor that has been aged by S7 packaging, bend the lead ends on both sides of its connecting frame vertically upward, and then bend its vertically extending end protruding from the top surface of the capacitor shell toward the inside of the capacitor to form a B-type third pin 221 and a B-type fourth pin 222. The capacitor is a B-type second split 22.

[0075] S9. Connect the B-type first split body 21 and the B-type second split body 22 in parallel up and down, connect and fix the shells through the B-type first adhesive layer 223, buckle the first connecting frame 23 on the left outer side of the B-type second split body 22, wherein the upper and lower surfaces of the top of the first connecting frame 23 are coated with conductive connecting materials and are respectively aligned and fixed with the B-type first pin 211 and the B-type third pin 221, buckle the second connecting frame 24 on the right outer side of the B-type second split body 22, wherein the upper and lower surfaces of the top of the second connecting frame 24 are coated with conductive connecting materials and are respectively aligned and fixed with the B-type second pin 212 and the B-type fourth pin 222, and then reflow soldering is performed to make the B-type first split body 21 and the B-type second split body 22 form a conductive connection to form a large-capacity low-ESR laminated solid aluminum capacitor.

[0076] Ten multilayer solid capacitors of Example 2 were taken for performance testing using a standard test method. The sample specification was 100 μF 25V, wherein the aluminum foil specification was 38VF. The test results are shown in Table 2 below.

[0077]

[0078] Example 3

[0079] This embodiment provides a large-capacity low-ESR laminated solid capacitor, which differs from the first embodiment only in that the arrangement of the silver paste dots 34 between the cathode regions of the capacitor chip 3 of the A-type first sub-body 11 and the A-type second sub-body 12 and between the cathode region of the capacitor chip 3 and the conductive frame is a six-point arrangement, such as Fig. 9 As shown, the six-point type is evenly spaced in three rows and two columns.

[0080] Ten multilayer solid capacitors of Example 3 were taken for performance testing using a standard test method. The sample specification was 100 μF 25V. The test results are shown in Table 3 below.

[0081]

[0082] Example 4

[0083] This embodiment provides a large-capacity low-ESR laminated solid capacitor, which is different from the first embodiment in that the arrangement of the silver paste dots 34 between the cathode area of ​​the capacitor chip 3 of the A-type first sub-body 11 and the A-type second sub-body 12 and between the cathode area of ​​the capacitor chip 3 and the conductive frame is a nine-point arrangement, such as Fig.10 As shown, the nine-point type is evenly spaced in three rows and three columns.

[0084] Ten multilayer solid capacitors of Example 4 were taken for performance testing using a standard test method. The sample specification was 100 μF 25V, wherein the aluminum foil specification was 38VF. The test results are shown in Table 4 below.

[0085]

[0086]

[0087] Example 5

[0088] This embodiment provides a large-capacity, low-ESR multilayer solid-state capacitor, which differs from Embodiment 2 only in that the silver paste dots 34 between the cathode areas of the capacitor chip 3 of the B-type first split 21 and the B-type second split 22 and between the cathode area of ​​the capacitor chip 3 and the conductive frame are arranged in a six-point manner.

[0089] Ten multilayer solid capacitors of Example 5 were taken for performance testing using a standard test method. The sample specification was 100 μF 25V, wherein the aluminum foil specification was 38VF. The test results are shown in Table 5 below.

[0090]

[0091] Example 6

[0092] This embodiment provides a large-capacity, low-ESR multilayer solid-state capacitor, which differs from Embodiment 2 only in that the silver paste dots 34 between the cathode areas of the capacitor chip 3 of the B-type first split 21 and the B-type second split 22 and between the cathode area of ​​the capacitor chip 3 and the conductive frame are arranged in a nine-point manner.

[0093] Ten multilayer solid capacitors of Example 6 were taken for performance testing using a standard test method. The sample specification was 100 μF 25V, of which the aluminum foil specification was 38VF. The test results are shown in Table 6 below.

[0094]

[0095] Example 7

[0096] like Figure 5 As shown, this embodiment provides a large-capacity low-ESR laminated solid capacitor, as a further improvement of embodiment 1, which includes an A-type parallel capacitor body 1', the A-type parallel capacitor body 1' includes an A-type third sub-body 13, an A-type first sub-body 11 and an A-type second sub-body 12 which are sequentially stacked and connected in parallel, the connection method between the A-type first sub-body 11 and the A-type second sub-body 12 is the same as that of embodiment 1, and the structure of the A-type third sub-body 13 is the same as that of the A-type first sub-body 11. Specifically, in the A-type third sub-body 13, after the conductive frame is connected to the anode area of ​​the capacitor chip 3, the A-type fifth pin 131 is led out from the shell, and the A-type fifth pin 131 is the anode pin, and after the conductive frame is connected to the cathode area of ​​the capacitor chip 3, the A-type sixth pin 132 is led out from the shell, and the A-type sixth pin 132 is the cathode pin, and the A-type fifth pin 131 and the A-type sixth pin 132 extend vertically downward toward the first sub-body 11.

[0097] Further, an A-type second adhesive layer 113 is provided between the bottom surface of the shell of the A-type third split body 13 and the top surface of the shell of the A-type first split body 11 to fix them to each other. The A-type fifth pin 131 is led out from the left side of the shell of the third split body 13 and covers and fits the outer surface of the A-type first pin 111 in the vertical direction, and a conductive connecting material is provided between the A-type fifth pin 131 and the A-type first pin 111. The A-type sixth pin 132 is led out from the right side of the shell of the third split body 13 and covers and fits the outer surface of the A-type second pin 112 in the vertical direction, and a conductive connecting material is provided between the A-type sixth pin 132 and the A-type second pin 112. Further, the conductive material is a conductive connecting material.

[0098] Ten multilayer solid capacitors of Example 7 were taken for performance testing using a standard test method, and the sample specification was 100 μF 25V, and the test results are shown in Table 7. In this comparative example, the aluminum foil specification was changed to 49VF (the thickness of the aluminum foil oxide film was increased, thereby reducing the capacitance value) to ensure that the capacity of the three capacitors does not exceed the upper limit of the 100 μF specification capacity of 120 μF when they are connected in parallel.

[0099]

[0100] Example 8

[0101] like Figure 6 As shown, this embodiment provides a large-capacity, low-ESR multilayer solid-state capacitor, which is a further improvement on Example 2 and includes a B-type parallel capacitor body 2', wherein the B-type parallel capacitor body 2' includes a B-type first split 21, a B-type second split 22 and a B-type third split 25 which are sequentially stacked and connected in parallel from top to bottom, and the connection method between the B-type first split 21 and the B-type second split 22 is the same as that in Example 2, and the structure of the B-type third split 25 is the same as that of the B-type second split 22.

[0102] Further, in the B-type third sub-body 25, after the conductive frame is connected to the anode area of ​​the capacitor chip 3, the B-type fifth pin 251 is led out from the shell, and the B-type fifth pin 251 is the anode pin. After the conductive frame is connected to the cathode area of ​​the capacitor chip 3, the B-type sixth pin 252 is led out from the shell, and the B-type sixth pin 252 is the cathode pin. Specifically, the B-type fifth pin 251 and the B-type sixth pin 252 are led out from the left and right sides of the shell and extend vertically upward to the top of the shell protruding from the B-type third sub-body 25, and then bend toward the inner direction of the shell of the B-type third sub-body 25.

[0103] Furthermore, a B-type second adhesive layer 253 is provided between the shell bottom surface of the B-type second sub-body 22 and the shell top surface of the B-type third sub-body 25 to fix them to each other.

[0104] Furthermore, the B-type second sub-body 22 and the B-type third sub-body 25 are conductively connected via a third connecting frame 26 and a fourth connecting frame 27 . The third connecting frame 26 and the fourth connecting frame 27 are C-shaped and are buckled on the left and right sides of the B-type third sub-body 25 .

[0105] Specifically, the upper surface and the lower surface of the top end of the third connecting frame 26 are respectively connected to the bottom of the first connecting frame 23 and the B-type fifth pin 251 through conductive materials, and then extend downward to protrude from the bottom of the B-type third split 25 and then bend toward the inside of the B-type third split 25; the upper surface and the lower surface of the top end of the fourth connecting frame 27 are respectively connected to the bottom of the second connecting frame 24 and the B-type sixth pin 252 through conductive materials, and then extend downward to protrude from the bottom of the B-type third split 25 and then bend toward the inside of the B-type third split 25.

[0106] Ten multilayer solid capacitors of Example 8 were taken for performance testing using a standard test method, with the sample specification being 100 μF 25V, and the test results are shown in Table 8. In this embodiment, the aluminum foil specification is 49VF, ensuring that the capacity of three capacitors connected in parallel does not exceed the upper limit of the 100 μF specification capacity of 120 μF.

[0107]

[0108]

[0109] Comparative Example 1

[0110] This comparative example provides a laminated solid capacitor, which includes a capacitor chip 3, a conductive frame and a shell, wherein the capacitor chip 3 and the conductive frame are arranged in the shell, and the capacitor chip 3 is divided into an anode area 31 and a cathode area 33 by a silicone strip 32. Further, four capacitor chips 3 are arranged on both sides of the conductive frame, and the anode areas of the capacitor chip 3 and the anode areas of the capacitor chip 3 and the connecting frame are connected by resistance welding, and the cathode areas of the capacitor chip 3 and the cathode areas of the capacitor chip 3 and the conductive frame are connected by silver paste. Specifically, a plurality of silver paste points 34 are arranged between the cathode areas of the capacitor chip 3 and between the cathode areas of the capacitor chip 3 and the conductive frame. In this comparative example, the silver paste points 34 are arranged in a four-point manner. After the conductive frame is connected to the anode area and cathode area of ​​the capacitor chip 3, the capacitor pins are led out from the left and right sides of the shell.

[0111] Ten multilayer solid capacitors of Comparative Example 1 were taken for performance testing using a standard test method. The sample specification was 100 μF 25V, and the aluminum foil specification was 38VF. The test results are shown in Table 9 below.

[0112]

[0113]

[0114] Comparative Example 2

[0115] This comparative example provides a laminated solid capacitor, which is different from comparative example 1 in that the silver paste dots 34 are arranged in a single-point manner, such as Figure 7 As shown, the single-point type is that only one silver paste dot 34 is set in the center area of ​​the cathode area.

[0116] Ten multilayer solid capacitors of Comparative Example 2 were taken for performance testing using a standard test method. The sample specification was 100 μF 25V, and the aluminum foil specification was 38VF. The test results are shown in Table 10 below.

[0117]

[0118] Comparative Example 3

[0119] This comparative example provides a laminated solid-state capacitor, which differs from comparative example 1 in that six capacitor chips 3 are provided on both sides of the conductive frame. However, the inventors of this application found that the products of this comparative example all had failure modes of delamination, deformation and overheating during the test, and the product performance was unqualified. The laminated solid-state capacitor provided in the embodiment of the present invention optimizes the layout and connection method of the capacitor chip by adopting a split parallel structure, reduces the interlayer delamination and deformation problems caused by thermal stress and mechanical stress, thereby improving the structural stability and reliability of the product. At the same time, the split parallel structure can more efficiently utilize space and increase the effective connection area of ​​the capacitor chip, thereby significantly improving the capacitance and meeting the needs of high-capacity applications.

[0120] It should be noted that the conductive connecting material used in the embodiments of the present invention and the comparative examples is a lead-free high-temperature solder paste containing 1% to 3% by mass of silver; the A-type first adhesive layer 123, the A-type second adhesive layer 113, the B-type first adhesive layer 223 and the B-type second adhesive layer 253 are one of epoxy glue, polyurethane glue, acrylic glue or other conventional glues for electronic appliances.

[0121] Obviously, the embodiments described above are only some embodiments of the present application, rather than all embodiments. The preferred embodiments of the present application are given in the accompanying drawings, but they do not limit the patent scope of the present application. The present application can be implemented in many different forms. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive. Although the present application is described in detail with reference to the aforementioned embodiments, for those skilled in the art, it is still possible to modify the technical solutions recorded in the aforementioned specific implementation methods, or to perform equivalent replacement of some of the technical features therein. Any equivalent structure made using the contents of the specification and drawings of this application, directly or indirectly used in other related technical fields, is similarly within the scope of patent protection of this application.

Claims

1. A large-capacity, low-ESR multilayer solid capacitor, characterized in that: The invention comprises a parallel capacitor body, wherein the parallel capacitor body comprises a plurality of capacitor split bodies which are stacked and connected in parallel; the capacitor split bodies comprise a plurality of capacitor chips (3), a conductive frame and a shell; the capacitor chips (3) and the conductive frame are arranged in the shell; a plurality of stacked capacitor chips (3) are arranged on both sides of the conductive frame; the conductive frame leads anode pins and cathode pins to the two sides of the shell respectively; the anode pins of the plurality of capacitor split bodies are conductively connected to each other; and the cathode pins of the plurality of capacitor split bodies are conductively connected to each other.

2. The large-capacity low-ESR multilayer solid capacitor according to claim 1, characterized in that: The parallel capacitor body is an A-type parallel capacitor body (1), and the A-type parallel capacitor body (1) comprises an A-type first sub-body (11) and an A-type second sub-body (12), wherein the A-type first sub-body (11) and the A-type second sub-body (12) are stacked up and connected in parallel, and the parallel connection between the A-type first sub-body (11) and the A-type second sub-body (12) is a contact parallel connection between pins.

3. The large-capacity low-ESR multilayer solid capacitor according to claim 1, characterized in that: The parallel capacitor body is a B-type parallel capacitor body (2), and the B-type parallel capacitor body (2) comprises a B-type first sub-body (21) and a B-type second sub-body (22), and the B-type first sub-body (21) and the B-type second sub-body (22) are stacked up and down and are connected in parallel through a connecting frame.

4. The large-capacity low-ESR multilayer solid capacitor according to claim 3, characterized in that: The connection frame comprises a first connection frame (23) and a second connection frame (24) which are C-shaped and buckled on the left and right sides of the B-type second split body (22).

5. The large-capacity low-ESR multilayer solid capacitor according to claim 1, characterized in that: The parallel capacitor body is an A-type parallel capacitor body (1'), and the A-type parallel capacitor body (1') comprises an A-type third sub-body (13), an A-type first sub-body (11) and an A-type second sub-body (12) which are sequentially stacked and connected in parallel, and the A-type third sub-body (13), the A-type first sub-body (11) and the A-type second sub-body (12) are connected in parallel with each other in contact with each other between pins.

6. The large-capacity low-ESR multilayer solid capacitor according to claim 1, characterized in that: The parallel capacitor body is a B-type parallel capacitor body (2'), and the B-type parallel capacitor body (2') comprises a B-type first sub-body (21), a B-type second sub-body (22) and a B-type third sub-body (25) stacked in sequence from top to bottom, and the B-type first sub-body (21), the B-type second sub-body (22) and the B-type third sub-body (25) are connected in parallel through a connection frame.

7. The large-capacity, low-ESR multilayer solid capacitor according to claim 1, characterized in that: The capacitor chip (3) is provided with an anode region and a cathode region, and a plurality of silver paste dots (34) are provided between the cathode regions of the capacitor chip (3) and between the cathode region of the capacitor chip (3) and the conductive frame.

8. The large-capacity, low-ESR multilayer solid capacitor according to claim 7, characterized in that: The silver paste dots (34) are arranged in a four-dot, six-dot or nine-dot style.

9. The large-capacity, low-ESR multilayer solid capacitor according to claim 1, characterized in that: An adhesive layer is also provided between the capacitor parts.

10. A method for preparing a large-capacity, low-ESR laminated solid capacitor, characterized in that: The following steps are involved: Step 1, cutting and punching the aluminum foil to separate the anode area and the cathode area through a silica gel strip (32); Step 2, after the cathode area of ​​the aluminum foil is impregnated in the impregnation liquid, a polymer layer, a carbon layer and a silver layer are sequentially generated from the inside to the outside of the cathode area to form a complete capacitor chip (3); Step 3, a plurality of capacitor chips (3) are stacked on the front and back sides of the conductive frame respectively, and the cathode areas of adjacent capacitor chips (3) and the cathode areas of the capacitor chips (3) and the conductive frame are bonded and fixed by a plurality of silver paste dots (34); Step 4, laser welding the conductive frame on which the plurality of capacitor chips (3) are stacked in step 3; Step 5: Packaging and aging to form a capacitor split body, and the conductive frame leads out the anode pin and the cathode pin on the left and right sides of the capacitor split body; Step 6: After a number of capacitors are stacked up and down and fixed by an adhesive layer, the anode pins and cathode pins of each capacitor are connected in parallel by contact between the pins or by connecting the frames.

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