Stacked chip structure, integrated circuit package and manufacturing method thereof

Abstract

The invention discloses a through-via power transfer structure for a chip stack and a method of manufacturing the same. An exemplary stacked chip structure includes a first chip and a second chip. The first chip has a first substrate, a first device layer, and a first interconnect structure. The second chip has a second substrate, a second device layer, and a second interconnect structure. A first through-via extends through the first substrate, the first device layer, the first interconnect structure, and into the second interconnect structure. A second through-via extends through the first substrate, the first device layer, and into the first interconnect structure. The second through-hole and the first through-hole may be electrically connected to the first device layer and the second device layer, respectively, and power may be transmitted to the first device layer and the second device layer via the second through-hole and the first through-hole, respectively. Embodiments of the present disclosure also relate to an integrated circuit package and a method of manufacturing the same.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a stacked chip structure, an integrated circuit package, and a method for manufacturing the same. Background Art

[0002] Advanced integrated circuit (IC) packaging techniques have been explored to further reduce the density of ICs and / or improve the performance of ICs. For example, IC packaging has evolved so that multiple ICs can be vertically stacked into a three-dimensional ("3D") package or a 2.5D package (e.g., a package that employs an interposer). While existing power delivery structures for stacked ICs of advanced IC packages have generally been adequate for their intended purposes, they have not been completely satisfactory in all respects. Summary of the invention

[0003] An embodiment of the present disclosure provides a stacked chip structure, comprising: a first chip attached to a second chip, wherein the first chip has a first substrate, a first device layer and a first interconnect structure, and the second chip has a second substrate, a second device layer and a second interconnect structure; and a first through hole and a second through hole, wherein: the first through hole extends through the first substrate, through the first device layer, through the first interconnect structure, and into the second interconnect structure, and the second through hole extends through the first substrate, through the first device layer, and into the first interconnect structure.

[0004] Another embodiment of the present disclosure also provides an integrated circuit package, comprising: a first die bonded to a second die, wherein the first die includes a first device layer and the second die includes a second device layer; a first power transmission through-hole extending through the first die and into the second die, wherein the first power transmission through-hole is connected to the second device layer; and a second power transmission through-hole extending into the first die, wherein the second power transmission through-hole is connected to the first device layer.

[0005] Another embodiment of the present disclosure also provides a method for manufacturing an integrated circuit package, comprising: bonding a first chip to a second chip, wherein the first chip has a first substrate, a first device layer and a first interconnect structure, and the second chip has a second substrate, a second device layer and a second interconnect structure; and forming a first through hole and a second through hole, wherein: the first through hole extends through the first substrate, through the first device layer, through the first interconnect structure, and into the second interconnect structure, and the second through hole extends through the first substrate, through the first device layer, and into the first interconnect structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. For clarity of discussion, the dimensions of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 is a cross-sectional view of part or all of a stacked chip structure with a power delivery structure according to various aspects of the present disclosure.

[0008] Figure 2A is a cross-sectional view of part or all of a stacked chip structure with another power delivery structure according to various aspects of the present disclosure.

[0009] Figure 2B is a cross-sectional view of part or all of a stacked chip structure with another power delivery structure according to various aspects of the present disclosure.

[0010] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E According to various aspects of the present disclosure Figure 1 A stacked chip structure and / or Figure 2A An enlarged cross-sectional view of a corresponding portion of the stacked chip structure.

[0011] Figure 4A , Figure 4B and Figure 4C is a top view of different configurations of guard rings according to various aspects of the present disclosure, which may be partially or fully formed around a through hole and may be formed in Figure 1 A stacked chip structure and / or Figure 2A The stacked chip structure is implemented in the

[0012] Figure 5A According to various aspects of the present disclosure Figure 2A A plan view of part or all of a power transmission structure of a stacked chip structure.

[0013] Figure 5B According to various aspects of the present disclosure Figure 2A Another plan view of part or all of the power transmission structure of the stacked chip structure.

[0014] Fig. 6A According to various aspects of the present disclosure Figure 1 A plan view of part or all of a power transmission structure of a stacked chip structure.

[0015] Figure 6B According to various aspects of the present disclosure Figure 2AA plan view of part or all of a power transmission structure of a stacked chip structure.

[0016] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 7F , Figure 7G , Figure 7H , Fig.7I and Figure 7J is a partial or complete plan view of a power transmission structure according to various aspects of the present disclosure, the power transmission structure having a configuration that can be at least Figure 2A and Figure 2B Various configurations implemented in a stacked chip structure.

[0017] Figure 8 is a cross-sectional view of part or all of another stacked chip structure having a power delivery structure according to various aspects of the present disclosure.

[0018] Figures 9 to 17 According to various aspects of the present disclosure Figure 1 A partial or complete cross-sectional view of a stacked chip structure during fabrication.

[0019] Figures 18 to 26 According to various aspects of the present disclosure Figure 2A A partial or complete cross-sectional view of a stacked chip structure during fabrication. DETAILED DESCRIPTION

[0020] The present disclosure relates generally to integrated circuit (IC) packaging and, more particularly, to an improved power delivery structure for stacked chips.

[0021] The following disclosure provides many different embodiments or examples for realizing the different features of the present disclosure. The specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted and formed, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, in order to facilitate the present disclosure to describe the relationship between a component and another component, spatial relative terms are used, for example, "lower", "upper", "horizontal", "vertical", "above...", "above...", "below...", "below...", "upward", "downward", "top", "bottom", etc. and their derivatives (e.g., "horizontally", "downwardly", "upwardly", etc.). Spatially relative terms are intended to cover different orientations of devices including components.

[0022] In addition, when "about," "approximately," "substantially," and the like are used to describe a value or a range of values, the term is intended to encompass values ​​within a reasonable range, taking into account variations inherent during manufacturing as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing components having characteristics associated with the value, the value or range of values ​​encompasses a reasonable range including the described value, such as within + / -10% of the described value. For example, a material layer having a thickness of "about 5 nm" may encompass a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing the material layer is known to those of ordinary skill in the art to be + / -10%. In another example, two components described as having "substantially the same" size and / or "substantially" orientation in a particular direction and / or configuration (e.g., "substantially parallel" or "substantially perpendicular") encompass size differences between the two components and / or slight orientation differences of the two components from the precisely specified orientation, which may be inherently but not intentionally generated by manufacturing tolerances associated with manufacturing the two components. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0023] Disclosed herein is a through-hole power transmission structure for a stacked chip structure that can reduce resistance-capacitance (RC) delay, improve power transmission efficiency, reduce the area consumed by the power transmission structure of the IC package, and thus improve chip (die) area utilization, reduce the through-hole pitch, increase power transmission design flexibility (e.g., by decoupling the through-hole size (e.g., through-hole pitch) from the chip bonding pitch), or a combination thereof. The through-hole power transmission structure described herein can provide a power transmission through-hole for each chip of the stacked chip structure. Different embodiments can have different advantages, and no particular advantage is required by any embodiment.

[0024] Figure 1 is a cross-sectional view of part or all of a stacked chip structure 100A having an improved power transmission structure according to various aspects of the present disclosure. Figure 2A is a cross-sectional view of part or all of a stacked chip structure 100B having another improved power transmission structure according to various aspects of the present disclosure. Figure 2B is a cross-sectional view of part or all of a stacked chip structure 100C having another improved power transmission structure according to various aspects of the present disclosure. Figure 8is a cross-sectional view of part or all of a stacked chip structure 100D having an improved power transmission structure according to various aspects of the present disclosure. The stacked chip structure 100B is similar to the stacked chip structure 100A in many respects, the stacked chip structure 100C is similar to the stacked chip structure 100B in many respects, and the stacked chip structure 100D is similar to the stacked chip structure 100A in many respects. Therefore, for the sake of clarity and simplicity, Figure 8 , Figure 2B , Figure 2A and Figure 1 Similar components in the drawings are identified by the same reference numerals. Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E is an enlarged cross-sectional view of a portion of a stacked chip structure 100A- 100D according to various aspects of the present disclosure. Figure 4A , Figure 4B and Figure 4C is a top view of a guard ring according to various aspects of the present disclosure, which may be partially or fully formed around a through-hole and may be implemented in the stacked chip structures 100A- 100D. Figure 5A is a plan view of part or all of a power transmission structure of a stacked chip structure 100B according to various aspects of the present disclosure. Figure 5B is another plan view of a portion or all of a power transmission structure of a stacked chip structure 100B according to various aspects of the present disclosure. Fig. 6A is a plan view of part or all of a power transmission structure of a stacked chip structure 100A according to various aspects of the present disclosure. Figure 6B is a plan view of part or all of a power transmission structure of a stacked chip structure 100B according to various aspects of the present disclosure. Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 7F , Figure 7G , Figure 7H , Fig.7I and Figure 7J is a partial or full plan view of a power transmission structure with various configurations according to various aspects of the present disclosure, which may be implemented in the stacked chip structures 100A-100D. For ease of description and understanding, this document also discusses Figure 1 , Figure 2A , Figure 2B , FIG. 3A to FIG. 3E , FIG. 4A to FIG. 4C , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , 7A to 7J and Figure 8 . Simplified for clarity Figure 1 , Figure 2A , Figure 2B , FIG. 3A to FIG. 3E , FIG. 4A to FIG. 4C , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , 7A to 7J and Figure 8 , to better understand the inventive concept of the present disclosure. Additional components may be added to the stacked chip structure, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the stacked chip structure.

[0025] refer to Figure 1 , the stacked chip structure 100A includes a chip stack having a chip 102 and a chip 104. The chip 104 is mounted on the chip 102 and is stacked vertically above the chip 102. The chip stack can form an IC (and / or semiconductor) package or part thereof. The chip 102 and the chip 104 can be the bottom chip and the top chip of the chip stack and / or the IC package, respectively. Each of the chip 102 and the chip 104 includes at least one functional IC, such as an IC configured to perform a logic function, a memory function, a digital function, an analog function, a mixed signal function, a radio frequency (RF) function, an input / output (I / O) function, a communication function, a power management function, other functions, or a combination thereof. In some embodiments, the chip 102 and the chip 104 provide the same function (for example, both can be a central processing unit (CPU)). In some embodiments, the chip 102 and the chip 104 provide different functions (for example, one can be a CPU, and the other can be a graphics processing unit (GPU) or a static random access memory (SRAM)). In some embodiments, chip 102 and / or chip 104 is a system on chip (SoC), which generally refers to a single chip and / or a monolithic die having multiple functions. In some embodiments, a SoC is a single chip having an entire system (such as a computer system) manufactured thereon. In some embodiments, an IC package provides an integrated system on chip (SoIC). SoIC can have a multi-chip, mixed node design, and chip 102 and chip 104 can have different functions (e.g., CPU, GPU, RF, SRAM, etc.), and can be manufactured according to different process nodes (e.g., 3nm (N3), N5, N65, 0.13 microns (μm) (C013), etc.), where the functions and process nodes can be selected based on design specifications (such as power, performance, area and cost (PPAC) specifications).

[0026] Each of chip 102 and chip 104 may include a device layer, such as device layer DL1 and device layer DL2, respectively. Device layer DL1 includes circuits fabricated on and / or over the front side of substrate 106, and device layer DL2 includes circuits fabricated on and / or over the front side of substrate 108. The circuits may be fabricated by front-end-of-line (FEOL) processing. Device layer DL1 and / or device layer DL2 may include various device components, such as a semiconductor substrate, a doped well (e.g., an n-well and / or a p-well), an isolation component (e.g., a shallow trench isolation (STI) structure and / or other suitable isolation structures), a gate (e.g., a gate stack having a gate electrode and a gate dielectric), a gate spacer along the sidewall of the gate, a source / drain (e.g., an epitaxial source / drain), other suitable device components / components, or a combination thereof. In some embodiments, device layer DL1 and / or device layer DL2 include a planar transistor. The channel of the planar transistor can be formed in a semiconductor substrate (e.g., substrate 106 and / or substrate 108) between corresponding sources / drains, and the corresponding gate of the planar transistor can be set on the channel (e.g., on a portion of the semiconductor substrate where the channel is formed between the source / drain). In some embodiments, the device layer DL1 and / or the device layer DL2 includes a non-planar transistor having a channel formed in a corresponding semiconductor fin, the semiconductor fin extending from the semiconductor substrate, the channel being located between the corresponding source / drain on / in the semiconductor fin, wherein the corresponding gate is set on the channel of the corresponding semiconductor fin and wraps the channel of the corresponding semiconductor fin (i.e., the non-planar transistor is a fin field effect transistor (FinFET)). In some embodiments, the device layer DL1 and / or the device layer DL2 includes a non-planar transistor having a channel formed in a semiconductor layer, the channel being suspended above the semiconductor substrate and extending between the corresponding source / drain, wherein the corresponding gate is set on the corresponding channel and at least partially surrounds the corresponding channel (i.e., the non-planar transistor is a full-all-around gate (GAA) transistor and / or a fork-piece transistor). Depending on design requirements, transistors of device layer DL1 and / or device layer DL2 can be configured as planar transistors and / or non-planar transistors. In some embodiments, device layer DL1 and / or device layer DL2 include stacked transistors, such as complementary field effect transistors (CFETs) and / or other stacked transistors.

[0027] The device layer DL1 and / or the device layer DL2 may include various passive electronic devices and / or active electronic devices, such as resistors, capacitors, inductors, diodes, p-type FETs (PFETs), n-type FETs (NFETs), metal oxide semiconductor (MOS) FETs (MOSFETs), complementary MOS (CMOS) transistors, bipolar junction transistors (BJTs), lateral diffusion MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable devices and / or components, or combinations thereof. The various electronic devices may be configured to provide functionally different regions of the IC, such as a logic region (i.e., a core region), a memory region, an analog region, a peripheral region (e.g., an I / O region), a pseudo region, other suitable regions, or combinations thereof. The logic region may be configured with standard cells, each of which may provide a logic device and / or logic function, such as an inverter, an AND gate, a NAND gate, an OR gate, a NOR gate, a NOT gate, an XOR gate, an XNOR gate, other suitable logic devices, or combinations thereof. The memory region may be configured with memory cells, each of which may provide a memory device and / or storage function, such as flash memory, non-volatile random access memory (NVRAM), SRAM, dynamic random access memory (DRAM), other volatile memory, other non-volatile memory, other suitable memory, or a combination thereof. In some embodiments, the memory cells and / or logic cells include transistors and interconnect structures, which may be combined to provide a memory device / function and a logic device / function, respectively.

[0028] refer to Figure 3A , provides an enlarged view of region I of stacked chip structure 100A, which depicts a portion of device components and / or device assemblies of device layer DL1 of chip 102. Figure 3A, the device layer DL1 includes various transistors, such as transistor T1 and transistor T2, formed above / on a substrate 106. Each of transistor T1 and transistor T2 includes a corresponding gate structure 110 disposed between corresponding source / drain 112 (e.g., epitaxial source / drain), the source / drain 112 may be disposed in the substrate 106, and each of transistor T1 and transistor T2 has a corresponding channel extending between the corresponding drain / source 112. The gate structure 110 may include a gate stack (e.g., a gate electrode disposed above a gate dielectric) and a gate spacer disposed along a sidewall of the gate stack, and the substrate 106 may be a semiconductor substrate (e.g., a silicon substrate). The device layer DL1 may also include an isolation structure 114, such as an STI structure, which separates and / or electrically isolates the transistor T1 and / or transistor T2 from other transistors or devices of the device layer DL1. The device layer DL1 may further include an insulator layer such as a dielectric layer 116 disposed over the substrate 106, and the gate structures 110 of the transistors T1 and T2 may be disposed in the dielectric layer 116. In some embodiments, the dielectric layer 116 has a multi-layer structure and may include, for example, an interlayer dielectric (ILD) layer and / or a contact etch stop layer (CESL).

[0029] refer to Figure 3B , provides an enlarged view of region II of the stacked chip structure 100A, which depicts a portion of a device component and / or device assembly of a device layer DL2 of the chip 104. Figure 3B , the device layer DL2 also includes various transistors, such as transistor T3 and transistor T4, formed above / on the substrate 108. Each of the transistors T3 and T4 includes a corresponding gate structure 118 disposed between corresponding sources / drains 120 (e.g., epitaxial sources / drains), the source / drain 120 being disposed in the substrate 108, and each of the transistors T3 and T4 having a corresponding channel extending between the corresponding sources / drains 120 in the substrate 108. The gate structure 118 may include a gate stack (e.g., a gate electrode disposed above a gate dielectric) and a gate spacer disposed along a sidewall of the gate stack, and the substrate 108 may be a semiconductor substrate. The device layer DL2 may also include an isolation structure 122 that separates and / or electrically isolates the transistors T3 and / or transistor T4 from other transistors or devices of the device layer DL2. The device layer DL2 may further include an insulator layer such as a dielectric layer 124 disposed over the substrate 108, and the gate structures 118 of the transistors T3 and T4 may be disposed in the dielectric layer 124. In some embodiments, the dielectric layer 124 has a multi-layer structure and may include, for example, an ILD layer and / or a CESL.

[0030] refer to Figure 1, Figure 3A and Figure 3B , each of chip 102 and chip 104 may include a front-side multilayer interconnect (FMLI) structure, such as an FMLI-1 structure over the front side of substrate 106 and an FMLI-2 structure over the front side of substrate 108, respectively. Each of the FMLI-1 structure and the FMLI-2 structure includes a combination of dielectric layers (depicted as insulating layer 120-1 and insulating layer 120-2) and conductive layers (e.g., patterned metal layers, each of which may be a set of metal lines, metal vias, metal contacts, or a combination thereof arranged in a desired pattern), which combine to form an interconnect (routing) structure. The interconnect structure may include vertically oriented conductive features (such as metal contacts and / or metal vias) that connect horizontally oriented conductive features (such as metal lines) in different layers / levels (or different planes) of the corresponding FMLI structure. In some embodiments, the routing structure of the FMLI-1 structure routes electrical signals between devices and / or components of device layer DL-1, the FMLI-1 structure, chip 102, chip 104, the FMLI-2 structure, external devices and / or components, or a combination thereof. In some embodiments, the routing structure of the FMLI-2 structure routes electrical signals between devices and / or components of device layer DL-2, the FMLI-2 structure, chip 104, chip 102, the FMLI-1 structure, external devices and / or components, or a combination thereof. In some embodiments, the FMLI-1 structure and / or the FMLI-2 structure distribute electrical signals (e.g., clock signals, voltage signals, ground signals, etc.) to devices / components of chip 102, devices / components of chip 104, external devices and / or components, or a combination thereof.

[0031] The FMLI-1 structure includes a device-level contact layer and / or via layer (collectively referred to as a via zero layer (V0 layer)), a metal zero layer (M0 layer), a via one layer (V1 layer), a metal one layer (M1 layer), a via two layer (V2 layer), a metal two layer (M2 layer) ... a via (X-1) layer (V(X-1) layer), a metal (X-1) layer (M(X-1) layer), a via X layer (VX layer), and a metal X layer (MX layer), where X is an integer (e.g., from 2 to 10). Each level of the FMLI-1 structure may include a conductive feature, such as a metal line 122 or a metal via 124, disposed in a portion of the insulating layer 120-1. The metal lines 122 of the M0 level, the M1 level, the M2 level, ... the M(X-1) level, and the MX level may be referred to as M0 lines, M1 lines, M2 lines, ... M(X-1) lines, and MX lines, respectively. The metal vias 124 of the V0 level, V1 level, V2 level, ... V(X-1) level, and VX level may be referred to as V0 vias, V1 vias, V2 vias, ... V(X-1) vias, and VX vias, respectively. Each metal via 124 may physically and / or electrically connect a metal line 122 below (e.g., a corresponding M1 line) and a metal line 122 above (e.g., a corresponding M2 line), a device level contact below (e.g., a source / drain contact) and a metal line 122 above (e.g., a corresponding M0 line), or a device component below (e.g., a gate and / or a source / drain) and a metal line 122 above (e.g., a corresponding M0 line).

[0032] The FMLI-2 structure may be similar to the FMLI-1 structure. For example, the FMLI-2 structure includes a corresponding V0 level, a corresponding M0 level, a corresponding V1 level, a corresponding M1 level, a corresponding V2 level, a corresponding M2 level, ... a via (Y-1) layer (V(Y-1) level), a metal (Y-1) layer (M(Y-1) level), a via Y layer (VY level), and a metal Y layer (MY level), where Y is an integer (e.g., from 2 to 10). Y may be the same as or different from X. Each level of the FMLI-2 structure may include a conductive component, such as a metal line 126 or a metal via 128, disposed in a portion of the insulating layer 120-2. The metal lines 126 of the M0 level, the M1 level, the M2 level, ... the M(Y-1) level, and the MY level may be referred to as M0 lines, M1 lines, M2 lines, M(Y-1) lines, and MY lines, respectively. The metal vias 128 of the V0 level, V1 level, V2 level, ... V(Y-1) level, and VY level may be referred to as V0 vias, V1 vias, V2 vias, ... V(Y-1) vias, and VY vias, respectively. Each metal via 128 may physically and / or electrically connect a metal line 126 below (e.g., a corresponding M1 line) and a metal line 126 above (e.g., a corresponding M2 line), a device level contact below (e.g., a source / drain contact) and a metal line 126 above (e.g., a corresponding M0 line), or a device component below (e.g., a gate and / or source / drain) and a metal line 126 above (e.g., a corresponding M0 line).

[0033] The device level (e.g., the bottommost level) of the FMLI-1 structure (e.g., the V0 level) may be manufactured by a middle-of-line (MOL) process, and additional levels of the FMLI-1 structure (e.g., the M0 level and above) may be manufactured by a back-end-of-line (BEOL) process. Thus, the V0 level of the chip 102 may be referred to as an MOL structure, and the M0 level and above of the chip 102 may be referred to as a BEOL structure. Again, referring to Figure 3A, region I may also include at least part of the V0 level, the M0 level, and the V1 level of the chip 102. The V0 level may include a dielectric layer 116, a dielectric layer 130 located above the dielectric layer 116, a source / drain contact (MD) located in the dielectric layer 116, a source / drain via (VD) located in the dielectric layer 130, and a gate contact (VG) (e.g., gate contact 132) located in the dielectric layer 130. The gate contact 132 connects the corresponding gate structure 110 (e.g., its gate electrode) to the corresponding metal line 122 of the M0 level of the FMLI-1 structure. The M0 level may include a dielectric layer 134 in which the metal line 122 is disposed. The V1 level may include a dielectric layer 136 in which the metal via 124 is disposed. The M1 level may include a dielectric layer 138 in which the metal line 122 is disposed. Dielectric layers 116, 130, 134, 136, and 138 may form part of insulating layer 120-1. The V0 level may include an MD level formed by source / drain contacts and a VD / VG level formed by source / drain vias and / or gate contacts.

[0034] The device level (e.g., V0 level) of the FMLI-2 structure can be manufactured by MOL processing, and the additional levels (e.g., M0 level and above) of the FMLI-2 structure can be manufactured by BEOL processing. Therefore, the V0 level of the chip 104 can be referred to as the MOL structure, and the M0 level and above of the chip 104 can be referred to as the BEOL structure. Figure 3B, region II may also include at least part of the V0 level, the M0 level, the V1 level, the M1 level, the V2 level, the M2 level, the V3 level, and the M3 level of the chip 104. For example, the V0 level may include a dielectric layer 124, a dielectric layer 140 located above the dielectric layer 124, a source / drain contact (e.g., source / drain contact 142) located in the dielectric layer 124, a source / drain via (e.g., source / drain via 144) located in the dielectric layer 140, and a gate contact located in the dielectric layer 140. The source / drain contact 142 connects the corresponding source / drain 120 to the source / drain via 144, and the source / drain via 144 connects the source / drain contact 142 to the corresponding metal line 126 of the M0 level of the FMLI-2 structure. The M0 level may include a dielectric layer 146 in which a metal line 126 is disposed; the V1 level may include a dielectric layer 148 in which a metal via 128 is disposed; the M1 level may include a dielectric layer 150 in which a metal line 126 is disposed; the V2 level may include a dielectric layer 152 in which a metal via 128 is disposed; the M2 level may include a dielectric layer 154 in which a metal line 126 is disposed; the V3 level may include a dielectric layer 156 in which a metal via 128 is disposed; and the M3 level may include a dielectric layer 158 in which a metal line 126 is disposed. Dielectric layer 124, dielectric layer 140, dielectric layer 146, dielectric layer 148, dielectric layer 150, dielectric layer 152, dielectric layer 154, dielectric layer 156, and dielectric layer 158 may form part of insulating layer 120-2.

[0035] Return to reference Figure 1, the chip 102 and the chip 104 are stacked and attached (bonded) front to front and / or face to face. For example, the chip 102 has a front side FS1 formed by an FMLI-1 structure and a back side BS1 (e.g., its back side) formed by a substrate 106, the chip 104 has a front side FS2 formed by an FMLI-2 structure and a back side BS2 (e.g., its back side) formed by a substrate 108, and the FMLI-1 structure is attached (bonded) to the FMLI-2 structure. The face-to-face bonding of the chip 102 and the chip 104 can be achieved by dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding), metal-to-metal bonding (e.g., copper-to-copper bonding), metal-to-dielectric bonding (e.g., copper-to-oxide bonding), other types of bonding, or combinations thereof. In the depicted embodiment, the chip 104 is mounted on the chip 102 using hybrid bonding (i.e., using metal-to-metal bonding and non-metal-to-non-metal bonding), and the chip 104 can be electrically connected to the chip 102 via the hybrid bonding. For example, each of chip 102 and chip 104 may include a bonding structure including a non-metallic portion (e.g., bonding layer 160 and bonding layer 162, respectively) and a metal portion (bonding pad 164 and bonding pad 166, respectively). Bonding pad 164 is disposed in bonding layer 160, and bonding pad 166 is disposed in bonding layer 162. In some embodiments, bonding layer 160 and bonding layer 162 are polymer layers, including, for example, benzocyclobutene (BCB), polyimide (PI), polybenzoxazole (PBO), other polymer materials, or combinations thereof. In some embodiments, bonding pad 164 and bonding pad 166 include copper, aluminum, other suitable metals, alloys thereof, or combinations thereof. In some embodiments, bonding layer 160, bonding layer 162, bonding pad 164, bonding pad 166, or combinations thereof have a multilayer structure. Bonding pad 164 may be connected to an interconnect structure of an FMLI-1 structure, and bonding pad 164 may also be connected to an interconnect structure of an FMLI-2 structure. For example, one or more bonding pads 164 may be connected to corresponding metal lines 122 of the MX level of the FMLI-1 structure, and one or more bonding pads 166 may be connected to corresponding metal lines 126 of the MY level of the FMLI-2 structure. In some embodiments, the chip interconnect structure (e.g., corresponding bonding pads 164 and corresponding bonding pads 166) may electrically connect the FMLI-1 structure and the FMLI-2 structure.

[0036] The stacked chip structure 100A also includes a power transmission structure for transmitting power directly to each chip, such as the chip 102 and the chip 104. For example, the power transmission structure of the stacked chip structure 100A includes a through substrate via (TSV) 170-1 and a TSV 170-2 (also referred to as a through via, a through silicon via, a semiconductor through via, or a combination thereof). The TSV 170-1 is electrically connected to the device layer DL1 via the FMLI-1 structure, and the TSV 170-2 is electrically connected to the device layer DL2 via the FMLI-2 structure. For example, TSV 170-1 is connected to a corresponding metal line 122 of the FMLI-1 structure (e.g., its M3 level), which is connected to the device layer DL1 (e.g., its transistors, such as transistor T1 and / or transistor T2), and TSV 170-2 is connected to a corresponding metal line 126 of the FMLI-2 structure (e.g., its M4 level), which is connected to the device layer DL2 (e.g., its transistors, such as transistor T3 and / or transistor T4). TSV 170-1 is also electrically connected to a voltage v1, which can be generated and / or provided by a power source, and TSV 170-2 is also electrically connected to a voltage v2, which can be generated and / or provided by a power source. Therefore, TSV 170-1 can transfer and / or supply power to the devices and / or device components of the device layer DL1, and TSV 170-2 can transfer and / or supply power to the devices and / or device components of the device layer DL2.

[0037] In such an embodiment, TSV 170-1 and TSV 170-2 transmit power directly to chip 102 and chip 104, respectively, without an intermediate connection, such as a chip bonding structure. For example, TSV 170-2 is directly connected to the FMLI-2 structure, rather than being connected to the FMLI-2 structure through a hybrid chip bond (e.g., a connection formed by corresponding bonding pad 164 and corresponding bonding pad 166), and TSV 170-1 is directly connected to the FMLI-1 structure. Eliminating the intermediate connection between TSV 170-2 and the FMLI-2 structure (and / or between TSV 170-1 and the FMLI-1 structure) can reduce the resistance and / or capacitance associated with the power transmission route to chip 104 (and / or the power transmission route to chip 102), thereby reducing RC delay. In addition, eliminating the intermediate connection (e.g., chip connection / bonding) between the power transmission TSV and the FMLI structure reduces IC design constraints and improves IC design flexibility. For example, since the power transmission TSVs do not need to land on and / or connect to chip bonds or connections to facilitate power transmission, the spacing between power transmission TSVs (i.e., TSV pitch) is less (and / or not) limited by the spacing between chip bonds and connections (i.e., chip bonding pitch), and the TSV pitch can be smaller or larger than the chip bonding pitch to optimize area utilization. In other words, the power transmission TSVs can be freely placed in the disclosed stacked chip structure without the need to align the power transmission TSVs with the chip bonds / connections. In some embodiments, the spacing between the power transmission TSVs can be reduced, thereby reducing the area consumed by the power transmission structure. Providing a dedicated power transmission TSV for each chip also eliminates the need for additional routing / interconnection between the power transmission TSVs and the chip, thereby reducing the complexity of IC design and manufacturing. Dedicated power transmission TSVs can further improve power transmission efficiency by reducing the length and / or complexity of the power transmission path to the chip.

[0038] refer to Figure 3C, according to some embodiments, an enlarged view of TSV 170-1 is provided. TSV 170-1 is disposed in chip 102, but not in chip 104. For example, TSV 170-1 is disposed in substrate 106 and extends through substrate 106, into insulating layer 120-1, and reaches the M3 level of FMLI-1 structure. In some embodiments, TSV 170-1 can extend to different levels of the FMLI-1 structure, such as extending to a corresponding metal line 122 of one of the M4 level to the MX level. In some embodiments, as shown, insulating layer 172 is disposed over back side BS1 of substrate 106, and TSV 170-1 can be disposed in insulating layer 172 and extend through insulating layer 172. In some embodiments, insulating layer 172 includes a dielectric material. Insulating layer 172 can have a multi-layer structure, such as dielectric layer 174 and dielectric layer 176. Dielectric layer 174 and dielectric layer 176 have different compositions. For example, dielectric layer 174 may be an oxide layer, and dielectric layer 176 may be a nitride layer.

[0039] TSV 170-1 may include a conductive core 182A, a barrier layer 184A, and a dielectric liner 186A. In some embodiments, the conductive core 182A is wrapped by the barrier layer 184A, and the barrier layer 184A is disposed along the bottom and sidewalls of the conductive core 182A. The barrier layer 184A is located between the dielectric liner 186A and the conductive core 182A, and the dielectric liner 186A is located between the barrier layer 184A and the substrate 106, the insulating layer 120-1, and the insulating layer 172. Therefore, the bottom of TSV 170-1 may be formed by the conductive core 182A, the barrier layer 184A, and the dielectric liner 186A, the top of TSV 170-1 may be formed by the barrier layer 184A and the dielectric liner 186A, and the sidewalls of TSV 170-1 may be formed by the dielectric liner 186A.

[0040] refer to Figure 3D , according to some embodiments, an enlarged view of TSV 170-2 is provided. TSV 170-2 is disposed in chip 102 and chip 104. For example, TSV 170-2 is disposed in substrate 106, insulating layer 120-1, chip bonding structure (e.g., bonding layer 160 and bonding layer 162 thereof) and extends through substrate 106, insulating layer 120-1, chip bonding structure, into insulating layer 120-2 of FMLI-2 structure to M4 level. In some embodiments, TSV 170-2 can extend to different levels of FMLI-2 structure, such as extending to corresponding metal line 126 of one of M5 level to MY level. In some embodiments, as shown, TSV 170-2 can also be disposed in insulating layer 172 (e.g., dielectric layer 174 and dielectric layer 176 thereof) and extend through insulating layer 172.

[0041] TSV 170-2 may include a conductive core 182B, a barrier layer 184B, and a dielectric liner 186B. In some embodiments, the conductive core 182B is wrapped by the barrier layer 184B, and the barrier layer 184B is disposed along the bottom and sidewalls of the conductive core 182B. The barrier layer 184B is located between the dielectric liner 186B and the conductive core 182B, and the dielectric liner 186B is located between the barrier layer 184A and the insulating layer 172, the substrate 106, the insulating layer 120-1, the bonding layer 160, the bonding layer 162, and the insulating layer 120-2. Therefore, the bottom of TSV 170-2 may be formed by the conductive core 182B, the barrier layer 184B, and the dielectric liner 186B, the top of TSV 170-2 may be formed by the barrier layer 184B and the dielectric liner 186B, and the sidewalls of TSV 170-2 may be formed by the dielectric liner 186B.

[0042] Each of the conductive core 182A and the conductive core 182B (which may also be referred to as a column, a metal column, a body metal layer, a metal filling layer, a conductive plug, a metal plug, etc.) includes a conductive material such as aluminum, copper, titanium, tantalum, tungsten, ruthenium, cobalt, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, their alloys, their silicides, or combinations thereof. For example, the conductive core 182A and the conductive core 182B may include copper (i.e., a copper plug), tungsten (i.e., a tungsten plug), or polysilicon (i.e., a polysilicon plug). In some embodiments, the conductive core 182A and the conductive core 182B include different conductive materials. The conductive core 182A and / or the conductive core 182B may have a multilayer structure. For example, the conductive core may include a seed layer and a metal plug, wherein the seed layer is located between the metal plug and the corresponding barrier layer. The seed layer may include copper, tungsten, other suitable metals, their alloys, or combinations thereof. In some embodiments, barrier layer 184A and / or barrier layer 184B is a seed layer for the TSV.

[0043] Barrier layer 184A and barrier layer 184B may include titanium, titanium alloy (e.g., TiN and / or TiC), tantalum, tantalum alloy (e.g., TaN and / or TaC), aluminum, aluminum alloy (e.g., AlON and / or Al2O3), other suitable barrier materials (e.g., materials that can prevent metal components from diffusing from the conductive core to substrate 106, insulating layer 120-1, insulating layer 120-2, bonding layer 160, bonding layer 162, insulating layer 172, or a combination thereof), or a combination thereof. Dielectric liner 186A and dielectric liner 186B include dielectric materials such as silicon oxide, silicon nitride, silicon carbonitride, other suitable dielectric materials, or a combination thereof. In some embodiments, barrier layer 184A and / or barrier layer 184B have a multilayer structure. In some embodiments, dielectric liner 186A and / or dielectric liner 186B have a multilayer structure.

[0044] refer to Figure 1 , Figure 3C and Figure 3D , TSV 170-1 has a diameter D1 (and / or width) (e.g., along the x-direction and / or y-direction) and a height H1 (e.g., along the z-direction), and TSV 170-2 has a diameter D2 (and / or width) (e.g., along the x-direction and / or y-direction) and a height H2 (e.g., along the z-direction). Diameter D2 is greater than diameter D1, and height H2 is greater than height H1. Thus, power delivery TSVs with different depths have different critical dimensions (CDs) (e.g., the diameter increases with increasing height), and the diameter of the power delivery TSV to the top die (e.g., TSV 170-2 to chip 104) is greater than the diameter of the power delivery TSV to the bottom die (e.g., TSV 170-1 to chip 102). In some embodiments, each of diameter D1 and diameter D2 is less than about 15 μm. For example, diameter D1 may be about 0.5 μm to about 10 μm, and diameter D2 may be about 2 μm to about 15 μm. The power transmission TSVs of the stacked chip structure 100A have approximately the same aspect ratio. For example, the aspect ratio R1 of the height H1 to the diameter D1 and the aspect ratio R2 of the height H2 to the diameter D2 are approximately the same (i.e., AR1 (=H1 / D1)=AR2 (=H2 / D2)). In some embodiments, each of the aspect ratio R1 and the aspect ratio R2 is about 5 to about 20. In some embodiments, the aspect ratio R1 and the aspect ratio R2 are about 10. For example, the diameter D1 may be about 2 μm, the height H1 may be about 20 μm, the diameter D2 may be about 3 μm, and the height H2 may be about 30 μm. In another example, the diameter D1 may be about 4.5 μm, the height H1 may be about 45 μm, the diameter D2 may be about 8 μm, and the height H2 may be about 80 μm. In some embodiments, the aspect ratio R1 and the aspect ratio R2 are adjusted / adjusted to provide substantially the same contact resistance (Rc) to the chip 102 and the chip 104. In some embodiments, diameter D1 and diameter D2 are adjusted / tuned to provide substantially the same contact resistance to chip 102 and chip 104. In some embodiments, height H1 and height H2 are adjusted / tuned to provide substantially the same contact resistance to chip 102 and chip 104.

[0045] In some embodiments, TSV 170-1 and / or TSV 170-2 have a circular shape in a top view ( FIG. 4A to FIG. 4C), and TSV 170-1 and / or TSV 170-2 may be cylindrical structures. TSV 170-1 and / or TSV 170-2 may have different shapes in top view, such as square, diamond, trapezoid, hexagon, octagon or other suitable shapes. In some embodiments, diameter D1 varies along height H1, and / or diameter D2 varies along height H2. For example, TSV 170-1 and TSV 170-2 may have a tapered sidewall profile (i.e., tapered sidewalls), as shown, such that diameter D1 increases from top to bottom along height H1, and diameter D2 increases from top to bottom along height H2. In some embodiments, diameter D1 decreases from top to bottom along height H1, and / or diameter D2 decreases from top to bottom along height H2. The present disclosure contemplates TSVs 170-1 and / or TSVs 170-2 having various sidewall profile configurations, such that TSV 170-1 may have various variations in diameter D1 along its height H1, and TSV 170-2 may have various variations in diameter D2 along its height H2. For example, TSV 170-1 and TSV 170-2 may have vertical sidewall profiles (i.e., substantially straight sidewalls), such that diameter D1 may be substantially the same from top to bottom along height H1, and diameter D2 may be substantially the same from top to bottom along height H2. In another example, TSV 170-1 and TSV 170-2 may have different sidewall profiles (e.g., one tapered, one vertical).

[0046] In the stacked chip structure 100A, each power transmission TSV has a corresponding guard ring. For example, the guard ring 190-1 is spaced apart from and located around the TSV 170-1, and the guard ring 190-2 is spaced apart from and located around the TSV 170-2. The insulating layer 120-1 may fill the space between the guard ring 190-1 and the TSV 170-1, and the insulating layer 120-1 may fill the space between the guard ring 190-2 and the TSV 170-2. FIG. 4A to FIG. 4C , from a top view (or bottom view), the guard ring 190-1 may be a circular ring ( Figure 4A ), Square Ring( Figure 4B ), octagonal ring( Figure 4C), hexagonal rings, or other suitably shaped rings. Guard ring 190-2 may also be a circular ring, a square ring, an octagonal ring, a hexagonal ring, or other suitably shaped ring located around TSV 170-2. In the depicted embodiment, guard ring 190-1 and guard ring 190-2 extend continuously around TSV 170-1 and TSV 170-2, respectively. In some embodiments, guard rings 190-1 and 190-2 are discontinuous around TSV 170-1 and TSV 170-2, respectively. For example, guard ring 190-1 and / or guard ring 190-2 may be formed by discrete segments that combine to form a ring around their respective TSVs.

[0047] refer to Figure 1 and Figure 3E , each of the guard ring 190-1 and the guard ring 190-2 can be formed by a portion of the FMLI-1 structure. In some embodiments, each of the guard ring 190-1 and the guard ring 190-2 has an interconnect structure stack disposed in the insulating layer 120-1 and extending through the insulating layer 120-1. The interconnect structure stack of the guard ring 190-1 may include a guard ring zero layer (g0 level), a guard ring one layer (g1 level) and a guard ring two layer (g2 level), and the interconnect structure stack of the guard ring 190-2 may include a g0 level, a g1 level, etc. to a guard ring g(B-1) layer (g(B-1) level) and a guard ring B layer (gB level), where B is an integer (e.g., from 2 to 10). Each guard ring level can be formed by one or more interconnect structures, and each interconnect structure may include a corresponding metal line 122 and a corresponding metal via 124. For example, the g2 level of guard rings 190 - 1 and 190 - 2 may include corresponding metal lines 122 of the M2 level disposed on corresponding metal vias 124 of the V2 level.

[0048] refer to Figure 3E , according to some embodiments, an enlarged view of region III of the stacked chip structure 100A is provided, and a portion of the guard ring 190-1 is provided. In such an embodiment, the guard ring 190-1 can be connected to the corresponding source / drain 112 in the substrate 106. For example, the interconnect structure stack of the guard ring 190-1 may include a device-level interconnect structure (g0 level) disposed on the corresponding source / drain 112 and an interconnect structure (g1 level) disposed on the device-level interconnect structure. The g0-level interconnect structure may include a corresponding source / drain contact 142 located in the dielectric layer 116, a corresponding drain / source via 144 located in the dielectric layer 130, and a corresponding metal line 122 located in the dielectric layer 134. The g1-level interconnect structure may include a corresponding metal via 124 located in the dielectric layer 136 and a corresponding metal line 122 located in the dielectric layer 138.

[0049] The interconnect structure stack may have more or fewer interconnect structures, and the number of interconnect structures of the interconnect structure stack may be more than, less than, or equal to the number of levels of the FMLI-1 structure. In the depicted embodiment, the guard ring 190-1 and the guard ring 190-2 have different heights, and the guard ring 190-1 and the guard ring 190-2 have uniform heights. For example, the guard ring 190-1 extends from the substrate 106 to the M2 level on both sides of the TSV 170-1, and the guard ring 190-2 extends from the substrate 106 to the MX level on both sides of the TSV 170-2. In this example, the TSV 170-1 may extend vertically beyond the top of the guard ring 190-1 (e.g., to the M3 level), and the TSV 170-2 may extend vertically beyond the top of the guard ring 190-2 (e.g., to the chip 104). In some embodiments, guard ring 190-1 is not connected to TSV 170-1, and guard ring 190-2 is not connected to TSV 170-2. For example, metal line 122 of the M3 level extends laterally over the top of guard ring 190-1, guard ring 190-1 does not include metal vias 124 in the V3 level, and guard ring 190-1 (e.g., its topmost metal line 122 (in the M2 level)) is not connected to the metal line 122 of the M3 level extending above it.

[0050] In some embodiments, a power transmission TSV extending through and / or into more than one chip may have a corresponding guard ring in each chip. For example, in chip 104, guard ring 190-3 may be spaced apart from TSV 170-2 and located around TSV 170-2. Insulating layer 120-2 may fill the gap between guard ring 190-3 and TSV 170-2. Guard ring 190-3 may also be a circular ring, a square ring, an octagonal ring, a hexagonal ring, or a ring of other suitable shapes located around TSV 170-2. In the depicted embodiment, guard ring 190-3 extends continuously around TSV 170-2. In some embodiments, guard ring 190-3 is discontinuous around TSV 170-2. In some embodiments, guard ring 190-3 has an interconnect structure stack that is disposed in insulating layer 120-2 and extends through insulating layer 120-2. In the depicted embodiment, where TSV 170-2 lands on the M4 level, the interconnect structure stack of guard ring 190-3 may include a g5 level, ... a guard ring g(C-1) layer (g(C-1) level), and a guard ring C layer (gC level), where C is an integer (e.g., 5 to 10). Each guard ring level may be formed by one or more interconnect structures, each of which may include a corresponding metal line 126 and a corresponding metal via 128. Similar to guard rings 190-1 and 190-2, guard ring 190-3 has a uniform height.

[0051] In some embodiments, guard ring 190-1 and / or guard ring 190-2 are electrically connected to a voltage. In some embodiments, guard ring 190-1 and / or guard ring 190-2 are electrically connected to electrical ground. In some embodiments, guard ring 190-1 and guard ring 190-2 are configured to electrically insulate TSV 170-1 and TSV 170-2 from device regions of chip 102, respectively. For example, TSV 170-1 may be disposed between a device region (e.g., having a transistor) of device layer DL-1 and a portion of the FMLI-1 structure above and connected to the device region, and guard ring 190-1 may be disposed between TSV 170-1 and these device regions, and guard ring 190-1 may electrically insulate TSV 170-1 from these device regions. TSV 170-2 may also be disposed between a device region of device layer DL-1 and a portion of the FMLI-1 structure above and connected to the device region, and a guard ring 190-2 may be disposed between TSV 170-2 and these device regions, and guard ring 190-2 may electrically insulate TSV 170-2 from these device regions. In some embodiments, guard ring 190-3 is configured to electrically insulate TSV 170-2 from the device region of chip 104. In some embodiments, guard ring 190-1, guard ring 190-2, guard ring 190-3, or a combination thereof absorbs and / or reduces thermal and / or mechanical stress from, within, and / or around the TSV. In some embodiments, guard ring 190-1, guard ring 190-2, guard ring 190-3, or a combination thereof provide structural support, integrity, reinforcement, or a combination thereof for the TSV.

[0052] The stacked chip structure 100A may also include an encapsulant 198 (also referred to as molding and / or molding compound). The chip 104 and its corresponding bonding structure (e.g., the bonding layer 162 with the bonding pad 166 therein) may be disposed in the encapsulant 198 and / or covered by the encapsulant 198. For example, the encapsulant 198 may circumferentially surround the chip 104. In some embodiments, the encapsulant 198 is disposed on the edge / sidewall of the chip 104. In some embodiments, the encapsulant 198 is disposed on the chip 102 and / or its corresponding bonding structure (e.g., the bonding layer 160 with the bonding pad 164 therein). The encapsulant 198 may include an organic material, such as an epoxy-based material.

[0053] In the stacked chip structure 100A, each power transmission TSV to a corresponding chip has a corresponding independent guard ring. In some embodiments, the power transmission TSVs can share a guard ring. For example, referring to Figure 2A and Figure 5A, the stacked chip structure 100B is configured with a TSV cluster having a shared guard ring. For example, TSV 170-1 and TSV 170-2 share a guard ring 190-4, and TSV 170-1 extends to the corresponding metal line 122 at the M4 level (providing the TSV landing pad of chip 102), rather than the M3 level. Guard ring 190-4 can be spaced apart from TSV 170-1 and TSV 170-2 and located around TSV 170-1 and TSV 170-2. Insulating layer 120-1 can fill the space between guard ring 190-4 and TSV 170-1, the space between guard ring 190-4 and TSV 170-2, and the space between TSV 170-1 and TSV 170-2. In the stacked chip structure 100A ( Figure 1 ), a portion of the guard ring 190-1 and a portion of the guard ring 190-2 (e.g., two guard ring sides) are disposed in a portion / region of the insulating layer 120-1 extending from the TSV 170-1 to the TSV 170-2, and an active region (e.g., a region of the device layer DL1 having transistors) may be located between the TSV 170-1 and the TSV 170-2. In contrast, in the stacked chip structure 100B, the guard ring 190-4 forms the periphery of the TSV region of the chip 102, and the portion / region of the insulating layer 120-1 extending from the TSV 170-1 to the TSV 170-2 does not have any portion of the guard ring. In other words, no guard ring is formed in the TSV 170-1 and the TSV 170-2 in the stacked chip structure 100B. The guard ring 190-4 may be a circular ring, a square ring, an octagonal ring, a hexagonal ring, or a ring of other suitable shapes. In some embodiments, the guard rings 190-4 are respectively arranged at different CDs ( Figure 5A ) (such as diameter D1 and diameter D2) around TSV 170-1 and TSV 170-2. In some embodiments, guard ring 190-4 extends continuously around TSV 170-1 and TSV 170-2 having the same CD ( Figure 5B ) (such as diameter D2 (or diameter D1)) and extends continuously around TSV 170-1 and TSV 170-2. In some embodiments, guard ring 190-4 is discontinuous.

[0054] Guard ring 190-4 may be formed by a portion of the FMLI-1 structure. In some embodiments, guard ring 190-4 has an interconnect structure stack that is disposed in insulating layer 120-1 and extends through insulating layer 120-1. The interconnect structure stack of guard ring 190-4 may include a g0 level, a g1 level, ... a guard ring g(D-1) layer (g(D-1) level) and a guard ring D layer (gD level), where D is an integer (e.g., from 2 to 10). Each guard ring level may be formed by one or more interconnect structures, each of which may include a corresponding metal line 122 and a corresponding metal via 124. Guard ring 190-4 has a different height than guard ring 190-1 and guard ring 190-2. For example, one side of the guard ring 190-4 near the TSV 170-1 extends from the substrate 106 to the M3 level (i.e., extends into the insulating layer 120-1), while one side of the guard ring 190-4 near the TSV 170-2 extends from the substrate 106 to the MX level (i.e., extends through the insulating layer 120-1). In such an example, the TSV 170-1 may extend vertically beyond the top of one side of the guard ring 190-4 (e.g., at the M3 level), but not beyond the top of the other side of the guard ring 190-4 (e.g., at the MX level), and the TSV 170-2 may extend vertically beyond both sides of the guard ring 190-4 to the TSV landing pads of the chip 104 (e.g., the corresponding metal line 126 at the M4 level or higher). In some embodiments, the guard ring 190-4 is not connected to the TSV 170-1 or the TSV 170-2.

[0055] In some embodiments, the guard ring 190-4 is connected to the doped regions in the substrate 106 and / or the corresponding source / drain 112. In some embodiments, the guard ring 190-4 is electrically connected to a voltage. In some embodiments, the guard ring 190-4 is electrically connected to an electrical ground. In some embodiments, the guard ring 190-4 is configured to electrically insulate the TSV 170-1 and the TSV 170-2 from the device region of the chip 102. In some embodiments, the guard ring 190-4 absorbs and / or reduces thermal and / or mechanical stresses from, within, and / or around the TSV. In some embodiments, the guard ring 190-4 provides structural support, integrity, reinforcement, or a combination thereof to its TSV.

[0056] In some embodiments, the power delivery TSVs may share a guard ring configured around each power delivery TSV. Figure 2B, the stacked chip structure 100C has a guard ring 190-5 shared by TSV 170-1 and TSV 170-2. The guard ring 190-5 may be spaced apart from and located around TSV 170-1 and TSV 170-2. The insulating layer 120-1 may fill the spaces between the guard ring 190-5 and TSV 170-1, between the guard ring 190-5 and TSV 170-2, and between TSV 170-1 and TSV 170-2. Similar to the guard ring 190-4, the guard ring 190-5 forms the periphery of the TSV region including TSV 170-1 and TSV 170-2. Compared to the guard ring 190-4, the guard ring 190-5 also includes an inner portion GI disposed in a portion / region of the insulating layer 120-1 extending from the TSV 170-1 to the TSV 170-2. With this configuration, the guard ring 190-5 is also formed around each of the TSV 170-1 and the TSV 170-2, and a portion of the guard ring 190-5 is located between the TSV 170-1 and the TSV 170-2. Compared to the stacked chip structure 100A, one side of the guard ring (i.e., a shared side / wall formed by the inner portion GI) is located between the TSV 170-1 and the TSV 170-2, rather than both sides (i.e., a corresponding side / wall of the guard ring 190-1 around the TSV 170-1 and a corresponding side or wall of the guard ring 190-2 around the TSV 170-2). The protection ring 190-5 may be and / or form a circular ring, a square ring, an octagonal ring, a hexagonal ring, or other suitable ring shapes around the TSV 170-1 and TSV 170-2, around the TSV 170-1, around the TSV 170-2, or around a combination thereof. In some embodiments, the protection ring 190-5 extends continuously around the TSV 170-1 and TSV 170-2, around the TSV 170-1, around the TSV 170-2, or around a combination thereof. In some embodiments, the protection ring 190-5 is discontinuous around the TSV 170-1 and TSV 170-2, around the TSV 170-1, around the TSV 170-2, or around a combination thereof. For example, the protection ring 190-5 may be formed by discrete segments.

[0057] Guard ring 190-5 may be formed by a portion of the FMLI-1 structure. In some embodiments, guard ring 190-5 has an interconnect structure stack that is disposed in insulating layer 120-1 and extends through insulating layer 120-1. The interconnect structure stack of guard ring 190-5 may include a g0 level, a g1 level, ... a guard ring g(D-1) layer (g(D-1) level) and a guard ring D layer (gD level), where D is an integer (e.g., from 2 to 10). Each guard ring level may be formed by one or more interconnect structures, each of which may include a corresponding metal line 122 and a corresponding metal via 124. Similar to guard ring 190-4, guard ring 190-5 has different heights. For example, the outer side of the protection ring 190-5 near the TSV 170-1 extends from the substrate 106 to the M3 level (i.e., extends into the insulating layer 120-1), while the outer side of the protection ring 190-5 near the TSV 170-2 extends from the substrate 106 to the MX level (i.e., extends through the insulating layer 120-1). In addition, the inner side (i.e., the inner portion GI) of the protection ring 190-5 located between the TSV 170-1 and the TSV 170-2 extends from the substrate 106 to the M3 level. In some embodiments, one side of the protection ring 190-5 located between the TSV 170-1 and the TSV 170-2 is higher or shorter than the outer side of the protection ring 190-5 near the TSV 170-1. For example, the inner side of the protection ring 190-5 can extend from the substrate 106 to any one of the M4 level to the MX level. In another example, the inner side of the guard ring 190-5 may extend from the substrate 106 to the M2 level and below. In the stacked chip structure 100C, the TSV 170-1 may extend vertically beyond the top of one outer side of the guard ring 190-5 (e.g., at the M3 level), but not beyond the top of the other outer side of the guard ring 190-5 (e.g., at the MX level), and the TSV 170-2 may extend vertically beyond both outer sides of the guard ring 190-5 to the TSV landing pad of the chip 104 (e.g., the corresponding metal line 126 at the M4 level or higher). In addition, the TSV 170-1 may or may not extend vertically beyond the inner side of the guard ring 190-5, and the TSV 170-2 may extend vertically beyond the inner side of the guard ring 190-5. In some embodiments, the guard ring 190-5 is not connected to the TSV 170-1 or the TSV 170-2.

[0058] In some embodiments, the guard ring 190-5 is connected to the doped regions in the substrate 106 and / or the corresponding source / drain 112. In some embodiments, the guard ring 190-5 is electrically connected to a voltage. In some embodiments, the guard ring 190-5 is electrically connected to an electrical ground. In some embodiments, the guard ring 190-5 is configured to electrically insulate the TSV 170-1 and the TSV 170-2 from the device region of the chip 102. In some embodiments, the guard ring 190-5 absorbs and / or reduces thermal and / or mechanical stresses from, within, and / or around the TSV. In some embodiments, the guard ring 190-5 provides structural support, integrity, reinforcement, or a combination thereof to its TSV.

[0059] The spacing between TSVs of the TSV cluster may be smaller than the spacing between TSVs with separate guard rings. Figure 1 ) between TSV 170-1 and TSV 170-2, the spacing S2 is in the stacked chip structure 100B ( Figure 2A ) and stacked chip structure 100C ( Figure 2B ) between TSV 170-1 and TSV 170-2 in the stacked chip structure 100A, and the spacing S1 is greater than the spacing S2. The spacing S1 is greater than the spacing S2 to accommodate a portion of the guard ring 190-1 and a portion of the guard ring 190-2 (i.e., two guard ring sides / walls) formed between TSV 170-1 and TSV 170-2 in the stacked chip structure 100A. In some embodiments, the spacing S1 is greater than about 3 μm. For example, the spacing S1 can be about 3 μm to about 100 μm. In some embodiments, the spacing S2 is greater than about 0.5 μm. For example, the spacing S2 can be about 0.5 μm to about 100 μm. Therefore, configuring the stacked chip structure 100B and the stacked chip structure 100C with a TSV cluster can reduce the occupied area of ​​the disclosed power transmission structure, which can increase the available space for devices in the device layer DL1. For example, referring to Fig. 6A and Figure 6B, the area consumed by eight TSVs (e.g., four TSVs 170-1 and four TSVs 170-2) of the stacked chip structure 100A may be greater than the area consumed by eight TSVs of the stacked chip structure 100B, each TSV having a corresponding protection ring (e.g., protection ring 190-1 or protection ring 190-2), and these TSVs are arranged into four TSV clusters, each TSV cluster including a corresponding TSV 170-1, a corresponding TSV 170-2, and a corresponding protection ring 190-4. In the stacked chip structure 100B, there is a spacing S3 between the TSV clusters, and the spacing S3 may be greater than the spacing S2 to accommodate the portion of the protection ring 190-4 between the TSV clusters. In some embodiments, the spacing S3 is greater than about 3 μm. For example, the spacing S3 may be about 3 μm to about 100 μm.

[0060] In some embodiments, all eight TSVs of the stacked chip structure 100A and the stacked chip structure 100B are electrically connected to the corresponding device layers. In such an embodiment, four TSVs 170-1 may be electrically connected to the device layer DL1 of the chip 102, and four TSVs 170-2 may be electrically connected to the device layer DL2 of the chip 104. In some embodiments, some TSVs of the stacked chip structure 100A and the stacked chip structure 100B are pseudo TSVs that are not electrically connected to the corresponding device layers. For example, in the stacked chip structure 100A, two TSVs 170-1 may be active TSVs electrically connected to the device layer DL1, two TSVs 170-1 may be pseudo TSVs that are not electrically connected to the device layer DL1, two TSVs 170-2 may be active TSVs electrically connected to the device layer DL2, and two TSVs 170-2 may be pseudo TSVs that are not electrically connected to the device layer DL2. In another example, in the stacked chip structure 100B, two TSV clusters may be active TSV clusters electrically connected to the device layer DL1 and the device layer DL2, and two TSV clusters may be pseudo TSV clusters that are not electrically connected to the device layer DL1 or the device layer DL2. In some embodiments, the TSV clusters may include active TSVs and pseudo TSVs, such as TSV 170-1 and TSV 170-2, respectively (or vice versa). The pseudo TSVs of the stacked chip structure 100A and / or the stacked chip structure 100B may extend from the substrate 106 to the TSV landing pads that are not electrically connected to the device layer. The pseudo TSVs may enhance heat dissipation and / or structural strength.

[0061] The present disclosure contemplates various configurations and / or arrangements of TSV clusters that may share a guard ring. For example, 7A to 7E Various TSV clusters are shown that may share a corresponding guard ring 190 - 4 . Fig. 7A shows a 2x1 TSV cluster surrounded by a corresponding guard ring 190-4, Figure 7BA 1x2 TSV cluster is shown surrounded by a corresponding guard ring 190-4, Figure 7C A 2x2 TSV cluster is shown surrounded by a corresponding guard ring 190-4, Fig.7D A 3x3 TSV cluster is shown surrounded by a corresponding guard ring 190-4, and Fig. 7E A 2x3x2 TSV cluster is shown surrounded by a corresponding guard ring 190-4. FIG. 7F to FIG. 7J Various TSV clusters are shown that may share a corresponding guard ring 190 - 5 . Figure 7F A 2x1 TSV cluster is shown surrounded by a corresponding guard ring 190-5, Figure 7G A 1x2 TSV cluster is shown surrounded by a corresponding guard ring 190-5, Figure 7H A 2x2 TSV cluster is shown surrounded by a corresponding guard ring 190 - 5 , Fig.7I A 3x3 TSV cluster is shown surrounded by a corresponding guard ring 190-5, and Figure 7J A 2x3x2 TSV cluster is shown surrounded by a corresponding guard ring 190-5. In such an embodiment, FIG. 7F to FIG. 7J Each TSV 170 - 1 and each TSV 170 - 2 of the TSV cluster may be surrounded by a corresponding portion of its corresponding guard ring 190 - 5 , as shown. 7A to 7J One or more TSVs of a TSV cluster may be dummy TSVs.

[0062] The disclosed power delivery structure can be incorporated into a stacked chip structure having a chip stack with more than two chips, so that each chip of the chip stack has a dedicated, independent power delivery TSV. Figure 8, the stacked chip structure 100D has a chip stack including chip 102, chip 104 and chip 102'. Chip 102' may include substrate 106', device layer DL3 and FMLI-3 structure, which may be similar to substrate 106 and / or substrate 108, device layer DL1 and / or device layer DL2 and FMLI-1 structure and / or FMLI-2 structure, respectively. The FMLI-3 structure includes a corresponding V0 level, a corresponding M0 level, a corresponding V1 level, a corresponding M1 level, a corresponding V2 level, a corresponding M2 level, ... a via (Z-1) layer (V(Z-1) level), a metal (Z-1) layer (M(Z-1) level), a via Z layer (VZ level) and a metal Z layer (MZ level), where Z is an integer (e.g., from 2 to 10). Z may be the same as or different from X and / or Y. Each level of the FMLI-3 structure may include conductive features such as metal lines 122' or metal vias 124' disposed in portions of the insulating layer 120-1'. The metal lines 122', metal vias 124', and insulating layer 120-1' may be similar to the metal lines 122 and / or metal lines 126, metal vias 124 and / or metal vias 128, and insulating layer 120-1 and / or insulating layer 120-2 described herein, respectively.

[0063] Chip 102 is disposed between chip 104 and chip 102'. In the depicted embodiment, chip 102 and chip 104 are bonded face-to-face, and chip 102 and chip 102' are bonded back-to-face (e.g., a front side FS3 (e.g., formed by an FMLI-3 structure) of chip 102' is attached and / or bonded to a back side BS1 (e.g., formed by substrate 106) of chip 102. In some embodiments, a chip bonding structure is located between chip 102 and chip 102', and chip 102 and chip 102' are bonded and / or attached via the chip bonding structure. In some embodiments, the chip bonding structure may include one or more bonding layers, such as one or more dielectric layers that facilitate dielectric-to-dielectric bonding. In some embodiments, the chip bonding structure is similar to the chip bonding structure between chip 102 and chip 104.

[0064] The stacked chip structure 100D includes a power transmission structure, which includes a TSV 170-1 electrically connected to the device layer DL1 via the FMLI-1 structure and a TSV 170-2 electrically connected to the device layer DL2 via the FMLI-2 structure, as described above. The power transmission structure also includes a TSV 170-3 electrically connected to the device layer DL3 via the FMLI-3 structure. For example, TSV 170-3 is connected to a corresponding metal line 122' of the FMLI-3 structure (e.g., its M3 level), and the metal line 122' is connected to the device layer DL3 (e.g., its transistor). TSV 170-3 is also electrically connected to a voltage V3, which can be generated and / or provided by a power supply. Therefore, TSV 170-3 can transmit and / or supply power to the device and / or device component of the device layer DL3. Therefore, each chip of the stacked chip structure 100D has a corresponding power transmission TSV connected thereto, and power can be directly transmitted to each chip via its corresponding power transmission TSV.

[0065] In this configuration, TSV 170 - 1 is disposed in chip 102 ′ and chip 102 but not in chip 104 , TSV 170 - 2 is disposed in chip 102 ′, chip 102 , and chip 104 , and TSV 170 - 3 is disposed in chip 102 ′ but not in chip 102 or chip 104 . For example, TSV 170-3 is disposed in substrate 106', device layer DL3, and insulating layer 120-1', and extends through substrate 106', device layer DL3, into insulating layer 120-1', to the M3 level of FMLI-3 structure; TSV 170-1 is disposed in substrate 106', device layer DL3, insulating layer 120-1', substrate 106, device layer DL1, and insulating layer 120-1, and extends through substrate 106', device layer DL3, insulating layer 120-1', substrate 106, device layer DL1, into insulating layer 120-1, to the M3 level of FMLI-1 structure; and TSV 170-2 is disposed in substrate 106', device layer DL3, insulating layer 120-1', substrate 106, device layer DL1, insulating layer 120-1, chip bonding structure and insulating layer 120-2, and extends through substrate 106', device layer DL3, insulating layer 120-1', substrate 106, device layer DL1, insulating layer 120-1, chip bonding structure, into insulating layer 120-2 to the M4 level of the FMLI-2 structure. In some embodiments, TSV 170-1 can extend to different levels of the FMLI-1 structure, TSV 170-2 can extend to different levels of the FMLI-2 structure, TSV 170-3 can extend to different levels of the FMLI-3 structure, or a combination thereof. TSV 170-3 can be similar to TSV 170-1 and / or TSV 170-2 described herein. For example, TSV 170-3 can include a conductive core, a barrier layer, and a dielectric liner as described herein.

[0066] Similar to the stacked chip structures 100A-100C, although the power transmission TSVs have different depths and different CDs, the aspect ratios of the power transmission TSVs are substantially the same. For example, in the stacked chip structure 100D, the TSV 170-3 may have a diameter D3 (and / or width) (e.g., along the x-direction and / or y-direction) and a height H3 (e.g., along the z-direction), the diameter D3 is smaller than the diameter D2 and the diameter D1, the height H3 is smaller than the height H2 and the height H1, and the aspect ratio R3 of the height H3 to the diameter D3 is substantially the same as the aspect ratio R2 and the aspect ratio R1 (i.e., AR1 (=H1 / D1)=AR2 (=H2 / D2)=AR3 (=H3 / D3)). In some embodiments, the diameter D3 is less than about 15 μm. For example, the diameter D3 may be about 0.5 μm to about 10 μm. In some embodiments, the aspect ratio R3, the aspect ratio R2, and the aspect ratio R1 are about 5 to about 20, such as about 10. For example, the diameter D3 may be about 2 μm and the height H3 may be about 20 μm, the diameter D1 may be about 3 μm and the height H1 may be about 30 μm, the diameter D2 may be about 4.5 μm and the height H2 may be about 45 μm.

[0067] Each power transmission TSV has a corresponding guard ring in the chip 102'. For example, the guard ring 190-6 is spaced apart from and around the TSV 170-3, the guard ring 190-7 is spaced apart from and around the TSV 170-1, and the guard ring 190-8 is spaced apart from and around the TSV 170-2. The insulating layer 120-1' may fill the space between the guard ring 190-6 and the TSV 170-3, the space between the guard ring 190-7 and the TSV 170-1, and the space between the guard ring 190-8 and the TSV 170-2. The guard ring 190-6, the guard ring 190-7, and the guard ring 190-8 may be a circular ring, a square ring, an octagonal ring, a hexagonal ring, or other suitable ring shapes. In the depicted embodiment, guard rings 190-6, 190-7, and 190-8 extend continuously around TSV 170-3, TSV 170-1, and TSV 170-2, respectively. In some embodiments, guard rings 190-6, 190-7, 190-8, or a combination thereof are discontinuous. For example, guard rings 190-6, 190-7, 190-8, or a combination thereof may be formed of discrete segments that combine to form a ring.

[0068] Each of the guard rings 190-6, 190-7, and 190-8 may be formed by a portion of the FMLI-3 structure. In some embodiments, each of the guard rings 190-6, 190-7, and 190-8 has an interconnect structure stack disposed in the insulating layer 120-1' and extending through the insulating layer 120-1'. The interconnect structure stack of the guard ring 190-6 may include a g0 level, a g1 level, and a g2 level. The interconnect structure stack of the guard ring 190-7 may include a g0 level, a g1 level, ... a guard ring g(E-1) layer (g(E-1) level) and a guard ring E layer (gE level), where E is an integer (e.g., from 2 to 10). The interconnect structure stack of guard ring 190-8 may include a g0 level, a g1 level, ... a guard ring g(F-1) layer (g(F-1) level) and a guard ring F layer (gF level), where F is an integer (e.g., from 2 to 10). E may be different from or the same as F. Each guard ring level may be formed by one or more interconnect structures, each of which may include a corresponding metal line 122' and a corresponding metal via 124'. In the depicted embodiment, the height of guard ring 190-6 is different from the height of guard ring 190-7 and the height of guard ring 190-8, guard ring 190-7 and guard ring 190-8 have the same height, and guard ring 190-6, guard ring 190-7, and guard ring 190-8 have uniform heights. For example, guard ring 190-6 extends from substrate 106 to the M2 level on both sides of TSV 170-3, guard ring 190-7 extends from substrate 106 to the MZ level (e.g., E=Z) on both sides of TSV 170-1, and guard ring 190-8 extends from substrate 106 to the MZ level (e.g., F=Z) on both sides of TSV 170-2. In such an example, TSV 170-3 may extend vertically beyond the top of guard ring 190-6 (e.g., to the M3 level), TSV 170-1 may extend vertically beyond the top of guard ring 190-7 (e.g., to chip 102), and TSV 170-2 may extend vertically beyond the top of guard ring 190-8 (e.g., to chip 104). In some embodiments, guard ring 190 - 6 is not connected to TSV 170 - 3 , guard ring 190 - 7 is not connected to TSV 170 - 1 , and guard ring 190 - 8 is not connected to TSV 170 - 2 . The present disclosure contemplates different guard ring heights.

[0069] In some embodiments, the guard ring 190-6, the guard ring 190-7, the guard ring 190-8, or a combination thereof is electrically connected to a voltage. In some embodiments, the guard ring 190-6, the guard ring 190-7, the guard ring 190-8, or a combination thereof is electrically connected to electrical ground. In some embodiments, the guard ring 190-6, the guard ring 190-7, and the guard ring 190-8 are configured to electrically insulate the TSV 170-3, the TSV 170-1, and the TSV 170-2 from the device region of the chip 102', respectively. In some embodiments, the guard ring 190-6, the guard ring 190-7, the guard ring 190-8, or a combination thereof absorbs and / or reduces thermal stress and / or mechanical stress from the TSV, within the TSV, and / or around the TSV. In some embodiments, the guard ring 190-6, the guard ring 190-7, the guard ring 190-8, or a combination thereof provides structural support, integrity, reinforcement, or a combination thereof for the TSV.

[0070] In various embodiments, each of the insulating layer 120-1 and the insulating layer 120-2 includes a dielectric material such as silicon oxide, tetraethyl orthosilicate (TEOS) oxide, phosphosilicate glass (PSG), boron-doped silicate glass (BSG), boron-doped PSG (BPSG), a low-k dielectric material (e.g., having a dielectric constant less than that of silicon oxide (e.g., k<3.9)), other suitable dielectric materials, or combinations thereof. Exemplary low-k dielectric materials include fluorosilicate glass (FSG), carbon-doped oxides, xerogels, aerogels, amorphous fluorinated carbon, polyparaxylene, BCB, polyimide, other low-k dielectric materials, or combinations thereof. In some embodiments, the insulating layer 120-1 and / or the insulating layer 120-2 include a low-k dielectric material (e.g., carbon-doped oxide) or an extremely low-k dielectric material (e.g., k≤2.5) (e.g., porous carbon-doped oxide). Dielectric layer 116, dielectric layer 130, and dielectric layers 134-138 may form part of insulating layer 120-1, and dielectric layer 124, dielectric layer 140, and dielectric layers 146-158 may form part of insulating layer 120-2, which may include any suitable dielectric material as described herein and / or have a multi-layer structure (e.g., ILD and CESL).

[0071] In some embodiments, the insulating layer 120-1 and / or the insulating layer 120-2 has a multilayer structure. For example, each of the insulating layer 120-1 and / or the insulating layer 120-2 may include at least one ILD layer, at least one CESL disposed between the corresponding ILD layers, and at least one CESL disposed between the corresponding ILD layer and the device substrate (e.g., substrate 106 and / or substrate 108). The material of the CESL may be different from the material of the ILD layer. For example, where the ILD layer includes a low-k dielectric material, the low-k dielectric material includes silicon and oxygen, and the CESL may include silicon and nitrogen (e.g., silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof) or other suitable dielectric materials (e.g., metal nitride). The ILD layer may have a multilayer structure, and the multilayer structure has a variety of dielectric materials. The CESL may have a multilayer structure, and the multilayer structure has a variety of dielectric materials.

[0072] In some embodiments, each level of the FMLI-1 structure (e.g., the second level including the M2 level and the V2 level) includes a corresponding ILD layer and / or a corresponding CESL of the insulating layer 120-1, and the corresponding metal line 122 and the metal via 124 are located in the corresponding ILD layer and / or in the corresponding CESL. In some embodiments, each level of the FMLI-2 structure includes a corresponding ILD layer and / or a corresponding CESL of the insulating layer 120-2, and the corresponding metal line 126 and the metal via 128 are located in the corresponding ILD layer and / or in the corresponding CESL. In some embodiments, each of the M0 level to the MX level of the FMLI-1 structure may include a corresponding ILD layer and / or a corresponding CESL, wherein the corresponding metal line 122 is located in the corresponding ILD layer and / or in the corresponding CESL. In some embodiments, each of the M0 level to the MY level of the FMLI-2 structure may include a corresponding ILD layer and / or a corresponding CESL, wherein the corresponding metal line 126 is located in the corresponding ILD layer and / or in the corresponding CESL. In some embodiments, each of the V0 to VX levels of the FMLI-1 structure may include a corresponding ILD layer and / or a corresponding CESL, wherein the corresponding metal via 124 is located in the corresponding ILD layer and / or the corresponding CESL. In some embodiments, each of the V0 to VY levels of the FMLI-2 structure may include a corresponding ILD layer and / or a corresponding CESL, wherein the corresponding metal via 128 is located in the corresponding ILD layer and / or the corresponding CESL.

[0073] In addition, in various embodiments described herein, metal lines 122, metal vias 124, metal lines 126, metal vias 128, source / drain contacts (e.g., source / drain contacts 142), source / drain vias (e.g., source / drain vias 144), and gate contacts (e.g., gate contacts 132) include conductive materials, including, for example, aluminum, copper, titanium, tantalum, tungsten, ruthenium, cobalt, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, silicides thereof, or combinations thereof. In some embodiments, metal lines 122, metal vias 124, metal lines 126, metal vias 128, source / drain contacts, source / drain vias, gate contacts, or combinations thereof include a bulk metal layer (also referred to as a metal fill layer, a conductive plug, a metal plug, etc.). In some embodiments, metal line 122, metal via 124, metal line 126, metal via 128, source / drain contact, source / drain via, gate contact, or a combination thereof include a barrier layer, an adhesion layer, other suitable layers, or a combination thereof disposed between a bulk metal layer and a corresponding insulating layer. The barrier layer may include titanium, a titanium alloy (e.g., TiN), tantalum, a tantalum alloy (e.g., TaN), other suitable barrier materials (e.g., materials that can prevent metal components from diffusing from a bulk metal layer into a surrounding dielectric), or a combination thereof. In some embodiments, metal line 122, metal via 124, metal line 126, metal via 128, source / drain contact, source / drain via, gate contact, or a combination thereof include different metal materials. For example, a lower metal line 122 and / or metal via 124 closer to device layer DL1 may include tungsten, ruthenium, cobalt, or a combination thereof, while a higher metal line 122 and / or metal via 124 farther from device layer DL1 may include copper. In another example, the lower metal line 126 and / or metal via 128 closer to the device layer DL2 may include tungsten, ruthenium, cobalt, or a combination thereof, while the higher metal line 126 or metal via 128 farther from the device layer DL2 may include copper. In some embodiments, the metal line 122, metal via 124, metal line 126, metal via 128, source / drain contacts, source / drain vias, gate contacts, or a combination thereof include the same metal material.

[0074] refer to Figures 9 to 17 , Figures 9 to 17 The stacked chip structure 200 according to various aspects of the present disclosure is used to form a power transmission structure (such as Figure 1 The power transmission structure of the stacked chip structure 100A is a partial or full cross-sectional view at various manufacturing stages. For clarity, it has been simplified. Figures 9 to 17To better understand the inventive concepts of the present disclosure. Additional components may be added to the stacked chip structure 200, and some components described below may be replaced, modified, or eliminated in other embodiments of the stacked chip structure 200.

[0075] refer to Fig. 9 After the stacked chip structure 200 is subjected to FEOL processing (e.g., to form the device layer DL1 and the device layer DL2 of the chip 102 and the chip 104, respectively), the stacked chip structure 200 may be subjected to MEOL processing and BEOL processing to form a FMLI-1 structure (e.g., M0 level to MX level and V0 level to VX level) above the device layer DL1. The FMLI-1 structure may be connected to the devices of the device layer DL1, such as transistors (e.g., transistor T1 and / or transistor T2). While the FMLI-1 structure is being formed, an interconnect structure stack of a guard ring 190-1 (e.g., g0 level to g2 level) and a guard ring 190-2 (e.g., g0 level to gB level) may be formed above the device layer DL1. The interconnect structure stack of the guard ring 190-1 and the guard ring 190-2 may be connected to the device layer DL1, such as to a doped region formed in the substrate 106. The guard ring 190-1 may be a metal ring ( FIG. 4A to FIG. 4C ), and the guard ring 190-2 can be a metal ring having an inner dimension of the dielectric region 210-2 defining the insulating layer 120-1. As described herein, TSV170-1 and TSV 170-2 will be formed in and extend through the dielectric region 210-1 and the dielectric region 210-2, respectively. Portions of the FMLI-1 structure (e.g., the corresponding metal line 122 at the M3 level) overlap with the guard ring 190-1 and will provide a TSV landing pad for the chip 102. In some embodiments, the guard ring 190-1 and the guard ring 190-2 have uniform heights. For example, both sides of the guard ring 190-1 can extend from the device layer DL1 to the M2 level, and both sides of the guard ring 190-2 can extend from the device layer DL2 to the MX level.

[0076] In some embodiments, forming a given level of the FMLI-1 structure (e.g., metal vias 124 at the V2 level and metal lines 122 at the M2 level) and forming the interconnect structures of the guard rings 190-1 and 190-2 at a given level (e.g., metal vias 124 and metal lines 122 at the g2 level) includes depositing a portion of the insulating layer 120-1, such as an ILD layer of the insulating layer 120-1 over the front side of the substrate 106. In some embodiments, depositing the portion of the insulating layer 120-1 includes depositing the CESL before depositing the ILD layer, such that the ILD layer is deposited over the CESL. The portion of the insulating layer 120-1 (e.g., the ILD layer and / or the CESL) is formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable deposition methods, or combinations thereof. A planarization process may be performed after depositing the portion of the insulating layer 120-1.

[0077] In some embodiments, the interconnect structures of metal lines 122 and metal vias 124 at a given level of the FMLI-1 structure and guard rings 190-1 and guard rings 190-2 at a given level are formed by a dual damascene process, which may involve depositing conductive materials for via / metal line pairs simultaneously. In such embodiments, metal vias 124 and metal lines 122 may share barrier layers and conductive plugs, rather than each having corresponding different barrier layers and conductive plugs (e.g., where the barrier layer of the corresponding metal line 122 separates the conductive plug of the corresponding metal line 122 from the conductive plug of its corresponding metal via 124). In some embodiments, the dual damascene process includes performing a patterning process to form an interconnect opening that extends through a portion of the insulating layer 120-1 to expose the underlying conductive features. The patterning process may include a first photolithography step and a first etching step to form a trench opening of an interconnect opening (corresponding to metal line 122) in insulating layer 120-1, and a second photolithography step and a second etching step to form a through hole opening of an interconnect opening (corresponding to metal through hole 124) in insulating layer 120-1. The first photolithography / etching step and the second photolithography / etching step may be performed in any order (e.g., trench first and through hole later or through hole first and trench later). The first etching step and the second etching step are configured to selectively remove insulating layer 120-1 relative to the patterned mask layer. The first etching step and the second etching step may be dry etching, wet etching, other suitable etching, or a combination thereof.

[0078] After performing the patterning process, the dual damascene process may include performing a first deposition process to form a barrier material partially filling the interconnect opening above the insulating layer 120-1, and performing a second deposition process to form a body conductive material above the barrier material, wherein the body conductive material fills the remaining portion of the interconnect opening. In such an embodiment, the barrier material and the body conductive material may be disposed in the interconnect opening and above the top surface of the insulating layer 120-1. The first deposition process and the second deposition process may be CVD, PVD, ALD, other suitable deposition methods, or a combination thereof. A CMP process and / or other planarization process may be performed to remove excess body conductive material and barrier material from above the top surface of the portion of the insulating layer 120-1, resulting in a patterned via layer (e.g., metal via 124) and a patterned metal layer (e.g., metal line 122) of a given level of the FMLI-1 structure, and a corresponding interconnect structure of the guard ring 190-1 and the guard ring 190-2. The CMP process planarizes the top surfaces of the insulating layer 120-1 and the metal line 122. The barrier material and the bulk conductive material may continuously fill the trench openings and the via openings of the interconnect openings, such that the metal lines 122 and the metal vias 124 share the barrier layer and the conductive plugs.

[0079] In some embodiments, for a given level of the FMLI-1 structure, the metal lines 122 and metal vias 124 of the interconnect structures of the guard rings 190-1 and 190-2 at the given level are respectively formed simultaneously with the metal lines 122 and metal vias 124 of the given level of the FMLI-1 structure. In some embodiments, for a given level of the FMLI-1 structure, the metal lines 122 and metal vias 124 of the interconnect structures of the guard rings 190-1 and 190-2 at the given level are respectively formed at least partially simultaneously with the metal lines 122 and metal vias 124 of the given level of the FMLI-1 structure. In some embodiments, for a given level of the FMLI-1 structure, the metal lines 122 and metal vias 124 of the interconnect structures of the guard rings 190-1 and 190-2 at the given level are respectively formed by a different process than the metal lines 122 and metal vias 124 of the given level of the FMLI-1 structure. In some embodiments, for a given level of the FMLI-1 structure, the metal lines 122 and metal vias 124 of the interconnect structures of the guard rings 190-1 and 190-2 at the given level, and the metal lines 122 and / or metal vias 124 at the given level of the FMLI-1 structure are formed by the same single damascene process, respectively. In some embodiments, for a given level of the FMLI-1 structure, the metal lines 122 and metal vias 124 of the interconnect structures of the guard rings 190-1 and 190-2 at the given level, and the metal lines 122 and / or metal vias 124 at the given level of the FMLI-1 structure are formed by different single damascene processes, respectively. In some embodiments, for a given level of the FMLI-1 structure, the metal lines 122 and metal vias 124 of the interconnect structures of the guard rings 190-1 and 190-2 at the given level, and the metal lines 122 and / or metal vias 124 at the given level of the FMLI-1 structure are formed by the same dual damascene process, respectively. In some embodiments, for a given level of the FMLI-1 structure, the metal lines 122 and metal vias 124 of the interconnect structures of the guard ring 190-1 and the guard ring 190-2 at the given level, and the metal lines 122 and / or metal vias 124 of the given level of the FMLI-1 structure are formed respectively by different dual damascene processes. In some embodiments, the guard ring 190-1 and the guard ring 190-2 are formed simultaneously. In some embodiments, the guard ring 190-1 and the guard ring 190-2 are formed separately.

[0080] The MEOL processing and BEOL processing of the stacked chip structure 200 may also include forming an FMLI-2 structure (e.g., M0 level to MY level and V0 level to VY level) above the device layer DL2. The FMLI-2 structure may be connected to a device of the device layer DL2, such as a transistor (e.g., transistor T3 and / or transistor T4). An interconnect structure stack (e.g., gC level and below) of a guard ring 190-3 may be formed above the device layer DL2 while the FMLI-2 structure is formed. The guard ring 190-3 may be a metal ring having an inner dimension of a dielectric region 210-3 defining the insulating layer 120-2. As further described herein, the TSV 170-2 will also be formed in the dielectric region 210-3 and extend through the dielectric region 210-3, and the guard ring 190-3 overlaps a portion of the FMLI-2 structure (e.g., a corresponding metal line 126 at the M4 level or higher), which will provide a TSV landing pad for the chip 104. In some embodiments, as shown, guard ring 190-3 may have a uniform height. A given level of the FMLI-2 structure (e.g., metal vias 128 at the VY level and metal lines 126 at the MY level) and the interconnection structure of guard ring 190-3 at a given level (e.g., metal vias 128 and metal lines 126 at the gC level) may be formed as described above with reference to forming a given level of the FMLI-1 structure and the interconnection structure of guard ring 190-1 and guard ring 190-2 at a given level. For example, insulating layer 120-2, metal line 126, and metal via 128 may be formed in a manner similar to insulating layer 120-1, metal line 122, and metal via 124 as described above, respectively.

[0081] refer to Fig.10, bonding chip 104 to chip 102 face-to-face to form a chip stack. In some embodiments, the FMLI-2 structure is hybrid bonded to the FMLI-1 structure. For example, the hybrid bonding may include forming a bonding layer 160 (e.g., formed by the MX layer of the FMLI-1 structure) having a bonding pad 164 disposed therein over the front side FS1 of the chip 102; forming a bonding layer 162 (e.g., formed by the MY layer of the FMLI-2 structure) having a bonding pad 166 disposed therein over the front side FS2 of the chip 104; flipping the chip 104 so that its front side FS2 faces the front side FS1 of the chip 102; aligning the chip 104 with the chip 102 (e.g., aligning the bonding pad 166 with the bonding pad 164); and pressing the chip 104 and the chip 102 together to achieve bonding of the bonding pad 166 with the bonding pad 164 (e.g., metal-to-metal bonding) and / or bonding of the bonding layer 162 with the bonding layer 160 (e.g., non-metal-to-non-metal bonding). In some embodiments, bonding includes performing an annealing process (e.g., heating) and / or other suitable processes to achieve bonding of bonding pad 166 and bonding pad 164 and / or bonding of bonding layer 162 and bonding layer 160. In some embodiments, bonding includes aligning a TSV landing pad of chip 104 (e.g., provided by a corresponding metal line 126 at the M4 level in the illustrated embodiment) with a guard ring 190-2 of chip 102. For example, the TSV landing pad of chip 104 can be centrally aligned with guard ring 190-2 and / or dielectric region 210-3. In some embodiments, bonding includes aligning guard ring 190-3 with guard ring 190-2. For example, guard ring 190-3 can be centrally aligned with guard ring 190-2.

[0082] After bonding, encapsulant 198 and / or molding compound may be formed around chip 104 and over chip 102. Encapsulant 198 may encapsulate chip 104. Encapsulant 198 may cover exposed portions of bonding layer 160 (i.e., portions not covered by chip 104) and sidewalls of chip 104. Encapsulant 198 may fill a space between the sidewalls of chip 104 and the sidewalls of chip 102. In some embodiments, forming encapsulant 198 includes depositing an encapsulant material, such as a polymer material and / or a dielectric material, and performing a planarization process, which may remove the encapsulant material covering backside BS2 of chip 104.

[0083] refer to Fig.11In some embodiments, the carrier substrate 215 is attached to the front side of the stacked chip structure 200, which allows the stacked chip structure 100 to be flipped and can be used for backside processing. The carrier substrate 215 can be attached by direct bonding, hybrid bonding, adhesives, other bonding and / or attachment techniques / processes, or a combination thereof. In some embodiments, the carrier substrate 215 is attached to the back side BS2 and the sealant 198 of the chip 104. The bonding process may include alignment, annealing, other processes, or a combination thereof. In some embodiments, the carrier substrate 215 includes silicon, soda-lime glass, fused silica, fused quartz, calcium fluoride, other suitable carrier substrate materials, or a combination thereof. In some embodiments, the carrier substrate 215 is configured to provide sufficient rigidity and / or mechanical support. In some embodiments, the carrier substrate 215 is attached to the substrate 108 and / or the sealant 198 by a bonding layer. The bonding layer may be an oxide layer and / or another suitable material layer that facilitates the bonding of the carrier substrate 215 with the substrate 108 and / or the sealant 198. In some embodiments, carrier substrate 215 is attached to substrate 108 and / or encapsulant 198 by a suitable adhesive.

[0084] refer to Fig.12 , flip the stacked chip structure 200, and apply a thinning process to the back side BS1 of the substrate 106 of the chip 102. The thinning process reduces the thickness of the substrate 106 (e.g., along the z direction). The thinning process is a grinding process, a planarization process (e.g., CMP), an etching process, other suitable processes, or a combination thereof. In some embodiments, the thinning process is a multi-step process, such as a mechanical grinding process to remove a sufficient amount of the substrate 106, followed by a chemical thinning process (e.g., using an etching chemical) to further thin the substrate 106.

[0085] refer to Fig.13 and Fig.14 , processing of the stacked chip structure 200 may continue by forming TSVs for each chip of the chip stack, such as forming TSVs 170-1 and TSVs 170-2 for chip 102 and chip 104, respectively. TSVs 170-1 and TSVs 170-2 may be formed simultaneously by any suitable process. Fig.13, forming the TSV may include forming a TSV trench 220-1 and a TSA trench 220-2, wherein the TSV trench 220-1 exposes a TSV landing pad of the chip 102 (e.g., provided by a corresponding metal line 122 of the M3 level), and the TSA trench 220-2 exposes a TSV landing pad of the chip 104 (e.g., provided by a corresponding metal line 126 of the M4 level). The TSV landing pad of the chip 102 is electrically connected to one or more devices and / or device components of the device layer DL1 via a conductive portion of the FMLI-1 structure (e.g., a routing path formed by a combination of metal lines 122 and metal vias 124), and the TSV landing pad of the chip 104 is electrically connected to one or more devices or device components of the device layer DL2 via a conductive portion of the FMLI-2 structure (e.g., a routing path formed by a combination of metal lines 126 and metal vias 128). The TSV trench 220-1 extends through the substrate 106, the device layer DL1, and into the insulating layer 120-1. The TSV trench 220-2 extends through the substrate 106, the device layer DL1, the insulating layer 120-1, the chip bonding structure (e.g., its bonding layer 160 and bonding layer 162), and into the insulating layer 120-2. The TSV trench 220-1 is formed in the dielectric region 210-1 of the insulating layer 120-1, so that the guard ring 190-1 is located around the TSV trench 220-1, and the TSV trench 220-2 is formed in the dielectric region 210-2 of the insulating layer 120-1 and the dielectric region 210-3 of the insulating layer 120-2, so that the guard rings 190-2 and 190-3 are located around the TSV trench 220V-2. In some embodiments, before forming the TSV trench, the insulating layer 172 is formed over the back side BS1 of the chip 102. In such an embodiment, TSV trench 220 - 1 and TSV trench 220 - 2 may also extend through dielectric layer 176 and dielectric layer 174 .

[0086] In some embodiments, forming the TSV trenches includes forming a patterned mask layer 225 having openings therein (e.g., opening 228-1 and opening 228-2) that overlap dielectric regions defined by guard rings of chip 102 and / or chip 104. For example, opening 228-1 overlaps dielectric region 210-1 of insulating layer 120-1, which is defined by guard ring 190-1 of chip 102, and opening 228-2 overlaps dielectric region 210-2 of insulating layer 120-1 and dielectric region 210-3, which is defined by guard ring 190-2 and which is defined by guard ring 190-3. The patterned mask layer 225 can be formed by a photolithography process, which can include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof. In some embodiments, the patterned mask layer 225 is a patterned hard mask layer. In some embodiments, the patterned mask layer 225 is a patterned photoresist layer.

[0087] In some embodiments, forming the TSV trench includes etching the chip 102 and the chip 104 using the patterned mask layer 225 as an etching mask. For example, portions of the insulating layer 172, the substrate 106, the device layer DL1, and the insulating layer 120-1 that overlap with the opening 228-1 and are exposed by the opening 228-1 are removed by an etching process to form the TSV trench 220-1, and portions of the insulating layer 172, the substrate 106, the device layer DL1, the insulating layer 120-1, the chip bonding structure, and the insulating layer 120-2 that overlap with the opening 228-2 and are exposed by the opening 228-2 are removed by an etching process to form the TSV trench 220-2. The etching process can selectively remove the insulating layer 120-1 and the insulating layer 120-2 relative to the metal line 122 and the metal line 126, respectively. For example, the etching process etches the insulating layer 120-1 without etching (or negligibly) the metal line 122, and the etching process etches the insulating layer 120-2 without etching (or negligibly) the metal line 126, so that the etching can stop when reaching the TSV landing pad. Therefore, although the TSV trench 220-1 and the TSV trench 220-2 have different depths and different CDs (e.g., different diameters / widths), the TSV trench 220-1 and the TSV trench 220-2 can be etched into the stacked chip structure 200 at the same time. In some embodiments, the etchant of the etching process can etch the dielectric material (e.g., the insulating layer 120-1 and the insulating layer 120-2) at a higher rate than the metal material (e.g., the metal line 122 and / or the metal line 126).

[0088] The TSV etching process may be dry etching, wet etching, other etching, or a combination thereof. In some embodiments, the TSV etching process is an isotropic dry etching. In some embodiments, a Bosch process is implemented to extend the TSV groove through the substrate 106, the device layer DL1, the insulating layer 120-1, the chip bonding structure, the insulating layer 120-2, or a combination thereof. The Bosch process generally refers to high aspect ratio plasma etching, which involves alternating etching phases and deposition phases, wherein one cycle includes an etching phase and a deposition phase, and the cycle is repeated until the TSV groove has a desired depth. In some embodiments, the TSV etching process is a multi-step process, and the multi-step process may use different etchants and / or different etching parameters to etch the insulating layer 172, the substrate 106, the device layer DL1, the insulating layer 120-1, the chip bonding structure, the insulating layer 120-2, or a combination thereof separately. The TSV etching process may partially or completely remove the patterned mask layer 225 from above the insulating layer 172. In some embodiments, the patterned mask layer 225 is removed by another etching process and / or a photoresist stripping process.

[0089] refer to Fig.14 , forming the TSV may further include filling the TSV trenches with a conductive material. In some embodiments, filling the TSV trenches 220-1 and the TSV trenches 220-2 includes depositing a dielectric material (e.g., SiN, SiCN, and / or oxide) over the back side of the stacked chip structure 200, the dielectric material partially filling the TSV trenches 220-1 and the TSV trenches 220-2, depositing a barrier material (e.g., Ti, TiN, and / or TaN) over the dielectric material partially filling the TSV trenches 220-1 and the TSV trenches TSV-2, depositing a bulk conductive material (e.g., Cu) over the barrier material filling the remaining portions of the TSV trenches 220-1 and the TSV trenches 220-2, and performing a planarization process (e.g., CMP) to remove excess dielectric material, barrier material, and bulk conductive material from over the insulating layer 172. The insulating layer 172 (e.g., the dielectric layer 176 thereof) may be used as a planarization stop layer, and the planarization process may be performed until the insulating layer 172 is reached. In some embodiments, the planarization process removes the patterned mask layer 225 .

[0090] The remaining dielectric material forms a dielectric liner (e.g., dielectric liner 186A and dielectric liner 186B), the remaining barrier material forms a barrier layer (e.g., barrier layer 184A and barrier layer 184B), and the remaining body conductive material forms a conductive core of the TSV (e.g., conductive core 182A and conductive core 182B). Therefore, the various layers of TSV 170-1 and TSV 170-2 can be deposited simultaneously. The dielectric material is formed by CVD (e.g., PECVD and / or LPCVD), thermal oxidation, chemical oxidation, other suitable deposition processes, or a combination thereof. The barrier material is formed by PVD, CVD, ALD, other suitable deposition processes, or a combination thereof. The body conductive material is formed by electrochemical plating (ECP), electroplating, chemical plating, PVD, CVD, other suitable deposition processes, or a combination thereof. In some embodiments, the dielectric material and the barrier material are conformally deposited above the stacked chip structure 200 so that the dielectric material and the barrier material have a substantially uniform thickness. In some embodiments, the bulk conductive material is blanket deposited.

[0091] refer to Fig.15 and Fig.16 , stacked chip structure 200 may be processed to form a bump structure over backside BS1 of chip 102. The bump structure may electrically connect chip 102 and / or chip 104 to a power source, as described herein. Fig.15 , forming the bump structure may include forming a patterned passivation layer 230 over the back side BS1 of the chip 102. The patterned passivation layer 230 may be formed over the insulating layer 172 so that the insulating layer 172 is located between the patterned passivation layer 230 and the back side BS1 of the chip 102. The patterned passivation layer 230 has openings therein that expose the TSVs, such as an opening 232-1 that exposes the TSV 170-1 and an opening 232-2 that exposes the TSV 170-2. In some embodiments, the patterned passivation layer 230 has an opening 232-3 that exposes the insulating layer 172. The patterned passivation layer 230 includes an electrically insulating material, such as polyimide, undoped silicate glass, BCB, polybenzoxazole, silicon oxynitride, silicon nitride, silicon oxide, epoxy resin, other suitable insulating materials, or combinations thereof. For example, the patterned passivation layer 230 is a patterned polyimide layer. In some embodiments, the patterned passivation layer 230 has a multi-layer structure having a plurality of dielectric materials. For example, the patterned passivation layer 230 may include a SiN layer and a USG layer.

[0092] The patterned passivation layer 230 can be formed by depositing an electrically insulating material over the back side of the stacked chip structure 200 and performing a patterning process on the electrically insulating material to form an opening therein. The patterning process may include a photolithography process and an etching process. The photolithography process may form a patterned photoresist layer over the electrically insulating material, and the patterned photoresist layer may have an opening overlapping with TSV 170-1 and TSV 170-2. The photolithography process may include photoresist coating, soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, rinsing, drying, other suitable processes or combinations thereof. Then, the etching process may use the patterned photoresist layer as an etching mask. For example, the etching process may remove the portion of the electrically insulating material exposed by the opening of the patterned photoresist layer. The etching process may be performed until the TSV and / or the insulating layer 172 is reached and exposed. The etching process may be dry etching, wet etching, other suitable etching or a combination thereof. In some embodiments, the etching process partially or completely removes the patterned photoresist layer from the electrically insulating material. In some embodiments, the patterned photoresist layer is removed by a photoresist stripping process or other etching process.

[0093] refer to Fig.16 , forming the bump structure may include forming a connector 240-1 in the opening 232-1 and above the TSV 170-1, forming a connector 240-2 in the opening 232-2 and above the TSV 170-2, and forming a connector 240-3 in the opening 232-3 and above the insulating layer 172. The chip 102 and the chip 104 may be electrically connected to an external circuit, another chip, a package substrate, a printed circuit board (PCB), an interposer, other packaging components, or a combination thereof through the connector 240-1 and the connector 240-2, respectively. For example, the TSV 170-1 may be electrically connected to a power supply through the connector 240-1, wherein the power supply may be configured to provide a voltage v1 to the chip 102, and the TSV 170-2 may be electrically connected to a power supply through the connector 240-2, wherein the power supply may be configured to provide a voltage v2 to the chip 104. Each connector may include a corresponding under-bump metallization (UBM) layer, a corresponding column, and a corresponding solder bump / cap. For example, connector 240-1 may include UBM layer 242-1, pillar 244-1, and bump 246-1; connector 240-2 may include UBM layer 242-2, pillar 244-2, and bump 246-2; and connector 240-3 may include UBM layer 242-3, pillar 244-3, and bump 246-3. In some embodiments, connector 240-1, connector 240-2, connector 240-3, or a combination thereof may be formed as a controlled collapse chip connection bump (C4 bump), a ball grid array (BGA) bump, a land grid array (LGA) bump, a pin grid array (PGA) bump, a micro bump, etc.

[0094] Connector 240-1, connector 240-2 and connector 240-3 can be formed by a bump process. One or more patterning processes (e.g., photolithography and / or etching processes) can be performed to pattern one or more layers deposited during the bump process. The bump process may include forming a UBM layer in the opening of the patterned passivation layer 230. For example, UBM layer 242-1 may be formed in opening 232-1 above TSV 170-1, UBM layer 242-2 may be formed in opening 232-2 above TSV170-2, and UBM layer 242-3 may be formed in opening 232-3 above insulating layer 172. In some embodiments, the UBM layer provides a low resistance electrical connection between the column / bump and the TSV. In some embodiments, the UBM layer hermetically seals and prevents metal from diffusing from the column / bump into the stacked chip structure 200. In some embodiments, the UBM layer has a multilayer structure, and the multilayer structure may include an adhesive layer, a diffusion barrier layer, a seed layer, an oxidation barrier layer, other suitable layers, or a combination thereof. In some embodiments, the adhesive layer includes titanium, chromium, aluminum, other metals, their alloys, or a combination thereof. In some embodiments, the diffusion barrier layer includes titanium, tantalum, other metals, their alloys, or a combination thereof. In some embodiments, the seed layer includes copper, other metals, their alloys, or a combination thereof. In some embodiments, the oxidation barrier layer includes gold, other metals, their alloys, or a combination thereof. The UBM layer can be formed by depositing (e.g., by CVD, PVD, electroplating, sputtering, evaporation, other methods, or a combination thereof) one or more UBM materials (wherein one or more UBM materials partially fill the opening therein) and patterning one or more UBM materials over the patterned passivation layer 230. In some embodiments, the UBM layer can be omitted from the bump structure.

[0095] The bump process may include forming pillars in openings of the patterned passivation layer 230. For example, pillar 244-1 may be formed in opening 232-1 above UBM layer 242-1, pillar 244-2 may be formed in opening 232-2 above UBM layer 242-2, and pillar 244-3 may be formed in opening 232-3 above UBM layer 242-3. In some embodiments, the pillars include copper or their alloys, and therefore, the pillars may be referred to as copper pillars. In some embodiments, a seed layer, such as a copper seed layer, may be formed before forming the pillars, and the seed layer may be formed by an electroplating process and / or other processes.

[0096] The bump process may include forming a solder bump / cap above the column. For example, bump 246-1 may be formed above column 244-1, bump 246-2 may be formed above column 244-2, and bump 246-3 may be formed above column 244-3. In some embodiments, solder bumps (e.g., bumps 246-1, 246-2, and 246-3, respectively) may partially fill opening 232-1, opening 232-2, and opening 232-3, respectively. In some embodiments, bump 246-1, bump 246-2, bump 246-3, or a combination thereof include solder material (e.g., lead-based material, such as Sn, Pb, Ni, Au, Ag, Cu, Bi, a combination thereof, a mixture of other conductive materials, etc.). In some embodiments, the solder material includes a lead-free material. The bumps are formed by electroplating processes and / or other suitable processes. In some embodiments, a reflow process (e.g., a thermal process) may be performed on the solder material. In some embodiments, bump 246-1, bump 246-2, bump 246-3, or a combination thereof, has a hemispherical, spherical, elliptical, or other suitable shape. In some embodiments, bump 246-1, bump 246-2, bump 246-3, or a combination thereof, is referred to as a solder ball. In some embodiments, a diffusion barrier layer (comprising, for example, nickel) may be formed between the pillar and the bump to prevent the formation of an intermetallic layer and / or a void therebetween.

[0097] refer to Fig.17 , the carrier substrate 215 is removed from the front side of the stacked chip structure 200 by a suitable process (such as a grinding process), and the stacked chip structure 200 is flipped so that the chip 102 and the chip 104 provide a bottom die and a top die, respectively. The stacked chip structure 200 is configured as a stacked chip structure 100A, and the stacked chip structure 100 may be an IC package or a portion thereof.

[0098] refer to Figures 18 to 26 , Figures 18 to 26 The stacked chip structure 300 according to various aspects of the present disclosure is used to form a power transmission structure (such as Figure 2A The manufacturing of the stacked chip structure 300 is similar to the manufacturing of the stacked chip structure 200. Therefore, for the sake of simplicity and conciseness, similar aspects between them will not be repeated. For the sake of clarity, the Figures 18 to 26 To better understand the inventive concepts of the present disclosure. Additional components may be added to the stacked chip structure 300 , and some components described below may be replaced, modified, or eliminated in other embodiments of the stacked chip structure 300 .

[0099] refer to Fig.18The stacked chip structure 300 is subjected to the same Fig. 9 Similar processing is described. For example, after the stacked chip structure 300 has been subjected to FEOL processing (e.g., forming the device layer DL1 and the device layer DL2 of the chip 102 and the chip 104, respectively), the stacked chip structure 200 can be subjected to MEOL processing and BEOL processing to form the FMLI-1 structure above the device layer DL1 and the FMLI-2 structure above the device layer DL2. While the FMLI-1 structure is being formed, an interconnect structure stack of the guard ring 190-4 can be formed above the device layer DL1 (e.g., the g0 level to the g3 level of the side / wall near the power transmission TSV (e.g., TSV 170-1) of the chip 102, and the g0 level to the gD level of the side / wall near the power transmission TSA (e.g., TSV170-2) of the chip 104). The interconnect structure stack of the guard ring 190-4 can be connected to the device layer DL1, such as to a doped region formed in the substrate 106. The guard ring 190-4 may be a metal ring ( FIG. 4A to FIG. 4C ). As further described herein, TSV 170-1 and TSV 170-2 will be formed in and extend through dielectric region 310-1. Portions of the FMLI-1 structure (e.g., corresponding metal line 122 at the M4 level) overlap with guard ring 190-4 and will provide TSV landing pads for chip 102. In some embodiments, guard ring 190-4 has a non-uniform height. For example, one side of guard ring 190-4 near the power delivery TSV of chip 102 may extend from device layer DL1 to the M3 level, and one side of guard ring 190-4 near the power delivery TSV of chip 104 may extend from device layer DL1 to the MX level.

[0100] refer to Figures 19 to 21 The stacked chip structure 300 is subjected to the same conditions as described above. Figures 10 to 12 For example, chip 104 is bonded face-to-face with chip 102 to form a stacked chip structure 300 ( Fig.19 ); an encapsulant 198 and / or a molding compound may be formed around the chip 104 and over the chip 102 ( Fig.19 ); attaching the carrier substrate 215 to the front side of the stacked chip structure 300 ( Fig. 20 ); and the stacked chip structure 300 is turned over, and a thinning process is applied to the back side BS1 of the substrate 106 of the chip 102 ( Fig.21). The bonding may include aligning the TSV landing pads of chip 104 (e.g., provided by corresponding metal lines 126 at the M4 level in the illustrated embodiment) with the guard ring 190-4 of chip 102. For example, the TSV landing pads of chip 104 may be aligned to overlap with the dielectric region 310-1 of chip 102. In some embodiments, the bonding includes aligning the guard ring 190-3 with the guard ring 190-4. For example, the guard ring 190-3 may be aligned with the edge of the guard ring 190-4.

[0101] refer to Fig. 22 and Fig.23 The stacked chip structure 300 is subjected to the same conditions as described above. Fig.13 and Fig.14 Similar processing is described above. For example, TSV 170-1 and TSV 170-2 are formed simultaneously. Fig. 22 , such processing may include forming a TSV trench 320-1 and a TSA trench 320-2, wherein the TSV trench 320-1 exposes a TSV landing pad of the chip 102 (e.g., provided by a corresponding metal line 122 at the M4 level), and the TSA trench 320-2 exposes a TSV landing pad of the chip 104 (e.g., provided by a corresponding metal line 126 at the M4 level). The TSV trench 320-1 extends through the substrate 106, the device layer DL1, and into the insulating layer 120-1. The TSV trench 320-2 extends through the substrate 106, the device layer DL1, the insulating layer 120-1, the chip bonding structure, and into the insulating layer 120-2. Both TSV trench 320-1 and TSV trench 320-2 are formed in dielectric region 310-1 of insulating layer 120-1, so that guard ring 190-4 is located around TSV trench 320-1 and TSV trench 320-2. In some embodiments, before forming the TSV trenches, insulating layer 172 is formed over backside BS1 of chip 102, and TSV trench 320-1 and TSV trench 320-2 may extend through dielectric layer 174 and dielectric layer 176.

[0102] TSV trench 320-1 and TSV trench 320-2 may be formed similarly to TSV trench 220-1 and TSV-trench 220-2. In some embodiments, forming the TSV trench includes forming a patterned mask layer 325 having openings therein (e.g., opening 328-1 and opening 328-2), the openings overlapping the dielectric regions defined by the guard rings of chip 102 and / or chip 104. For example, opening 328-1 and opening 328-2 overlap with dielectric region 310-1 of insulating layer 120-1, which is defined by guard ring 190-4 of chip 102, and opening 328-2 overlaps with dielectric region 210-3, which is defined by guard ring 190-3. Patterned mask layer 325 may be similar to patterned mask layer 225 described above. In some embodiments, forming the TSV trenches includes etching the chip 102 and the chip 104 using the patterned mask layer 325 as an etching mask. The etching may be similar to that described above with reference to Fig.13 The TSV etching process may partially or completely remove the patterned mask layer 325. In some embodiments, the patterned mask layer 325 is removed by an etching process and / or a photoresist stripping process.

[0103] refer to Fig.23 , forming the TSV may also include filling the TSV trenches with a conductive material. In some embodiments, filling the TSV trenches 320-1 and 320-2 is performed in a manner similar to filling the TSV trenches 220-1 and 220-2, such as described above with reference to Fig.14 In such an embodiment, the TSV trench 320-1 and the TSV trench 320-2 may be filled with a dielectric material, a barrier material, and a bulk conductive material, the dielectric material forming a dielectric liner (e.g., dielectric liner 186A and dielectric liner 186B), the barrier material forming a barrier layer (e.g., barrier layer 184A and barrier layer 184B), and the bulk conductive material forming a conductive core (e.g., conductive core 182A and conductive core 182B) of TSV 170-1 and TSV 170-2. In some embodiments, the planarization process performed when filling the TSV trenches may remove the patterned mask layer 325.

[0104] refer to Fig.24 The stacked chip structure 300 is subjected to the same Fig.15Similar processing. For example, a patterned passivation layer 330 having openings (e.g., opening 332-1, opening 332-2, and opening 332-3) therein may be formed over the back side BS1 of the chip 102. The patterned passivation layer 330 may be configured and formed similarly to the patterned passivation layer 230. In some embodiments, since the TSVs are more closely spaced when arranged into TSV clusters, a redistribution layer (RDL) structure 350 may be formed over the back side BS1 of the chip 102 before forming the patterned passivation layer 330. The RDL structure 350 may electrically connect the TSV 170-1 and the TSV 170-2 to corresponding connectors, which may be used for external connection (e.g., connection to a corresponding power supply). In some embodiments, the RDL structure 350 redistributes the connectors to different locations, for example, to increase the spacing between the connectors of the TSVs of the TSV cluster. In some embodiments, RDL structure 350 redistributes the connection layout between devices and / or components of chip 102 and / or chip 104 to facilitate signal transmission and / or power transmission.

[0105] The RDL structure 350 may include an insulating layer 352 having an RDL line 354 and an RDL via 356 disposed therein. The RDL line 354 and the RDL via 356 may be configured to provide an RDL interconnect (or routing) 358-1 and an RDL interconnect (or wiring) 358-2. The RDL interconnect 358-1 may electrically connect the TSV 170-1 to the bump structure and / or an external circuit, and the RDL interconnect 358-2 may electrically connect the TSV 170-2 to the bump structure and / or an external circuit. Each of the RDL interconnects 358-1 and the RDL interconnects 358-2 may include a corresponding RDL via 356 disposed between a corresponding lower RDL line 354 and a corresponding upper RDL line 354 disposed on the TSV 170-1 or the TSV 170-2. In such an embodiment, the opening in the patterned passivation layer 330 exposes the RDL structure 350, rather than the TSV. For example, opening 332-1 exposes upper RDL line 354 of RDL interconnect 358-1, opening 332-2 exposes upper RDL line 354 of RDL interconnect 358-2, and opening 332-3 exposes insulating layer 352. RDL interconnect 358-1 and RDL interconnect 358-2 thus redistribute connections to TSV 170-1 and TSV 170-2 to different locations.

[0106] The insulating layer 352 includes an electrically insulating material, such as a polymer material (e.g., polyimide and / or BCB) and / or a dielectric material, and the insulating layer 352 may have a multi-layer structure (e.g., the lower RDL line 354 may be disposed in a first dielectric layer, the RDL via 356 may be disposed in a second dielectric layer, and the upper RDL line 354 may be disposed in a third dielectric layer). The RDL line 354 and the RDL via 356 include a conductive material, which may include aluminum, copper, titanium, tantalum, tungsten, ruthenium, cobalt, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, silicides thereof, or combinations thereof. In some embodiments, the RDL line 354 and the RDL via 356 include the same conductive material. In some embodiments, the RDL line 354 and the RDL via 356 include different conductive materials. In some embodiments, the RDL line 354 and / or the RDL via 356 have a multi-layer structure.

[0107] refer to Fig.25 The stacked chip structure 300 is subjected to the same Fig.16For example, connector 340-1 is formed in opening 332-1 and above upper RDL line 354 of RDL interconnect 358-1 (connected to TSV 170-1), connector 340-2 is formed in opening 332-2 and above upper RDL line 354 of RDL interconnect line 358-2 (connected to TSV 170-2), and connector 340-3 is formed in opening 332-3 and above insulating layer 350. Chip 102 and chip 104 can be electrically connected to an external circuit, another chip, a package substrate, a PCB, an interposer, other package components, or a combination thereof through connector 340-1 and connector 340-2, respectively. For example, TSV 170-1 may be electrically connected to a power source through connector 340-1 (and RDL interconnect 358-1), where the power source may be configured to provide voltage v1 to chip 102, and TSV 170-2 may be electrically connected to a power source through connector 340-2 (and RDL interconnect 358-2), where the power source may be configured to provide voltage v2 to chip 104. Connectors 340-1, 340-2, and 340-3 may be formed by a bump process as described above, and connectors 340-1, 340-2, and 340-3 may be similar to connectors 240-1, 240-2, and 240-3, respectively. For example, connector 340-1 may include UBM layer 342-1, pillar 344-1, and bump 346-1; connector 340-2 may include UBM layer 342-2, pillar 344-2, and bump 346-2; and connector 340-3 may include UBM layer 342-3, pillar 344-3, and bump 346-3. The UBM layers, pillars, and bumps of connectors 340-1, 340-2, and 340-3 may be configured and formed similarly to the UBMs, pillars, and bumps of connectors 240-1, 240-2, and 240-3, respectively.

[0108] refer to Fig.26 The stacked chip structure 300 is subjected to the same Fig.17The similar processing described. For example, the carrier substrate 215 is removed from the front side of the stacked chip structure 300 by a suitable process, and the stacked chip structure 30 is flipped so that the chip 102 and the chip 104 provide the bottom die and the top die of the stacked chip structure 200, respectively. The stacked chip structure 300 is configured as a stacked chip structure 100B, and the stacked chip structure 300 can be an IC package or a portion thereof. In the stacked chip structure 100B, since the power transmission TSV is directly connected to the chip, the power transmission TSV can overlap with the chip bonding member, and there is no need to adjust the spacing between the chip bonding members of the chip bonding structure to accommodate the TSV cluster. For example, in the stacked chip structure 300, a short power transmission TSV (e.g., TSV 170-1) can overlap with a chip bonding member (e.g., formed by a corresponding bonding pad 164 and a corresponding bonding pad 166).

[0109] Disclosed herein is a through-hole power transmission structure for a chip stack and a method for manufacturing the same. The present disclosure provides many different embodiments. An exemplary stacked chip structure includes: a first chip attached to a second chip. The first chip has a first substrate, a first device layer, and a first interconnect structure. The second chip has a second substrate, a second device layer, and a second interconnect structure. The stacked chip structure also includes a first through-hole and a second through-hole. The first through-hole extends through the first substrate, through the first device layer, through the first interconnect structure, and into the second interconnect structure. The second through-hole extends through the first substrate, through the first device layer, and into the first interconnect structure. In some embodiments, the stacked chip structure also includes: a first guard ring located around the first through-hole; and a second guard ring located around the second through-hole. In some embodiments, the stacked chip structure also includes a guard ring located around the first through-hole and the second through-hole. In some embodiments, the first interconnect structure is bonded to the second interconnect structure.

[0110] In some embodiments, the first through hole has a first critical dimension, the second through hole has a second critical dimension, and the first critical dimension is different from the second critical dimension. In some embodiments, the first through hole has a first aspect ratio, the second through hole has a second aspect ratio, and the first aspect ratio is approximately equal to the second aspect ratio. In some embodiments, the first through hole is electrically connected to the second device layer (e.g., via a second interconnect structure), and the second through hole is electrically connected to the first device layer (e.g., via a first interconnect structure). In some embodiments, the first through hole is a first power transmission through hole connected to a first power supply, and the first power transmission through hole supplies power to the second device layer; and the second through hole is a second power transmission through hole connected to a second power supply, and the second power transmission through hole supplies power to the first device layer. In some embodiments, power is transmitted to the second device layer through the first through hole, and is transmitted to the first device layer through the second through hole. In some embodiments, the first through hole is connected to a first voltage, and the second through hole is connected to a second voltage.

[0111] An exemplary integrated circuit (IC) package includes: a first die, which is bonded face-to-face with a second die. The first die includes a first device layer, and the second die includes a second device layer. The IC package also includes: a first power transmission through-hole extending through the first die and into the second die. The first power transmission through-hole is connected to the second device layer. The IC package also includes: a second power transmission through-hole extending into the first die. The second power transmission through-hole is connected to the first device layer. In some embodiments, the first die also includes a first routing structure, and the second die also includes a second routing structure. The second power transmission through-hole can be connected to the first device layer via the first routing structure, and the first power transmission through-hole can be connected to the second device layer via the second routing structure. In some embodiments, the IC package also includes a third die bonded to the first die. In some embodiments, the IC package also includes a third die bonded face-to-back with the first die and a third power transmission through-hole. The third die includes a third device layer. The first power transmission through-hole also extends through the third die, and the second power transmission through-hole also extends through the third die. A third power delivery through via extends into the third die and is connected to the third device layer.

[0112] In some embodiments, the first die includes a first guard ring and a second guard ring. The first power transmission through-hole extends through the first guard ring, and the second power transmission through-hole extends through the second guard ring. The first guard ring has a first height, the second guard ring has a second height, and the first height is greater than the second height. In some embodiments, the first die includes a guard ring. The first power transmission through-hole extends through the guard ring, and the second power transmission through-hole extends through the guard ring. The guard ring has a first side proximate to the first power transmission through-hole and a second side proximate to the second power transmission through-hole. The first side has a first height, the second side has a second height, and the first height is greater than the second height.

[0113] An exemplary method includes: bonding a first chip to a second chip, and forming a first through-hole and a second through-hole. The first chip has a first substrate, a first device layer, and a first interconnect structure. The second chip has a second substrate, a second device layer, and a second interconnect structure. The first through-hole extends through the first substrate, through the first device layer, through the first interconnect structure, and into the second interconnect structure. The second through-hole extends through the first substrate, through the first device layer, and into the first interconnect structure. In some embodiments, the method also includes forming the first through-hole and the second through-hole simultaneously. In some embodiments, the method also includes performing a thinning process to reduce the thickness of the first substrate after bonding and before forming the first through-hole and the second through-hole.

[0114] In some embodiments, forming the first through hole and the second through hole includes performing an etching process, the etching process forming the first through hole opening and the second through hole opening, and depositing a conductive material into the first through hole opening and the second through hole opening. The first through hole opening extends through the first substrate, through the first device layer, through the first interconnect structure, and into the second interconnect structure. The first through hole opening can expose the first landing pad. The second through hole opening extends through the first substrate, through the first device layer, and into the first interconnect structure. The second through hole opening exposes the second landing pad.

[0115] In some embodiments, the method further comprises forming a guard ring in the first interconnect structure, and the first through-hole and the second through-hole are formed through the guard ring. In some embodiments, the method further comprises forming a first guard ring and a second guard ring in the first interconnect structure, the first through-hole is formed through the first guard ring, and the second through-hole is formed through the second guard ring.

[0116] In some embodiments, forming the first through-hole and the second through-hole includes: performing an etching process, the etching process forming a first through-hole opening and a second through-hole opening, wherein: the first through-hole opening extends through the first substrate, through the first device layer, through the first interconnect structure, and into the second interconnect structure, wherein the first through-hole opening exposes a first landing pad, and the second through-hole opening extends through the first substrate, through the first device layer, and into the first interconnect structure, wherein the second through-hole opening exposes a second landing pad; and depositing a conductive material into the first through-hole opening and the second through-hole opening.

[0117] In some embodiments, the method further includes: after the bonding and before forming the first through-via and the second through-via, performing a thinning process to reduce a thickness of the first substrate.

[0118] In some embodiments, the method further includes forming a guard ring in the first interconnect structure, wherein the first through-via and the second through-via are formed to pass through the guard ring.

[0119] In some embodiments, the method further includes forming a first guard ring and a second guard ring in the first interconnect structure, wherein the first through-via is formed through the first guard ring, and the second through-via is formed through the second guard ring.

[0120] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A stacked chip structure, comprising: a first chip attached to a second chip, wherein the first chip has a first substrate, a first device layer, and a first interconnect structure, and the second chip has a second substrate, a second device layer, and a second interconnect structure; and A first through hole and a second through hole, wherein: The first through-hole extends through the first substrate, through the first device layer, through the first interconnect structure, and into the second interconnect structure, and The second through-via extends through the first substrate, through the first device layer, and into the first interconnect structure.

2. The stacked chip structure according to claim 1, wherein: The first interconnect structure is bonded to the second interconnect structure.

3. The stacked chip structure according to claim 1, further comprising: A first protection ring, located around the first through hole; as well as The second protection ring is located around the second through hole. 4 . The stacked chip structure according to claim 1 , further comprising a guard ring located around the first through-hole and the second through-hole.

5. The stacked chip structure according to claim 1, wherein: The first through-hole has a first critical dimension, the second through-hole has a second critical dimension, and the first critical dimension is different from the second critical dimension.

6. The stacked chip structure according to claim 1, wherein: The first through hole has a first aspect ratio, the second through hole has a second aspect ratio, and the first aspect ratio is approximately equal to the second aspect ratio.

7. The stacked chip structure according to claim 1, wherein: The first through-hole is electrically connected to the second device layer, and The second through via is electrically connected to the first device layer.

8. The stacked chip structure according to claim 1, wherein: The first through-via is a first power transmission via connected to a first power source, and the first power transmission via supplies power to the second device layer; and The second through-via is a second power transmission via connected to a second power source, and the second power transmission via supplies power to the first device layer.

9. An integrated circuit package, comprising: A first die bonded to a second die, wherein the first die includes a first device layer and the second die includes a second device layer; a first power delivery through-via extending through the first die and into the second die, wherein the first power delivery through-via is connected to the second device layer; and A second power transmission through-via extends into the first die, wherein the second power transmission through-via is connected to the first device layer.

10. A method for manufacturing an integrated circuit package, comprising: bonding a first chip to a second chip, wherein the first chip has a first substrate, a first device layer, and a first interconnect structure, and the second chip has a second substrate, a second device layer, and a second interconnect structure; and A first through hole and a second through hole are formed, wherein: The first through-hole extends through the first substrate, through the first device layer, through the first interconnect structure, and into the second interconnect structure, and The second through-via extends through the first substrate, through the first device layer, and into the first interconnect structure.

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