Wireless electric energy and data synchronous transmission system

Abstract

The invention discloses a wireless electric energy and data synchronous transmission system which comprises a direct-current carrier separation circuit, an electric energy transmitting circuit, an electric energy receiving circuit, a communication circuit and a direct-current carrier synthesis circuit. The communication circuit comprises a first data transceiving circuit, a first transceiving coil, a second transceiving coil and a second data transceiving circuit; the direct-current carrier separation circuit is respectively connected with the electric energy transmitting circuit and the first data transceiving circuit, and is used for performing electric energy and communication signal separation on the received direct-current carrier signal; and the direct current carrier synthesis circuit is connected with the electric energy receiving circuit and the second data transceiving circuit, and is used for coupling the received electric energy and the communication signal to form a direct current carrier signal. According to the invention, synchronous transmission of wireless electric energy and data can be realized, the stability, safety and expandability of an underground equipment system are improved, the operation cost of the system is reduced, and the operation efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless power and communication transmission for oil field development, and in particular to a wireless power and data synchronous transmission system. Background Art

[0002] Many oil fields in my country have now entered the high water content and ultra-high water content period. Many oil layers are small and have extremely complex oil and water distribution. The remaining oil is highly dispersed. The liquid production and water content of each layer change with the development dynamics. It is necessary to carry out stratified oil production and accurately control the liquid production of each layer.

[0003] Currently, the most effective technology for precise control of stratified oil production is cable real-time measurement and control of oil production. However, cable-controlled oil production may encounter problems such as pipe creep, lifting life limit, working life limit, low success rate of multiple wet connections of cables, and difficulty in fault maintenance.

[0004] In addition to cable-based real-time measurement, control, and extraction technology, wireless power and signal synchronous transmission technology has been added. Wireless transmission technology directly converts electrical energy or signals into intangible soft media such as electromagnetic waves, light waves, and sound waves, transferring energy from input devices to output devices through space without the need for wires or other physical contact. Wireless power and signal synchronous transmission technology can separate cable-based control and extraction, providing greater flexibility and significantly resolving the aforementioned issues. It also facilitates downhole maintenance, as pump inspections do not require all downhole equipment to be brought out; the wireless transmission portion or all of the equipment can be brought out depending on the maintenance situation. However, existing wireless power and data synchronous transmission systems still present certain challenges. Summary of the Invention

[0005] The present invention provides a wireless power and data synchronous transmission system, which can realize the synchronous transmission of wireless power and data, improve the stability, safety and scalability of the downhole equipment system, reduce the system operation cost and improve the operation efficiency.

[0006] The present invention provides a wireless power and data synchronous transmission system, comprising: a DC carrier separation circuit, a power transmission circuit, a power receiving circuit, a communication circuit and a DC carrier synthesis circuit; the communication circuit comprises a first data transceiver circuit, a first transceiver coil, a second transceiver coil and a second data transceiver circuit; the DC carrier separation circuit is respectively connected to the power transmission circuit and the first data transceiver circuit, and is used to separate the received DC carrier signal into power and communication signals; the power transmission circuit comprises an inverter module and a transmitting coil, the inverter module is connected to the transmitting coil, the inverter module is used to convert the input DC power signal into an AC power signal, and the transmitting coil is used to convert the AC power signal into electromagnetic energy and send it out; the power receiving circuit comprises The invention comprises a rectifier module and a receiving coil arranged in pair with the transmitting coil, the rectifier module is connected to the receiving coil, the receiving coil is used to receive electromagnetic energy and convert it into an AC power signal, and the rectifier module is used to convert the AC power signal into a DC power signal; the first transceiver coil is coupled to the second transceiver coil, the first data transceiver circuit is connected to the first transceiver coil, and the second data transceiver circuit is connected to the second transceiver coil; the second data transceiver circuit is used to receive a communication signal sent by the first data transceiver circuit, or to send a communication signal to the first data transceiver circuit; the DC carrier synthesis circuit is respectively connected to the power receiving circuit and the second data transceiver circuit, and the DC carrier synthesis circuit is used to couple the received power and communication signal to form a DC carrier signal.

[0007] Optionally, the first data transceiver circuit includes a first serial port level conversion circuit, a first modulation circuit, a first isolation transformer, and a first resonant circuit; the second data transceiver circuit includes a second resonant circuit, a second isolation transformer, a first demodulation circuit, and a second serial port level conversion circuit; the input end of the first serial port level conversion circuit is connected to the output end of the DC carrier separation circuit, the input end of the first modulation circuit is connected to the data sending end of the first serial port level conversion circuit, the output end of the first modulation circuit is connected to the first coil of the first isolation transformer, and the first modulation circuit is used to modulate the data sent by the first serial port level conversion circuit to form a first modulation signal; the first end of the first resonant circuit is connected to the second coil of the first isolation transformer, and the first resonant circuit is connected to the second resonant circuit of the first isolation transformer. The second end of the circuit is connected to the first transceiver coil, and the first resonant circuit is used to select the frequency and filter the first modulated signal to form a first resonant signal; the first end of the second resonant circuit is connected to the second transceiver coil, and the second end of the second resonant circuit is connected to the first coil of the second isolation transformer, and the second resonant circuit is used to select the frequency and filter the first resonant signal to form a second resonant signal; the input end of the first demodulation circuit is connected to the second coil of the second isolation transformer, the output end of the first demodulation circuit is connected to the receiving data end of the second serial port level conversion circuit, the output end of the second serial port level conversion circuit is connected to the input end of the DC carrier synthesis circuit, and the first demodulation circuit is used to demodulate the input second resonant signal and output it as a serial port data waveform.

[0008] Optionally, the second data transceiver circuit also includes a second modulation circuit, and the first data transceiver circuit also includes a second demodulation circuit; the input end of the second modulation circuit is connected to the sending data end of the second serial port level conversion circuit, and the output end of the second modulation circuit is connected to the third coil of the second isolation transformer. The second modulation circuit is used to modulate the data sent by the second serial port level conversion circuit to form a second modulation signal; the second resonant circuit is also used to select and filter the second modulation signal to form a third resonant signal; the first resonant circuit is also used to select and filter the third resonant signal to form a fourth resonant signal; the input end of the second demodulation circuit is connected to the third coil of the first isolation transformer, and the output end of the second demodulation circuit is connected to the receiving data end of the first serial port level conversion circuit. The second demodulation circuit is used to demodulate the input fourth resonant signal and output it as a serial port data waveform.

[0009] Optionally, the first demodulation circuit and the second demodulation circuit have the same structure, and the first demodulation circuit includes a first filtering circuit, a second filtering circuit, a signal amplifying circuit, a signal detection circuit and a signal shaping circuit; the input end of the first filtering circuit serves as the input end of the first demodulation circuit, and the output end of the first filtering circuit is connected to the input end of the second filtering circuit; the output end of the second filtering circuit is connected to the input end of the signal amplifying circuit, and the output end of the signal amplifying circuit is connected to the input end of the signal detection circuit, and the signal detection circuit is used to convert the resonant signal into a baseband signal; the input end of the signal shaping circuit is connected to the output end of the signal detection circuit, and the output end of the signal shaping circuit serves as the output end of the first demodulation circuit, and the signal shaping circuit is used to convert the baseband signal into a square wave pulse signal.

[0010] Optionally, the first modulation circuit and the second modulation circuit have the same structure, and the first modulation circuit includes a first inverter, a second inverter, an active oscillator, a NAND gate, a first diode, a first capacitor, a second capacitor, a third capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and a transistor; the input end of the first inverter serves as the input end of the first modulation circuit; the first input end of the NAND gate is connected to the output end of the first inverter, and the second input end of the NAND gate is connected to the output end of the active oscillator; the input end of the second inverter is connected to the output end of the NAND gate, and the cathode of the first diode is connected to the output end of the second inverter; the first end of the first resistor is connected to the anode of the first diode, and the second end of the first resistor is connected to the anode of the first diode. The second end of the first resistor is connected to the first end of the fifth resistor, and the second end of the fifth resistor is connected to the base of the transistor; the first end of the fourth resistor is connected to the power supply, the second end of the fourth resistor is connected to the first end of the first capacitor, and the second end of the first capacitor is grounded; the second capacitor is connected to the first capacitor in parallel, the first end of the second resistor is connected to the first end of the second capacitor, the second end of the second resistor is connected to the first end of the third resistor, and the second end of the third resistor is connected to the second end of the fifth resistor; the first end of the sixth resistor is connected to the collector of the transistor, the second end of the sixth resistor is connected to the first end of the third capacitor, and the emitter of the transistor is grounded; the first end of the seventh resistor is connected to the first end of the second resistor, and the second end of the seventh resistor is connected to the second end of the third capacitor.

[0011] Optionally, the first resonant circuit and the second resonant circuit have the same structure, and the first resonant circuit includes a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first inductor, a second inductor, a third inductor, a fourth inductor and a fifth inductor; the first end of the first inductor is connected to the first end of the second coil of the first isolation transformer, the second end of the first inductor is connected to the first end of the fourth capacitor, and the second end of the fourth capacitor is connected to the first end of the first transceiver coil; the first end of the second inductor is connected to the second end of the fourth capacitor, the second end of the second inductor is connected to the first end of the third inductor, and the second end of the third inductor is connected to the second end of the first transceiver coil; the first end of the fourth inductor is connected to the first end of the fourth capacitor, the second end of the fourth inductor is connected to the first end of the fifth inductor, and the second end of the fifth inductor is connected to the first end of the second coil of the first isolation transformer; the first end of the fifth capacitor is connected to the first end of the fourth capacitor, the second end of the fifth capacitor is connected to the first end of the sixth capacitor, the second end of the sixth capacitor is connected to the second end of the third inductor, and the seventh capacitor is connected in parallel with the sixth capacitor.

[0012] Optionally, the inverter module includes a pulse width modulation (PWM) signal generating circuit, a drive circuit and an inverter circuit; the PWM signal generating circuit includes a PWM control chip, which is used to generate a PWM signal; the drive circuit includes a first drive chip and a second drive chip, both of which are connected to the PWM control chip, and the first drive chip and the second drive chip are used to convert the PWM signal into a drive signal; the control end of the inverter circuit is connected to the drive circuit, and converts the DC power signal into an AC power signal based on the drive signal, and outputs the AC power signal through the AC output end of the drive chip.

[0013] Optionally, the inverter circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor; the gate of the first transistor is connected to the first output end of the first driver chip, the gate of the second transistor is connected to the second output end of the first driver chip, the gate of the third transistor is connected to the first output end of the second driver chip, the gate of the fourth transistor is connected to the second output end of the second driver chip, the first electrode of the first transistor is connected to the first electrode of the third transistor, the second electrode of the first transistor is connected to the first electrode of the second transistor, the second electrode of the third transistor is connected to the first electrode of the fourth transistor, and the second electrode of the second transistor is connected to the second electrode of the fourth transistor.

[0014] Optionally, the inverter module further includes a filter circuit, the input end of the filter circuit is connected to the AC output end, and the output end of the filter circuit outputs a filtered AC voltage.

[0015] Optionally, the rectifier module includes a resonance unit, a rectification unit and a filtering unit; the input end of the resonance unit is connected to the first end of the receiving coil, the output end of the resonance unit is connected to the first input end of the rectification unit, and the second input end of the rectification unit is connected to the second end of the receiving coil; the first input end of the filtering unit is connected to the first output end of the rectification unit, the second input end of the filtering unit is connected to the second output end of the rectification unit, and the output end of the filtering unit serves as the output end of the rectifier module.

[0016] A wireless power and data synchronous transmission system according to an embodiment of the present invention includes a DC carrier separation circuit, an electric power transmission circuit, an electric power receiving circuit, a communication circuit, and a DC carrier synthesis circuit. The communication circuit includes a first data transceiver circuit, a first transceiver coil, a second transceiver coil, and a second data transceiver circuit. The DC carrier separation circuit separates the received DC carrier signal into electric power and communication signals, thereby decoupling signal transmission and energy transmission. Signal transmission does not cause energy fluctuations, and energy transmission does not interfere with signal transmission. Simultaneously, wireless power and data synchronous transmission can be achieved, thereby improving the stability, safety, and scalability of downhole equipment systems, reducing system operating costs, and improving operating efficiency. By coupling the first transceiver coil with the second transceiver coil, the first data transceiver circuit is connected to the first transceiver coil, and the second data transceiver circuit is connected to the second transceiver coil. The second data transceiver circuit receives communication signals transmitted by the first data transceiver circuit, or transmits communication signals to the first data transceiver circuit. This enables signal transmission in half-duplex mode, i.e., signals can be transmitted both from the primary side to the secondary side and from the secondary side to the primary side.

[0017] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 This is a schematic structural diagram of a wireless power and data synchronous transmission system provided by an embodiment of the present invention;

[0020] Figure 2 1 is a structural diagram of another wireless power and data synchronous transmission system provided by an embodiment of the present invention;

[0021] Figure 3is a structural diagram of a first demodulation circuit provided by an embodiment of the present invention;

[0022] Figure 4 is a structural diagram of a first modulation circuit provided by an embodiment of the present invention;

[0023] Figure 5 is a structural diagram of a first resonant circuit provided by an embodiment of the present invention;

[0024] Figure 6 1 is a schematic structural diagram of an inverter module provided by an embodiment of the present invention;

[0025] Figure 7 1 is a structural diagram of another inverter module provided by an embodiment of the present invention;

[0026] Figure 8 It is a structural schematic diagram of a rectifier module provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar items and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present invention described herein can be implemented in sequences other than those illustrated or described herein. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0029] The wireless power and data synchronous transmission system provided by the present invention is suitable for different types of electrical equipment (such as power grids, household appliances, or industrial and commercial electrical equipment), and can be applied to user terminals (for example, mobile phones, smart devices, televisions, etc.), transportation vehicles (such as new energy vehicles, electric bicycles, etc.) and other electrical equipment fields. It can be adapted to different application scenarios such as power supply scenarios for large electrical equipment (for example, power grids, industrial equipment, etc.), power supply scenarios for small and medium-sized distributed electrical equipment (for example, vehicle-mounted electrical equipment, household electrical equipment, etc.), and power supply scenarios for mobile electrical equipment (for example, mobile phones, smart devices, etc.). The power supply scenario of oil field underground equipment will be used as an example for explanation, and no further details will be given below.

[0030] Figure 1 FIG. 1 is a structural diagram of a wireless power and data synchronous transmission system provided by an embodiment of the present invention. Figure 1 As shown, the wireless power and data synchronous transmission system includes: a DC carrier separation circuit 11, a power transmitting circuit 12, a power receiving circuit 13, a communication circuit 14 and a DC carrier synthesis circuit 15.

[0031] The communication circuit 14 includes a first data transceiver circuit 141 , a first transceiver coil LP2 , a second transceiver coil LS2 , and a second data transceiver circuit 142 .

[0032] The DC carrier separation circuit 11 is connected to the power transmission circuit 12 and the first data transceiver circuit 14 respectively, and is used to separate the received DC carrier signal into power and communication signals.

[0033] The power transmission circuit 12 includes an inverter module 120 and a transmitting coil LP1. The inverter module 120 is connected to the transmitting coil LP1. The inverter module 120 is used to convert the input DC power signal into an AC power signal. The transmitting coil LP1 is used to convert the AC power signal into electromagnetic energy and transmit it.

[0034] The power receiving circuit 13 includes a rectifier module 130 and a receiving coil LS1 arranged in pair with the transmitting coil LP1. The rectifier module 130 is connected to the receiving line LS1. The receiving coil LS1 is used to receive electromagnetic energy and convert it into an AC power signal. The rectifier module 130 is used to convert the AC power signal into a DC power signal.

[0035] The first transceiver coil LP2 is coupled to the second transceiver coil LS2, the first data transceiver circuit 141 is connected to the first transceiver coil LP2, and the second data transceiver circuit 142 is connected to the second transceiver coil LS2; the second data transceiver circuit 142 is used to receive communication signals sent by the first data transceiver circuit 141, or to send communication signals to the first data transceiver circuit 141.

[0036] The DC carrier synthesis circuit 15 is connected to the power receiving circuit 13 and the second data transceiver circuit 15 respectively. The DC carrier synthesis circuit 15 is used to couple the received power and communication signal to form a DC carrier signal.

[0037] Specifically, the transmitting coil LP1 and the receiving coil LS1 can be tightly wound enameled wires, which are excited by a high-frequency power supply, and the transmitted magnetic field energy is transmitted to the receiving coil LS1 to the greatest extent possible by the principle of resonant magnetic coupling. Finally, the high-frequency magnetic field generated is received by the receiving coil LS1, and an electromotive force is induced on the low-voltage side according to the electromagnetic induction theorem, and a stable DC voltage output is obtained after processing by the rectifier module 130.

[0038] The types of the inverter module 120 and the rectifier module 130 can be selected according to actual needs. For example, the rectifier module 130 can be a full-wave rectifier, a half-wave rectifier, or a bridge rectifier. The inverter module 120 can be a half-bridge inverter or a full-bridge device.

[0039] The DC carrier separation circuit 11 can be any circuit capable of separating a DC carrier signal into electric energy and a communication signal. The DC carrier synthesis circuit 15 can be any circuit capable of synthesizing an electric energy and a communication signal into a DC carrier signal.

[0040] Continue to refer Figure 1 , the working process of the wireless power and data synchronous transmission system is:

[0041] The DC carrier signal is separated into DC power by the DC carrier separation circuit 11. This DC power voltage can range from 40 to 80 V. Wireless power transmission requires converting the DC power signal into an AC power signal, a process known as power inversion. The DC power signal is converted into an AC power signal by the inverter module 120. The AC power signal passes through the transmitting coil LP1, converting the electrical energy into electromagnetic energy, enabling wireless power transmission.

[0042] The receiving coil LS1 absorbs the electromagnetic energy output by the transmitting coil LP1 and converts it into AC power. This AC power needs to be converted into DC power. This process is the power rectification process, that is, after passing through the rectification module 130, the required DC power signal is finally output.

[0043] In some feasible embodiments, the data transmitting circuit may be the first data transceiver circuit 141, and the data receiving circuit may be the second data transceiver circuit 142. In this case, the data transmission direction is consistent with the power transmission direction. The first data transceiver circuit 141 may generate a communication signal based on the communication frequency, and transmit the communication signal to the second transceiver coil LS2 via the first transceiver coil LP2 by magnetic field coupling. Finally, the communication signal is transmitted to the second data transceiver circuit 142. The DC carrier synthesis circuit 15 couples the received power and communication signal to form a DC carrier signal. Here, the magnetic field coupling method may specifically be electromagnetic induction or magnetic resonance, which can be determined based on the actual application scenario and is not specifically limited here.

[0044] In some feasible embodiments, the data transmitting circuit may be the second data transceiver circuit 142, and the data receiving circuit may be the first data transceiver circuit 141. In this case, the data transmission direction is opposite to the power transmission direction. The second data transceiver circuit 142 generates a communication signal based on the communication frequency and transmits it to the second transceiver coil LS2. The communication signal is then transmitted to the first transceiver coil LP2 through the second transceiver coil LS2 in a magnetic field coupling manner, and finally the communication signal is transmitted to the first data transceiver circuit 141.

[0045] A wireless power and data synchronous transmission system according to an embodiment of the present invention includes a DC carrier separation circuit, an electric power transmission circuit, an electric power receiving circuit, a communication circuit, and a DC carrier synthesis circuit. The communication circuit includes a first data transceiver circuit, a first transceiver coil, a second transceiver coil, and a second data transceiver circuit. The DC carrier separation circuit separates the received DC carrier signal into electric power and communication signals, thereby decoupling signal transmission and energy transmission. Signal transmission does not cause energy fluctuations, and energy transmission does not interfere with signal transmission. Simultaneously, wireless power and data synchronous transmission can be achieved, thereby improving the stability, safety, and scalability of downhole equipment systems, reducing system operating costs, and improving operating efficiency. By coupling the first transceiver coil with the second transceiver coil, the first data transceiver circuit is connected to the first transceiver coil, and the second data transceiver circuit is connected to the second transceiver coil. The second data transceiver circuit receives communication signals transmitted by the first data transceiver circuit, or transmits communication signals to the first data transceiver circuit. This enables signal transmission in half-duplex mode, i.e., signals can be transmitted both from the primary side to the secondary side and from the secondary side to the primary side.

[0046] Figure 2 FIG. 1 is a structural diagram of another wireless power and data synchronous transmission system provided by an embodiment of the present invention. Figure 2 As shown, optionally, the first data transceiver circuit 141 includes a first serial port level conversion circuit 1411, a first modulation circuit 1412, a first isolation transformer T1, and a first resonant circuit 1413; the second data transceiver circuit 142 includes a second resonant circuit 1421, a second isolation transformer T2, a first demodulation circuit 1422, and a second serial port level conversion circuit 1423.

[0047] The input end of the first serial port level conversion circuit 1411 is connected to the output end of the DC carrier separation circuit 11, the input end of the first modulation circuit 1412 is connected to the data transmission end TXD1 of the first serial port level conversion circuit 1411, and the output end of the first modulation circuit 1412 is connected to the first coil of the first isolation transformer T1. The first modulation circuit 1412 is used to modulate the data sent by the first serial port level conversion circuit 1411 to form a first modulated signal.

[0048] The first end of the first resonant circuit 1413 is connected to the second coil of the first isolation transformer T1, and the second end of the first resonant circuit 1413 is connected to the first transceiver coil LP2. The first resonant circuit 1413 is used to select and filter the first modulated signal to form a first resonant signal.

[0049] The first end of the second resonant circuit 1421 is connected to the second transceiver coil LS2, and the second end of the second resonant circuit 1421 is connected to the first coil of the second isolation transformer T2. The second resonant circuit 1421 is used to select and filter the first resonant signal to form a second resonant signal.

[0050] The input end of the first demodulation circuit 1422 is connected to the second coil of the second isolation transformer T2, the output end of the first demodulation circuit 1422 is connected to the receiving data end RXD2 of the second serial port level conversion circuit 1423, and the output end of the second serial port level conversion circuit 1423 is connected to the input end of the DC carrier synthesis circuit 15. The first demodulation circuit 1422 is used to demodulate the input second resonant signal and output it as a serial port data waveform.

[0051] The second data transceiver circuit 142 also includes a second modulation circuit 1424, and the first data transceiver circuit 141 also includes a second demodulation circuit 1414; the input end of the second modulation circuit 1424 is connected to the data transmission end TXD2 of the second serial port level conversion circuit 1423, and the output end of the second modulation circuit 1424 is connected to the third coil of the second isolation transformer T2. The second modulation circuit 1424 is used to modulate the data sent by the second serial port level conversion circuit 1423 to form a second modulated signal.

[0052] The second resonant circuit 1421 is further used to perform frequency selection and filtering on the second modulated signal to form a third resonant signal; the first resonant circuit 1413 is further used to perform frequency selection and filtering on the third resonant signal to form a fourth resonant signal.

[0053] The input end of the second demodulation circuit 1424 is connected to the third coil of the first isolation transformer T1, and the output end of the second demodulation circuit 1424 is connected to the receiving data end RXD1 of the first serial port level conversion circuit 1411. The second demodulation circuit 1424 is used to demodulate the input fourth resonant signal and output it as a serial port data waveform.

[0054] To transmit the communication code wirelessly, the code must first be modulated onto a high-frequency signal. This process is called signal modulation. The modulated signal carries the high-frequency signal of the communication code. To maximize transmission efficiency, the modulated signal is resonantly compensated and transmitted via the first transceiver coil LP2.

[0055] To maximize signal input efficiency, the input signal to the second transceiver coil LS2 undergoes resonance compensation to maximize the received modulation amplitude. The modulated signal then undergoes demodulation to separate the communication command from the high-frequency modulation signal. This process is known as signal demodulation. The demodulated communication command amplitude fluctuates, requiring normalization and shaping. At this point, communication command reception is complete.

[0056] In this embodiment, the first modulation circuit 1412 and the second demodulation circuit 1414 are isolated from the first resonant circuit 1413 by the first isolation transformer T1, thereby preventing the first resonant circuit 1413 from being affected by the first modulation circuit 1412 and the second demodulation circuit 1414, resulting in a change in the resonant frequency and affecting the resonant inductive coupling effect. Similarly, in this embodiment, the first demodulation circuit 1422 and the second modulation circuit 1424 are isolated from the second resonant circuit 1421 by the second isolation transformer T2, thereby preventing the second resonant circuit 1421 from being affected by load circuits such as the first demodulation circuit 1422 and the second modulation circuit 1424, resulting in a change in the resonant frequency and affecting the energy transmission efficiency.

[0057] In some embodiments, the first demodulation circuit 1422 and the second demodulation circuit 1414 have the same structure, the first modulation circuit 1412 and the second modulation circuit 1424 have the same structure, and the first resonance circuit 1413 and the second resonance circuit 1421 have the same structure. The following description will take the first modulation circuit 1412, the first resonance circuit 1413, and the first demodulation circuit 1422 as examples.

[0058] As a preferred implementation of this embodiment, Figure 3 This is a schematic diagram of the structure of a first demodulation circuit provided by an embodiment of the present invention, combined with Figure 2 and Figure 3 The first demodulation circuit 1422 includes a first filtering circuit 101 , a second filtering circuit 102 , a signal amplifying circuit 103 , a signal detecting circuit 104 and a signal shaping circuit 105 .

[0059] The input end of the first filtering circuit 101 serves as the input end of the first demodulation circuit 1422, and the output end of the first filtering circuit 101 is connected to the input end of the second filtering circuit 102; the output end of the second filtering circuit 102 is connected to the input end of the signal amplifying circuit 103, and the output end of the signal amplifying circuit 103 is connected to the input end of the signal detection circuit 104, and the signal detection circuit 104 is used to convert the resonant signal into a baseband signal; the input end of the signal shaping circuit 105 is connected to the output end of the signal detection circuit 104, and the output end of the signal shaping circuit 105 serves as the output end of the first demodulation circuit 1422, and the signal shaping circuit 105 is used to convert the baseband signal into a square wave pulse signal.

[0060] Specifically, the first filtering circuit 101 includes an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a sixth inductor L6, a seventh inductor L7, an eighth inductor L8, a second diode D2 and a third diode D3.

[0061] A first end of the eighth resistor R8 is connected to the first end of the second coil of the second isolation transformer T2, a second end of the eighth resistor R8 is connected to the first end of the eighth capacitor C8, a second end of the eighth capacitor C8 is connected to the first end of the sixth inductor L6, a second end of the sixth inductor L6 is connected to the first end of the ninth capacitor C9, and a second end of the ninth capacitor C9 is grounded.

[0062] A first end of the ninth resistor R9 is connected to the first end of the eighth capacitor C8, a second end of the ninth resistor R9 is respectively connected to the tenth capacitor C10 and the first end of the seventh inductor L7, a second end of the seventh inductor L7 is grounded, a second end of the tenth capacitor C10 is connected to the first end of the tenth resistor R10, a second end of the tenth resistor R10 is connected to the first end of the eighth inductor L8, and a second end of the eighth inductor L8 is grounded.

[0063] The cathode of the second diode D2 is connected to the second end of the ninth resistor R9, and the anode of the second diode D2 is grounded; the anode of the third diode D3 is connected to the cathode of the second diode D2, and the cathode of the third diode D3 is grounded.

[0064] A first end of the eleventh capacitor C11 is connected to the second end of the ninth resistor R9 , and an output end of the eleventh capacitor C11 serves as an output end of the first filter circuit 101 .

[0065] Optionally, the second filtering circuit 102 is a bandpass filtering circuit. The second filtering circuit 102 includes a first operational amplifier U1A, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a twelfth capacitor C12, and a thirteenth capacitor C13.

[0066] A first end of the eleventh resistor R11 serves as an input end of the second filter circuit 102. A second end of the eleventh resistor R11 is electrically connected to the inverting input end of the first operational amplifier U1A. A first end of the twelfth resistor R12 is connected to the output end of the first operational amplifier U1A. A second end of the twelfth resistor R12 is connected to the first end of the twelfth capacitor C12. A second end of the twelfth capacitor C12 is connected to the first end of the thirteenth resistor R13. A first end of the thirteenth capacitor C13 is connected to the first end of the twelfth capacitor C12. A second end of the thirteenth capacitor C13 is grounded. A second end of the thirteenth resistor R13 serves as an output end of the second filter circuit 102.

[0067] The center frequency of the second filter circuit 102 is 3 MHz. The amplification factor of the first operational amplifier U1A is AF1 = R13 / 2R11. The first operational amplifier U1A, the eleventh resistor R11, and the thirteenth resistor R13 form an active bandpass filter. The twelfth resistor R12, the twelfth capacitor C12, and the thirteenth capacitor C13 form a passive bandpass filter.

[0068] Signal amplification circuit 103 includes a fourteenth resistor R14, a fifteenth resistor R15, and a second operational amplifier U2A. The first end of the fourteenth resistor R14 serves as the input of signal amplification circuit 103, and the second end of the fourteenth resistor R14 is connected to the inverting input of the second operational amplifier U2A. The fifteenth resistor R15 is connected between the inverting input of the second operational amplifier U2A and the output of the second operational amplifier U2A. The amplification factor AF2 of signal amplification circuit 103 is equal to R15 / R14.

[0069] The signal detection circuit 104 includes a fourth diode D4, a sixteenth resistor R16, and a fourteenth capacitor C14. The anode of the fourth diode D4 serves as the input terminal of the signal detection circuit 104, the cathode of the fourth diode D4 is connected to the first terminal of the fourteenth capacitor C14, and the second terminal of the fourteenth capacitor C14 is grounded. The first terminal of the sixteenth resistor R16 is connected to the first terminal of the fourteenth capacitor C14, the second terminal of the sixteenth resistor R16 is grounded, and the first terminal of the sixteenth resistor R16 serves as the output terminal of the signal detection circuit 104.

[0070] The fourth diode D4 has a unidirectional conduction characteristic and is used to remove the negative half waveform of the modulated signal. The fourteenth capacitor C14 filters out the modulated high-frequency signal. The sixteenth resistor R16 is a current loop for the detection signal, and a detected level signal is formed at both ends of the resistor.

[0071] The signal shaping circuit 105 includes a fifteenth capacitor C15, a third operational amplifier U3A and a third inverter U3E; the first end of the fifteenth capacitor C15 serves as the input end of the signal shaping circuit 105, the first end of the fifteenth capacitor C15 is connected to the non-inverting input end of the third operational amplifier U3A, and the second end of the fifteenth capacitor C15 is connected to the inverting input end of the third operational amplifier U3A.

[0072] An input end of the third inverter U3E is connected to an output end of the third operational amplifier U3A, and an output end of the third inverter U3E serves as an output end of the signal shaping circuit 105 .

[0073] It should be understood that the second filtering circuit 102, the signal amplifying circuit 103 and the signal shaping circuit 105 also include peripheral circuits or pin connections composed of other electrical components. The peripheral circuits and pin connections are as follows: Figure 3 As shown, no further details are given here.

[0074] Figure 4 is a structural diagram of a first modulation circuit provided by an embodiment of the present invention, such as Figure 4 As shown, the first modulation circuit 1412 includes a first inverter U1E, a second inverter U2E, an active oscillator XT1, a NAND gate U2F, a first diode D1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and a transistor T1.

[0075] The input end of the first inverter U1E serves as the input end of the first modulation circuit 1412; the first input end of the NAND gate U2F is connected to the output end of the first inverter U1E, and the second input end of the NAND gate U2F is connected to the output end of the active oscillator XT1; the input end of the second inverter U2E is connected to the output end of the NAND gate U2F, and the cathode of the first diode D1 is connected to the output end of the second inverter U2E.

[0076] A first end of the first resistor R1 is connected to the anode of the first diode D1, a second end of the first resistor R1 is connected to the first end of the fifth resistor R5, and a second end of the fifth resistor R5 is connected to the base of the transistor T1; a first end of the fourth resistor R4 is connected to the power supply VCC, a second end of the fourth resistor R4 is connected to the first end of the first capacitor C1, and a second end of the first capacitor C1 is grounded; a second capacitor C2 is connected in parallel with the first capacitor C1, a first end of the second resistor R2 is connected to the first end of the second capacitor C2, a second end of the second resistor R2 is connected to the first end of the third resistor R3, and a second end of the third resistor R3 is connected to the second end of the fifth resistor R5.

[0077] A first end of the sixth resistor R6 is connected to the collector of the transistor T1, a second end of the sixth resistor R6 is connected to the first end of the third capacitor C3, and the emitter of the transistor T1 is grounded; a first end of the seventh resistor R7 is connected to the first end of the second resistor R2, and a second end of the seventh resistor R7 is connected to the second end of the third capacitor C3.

[0078] In some embodiments, active oscillator XT1 is configured to output a 3MHz high-frequency carrier signal. In this case, the square wave signal, inverted by first inverter U1E, is modulated onto the 3MHz high-frequency carrier signal. The modulated signal is then fed into second inverter U2E for signal inversion. The inverted modulated signal by second inverter U2E controls the on and off state of transistor T1. T1's on-frequency is the carrier frequency of 3MHz, generating a 3MHz ground-to-ground on-off signal in transistor T1. Consequently, a 3MHz first modulated signal is alternately generated across the first coil of first isolation transformer T1, and a 3MHz first modulated signal is outputted from the second coil of first isolation transformer T1.

[0079] Figure 5 is a structural diagram of a first resonant circuit provided by an embodiment of the present invention, such as Figure 5 As shown, the first resonant circuit 1413 includes a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4 and a fifth inductor L5.

[0080] The first end of the first inductor L1 is connected to the first end of the second coil of the first isolation transformer T1, the second end of the first inductor L1 is connected to the first end of the fourth capacitor C4, and the second end of the fourth capacitor C4 is connected to the first end of the first transceiver coil LP2.

[0081] The first end of the second inductor L2 is connected to the second end of the fourth capacitor C4 , the second end of the second inductor L2 is connected to the first end of the third inductor L3 , and the second end of the third inductor L3 is connected to the second end of the first transceiver coil LP2 .

[0082] A first end of the fourth inductor L4 is connected to a first end of the fourth capacitor C4, a second end of the fourth inductor L4 is connected to a first end of the fifth inductor L5, and a second end of the fifth inductor L5 is connected to a first end of the second coil of the first isolation transformer T1;

[0083] The first end of the fifth capacitor C5 is connected to the first end of the fourth capacitor C4, the second end of the fifth capacitor C5 is connected to the first end of the sixth capacitor C6, the second end of the sixth capacitor C6 is connected to the second end of the third inductor L3, and the seventh capacitor C7 is connected in parallel with the sixth capacitor C6.

[0084] The first inductor L1, the fourth inductor L4, the fifth inductor L5 and the fourth capacitor C4 form a series LC resonant circuit. The resonant frequency is 3 MHz. The impedance is minimum at the resonant frequency, and the first modulated signal can pass through without attenuation. At the same time, the impedance of the electric energy wireless signal below 3 MHz is very large. Therefore, the series LC resonant circuit here enables the carrier to pass through without attenuation, thereby blocking the wireless energy.

[0085] The second inductor L2, the third inductor L3, and the sixth capacitor C6 form a parallel LC resonant circuit with a harmonic frequency of 3 MHz. Because the LC parallel resonant circuit has its highest impedance at the 3 MHz resonant frequency, the 3 MHz first modulated signal can pass through without attenuation. However, the power signal frequency is much lower than 3 MHz, exhibiting capacitive reactance, thus absorbing the power coil coupled signal. The 3 MHz first modulated signal is transmitted through the first transceiver coil LP2, thereby preventing crosstalk from wireless power signals in the communication transmission process.

[0086] Figure 6FIG. 1 is a schematic diagram of the structure of an inverter module provided by an embodiment of the present invention. Figure 6 As shown, the inverter module 120 includes a pulse width modulation (PWM) signal generating circuit 201 , a driving circuit 202 and an inverter circuit 203 .

[0087] The PWM signal generating circuit 201 includes a PWM control chip U1 , which is used to generate a PWM signal.

[0088] The driving circuit 202 is connected to the PWM control chip U1 , and is used to convert the PWM signal into a driving signal.

[0089] The control terminal of the inverter circuit 203 is connected to the driving circuit 202 , converts the DC power signal into an AC power signal based on the driving signal, and outputs the AC power signal through the AC output terminal of the driving chip.

[0090] Optionally, the inverter module 120 further includes a filter circuit 204 , wherein an input end of the filter circuit 204 is connected to the AC output end, and an output end of the filter circuit 204 outputs a filtered AC voltage.

[0091] Figure 7 This is a structural diagram of another inverter module provided by an embodiment of the present invention. Figure 7 As shown, the PWM signal generating circuit 201 includes a sliding resistor Rw, a seventeenth resistor R17, an eighteenth resistor R18 and a nineteenth resistor R19.

[0092] Optionally, the PWM control chip U1 is a 16-pin PWM chip. Exemplarily, the PWM control chip U1 is a G3525AN model PWM chip.

[0093] The first pin IN- of the PWM control chip U1 is connected to the slider of the sliding rheostat Rw through the seventeenth resistor R17. The first end of the sliding rheostat Rw is connected to the sixteenth pin VREF of the PWM control chip U1. The second end of the sliding rheostat Rw is grounded.

[0094] A first end of the eighteenth resistor R18 is grounded, a second end of the eighteenth resistor R18 is connected to a first end of the nineteenth resistor R19, and a second end of the nineteenth resistor R19 is connected to a first end of the sliding rheostat Rw.

[0095] The eleventh pin OUTA and the fourteenth pin OUTB of the PWM control chip U1 serve as output terminals of the PWM signal generating circuit 201 .

[0096] PWM control chip U1 uses constant-frequency pulse-width modulation for control. Adjusting the duty cycle can be accomplished by adjusting the sliding rheostat Rw. By adjusting the sliding rheostat Rw, the voltage of the reference signal can be changed, and two duty-cycle-adjustable rectangular waves (i.e., PWM signals) can be output at pins OUTA and OUTB. When the reference signal increases, the duty cycle of the PWM signal output from pin OUTA of PWM control chip U1 decreases, thereby adjusting the duty cycle.

[0097] It should be understood that the PWM control chip also includes a second pin IN+ and a third pin The fourth pin is OSCOUT, the fifth pin is CT, the sixth pin is RT, the seventh pin is DISC, the eighth pin is SS, the ninth pin is COMP, and the tenth pin is The 12th pin is GND, the 13th pin is VC and the 15th pin is VCC1. The PWM signal generating circuit 201 also includes peripheral circuits or pin connection methods composed of other electrical components. The peripheral circuits and pin connection methods are as follows: Figure 7 As shown, no further details are given.

[0098] Optionally, the driving circuit 202 includes a first driving chip U2 and a second driving chip U3 , and the driving circuit 202 further includes a sixteenth capacitor C16 , a seventeenth capacitor C17 , an eighteenth capacitor C18 , and a nineteenth capacitor C19 .

[0099] Optionally, in this embodiment, the model of the first driver chip U2 and the second driver chip U3 is IR2110, and the second pin IN and the third pin SD of the first driver chip U2, and the second pin IN and the third pin SD of the second driver chip U3 are respectively connected to the output end of the PWM signal generating circuit 201.

[0100] A first end of the sixteenth capacitor C16 is connected to the first pin VDD of the first driver chip U2 , a second end of the sixteenth capacitor C16 is connected to the fourth pin COM of the first driver chip U2 , and the fifth pin LO and the seventh pin HO of the first driver chip U2 are respectively connected to the inverter circuit 203 .

[0101] A first end of the seventeenth capacitor C17 is connected to the first pin VDD of the second driver chip U3, a second end of the seventeenth capacitor C17 is connected to the fourth pin COM of the second driver chip U3, a fifth pin LO and a seventh pin HO of the second driver chip U3 are respectively connected to the inverter circuit, a sixth pin VS of the first driver chip U2 is the first end Vouta of the AC output end, and a sixth pin BS of the second driver chip U3 is the second end Voutb of the AC output end.

[0102] A first end of an eighteenth capacitor C18 is connected to the eighth pin VB of the first driver chip U2, and a second end of the eighteenth capacitor C18 is connected to the sixth pin VS of the first driver chip U2. A first end of a nineteenth capacitor C19 is connected to the eighth pin VB of the second driver chip U3, and a second end of the nineteenth capacitor C19 is connected to the sixth pin VS of the second driver chip U3.

[0103] It should be understood that the drive circuit 14 also includes peripheral circuits or pin connections composed of other electrical components. The peripheral circuits and pin connections are as follows: Figure 7 As shown, no further details are given.

[0104] Optionally, the inverter circuit 203 includes a first transistor Q1, a second transistor Q2, a third transistor Q3 and a fourth transistor Q4; the gate of the first transistor Q1 is connected to the first output end of the first driver chip U2, the gate of the second transistor Q2 is connected to the second output end of the first driver chip U2, the gate of the third transistor Q3 is connected to the first output end of the second driver chip U3, and the gate of the fourth transistor Q4 is connected to the second output end of the second driver chip U3.

[0105] The first electrode of the first transistor Q1 is connected to the first electrode of the third transistor Q3, the second electrode of the first transistor Q1 is connected to the first electrode of the second transistor Q2, the second electrode of the third transistor Q3 is connected to the first electrode of the fourth transistor Q4, and the second electrode of the second transistor Q2 is connected to the second electrode of the fourth transistor Q4.

[0106] The first driver chip U2 and the second driver chip U3 are half-bridge driver chips, and each chip generates two complementary PWM signals according to the input PWM signal.

[0107] The complementary PWM signals generated by the second driver chip U2 control the on and off states of the first and second transistors Q1 and Q2. Because the second driver chip U2 outputs two complementary PWM signals, the on-states of the first and second transistors Q1 and Q2 are opposite: when the first transistor Q1 is on, the second transistor Q2 is off; and when the first transistor Q1 is off, the second transistor Q2 is on. Similarly, the two complementary PWM signals generated by the second driver chip U3 control the on and off states of the third and fourth transistors Q3 and Q4. Ultimately, the state logic controlled by the first, second, third, and fourth transistors Q1, Q2, Q3, and Q4 is: when the first and fourth transistors Q1 and Q4 are on, the second and third transistors Q2 and Q3 are off; or when the first and fourth transistors Q1 and Q4 are off, the second and third transistors Q2 and Q3 are on.

[0108] When the first transistor Q1 and the fourth transistor Q4 are turned on and the second transistor Q2 and the third transistor Q3 are turned off, the inverter circuit 203 outputs a forward voltage. When the second transistor Q2 and the third transistor Q3 are turned on and the first transistor Q1 and the fourth transistor Q4 are turned off, the inverter circuit 203 outputs a reverse voltage. The first transistor Q1, the second transistor Q2, the third transistor Q3 and the fourth transistor Q4 constitute a typical H-bridge circuit, which generates an alternating positive and negative alternating voltage by periodically switching the first transistor Q1, the second transistor Q2, the third transistor Q3 and the fourth transistor Q4, thereby completing the DC power supply to AC voltage inversion process.

[0109] Figure 8 FIG. 1 is a structural diagram of a rectifier module provided by an embodiment of the present invention. Figure 8 As shown, the rectifier module 130 includes a resonance unit 301 , a rectifier unit 302 and a filter unit 303 .

[0110] The input end of the resonance unit 301 is connected to the first end of the receiving coil LS1 , the output end of the resonance unit 301 is connected to the first input end of the rectification unit 302 , and the second input end of the rectification unit 302 is connected to the second end of the receiving coil LS1 .

[0111] A first input end of the filter unit 303 is connected to a first output end of the rectifier unit 302 , a second input end of the filter unit 303 is connected to a second output end of the rectifier unit 302 , and an output end of the filter unit 303 serves as an output end of the rectifier module 130 .

[0112] The rectifier unit 302 can rectify the input AC power signal. The filter unit 303 includes at least one capacitor. Figure 8 exemplarily shows that the rectifier circuit 302 may be a diode rectifier circuit, which may specifically include a first rectifier diode D11, a second rectifier diode D12, a third rectifier diode D13, and a fourth rectifier diode D14.

[0113] The first rectifier diode D11, the second rectifier diode D12, the third rectifier diode D13, and the fourth rectifier diode D14 are uncontrolled devices with a simple structure and low cost, which helps reduce the cost of the charger system. The anode of the first rectifier diode D11 is connected to the cathode of the second rectifier diode D12 and serves as the first input terminal of the rectifier unit 302. The cathode of the first rectifier diode D11 is connected to the cathode of the third rectifier diode D13 and serves as the first output terminal of the rectifier unit 302. The anode of the third rectifier diode D13 is connected to the cathode of the fourth rectifier diode D14 and serves as the second input terminal of the rectifier unit 302. The anode of the second rectifier diode D12 is connected to the anode of the fourth rectifier diode D14 and serves as the second output terminal of the rectifier unit 302.

[0114] After the AC power signal is input into the rectifier unit 302 through the first and second input terminals of the rectifier unit 302, when the AC power signal is greater than zero, the first rectifier diode D11, the first output terminal, the second output terminal, and the fourth rectifier diode D14 form a loop. When the AC power signal is less than zero, the third rectifier diode D13, the first output terminal, the second output terminal, and the second rectifier diode D12 form a loop. This rectifies the AC power signal and outputs a DC power signal.

[0115] It should be noted that the present invention adopts a high-redundancy parameter design for the device, and considers the influence of temperature, pressure, voltage, current, temperature drift, etc. on the system in the selection of parameters, increases the rated coefficients of the above parameters for device selection, and ensures the stable operation of the wireless power and data synchronous transmission system.

[0116] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A wireless power and data synchronous transmission system, characterized in that: include: DC carrier separation circuit, power transmission circuit, power receiving circuit, communication circuit and DC carrier synthesis circuit; The communication circuit includes a first data transceiver circuit, a first transceiver coil, a second transceiver coil and a second data transceiver circuit; The DC carrier separation circuit is connected to the power transmission circuit and the first data transceiver circuit respectively, and is used to separate the received DC carrier signal into power and communication signals; The power transmission circuit includes an inverter module and a transmitting coil. The inverter module is connected to the transmitting coil. The inverter module is used to convert the input DC power signal into an AC power signal. The transmitting coil is used to convert the AC power signal into electromagnetic energy and transmit it. The power receiving circuit includes a rectifier module and a receiving coil arranged in pair with the transmitting coil, the rectifier module is connected to the receiving coil, the receiving coil is used to receive electromagnetic energy and convert it into an AC power signal, and the rectifier module is used to convert the AC power signal into a DC power signal; The first transceiver coil is coupled to the second transceiver coil, the first data transceiver circuit is connected to the first transceiver coil, and the second data transceiver circuit is connected to the second transceiver coil; the second data transceiver circuit is used to receive a communication signal sent by the first data transceiver circuit, or to send a communication signal to the first data transceiver circuit; The DC carrier synthesis circuit is connected to the power receiving circuit and the second data transceiver circuit respectively, and is used to couple the received power and communication signals to form a DC carrier signal.

2. The wireless power and data synchronous transmission system according to claim 1, characterized in that: The first data transceiver circuit includes a first serial port level conversion circuit, a first modulation circuit, a first isolation transformer, and a first resonant circuit; the second data transceiver circuit includes a second resonant circuit, a second isolation transformer, a first demodulation circuit and a second serial port level conversion circuit; An input end of the first serial port level conversion circuit is connected to an output end of the DC carrier separation circuit, an input end of the first modulation circuit is connected to a data transmission end of the first serial port level conversion circuit, an output end of the first modulation circuit is connected to a first coil of the first isolation transformer, and the first modulation circuit is used to modulate data transmitted by the first serial port level conversion circuit to form a first modulated signal; A first end of the first resonant circuit is connected to the second coil of the first isolation transformer, and a second end of the first resonant circuit is connected to the first transceiver coil, wherein the first resonant circuit is used to perform frequency selection and filtering on the first modulated signal to form a first resonant signal; A first end of the second resonant circuit is connected to the second transceiver coil, and a second end of the second resonant circuit is connected to the first coil of the second isolation transformer, and the second resonant circuit is used to perform frequency selection and filtering on the first resonant signal to form a second resonant signal; The input end of the first demodulation circuit is connected to the second coil of the second isolation transformer, the output end of the first demodulation circuit is connected to the receiving data end of the second serial port level conversion circuit, and the output end of the second serial port level conversion circuit is connected to the input end of the DC carrier synthesis circuit. The first demodulation circuit is used to demodulate the input second resonant signal and output it as a serial port data waveform.

3. The wireless power and data synchronous transmission system according to claim 2, characterized in that: The second data transceiver circuit further includes a second modulation circuit, and the first data transceiver circuit further includes a second demodulation circuit; an input end of the second modulation circuit connected to a data transmission end of the second serial port level conversion circuit, an output end of the second modulation circuit connected to a third coil of the second isolation transformer, and the second modulation circuit configured to modulate data transmitted by the second serial port level conversion circuit to form a second modulation signal; The second resonant circuit is further used to perform frequency selection and filtering on the second modulated signal to form a third resonant signal; The first resonant circuit is further configured to perform frequency selection and filtering on the third resonant signal to form a fourth resonant signal; The input end of the second demodulation circuit is connected to the third coil of the first isolation transformer, and the output end of the second demodulation circuit is connected to the receiving data end of the first serial port level conversion circuit. The second demodulation circuit is used to demodulate the input fourth resonant signal and output it as a serial port data waveform.

4. The wireless power and data synchronous transmission system according to claim 3, characterized in that: The first demodulation circuit and the second demodulation circuit have the same structure, and the first demodulation circuit includes a first filtering circuit, a second filtering circuit, a signal amplification circuit, a signal detection circuit and a signal shaping circuit; The input end of the first filter circuit serves as the input end of the first demodulation circuit, and the output end of the first filter circuit is connected to the input end of the second filter circuit; The output end of the second filtering circuit is connected to the input end of the signal amplifying circuit, and the output end of the signal amplifying circuit is connected to the input end of the signal detecting circuit, and the signal detecting circuit is used to convert the resonant signal into a baseband signal; The input end of the signal shaping circuit is connected to the output end of the signal detection circuit, the output end of the signal shaping circuit serves as the output end of the first demodulation circuit, and the signal shaping circuit is used to convert the baseband signal into a square wave pulse signal.

5. The wireless power and data synchronous transmission system according to claim 3, characterized in that: The first modulation circuit and the second modulation circuit have the same structure, and the first modulation circuit includes a first inverter, a second inverter, an active oscillator, a NAND gate, a first diode, a first capacitor, a second capacitor, a third capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and a transistor; The input end of the first inverter serves as the input end of the first modulation circuit; The first input terminal of the NAND gate is connected to the output terminal of the first inverter, and the second input terminal of the NAND gate is connected to the output terminal of the active oscillator; The input terminal of the second inverter is connected to the output terminal of the NAND gate, and the cathode of the first diode is connected to the output terminal of the second inverter; The first end of the first resistor is connected to the anode of the first diode, the second end of the first resistor is connected to the first end of the fifth resistor, and the second end of the fifth resistor is connected to the base of the transistor; A first end of the fourth resistor is connected to a power supply, a second end of the fourth resistor is connected to a first end of the first capacitor, and a second end of the first capacitor is grounded; The second capacitor is connected in parallel with the first capacitor, the first end of the second resistor is connected to the first end of the second capacitor, the second end of the second resistor is connected to the first end of the third resistor, and the second end of the third resistor is connected to the second end of the fifth resistor; A first end of the sixth resistor is connected to the collector of the transistor, a second end of the sixth resistor is connected to the first end of the third capacitor, and an emitter of the transistor is grounded; The first end of the seventh resistor is connected to the first end of the second resistor, and the second end of the seventh resistor is connected to the second end of the third capacitor.

6. The wireless power and data synchronous transmission system according to claim 2, characterized in that: The first resonant circuit and the second resonant circuit have the same structure, and the first resonant circuit includes a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first inductor, a second inductor, a third inductor, a fourth inductor and a fifth inductor; The first end of the first inductor is connected to the first end of the second coil of the first isolation transformer, the second end of the first inductor is connected to the first end of the fourth capacitor, and the second end of the fourth capacitor is connected to the first end of the first transceiver coil; The first end of the second inductor is connected to the second end of the fourth capacitor, the second end of the second inductor is connected to the first end of the third inductor, and the second end of the third inductor is connected to the second end of the first transceiver coil; The first end of the fourth inductor is connected to the first end of the fourth capacitor, the second end of the fourth inductor is connected to the first end of the fifth inductor, and the second end of the fifth inductor is connected to the first end of the second coil of the first isolation transformer; The first end of the fifth capacitor is connected to the first end of the fourth capacitor, the second end of the fifth capacitor is connected to the first end of the sixth capacitor, the second end of the sixth capacitor is connected to the second end of the third inductor, and the seventh capacitor is connected in parallel with the sixth capacitor.

7. The wireless power and data synchronous transmission system according to claim 1, characterized in that: The inverter module includes a pulse width modulation (PWM) signal generating circuit, a driving circuit and an inverter circuit; The PWM signal generating circuit includes a PWM control chip, and the PWM control chip is used to generate a PWM signal; The driving circuit is connected to the PWM control chip, and the driving circuit is used to convert the PWM signal into a driving signal; The control end of the inverter circuit is connected to the drive circuit, converts the DC power signal into an AC power signal based on the drive signal, and outputs the AC power signal through the AC output end of the drive chip.

8. The wireless power and data synchronous transmission system according to claim 7, characterized in that: The inverter circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor; The gate of the first transistor is connected to the first output terminal of the first driver chip, the gate of the second transistor is connected to the second output terminal of the first driver chip, the gate of the third transistor is connected to the first output terminal of the second driver chip, and the gate of the fourth transistor is connected to the second output terminal of the second driver chip; The first electrode of the first transistor is connected to the first electrode of the third transistor, the second electrode of the first transistor is connected to the first electrode of the second transistor, the second electrode of the third transistor is connected to the first electrode of the fourth transistor, and the second electrode of the second transistor is connected to the second electrode of the fourth transistor.

9. The wireless power and data synchronous transmission system according to claim 7, characterized in that: The inverter module further includes a filter circuit, an input end of the filter circuit is connected to the AC output end, and an output end of the filter circuit outputs a filtered AC voltage.

10. The wireless power and data synchronous transmission system according to claim 1, characterized in that: The rectifier module includes a resonance unit, a rectifier unit and a filter unit; The input end of the resonance unit is connected to the first end of the receiving coil, the output end of the resonance unit is connected to the first input end of the rectification unit, and the second input end of the rectification unit is connected to the second end of the receiving coil; The first input end of the filter unit is connected to the first output end of the rectifier unit, the second input end of the filter unit is connected to the second output end of the rectifier unit, and the output end of the filter unit serves as the output end of the rectifier module.

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