MOSFET power semiconductor module, motor controller and automobile

Abstract

The invention relates to an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) power semiconductor module, a motor controller and an automobile. The MOSFET power semiconductor module comprises a substrate, a plurality of power electrode terminals, a plurality of signal terminals, an upper bridge chipset, a lower bridge chipset, a signal connecting piece, an interconnection heightening layer and an interconnection substrate, the substrate is provided with a signal copper layer area, a chipset area and a substrate power copper layer area. The plurality of power electrode terminals comprise a direct-current negative power electrode terminal, a direct-current positive power electrode terminal and an output power electrode terminal; each signal terminal is respectively connected with the driving areas on the silicon-based IGBT power chips in the upper bridge chip group and the lower bridge chip group through corresponding signal connecting pieces so as to form a driving path; the direct-current positive power electrode terminal is connected with the direct-current negative power electrode terminal through the power copper layer, the chipset, the interconnection heightening layer and the interconnection substrate on the substrate to form a power path. According to the invention, the problems of large electromagnetic interference and inconsistent dynamic and static current sharing are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor modules, and in particular to a MOSFET power semiconductor module, a motor controller and a car. Background Art

[0002] At present, the mainstream power semiconductor module structure usually consists of power chips, copper-clad ceramic substrates, interconnected copper bars or wires, power terminals, signal terminals, epoxy molding compounds or frame plastic shells, and a variety of solders. This structure uses a precise welding process to tightly connect the various components together to form a highly integrated power conversion unit. However, in the prior art, especially in the design of power modules using four or more parallel schemes, there are some inherent technical difficulties.

[0003] like Figure 1 and Figure 2 As shown, in the traditional four-parallel power module, the power chip is located in the upper and lower parts of the long side direction of the substrate, and the chip layout on the bridge arm of the four-parallel scheme is rectangular, wherein the power path (high current path) is: from the DC positive power electrode terminal 5 through the substrate upper bridge drain power copper layer 19-a, the upper bridge chipset, the upper bridge source power interconnection copper bus 20-a, the second substrate upper and lower bridge power interconnection copper layer 19-c (lower bridge drain power copper layer), the upper and lower bridge interconnection copper bus 20-b, the first substrate upper and lower bridge power interconnection copper layer 19-b (lower bridge drain power copper layer), the lower bridge chipset, the lower bridge source power interconnection copper bus 20-c, the substrate power negative copper layer 19-d to the DC negative power electrode terminal 4. This layout has the following problems: 1. Since there is a vertical cross-over area in the space between the upper and lower bridge power paths, when the module works transiently in the dead zone, the upper and lower bridge commutation paths will produce a strong magnetic field coupling effect in this area, thereby forming electromagnetic interference.

[0004] 2. The vertical cross-reattachment area between the lower bridge drive path and the power path will also cause problems. The magnetic field generated by the large current on the power path will interfere with the signal on the drive path, causing signal oscillation, thereby increasing the loss of the module and reducing the consistency of dynamic and static current sharing. This will not only reduce the efficiency of the module, but may also affect the stable operation of the module.

[0005] 3. Due to the large difference in parasitic resistance and parasitic inductance of the upper and lower bridge drive paths, this will lead to large differences in the design of the upper and lower bridge peripheral circuits. This difference will further affect the consistency of the upper and lower bridge signals, making it difficult for the module to achieve the ideal control effect during operation.

[0006] Therefore, it is necessary to develop a new MOSFET power semiconductor module, motor controller and automobile. Summary of the invention

[0007] The object of the present invention is to provide a MOSFET power semiconductor module, a motor controller and a car to solve the problems of large electromagnetic interference and inconsistent dynamic and static current sharing.

[0008] In a first aspect, a MOSFET power semiconductor module according to the present invention comprises: A substrate, on which an upper bridge chipset region, a substrate power cathode copper layer and a lower bridge chipset region are sequentially arranged from one side to the other side, wherein the upper bridge chipset region includes an upper bridge gate signal copper layer, an upper bridge source signal copper layer and an upper bridge drain power copper layer, and the lower bridge chipset region includes a lower bridge gate signal copper layer, a lower bridge source signal copper layer and a lower bridge drain power copper layer; A plurality of power electrode terminals, including a DC negative power electrode terminal, a DC positive power electrode terminal and an output power electrode terminal respectively connected to the substrate power negative copper layer, the substrate upper bridge drain power copper layer and the substrate lower bridge drain power copper layer; A plurality of signal terminals, including an upper bridge arm gate signal terminal, an upper bridge arm source signal terminal, a lower bridge arm gate signal terminal and a lower bridge arm source signal terminal respectively connected to the upper bridge gate signal copper layer of the substrate, the upper bridge source signal copper layer of the substrate, the lower bridge gate signal copper layer of the substrate and the lower bridge source signal copper layer of the substrate; The upper bridge chipset includes a plurality of MOSFET power chips respectively arranged on the upper bridge drain power copper layer of the substrate; The lower bridge chipset includes a plurality of MOSFET power chips respectively arranged on the lower bridge drain power copper layer of the substrate; A signal connector, used to connect the upper bridge gate signal copper layer, the upper bridge source signal copper layer, the lower bridge gate signal copper layer and the lower bridge source signal copper layer of the substrate to the driving area of ​​the corresponding MOSFET power chip; An interconnection pad layer is arranged on the upper bridge chipset region, the lower bridge chipset region and the substrate power cathode copper layer; An interconnection substrate, disposed on the interconnection pad layer; Among them, the upper bridge arm gate signal terminal, the upper bridge arm source signal terminal, the lower bridge arm gate signal terminal and the lower bridge arm source signal terminal are respectively connected to the driving area of ​​the MOSFET power chip in the upper bridge chipset and the lower bridge chipset through corresponding signal connectors to form a driving path; the DC positive power electrode terminal is respectively connected to the DC negative power electrode terminal through the power copper layer, the chipset, the interconnection pad layer and the interconnection substrate on the substrate to form a power path; and there is no overlapping area between the driving path and the power path in space.

[0009] Optionally, the signal connector includes: Connect the upper bridge gate signal copper layer of the substrate and the upper bridge gate binding wire of the MOSFET power chip; Connect the lower bridge gate signal copper layer of the substrate and the lower bridge gate binding wire of the MOSFET power chip; Connect the upper bridge source signal copper layer of the substrate and the upper bridge source binding wire of the MOSFET power chip; Connect the lower bridge source signal copper layer of the substrate and the lower bridge source binding wire of the MOSFET power chip.

[0010] Optionally, the driving path includes a gate path, the gate path includes an upper bridge gate path and a lower bridge gate path, and the upper bridge gate path and the lower bridge gate path are symmetrically arranged at 180° with the center as the origin; The upper bridge gate path is from the upper bridge arm gate signal terminal through the upper bridge gate signal copper layer of the substrate and the upper bridge gate binding wire to the gate area of ​​the MOSFET power chip in the upper bridge chipset; The lower bridge gate path extends from the lower bridge arm gate signal terminal through the lower bridge gate signal copper layer of the substrate and the lower bridge gate binding wire to the gate region of the MOSFET power chip in the lower bridge chipset.

[0011] Optionally, the driving path further includes a source path, the source path includes an upper bridge source path and a lower bridge source path, and the upper bridge source path and the lower bridge source path are symmetrically arranged at 180° with the center as the origin; The upper bridge source path is from the upper bridge arm source signal terminal through the upper bridge source signal copper layer of the substrate and the upper bridge source binding wire to the Kelvin source region of the MOSFET power chip in the upper bridge chipset; The lower bridge source path extends from the lower bridge arm source signal terminal through the lower bridge source signal copper layer of the substrate and the lower bridge source binding wire to the Kelvin source region of the MOSFET power chip in the lower bridge chipset.

[0012] Optionally, the interconnection padding layer includes an upper bridge source power interconnection padding layer arranged on each upper bridge chipset, two upper and lower bridge power interconnection padding layers arranged on the lower bridge drain power copper layer of the substrate, lower bridge source power interconnection padding layers respectively arranged on each lower bridge chipset, and four lower bridge and DC negative electrode interconnection padding layers arranged on the substrate power negative electrode copper layer; The interconnect substrate includes an interconnect copper layer, an insulating ceramic sheet and a signal shielding copper layer which are overlapped in sequence. The interconnect copper layer is divided into a first part which can cover all lower bridge source power interconnect padding layers and all lower bridge and DC negative pole interconnect padding layers, and a second part which can cover all upper bridge source power interconnect padding layers and all upper and lower bridge power interconnection padding layers.

[0013] Optionally, the power path runs from the DC positive power electrode terminal through the upper bridge drain power copper layer of the substrate, the upper bridge chipset, the upper bridge source power interconnection pad layer, the second part of the interconnected substrate, the upper and lower bridge power interconnection pad layer, the lower bridge drain power copper layer of the substrate, the lower bridge chipset, the lower bridge source power interconnection pad layer, the first part of the interconnected substrate lower bridge source power interconnection copper layer, the lower bridge and DC negative pole interconnection pad layer, and the substrate power negative copper layer to the DC negative pole power electrode terminal.

[0014] Optionally, the upper bridge chipset includes four MOSFET power chips, which are sequentially and spaced apart on the upper bridge drain power copper layer of the substrate; The lower bridge chipset comprises four MOSFET power chips, which are arranged in sequence and at intervals on the lower bridge drain power copper layer of the substrate.

[0015] Optionally, the bridge gate signal copper layer on the substrate, the bridge source signal copper layer on the substrate and the bridge drain power copper layer on the substrate are all arranged on one side of the substrate and extend along the length direction of the substrate; The gate signal copper layer of the lower bridge of the substrate, the source signal copper layer of the lower bridge of the substrate and the drain power copper layer of the lower bridge of the substrate are all arranged on the other side of the substrate and extend along the length direction of the substrate.

[0016] In a second aspect, a motor controller described in the present invention adopts the MOSFET power semiconductor module described in the present invention.

[0017] In a third aspect, a car according to the present invention adopts the motor controller according to the present invention.

[0018] Beneficial effects of the present invention: 1. The present invention significantly reduces the inductance problem caused by the long power path by optimizing the layout of each component in the module, reduces the cross-interference between the signal copper bus and the power copper bus, and improves the electrical stability. The system inductance simulation results show that compared with the 7.6nH of the existing four-parallel power module, the inductance of the present invention is reduced to 4.8nH, a decrease of 2.8nH. This helps to improve the electromagnetic compatibility, switching efficiency, system stability, overall performance of the power module and reduce the loss of the power module, especially in the fields of hybrid vehicles, extended-range power vehicles, engineering machinery, etc. to show better performance.

[0019] 2. The driving path of the upper and lower bridges of the present invention adopts a 180° symmetrical design with the center as the origin, so that the upper and lower gate-source paths are basically consistent, reducing the difference in driving parasitic parameters. In terms of parasitic inductance of the driving path: the four-parallel power module of the existing solution has a large electromagnetic interference of the overall system due to the complex circuit of the upper and lower bridges and the need for binding wires for connection. The driving path inductance of the upper and lower bridges is simulated at 1GHz, and the gate-source parasitic inductance of the upper and lower bridges is 34.7nH and 54nH respectively, and the inductance imbalance is 21.76%. The driving path parasitic inductance of the upper and lower bridges of the present invention is simulated at 1GHz, and the parasitic inductance of the upper and lower bridges is 12.33nH and 12.35nH respectively, and the inductance imbalance is only 0.1%, which is much lower than the 21.76% of the existing solution. In terms of parasitic resistance of the gate-source path: the four-parallel power module of the existing solution simulates the parasitic resistance of the gate-source path of the upper and lower bridges at 1Hz, and the parasitic resistance of the gate-source path of the upper and lower bridges is 44.6mΩ and 77.7mΩ respectively, and the resistance imbalance is 27.06%. The gate-source path resistance of the upper and lower bridges of the present invention is simulated at 1Hz, and the parasitic resistance of the gate-source path of the upper and lower bridges is 3.55mΩ and 3.56mΩ respectively, and the resistance imbalance is only 0.14%, which is much lower than 27.06% of the existing solution. Compared with the existing four-parallel power module, the present invention has greatly improved the parasitic inductance of the gate-source path. After the inductance is optimized, the gate drive signal of the power module is more stable, and the performance stability of the power module is better improved. There is also a great improvement in the loop resistance, which will further reduce the impact of the power loop on the drive loop and greatly improve the system stability of the power module.

[0020] 3. The driving path and the power path in the present invention have no spatial cross-over and re-pasting areas, which effectively reduces the gate switch oscillation caused by electromagnetic interference between each other. The mutual inductance of the gate and the power path of the upper and lower bridges is simulated at 1GHz. The mutual inductance of the upper bridge and the power path is only 0.47nH, and the mutual inductance of the lower bridge and the power path is only 0.68nH, and the mutual inductance imbalance is 18.26%. Compared with the four-parallel power module of the existing solution, because the four-parallel power module is more complicated, the gate binding line will cross the top of the power loop. The mutual inductance of the gate and the power loop of the upper and lower bridges is simulated at 1GHz. The mutual inductance of the gate and the power loop of the upper and lower bridges is 1.92nH and 10.2nH respectively, and the mutual inductance imbalance is 68.32%. The above shows that the present invention can well reduce the mutual inductance between the driving path and the power path, which will reduce the influence of the power path on the driving path, which is conducive to improving the system stability of the module. At the same time, the influence on the driving loop is reduced, which will help reduce the loss of the power module and greatly help to improve the overall efficiency of the power module.

[0021] 4. The commutation circuit of the power path of the present invention is simpler, making the commutation speed faster.

[0022] 5. In the MOSFET power semiconductor module of the present invention, the spatial structure formed by setting the interconnection pad layer and the interconnection substrate allows the current to flow in multiple directions. In particular, when the current in the power path passes through the interconnection pad layer, the interconnection substrate, the chip and the substrate, they will form some paths with the same current magnitude but flowing in the opposite direction. The magnetic fields generated by these reverse current paths will cancel each other out, thereby reducing the inductance of the entire loop, reducing the switching loss, reducing the turn-off spike, and fully improving the performance of the power module. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the structure of an existing four-parallel power module; Figure 2 is a schematic diagram of a drive path and a power path in an existing four-parallel power module; Figure 3 is a schematic structural diagram of the MOSFET power semiconductor module described in the embodiment of the present application; Figure 4 is a schematic structural diagram of a substrate in an embodiment of the present application; Figure 5 is a schematic diagram of the structure of an interconnect substrate in an embodiment of the present application; Figure 6 is a schematic diagram of the structure of the interconnected copper layer in an embodiment of the present application; Figure 7 is a schematic diagram of the distribution of the upper bridge chipset and the lower bridge chipset in the embodiment of the present application; Figure 8 It is a structural schematic diagram of the MOSFET power semiconductor module (excluding the interconnection pad layer and the interconnection substrate) described in the embodiment of the present application; Fig. 9 It is a schematic diagram of the structure of the MOSFET power semiconductor module (excluding the interconnection substrate) described in the embodiment of the present application; Fig.10 is a schematic diagram of the drive path and the drive path in the embodiment of the present application; Fig.11 It is a structural schematic diagram of the MOSFET power semiconductor module (with a heat dissipation structure) described in the embodiment of the present application; In the figure: 1. temperature sensor, 2. lower bridge arm gate signal terminal, 3. lower bridge arm source signal terminal, 4. DC negative power electrode terminal, 5. DC positive power electrode terminal, 6. substrate, 6-a1. upper bridge gate signal copper layer of substrate, 6-a2. lower bridge gate signal copper layer of substrate, 6-b1. upper bridge source signal copper layer of substrate, 6-b2. lower bridge source signal copper layer of substrate, 6-c. upper bridge drain power copper layer of substrate, 6-d. lower bridge drain power copper layer of substrate, 6-e. negative power copper layer of substrate, 7. MOSFET power chip, 8. signal connector, 8-a1. upper bridge gate binding wire, 8-a2. lower bridge gate binding wire, 8-b1. upper bridge source binding wire, 8-b2. lower bridge source binding wire, 9. interconnection pad layer, 9-a. upper bridge source power interconnection pad layer, 9-b , upper and lower bridge power interconnection padding layer, 9-c, lower bridge source power interconnection padding layer, 9-d, lower bridge and DC negative pole interconnection padding layer, 10-interconnection substrate, 10-a, insulating ceramic sheet, 10-b, interconnection copper layer, 10-b1, first part, 10-b2, second part, 10-c, signal shielding copper layer, 11. Upper bridge arm gate signal terminal, 12. Upper bridge arm source signal terminal, 13. Upper bridge arm drain signal terminal, 14. Output power electrode terminal, 15. Power chip area, 16. Power path, 17. Drive path, 18. Heat dissipation structure, 19-a. Upper bridge drain power copper layer on substrate, 19-b. Upper and lower bridge power interconnection copper layer of the first substrate, 19-c. Upper and lower bridge power interconnection copper layer of the second substrate, 19-d. Substrate power negative copper layer, 20-a. Upper bridge source power interconnection copper busbar, 20-b. Upper and lower bridge interconnection copper busbar, 20-c. Lower bridge source power interconnection copper busbar.

[0024] The arrows in the figure indicate the direction of current flow. DETAILED DESCRIPTION

[0025] The following will describe the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention, not for limiting the scope of protection of the present invention.

[0026] like Figure 3 As shown, in an embodiment of the present application, a MOSFET power semiconductor module includes a substrate 6, and a plurality of power electrode terminals, a plurality of signal terminals, an upper bridge chipset, a lower bridge chipset, a signal connector 8, an interconnection pad layer 9 and an interconnection substrate 10 arranged on the substrate 6.

[0027] like Figure 3As shown, in the embodiment of the present application, an upper bridge chipset area, a substrate power negative copper layer 6-e and a lower bridge chipset area are provided on the substrate 6 from one side to the other, the upper bridge chipset area includes a substrate upper bridge gate signal copper layer 6-a1, a substrate upper bridge source signal copper layer 6-b1 and a substrate upper bridge drain power copper layer 6-c, and the lower bridge chipset area includes a substrate lower bridge gate signal copper layer 6-a2, a substrate lower bridge source signal copper layer 6-b2 and a substrate lower bridge drain power copper layer 6-d.

[0028] like Figure 3 As shown, in the embodiment of the present application, multiple power electrode terminals include a DC negative power electrode terminal 4, a DC positive power electrode terminal 5 and an output power electrode terminal 14, which are respectively connected to the substrate power negative copper layer 6-e, the substrate upper bridge drain power copper layer 6-c and the substrate lower bridge drain power copper layer 6-d.

[0029] like Figure 3 As shown, in the embodiment of the present application, multiple signal terminals include an upper bridge arm gate signal terminal 11, an upper bridge arm source signal terminal 12, a lower bridge arm gate signal terminal 2 and a lower bridge arm source signal terminal 3, which are respectively connected to the upper bridge gate signal copper layer 6-a1, the upper bridge source signal copper layer 6-b1, the lower bridge gate signal copper layer 6-a2 and the lower bridge source signal copper layer 6-b2 of the substrate.

[0030] like Figure 3 As shown, in the embodiment of the present application, the upper bridge chipset includes a plurality of MOSFET power chips 7 respectively arranged on the upper bridge drain power copper layer 6 - c of the substrate.

[0031] like Figure 3 As shown, in the embodiment of the present application, the lower bridge chipset includes a plurality of MOSFET power chips 7 (eg, silicon carbide-based MOSFET power chips) respectively arranged on the lower bridge drain power copper layer 6 - d of the substrate.

[0032] like Figure 3 As shown, in an embodiment of the present application, the signal connector 8 is used to connect the bridge gate signal copper layer 6-a1 on the substrate, the bridge source signal copper layer 6-b1 on the substrate, the bridge gate signal copper layer 6-a2 under the substrate, and the bridge source signal copper layer 6-b2 under the substrate with the corresponding driving area of ​​the MOSFET power chip 7.

[0033] like Figure 3 As shown, in the embodiment of the present application, the interconnection pad layer 9 is arranged on the upper bridge chipset area, the lower bridge chipset area and the substrate power negative electrode copper layer 6-e.

[0034] like Figure 3 As shown, in the embodiment of the present application, the interconnection substrate 10 is disposed on the interconnection pad layer 9 .

[0035] In the embodiment of the present application, the upper bridge arm gate signal terminal 11, the upper bridge arm source signal terminal 12, the lower bridge arm gate signal terminal 2 and the lower bridge arm source signal terminal 3 are respectively connected to the driving area of ​​the MOSFET power chip 7 in the upper bridge chipset and the lower bridge chipset through the corresponding signal connector 8 to form a driving path; the DC positive power electrode terminal 5 is respectively connected to the DC negative power electrode terminal 4 through the power copper layer, the chipset, the interconnection pad layer 9 and the interconnection substrate 10 on the substrate 6 to form a power path; and there is no overlapping area between the drive path and the power path in space.

[0036] like Figure 4 As shown, in a possible embodiment, the upper substrate bridge gate signal copper layer 6-a1, the upper substrate bridge source signal copper layer 6-b1 and the upper substrate bridge drain power copper layer 6-c are all arranged on the right side of the substrate 6, and all extend along the length direction of the substrate 6. The lower substrate bridge gate signal copper layer 6-a2, the lower substrate bridge source signal copper layer 6-b2 and the lower substrate bridge drain power copper layer 6-d are all arranged on the left side of the substrate 6, and all extend along the length direction of the substrate 6. The substrate power cathode copper layer 6-e is arranged in the area between the upper substrate bridge drain power copper layer 6-c and the lower substrate bridge drain power copper layer 6-d.

[0037] like Figure 3 As shown, in a possible embodiment, the temperature sensor 1 is disposed at the lower left corner of the substrate 6 .

[0038] like Figure 3 and Figure 4 As shown, in a possible embodiment, one end of the lower bridge arm gate signal terminal 2 is connected to the lower bridge gate signal copper layer 6-a2 of the substrate. One end of the lower bridge arm source signal terminal 3 is connected to the lower bridge source signal copper layer 6-b2 of the substrate. One end of the DC negative power electrode terminal 4 is connected to the substrate power negative copper layer 6-e. One end of the DC positive power electrode terminal 5 is connected to the upper bridge drain power copper layer 6-c of the substrate. And the lower bridge arm gate signal terminal 2, the lower bridge arm source signal terminal 3, the DC negative power electrode terminal 4 and the DC positive power electrode terminal 5 are all located at the first end of the substrate 6.

[0039] like Figure 8 As shown, in a possible embodiment, the upper bridge chipset includes four MOSFET power chips 7, which are arranged in sequence on the upper bridge drain power copper layer 6-c of the substrate. The lower bridge chipset includes four MOSFET power chips 7, which are arranged in sequence on the lower bridge drain power copper layer 6-d of the substrate.

[0040] like Figure 8As shown, in a possible embodiment, the signal connector 8 includes an upper bridge gate binding wire 8-a1 connecting the upper bridge gate signal copper layer 6-a1 of the substrate and the MOSFET power chip 7, a lower bridge gate binding wire 8-a2 connecting the lower bridge gate signal copper layer 6-a2 of the substrate and the MOSFET power chip 7, an upper bridge source binding wire 8-b1 connecting the upper bridge source signal copper layer 6-b1 of the substrate and the MOSFET power chip 7, and a lower bridge source binding wire 8-b2 connecting the lower bridge source signal copper layer 6-b2 of the substrate and the MOSFET power chip 7.

[0041] like Fig. 9 As shown, in a possible embodiment, the interconnection padding layer 9 includes an upper bridge source power interconnection padding layer 9-a arranged on each upper bridge chipset, two upper and lower bridge power interconnection padding layers 9-b arranged on the lower bridge drain power copper layer 6-d of the substrate, a lower bridge source power interconnection padding layer 9-c respectively arranged on each lower bridge chipset, and four lower bridge and DC negative pole interconnection padding layers 9-d arranged on the substrate power negative pole copper layer 6-e.

[0042] like Figure 5 , Figure 6 and Fig.10 As shown, in a possible embodiment, the interconnect substrate 10 includes an interconnect copper layer 10-b, an insulating ceramic sheet 10-a and a signal shielding copper layer 10-c which are arranged in sequence and overlapped. The interconnect copper layer 10-b includes a first part 10-b1 and a second part 10-b2, the first part 10-b1 can cover all lower bridge source power interconnect padding layers 9-c and all lower bridge and DC negative pole interconnection padding layers 9-d; the second part 10-b2 can cover all upper bridge source power interconnection padding layers 9-a and all upper and lower bridge power interconnection padding layers 9-b.

[0043] like Figure 4 As shown, in a possible embodiment, one end of the upper bridge arm gate signal terminal 11 is connected to the upper bridge gate signal copper layer 6-a1 of the substrate. One end of the upper bridge arm source signal terminal 12 is connected to the upper bridge source signal copper layer 6-b1 of the substrate. One end of the upper bridge arm drain signal terminal 13 is connected to the upper bridge drain power copper layer 6-c of the substrate. One end of the output power electrode terminal 14 is connected to the lower bridge drain power copper layer 6-d of the substrate. And the upper bridge arm gate signal terminal 11, the upper bridge arm source signal terminal 12, the upper bridge arm drain signal terminal 13 and the output power electrode terminal 14 are all located at the second end of the substrate 6.

[0044] like Figure 8 and Fig.10As shown, in the embodiment of the present application, in the MOSFET power semiconductor module, the driving path 17 (the driving path is the chip control signal path, generally a small current) includes a gate path and a source path, wherein: the gate path includes an upper bridge gate path and a lower bridge gate path, and the upper bridge gate path and the lower bridge gate path are symmetrically arranged at 180° with the center as the origin; the source path includes an upper bridge source path and a lower bridge source path, and the upper bridge source path and the lower bridge source path are symmetrically arranged at 180° with the center as the origin. The specific paths are as follows: Upper bridge gate path: from the upper bridge arm gate signal terminal 11 through the upper bridge gate signal copper layer 6 - a1 of the substrate and the upper bridge gate binding wire 8 - a1 to the gate region of the MOSFET power chip 7 in the upper bridge chipset.

[0045] Upper bridge source path: from the upper bridge arm source signal terminal 12 through the upper bridge source signal copper layer 6 - b1 of the substrate, the upper bridge source binding wire 8 - b1 to the Kelvin source region of the MOSFET power chip 7 in the upper bridge chipset.

[0046] Lower bridge gate path: from the lower bridge arm gate signal terminal 2 through the substrate lower bridge gate signal copper layer 6-a2, the lower bridge gate binding wire 8-a2 to the gate area of ​​the MOSFET power chip 7 in the lower bridge chipset.

[0047] Lower bridge source path: from the source signal terminal 3 through the substrate lower bridge source signal copper layer 6-b2, the lower bridge source binding wire 8-b2 to the Kelvin source region of the MOSFET power chip 7 in the lower bridge chipset.

[0048] In the embodiment of the present application, the upper bridge gate path, the upper bridge source path, the lower bridge gate path and the lower bridge source path are substantially consistent, thereby reducing the difference in driving parasitic parameters.

[0049] like Fig. 9 and 10 As shown, in the embodiment of the present application, the power path 16 (large current path) in the MOSFET power semiconductor module is as follows: From the DC positive power electrode terminal 5 through the substrate upper bridge drain power copper layer 6-c, the upper bridge chipset, the upper bridge source power interconnection padding layer 9-a, the second part 10-b2 of the interconnection copper layer 10-b, the upper and lower bridge power interconnection padding layer 9-b (that is, the lower bridge drain power interconnection padding layer), the substrate lower bridge drain power copper layer 6-d, the lower bridge chipset, the lower bridge source power interconnection padding layer 9-c, the first part 10-b1 of the interconnection copper layer 10-b, the lower bridge and DC negative interconnection padding layer 9-d, and the substrate power negative copper layer 6-e to the DC negative power electrode terminal 4.

[0050] In the embodiment of the present application, there is no spatial cross-over area between the drive path and the power path, which greatly reduces the gate switch oscillation caused by mutual electromagnetic interference.

[0051] In the embodiment of the present application, the commutation loop of the power path is reduced more than that of the existing solution, for example: the power path of the chip drain or the front end of the drain and the path of the upper and lower bridge power interconnection are reduced, so that the commutation is faster. At the same time, when the upper and lower bridges are interconnected on the upper substrate, there is a reverse cancellation of the current path (in the entire power path, the "opposite current path" increases, and the magnetic field generated by the opposite current will cancel each other), thereby reducing the circuit inductance, reducing the switching loss, reducing the turn-off spike, and fully improving the performance of the module.

[0052] In the embodiment of the present application, the MOSFET power chip 7 is interconnected with the substrate 6 by welding with welding materials. The temperature sensor 1, the lower bridge arm gate signal terminal 2, the lower bridge arm source signal terminal 3, the DC negative power electrode terminal 4, the DC positive power electrode terminal 5, the upper bridge arm gate signal terminal 11, the upper bridge arm source signal terminal 12, the upper bridge arm drain signal terminal 13, and the output power electrode terminal 14 are electrically interconnected with the substrate 6 by welding with welding materials. The gate / source signal of the MOSFET power chip 7 is interconnected with the gate / source terminal through the gate / source signal binding line. The electrical interconnection between the upper and lower bridge arms of the MOSFET power chip 7 is interconnected through the interconnection pad layer 9 and the interconnection substrate 10. The MOSFET power chip 7 is interconnected with the interconnection pad layer 9 by welding with welding materials. The interconnection pad layer 9 and the interconnection substrate 10 are interconnected by welding with welding materials.

[0053] In a possible embodiment, the lower bridge arm gate signal terminal 2, the lower bridge arm source signal terminal 3, the DC negative power electrode terminal 4, the DC positive power electrode terminal 5, the upper bridge arm gate signal terminal 11, the upper bridge arm source signal terminal 12, the upper bridge arm drain signal terminal 13, and the output power electrode terminal 14 are distributed around the substrate 6 and meet a certain electrical gap.

[0054] In a possible embodiment, when the interconnection pad layer 9 is electrically connected to the interconnection substrate 10 , it is connected to the interconnection copper layer 10 - b of the interconnection substrate 10 .

[0055] like Figure 7 As shown, in a possible embodiment, all components need to meet the electrical clearance and creepage distance when interconnected. The signal connector 8 needs to meet the electrical clearance when bound. Each part of the power chip area 15 needs to meet the electrical clearance and creepage distance.

[0056] like Fig.11As shown, in a possible embodiment, in order to ensure a good heat dissipation effect of the MOSFET power semiconductor module, a heat dissipation structure 18 is provided on the back side of the MOSFET power semiconductor module.

[0057] The above-mentioned embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above-mentioned embodiments. Any other changes, modifications, substitutions, combinations and simplifications made without departing from the spirit and principle of the present invention shall be equivalent replacement modes and shall be included in the protection scope of the present invention.

Claims

1. A MOSFET power semiconductor module, characterized in that: include: A substrate (6), on which an upper bridge chipset region, a substrate power negative copper layer (6-e) and a lower bridge chipset region are sequentially arranged from one side to the other side, the upper bridge chipset region comprising an upper bridge gate signal copper layer (6-a1) on the substrate, an upper bridge source signal copper layer (6-b1) on the substrate and an upper bridge drain power copper layer (6-c) on the substrate, and the lower bridge chipset region comprising a lower bridge gate signal copper layer (6-a2) on the substrate, a lower bridge source signal copper layer (6-b2) on the substrate and a lower bridge drain power copper layer (6-d) on the substrate; A plurality of power electrode terminals, including a DC negative power electrode terminal (4), a DC positive power electrode terminal (5), and an output power electrode terminal (14) respectively connected to the substrate power negative copper layer (6-e), the substrate upper bridge drain power copper layer (6-c), and the substrate lower bridge drain power copper layer (6-d); A plurality of signal terminals, including an upper bridge arm gate signal terminal (11), an upper bridge arm source signal terminal (12), a lower bridge arm gate signal terminal (2) and a lower bridge arm source signal terminal (3) respectively connected to the upper bridge gate signal copper layer (6-a1) of the substrate, the upper bridge source signal copper layer (6-b1) of the substrate, the lower bridge gate signal copper layer (6-a2) of the substrate and the lower bridge source signal copper layer (6-b2) of the substrate; An upper bridge chipset, comprising a plurality of MOSFET power chips (7) respectively arranged on the upper bridge drain power copper layer (6-c) of the substrate; A lower bridge chipset, comprising a plurality of MOSFET power chips (7) respectively arranged on the lower bridge drain power copper layer (6-d) of the substrate; A signal connector (8) used to connect the upper bridge gate signal copper layer (6-a1), the upper bridge source signal copper layer (6-b1), the lower bridge gate signal copper layer (6-a2), and the lower bridge source signal copper layer (6-b2) to a corresponding MOSFET power chip (7) drive region; An interconnection pad layer (9) is arranged on the upper bridge chipset region, the lower bridge chipset region and the substrate power negative electrode copper layer (6-e); An interconnection substrate (10) is arranged on the interconnection pad layer (9); The upper bridge arm gate signal terminal (11), the upper bridge arm source signal terminal (12), the lower bridge arm gate signal terminal (2) and the lower bridge arm source signal terminal (3) are respectively connected to the drive area of ​​the MOSFET power chip (7) in the upper bridge chipset and the lower bridge chipset through corresponding signal connectors (8) to form a drive path; the DC positive power electrode terminal (5) is respectively connected to the DC negative power electrode terminal (4) through the power copper layer on the substrate (6), the chipset, the interconnection pad layer (9) and the interconnection substrate (10) to form a power path; and there is no overlapping area between the drive path and the power path in space.

2. The MOSFET power semiconductor module according to claim 1, characterized in that: The signal connection element (8) comprises: Connecting the upper bridge gate signal copper layer (6-a1) of the substrate and the upper bridge gate binding wire (8-a1) of the MOSFET power chip (7); A lower bridge gate binding wire (8-a2) connecting the lower bridge gate signal copper layer (6-a2) of the substrate and the lower bridge gate of the MOSFET power chip (7); An upper bridge source binding wire (8-b1) connecting the upper bridge source signal copper layer (6-b1) of the substrate and the upper bridge source of the MOSFET power chip (7); A lower bridge source binding wire (8-b2) is connected between the lower bridge source signal copper layer (6-b2) of the substrate and the lower bridge source of the MOSFET power chip (7).

3. The MOSFET power semiconductor module according to claim 2, characterized in that: The driving path includes a gate path, the gate path includes an upper bridge gate path and a lower bridge gate path, and the upper bridge gate path and the lower bridge gate path are symmetrically arranged at 180° with the center as the origin; The upper bridge gate path extends from the upper bridge arm gate signal terminal (11) through the upper bridge gate signal copper layer (6-a1) of the substrate and the upper bridge gate binding wire (8-a1) to the gate region of the MOSFET power chip (7) in the upper bridge chipset; The lower bridge gate path extends from the lower bridge arm gate signal terminal (2) through the substrate lower bridge gate signal copper layer (6-a2), the lower bridge gate binding wire (8-a2) to the gate region of the MOSFET power chip (7) in the lower bridge chipset.

4. The MOSFET power semiconductor module according to claim 3, characterized in that: The driving path also includes a source path, the source path includes an upper bridge source path and a lower bridge source path, and the upper bridge source path and the lower bridge source path are symmetrically arranged at 180° with the center as the origin; The upper bridge source path extends from the upper bridge arm source signal terminal (12) through the upper bridge source signal copper layer (6-b1) of the substrate and the upper bridge source binding wire (8-b1) to the Kelvin source region of the MOSFET power chip (7) in the upper bridge chipset; The lower bridge source path runs from the lower bridge arm source signal terminal (3) through the substrate lower bridge source signal copper layer (6-b2), the lower bridge source binding wire (8-b2) to the Kelvin source region of the MOSFET power chip (7) in the lower bridge chipset.

5. The MOSFET power semiconductor module according to claim 1, characterized in that: The interconnection padding layer (9) comprises an upper bridge source power interconnection padding layer (9-a) arranged on each upper bridge chipset, two upper and lower bridge power interconnection padding layers (9-b) arranged on the lower bridge drain power copper layer (6-d) of the substrate, lower bridge source power interconnection padding layers (9-c) respectively arranged on each lower bridge chipset, and four lower bridge and DC negative electrode interconnection padding layers (9-d) arranged on the substrate power negative electrode copper layer (6-e); The interconnection substrate (10) comprises an interconnection copper layer (10-b), an insulating ceramic sheet (10-a) and a signal shielding copper layer (10-c) which are arranged in sequence and overlap each other; the interconnection copper layer (10-b) is divided into a first part (10-b1) which can cover all lower bridge source power interconnection padding layers (9-c) and all lower bridge and DC negative pole interconnection padding layers (9-d), and a second part (10-b2) which can cover all upper bridge source power interconnection padding layers (9-a) and all upper and lower bridge power interconnection padding layers (9-b).

6. The MOSFET power semiconductor module according to claim 2, characterized in that: The power path is from the DC positive power electrode terminal (5) through the upper bridge drain power copper layer (6-c) of the substrate, the upper bridge chipset, the upper bridge source power interconnection padding layer (9-a), the second part (10-b2) of the interconnection copper layer (10-b), the upper and lower bridge power interconnection padding layer (9-b), the substrate lower bridge drain power copper layer (6-d), the lower bridge chipset, the lower bridge source power interconnection padding layer (9-c), the first part (10-b1) of the interconnection copper layer (10-b), the lower bridge and DC negative interconnection padding layer (9-d), and the substrate power negative copper layer (6-e) to the DC negative power electrode terminal (4).

7. The MOSFET power semiconductor module according to claim 1, characterized in that: The upper bridge chipset comprises four MOSFET power chips (7), which are arranged in sequence and at intervals on the upper bridge drain power copper layer (6-c) of the substrate; The lower bridge chipset comprises four MOSFET power chips (7), which are arranged in sequence and at intervals on the lower bridge drain power copper layer (6-d) of the substrate.

8. The MOSFET power semiconductor module according to claim 1, characterized in that: The substrate bridge gate signal copper layer (6-a1), the substrate bridge source signal copper layer (6-b1) and the substrate bridge drain power copper layer (6-c) are all arranged on one side of the substrate (6) and extend along the length direction of the substrate (6); The substrate lower bridge gate signal copper layer (6-a2), the substrate lower bridge source signal copper layer (6-b2) and the substrate lower bridge drain power copper layer (6-d) are all arranged on the other side of the substrate (6) and extend along the length direction of the substrate (6).

9. A motor controller, characterized in that: A MOSFET power semiconductor module as claimed in any one of claims 1 to 8 is used.

10. An automobile, characterized in that: The motor controller as claimed in claim 9 is used.

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