MOSFET power semiconductor modules, motor controllers and automobiles

Abstract

This invention relates to a MOSFET power semiconductor module, a motor controller, and an automobile, comprising a substrate, multiple power electrode terminals, multiple signal terminals, an upper-bridge chipset, a lower-bridge chipset, signal connectors, interconnect layers, and an interconnect substrate. The substrate has a signal copper layer region, a chipset region, and a substrate power copper layer region. The multiple power electrode terminals include a DC negative power electrode terminal, a DC positive power electrode terminal, and an output power electrode terminal. Each signal terminal is connected to a driving region on a silicon-based IGBT power chip in the upper-bridge and lower-bridge chipsets via a corresponding signal connector to form a driving path. The DC positive power electrode terminal is connected to the DC negative power electrode terminal via the power copper layer on the substrate, the chipset, the interconnect layers, and the interconnect substrate to form a power path. This invention solves the problems of high electromagnetic interference and inconsistent dynamic and static current sharing.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor module technology, specifically to a MOSFET power semiconductor module, a motor controller, and an automobile. Background Technology

[0002] Currently, mainstream power semiconductor module structures typically consist of power chips, copper-clad ceramic substrates, interconnect copper busbars or bonding wires, power terminals, signal terminals, epoxy molding compound or frame plastic housing, and various solders. This structure uses precise soldering processes to tightly connect the various components, forming a highly integrated power conversion unit. However, in existing technologies, especially in power module designs employing four or more parallel configurations, some inherent technical challenges exist.

[0003] like Figure 1 and Figure 2 As shown, in a traditional quad-parallel power module, the power chips are positioned in the upper and lower parts along the long side of the substrate. The chip layout on the bridge arms of the quad-parallel scheme is rectangular. The power path (high-current path) is as follows: from the DC positive power electrode terminal 5, through the upper bridge drain power copper layer 19-a, the upper bridge chipset, the upper bridge source power interconnect copper bus 20-a, the upper and lower bridge power interconnect copper layers 19-c (lower bridge drain power copper layer) on the second substrate, the upper and lower bridge interconnect copper bus 20-b, the upper and lower bridge power interconnect copper layers 19-b (lower bridge drain power copper layer) on the first substrate, the lower bridge chipset, the lower bridge source power interconnect copper bus 20-c, and the substrate power negative copper layer 19-d to the DC negative power electrode terminal 4. This layout has the following problems:

[0004] 1. Because the power paths of the upper and lower bridges have a vertically overlapping area in space, when the module is operating in the dead zone transient state, the commutation paths of the upper and lower bridges will generate a strong magnetic field coupling effect in this area, which will then form electromagnetic interference.

[0005] 2. The vertically intersecting area between the lower bridge drive path and the power path can also cause problems. The magnetic field generated by the large current in the power path can interfere with the signal in the drive path, causing signal oscillation, which in turn increases the module's losses and reduces the consistency of dynamic and static current sharing. This not only reduces the module's efficiency but may also affect the module's stable operation.

[0006] 3. Due to the significant differences in parasitic resistance and inductance between the upper and lower bridge drive paths, the peripheral circuits of the upper and lower bridges will have substantial design differences. These differences will further affect the consistency of the upper and lower bridge signals, making it difficult for the module to achieve the desired control effect during operation.

[0007] Therefore, it is necessary to develop a new MOSFET power semiconductor module, motor controller, and automobile. Summary of the Invention

[0008] The purpose of this invention is to provide a MOSFET power semiconductor module, a motor controller, and an automobile to solve the problems of high electromagnetic interference and inconsistent dynamic and static current sharing.

[0009] In a first aspect, the MOSFET power semiconductor module of the present invention includes:

[0010] A substrate having an upper bridge chip assembly region, a substrate power negative electrode copper layer, and a lower bridge chip assembly region sequentially arranged from one side to the other. The upper bridge chip assembly region includes a substrate upper bridge gate signal copper layer, a substrate upper bridge source signal copper layer, and a substrate upper bridge drain power copper layer. The lower bridge chip assembly region includes a substrate lower bridge gate signal copper layer, a substrate lower bridge source signal copper layer, and a substrate lower bridge drain power copper layer.

[0011] Multiple power electrode terminals, including a DC negative power electrode terminal, a DC positive power electrode terminal, and an output power electrode terminal, which are respectively connected to the substrate power negative electrode copper layer, the substrate upper bridge drain power copper layer, and the substrate lower bridge drain power copper layer.

[0012] Multiple signal terminals, including an upper bridge arm gate signal terminal, an upper bridge arm source signal terminal, a lower bridge arm gate signal terminal, and a lower bridge arm source signal terminal, which are respectively connected to the upper bridge gate signal copper layer, the upper bridge source signal copper layer, the lower bridge gate signal copper layer, and the lower bridge source signal copper layer on the substrate.

[0013] The bridge chipset includes multiple MOSFET power chips respectively disposed on the power copper layer of the bridge drain on the substrate;

[0014] The lower bridge chipset includes multiple MOSFET power chips respectively disposed on the power copper layer of the lower bridge drain on the substrate;

[0015] Signal connectors are used to connect the upper bridge gate signal copper layer, the upper bridge source signal copper layer, the lower bridge gate signal copper layer, and the lower bridge source signal copper layer on the substrate to the driving area of ​​the corresponding MOSFET power chip.

[0016] The interconnect pad is disposed on the upper bridge chipset region, the lower bridge chipset region and the substrate power negative electrode copper layer;

[0017] An interconnect substrate is disposed on the higher layer of the interconnect pad;

[0018] The upper bridge arm gate signal terminal, upper bridge arm source signal terminal, lower bridge arm gate signal terminal, and lower bridge arm source signal terminal are respectively connected to the driving areas of the MOSFET power chips in the upper bridge chipset and the lower bridge chipset through corresponding signal connectors to form a driving path; the DC positive power electrode terminal is respectively connected to the DC negative power electrode terminal through the power copper layer, chipset, interconnect pad layer, and interconnect substrate on the substrate to form a power path; and the driving path and the power path have no overlapping areas in space.

[0019] Optionally, the signal connector includes:

[0020] Connecting the upper gate signal copper layer of the substrate to the upper gate of the MOSFET power chip;

[0021] Connecting the lower bridge gate signal copper layer of the substrate and the lower bridge gate of the MOSFET power chip;

[0022] The upper bridge source signal copper layer on the substrate connects the upper bridge source of the MOSFET power chip via a bonding wire.

[0023] The lower bridge source signal copper layer of the substrate connects the lower bridge source of the MOSFET power chip via a bonding wire.

[0024] Optionally, the driving path includes a gate path, which includes an upper bridge gate path and a lower bridge gate path, and the upper bridge gate path and the lower bridge gate path are symmetrically arranged at 180° with the center as the origin.

[0025] The upper bridge gate path extends from the upper bridge arm gate signal terminal through the upper bridge gate signal copper layer on the substrate and the upper bridge gate bonding wire to the gate region of the MOSFET power chip in the upper bridge chipset.

[0026] The lower bridge gate path extends from the lower bridge arm gate signal terminal through the lower bridge gate signal copper layer on the substrate and the lower bridge gate bonding wire to the gate region of the MOSFET power chip in the lower bridge chipset.

[0027] Optionally, the drive path further includes a source path, which includes an upper bridge source path and a lower bridge source path, and the upper bridge source path and the lower bridge source path are symmetrically arranged at 180° with the center as the origin.

[0028] The upper bridge source path runs from the upper bridge arm source signal terminal through the upper bridge source signal copper layer on the substrate and the upper bridge source bonding wire to the Kelvin source region of the MOSFET power chip in the upper bridge chipset.

[0029] The lower bridge source path runs from the lower bridge arm source signal terminal through the lower bridge source signal copper layer on the substrate and the lower bridge source bonding wire to the Kelvin source region of the MOSFET power chip in the lower bridge chipset.

[0030] Optionally, the interconnect pad high layer includes an upper bridge source power interconnect pad high layer disposed on each upper bridge chip group, two upper and lower bridge power interconnect pad high layers disposed on the lower bridge drain power copper layer of the substrate, lower bridge source power interconnect pad high layers disposed on each lower bridge chip group, and four lower bridge and DC negative interconnect pad high layers disposed on the power negative copper layer of the substrate.

[0031] The interconnect substrate includes interconnect copper layers, insulating ceramic sheets and signal shielding copper layers stacked in sequence. The interconnect copper layers are divided into a first part that covers all the lower bridge source power interconnect pads and all the lower bridge and DC negative interconnect pads, and a second part that covers all the upper bridge source power interconnect pads and all the upper and lower bridge power interconnect pads.

[0032] Optionally, the power path extends from the DC positive power electrode terminal through the upper bridge drain power copper layer on the substrate, the upper bridge chipset, the upper bridge source power interconnect pad layer, the second part of the interconnect substrate, the upper and lower bridge power interconnect pad layers, the lower bridge drain power copper layer on the substrate, the lower bridge chipset, the lower bridge source power interconnect pad layer, the first part of the lower bridge source power interconnect copper layer on the interconnect substrate, the lower bridge and DC negative interconnect pad layers, and the substrate power negative copper layer to the DC negative power electrode terminal.

[0033] Optionally, the upper bridge chipset includes four MOSFET power chips, which are respectively disposed at intervals on the upper bridge drain power copper layer of the substrate;

[0034] The lower bridge chipset includes four MOSFET power chips, which are sequentially and spaced apart on the lower bridge drain power copper layer of the substrate.

[0035] Optionally, the bridge gate signal copper layer, the bridge source signal copper layer, and the bridge drain power copper layer on the substrate are all disposed on one side of the substrate and extend along the length direction of the substrate.

[0036] The substrate lower bridge gate signal copper layer, substrate lower bridge source signal copper layer and substrate lower bridge drain power copper layer are all disposed on the other side of the substrate and extend along the length direction of the substrate.

[0037] Secondly, the motor controller described in this invention employs a MOSFET power semiconductor module as described in this invention.

[0038] Thirdly, the automobile described in this invention employs a motor controller as described in this invention.

[0039] The beneficial effects of this invention are:

[0040] 1. This invention significantly reduces the inductance problem caused by excessively long power paths by optimizing the layout of components within the module, reducing cross-interference between signal and power busbars, and improving electrical stability. System inductance simulation results show that, compared to 7.6nH in existing four-parallel power modules, the inductance of this invention is reduced to 4.8nH, a reduction of 2.8nH. This helps improve the electromagnetic compatibility, switching efficiency, system stability, overall performance of the power module, and reduces power module losses, particularly demonstrating superior performance in hybrid electric vehicles, range-extended electric vehicles, and construction machinery.

[0041] 2. The driving paths of the upper and lower bridges in this invention adopt a 180° symmetrical design with the center as the origin, making the upper and lower gate-source paths basically consistent and reducing the difference in driving parasitic parameters. Regarding the parasitic inductance of the driving path: In existing solutions with four parallel power modules, due to the complexity of the upper and lower bridge circuits and the need for bonding wires for connection, the overall system has greater electromagnetic interference. Simulation of the driving path inductance of the upper and lower bridges at 1GHz shows that the gate-source parasitic inductances of the upper and lower bridges are 34.7nH and 54nH, respectively, with an inductance imbalance of 21.76%. Simulation of the parasitic inductance of the driving path of the upper and lower bridges in this invention at 1GHz shows that the parasitic inductances of the upper and lower bridges are 12.33nH and 12.35nH, respectively, with an inductance imbalance of only 0.1%, far lower than the 21.76% of the existing solutions. Regarding the parasitic resistance of the gate-source path: In existing quad-parallel power modules, simulations at 1Hz show parasitic resistances of 44.6mΩ and 77.7mΩ for the upper and lower bridge gate-source paths, respectively, with a resistance imbalance of 27.06%. In contrast, simulations at 1Hz show parasitic resistances of 3.55mΩ and 3.56mΩ for the upper and lower bridge gate-source paths, respectively, with a resistance imbalance of only 0.14%, significantly lower than the 27.06% of existing solutions. Compared to existing quad-parallel power modules, this invention offers a significant improvement in gate-source path parasitic inductance. After inductance optimization, the gate drive signal of the power module is more stable, resulting in better performance stability. A significant improvement is also seen in loop resistance, further reducing the impact of the power loop on the drive loop and greatly enhancing the system stability of the power module.

[0042] 3. In this invention, the drive path and power path have no spatial overlap, effectively reducing gate switching oscillations caused by mutual electromagnetic interference. Simulations of the mutual inductance between the gates and power paths of the upper and lower bridges at 1 GHz show that the mutual inductance between the upper bridge and the power path is only 0.47 nH, and the mutual inductance between the lower bridge and the power path is only 0.68 nH, with a mutual inductance imbalance of 18.26%. Compared to the existing four-parallel power module, which is more complex and has gate bonding lines crossing over the power loop, simulations of the mutual inductance between the gates and power loops of the upper and lower bridges at 1 GHz show mutual inductances of 1.92 nH and 10.2 nH, respectively, with a mutual inductance imbalance of 68.32%. These findings demonstrate that this invention effectively reduces the mutual inductance between the drive path and the power path, thus reducing the impact of the power path on the drive path and improving the system stability of the module. Simultaneously, the reduced impact on the drive loop helps reduce power module losses and significantly improves the overall efficiency of the power module.

[0043] 4. The power path converter circuit of the present invention is simpler, resulting in a faster converter speed.

[0044] 5. In the MOSFET power semiconductor module, the spatial structure formed by the interconnect pad layers and interconnect substrate allows current to flow in multiple directions. Specifically, when current in the power path passes through the interconnect pad layers, interconnect substrate, chip, and substrate, they form paths with the same current magnitude but flowing in opposite directions. The magnetic fields generated by these reverse current paths cancel each other out, thereby reducing stray inductance throughout the circuit, lowering switching losses, reducing turn-off spikes, and significantly improving the performance of the power module. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the structure of an existing four-parallel power module;

[0046] Figure 2 This is a schematic diagram of the drive path and power path in an existing four-parallel power module;

[0047] Figure 3 This is a schematic diagram of the MOSFET power semiconductor module described in the embodiments of this application;

[0048] Figure 4 This is a schematic diagram of the substrate structure in an embodiment of this application;

[0049] Figure 5 This is a schematic diagram of the interconnect substrate structure in an embodiment of this application;

[0050] Figure 6 This is a schematic diagram of the interconnect copper layer structure in an embodiment of this application;

[0051] Figure 7 This is a schematic diagram showing the distribution of the upper bridge chipset and the lower bridge chipset in an embodiment of this application;

[0052] Figure 8 This is a schematic diagram of the structure of the MOSFET power semiconductor module (excluding interconnect pads and interconnect substrate) described in the embodiments of this application;

[0053] Figure 9 This is a schematic diagram of the MOSFET power semiconductor module (excluding the interconnect substrate) described in the embodiments of this application;

[0054] Figure 10 This is a schematic diagram of the driving path and the driving path in the embodiments of this application;

[0055] Figure 11 This is a schematic diagram of the MOSFET power semiconductor module (with heat dissipation structure) described in the embodiments of this application;

[0056] In the diagram: 1. Temperature sensor; 2. Lower bridge arm gate signal terminal; 3. Lower bridge arm source signal terminal; 4. DC negative power electrode terminal; 5. DC positive power electrode terminal; 6. Substrate; 6-a1. Upper bridge gate signal copper layer on the substrate; 6-a2. Lower bridge gate signal copper layer on the substrate; 6-b1. Upper bridge source signal copper layer on the substrate; 6-b2. Lower bridge source signal copper layer on the substrate; 6-c. Upper bridge drain power copper layer on the substrate; 6-d. Lower bridge drain power copper layer on the substrate; 6-e. Power negative copper layer on the substrate; 7. MOSFET power chip; 8. Signal connectors; 8-a1. Upper bridge gate bonding wire; 8-a2. Lower bridge gate bonding wire; 8-b1. Upper bridge source bonding wire; 8-b2. Lower bridge source bonding wire; 9. Interconnect pad layer; 9-a. Upper bridge source power interconnect pad layer; 9-b 9-c, Upper and lower bridge power interconnect layers; 9-d, Lower bridge source power interconnect layer; 10-Interconnect substrate; 10-a, Insulating ceramic sheet; 10-b, Interconnect copper layer; 10-b1, First part; 10-b2, Second part; 10-c, Signal shielding copper layer. 11. Upper bridge arm gate signal terminal; 12. Upper bridge arm source signal terminal; 13. Upper bridge arm drain signal terminal; 14. Output power electrode terminal; 15. Power chip area; 16. Power path; 17. Drive path; 18. Heat dissipation structure; 19-a. Upper bridge drain power copper layer on substrate; 19-b. Upper and lower bridge power interconnect copper layers on the first substrate; 19-c. Upper and lower bridge power interconnect copper layers on the second substrate; 19-d. Substrate power negative electrode copper layer; 20-a. Upper bridge source power interconnect copper busbar; 20-b. Upper and lower bridge interconnect copper busbar; 20-c. Lower bridge source power interconnect copper busbar.

[0057] The arrows in the diagram indicate the direction of current flow. Detailed Implementation

[0058] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0059] like Figure 3 As shown in the embodiment of this application, a MOSFET power semiconductor module includes a substrate 6, and a plurality of power electrode terminals, a plurality of signal terminals, an upper bridge chipset, a lower bridge chipset, a signal connector 8, an interconnect pad layer 9, and an interconnect substrate 10 disposed on the substrate 6.

[0060] like Figure 3 As shown in the embodiment of this application, the substrate 6 is provided with an upper bridge chip group region, a substrate power negative electrode copper layer 6-e, and a lower bridge chip group region from one side to the other. The upper bridge chip group region includes a substrate upper bridge gate signal copper layer 6-a1, a substrate upper bridge source signal copper layer 6-b1, and a substrate upper bridge drain power copper layer 6-c. The lower bridge chip group region includes a substrate lower bridge gate signal copper layer 6-a2, a substrate lower bridge source signal copper layer 6-b2, and a substrate lower bridge drain power copper layer 6-d.

[0061] like Figure 3 As shown in the embodiments of this application, the plurality of power electrode terminals include a DC negative power electrode terminal 4, a DC positive power electrode terminal 5, and an output power electrode terminal 14, which are respectively connected to the substrate power negative copper layer 6-e, the substrate upper bridge drain power copper layer 6-c, and the substrate lower bridge drain power copper layer 6-d.

[0062] like Figure 3 As shown in the embodiment of this application, the plurality of signal terminals include an upper bridge arm gate signal terminal 11, an upper bridge arm source signal terminal 12, a lower bridge arm gate signal terminal 2, and a lower bridge arm source signal terminal 3, which are respectively connected to the upper bridge gate signal copper layer 6-a1, the upper bridge source signal copper layer 6-b1, the lower bridge gate signal copper layer 6-a2, and the lower bridge source signal copper layer 6-b2 on the substrate.

[0063] like Figure 3 As shown in the embodiment of this application, the upper bridge chipset includes multiple MOSFET power chips 7 respectively disposed on the upper bridge drain power copper layer 6-c of the substrate.

[0064] like Figure 3As shown in the embodiments of this application, the lower bridge chipset includes multiple MOSFET power chips 7 (e.g., silicon carbide-based MOSFET power chips) respectively disposed on the lower bridge drain power copper layer 6-d of the substrate.

[0065] like Figure 3 As shown in the embodiment of this application, the signal connector 8 is used to connect the upper bridge gate signal copper layer 6-a1, the upper bridge source signal copper layer 6-b1, the lower bridge gate signal copper layer 6-a2, and the lower bridge source signal copper layer 6-b2 of the substrate to the driving area of ​​the corresponding MOSFET power chip 7.

[0066] like Figure 3 As shown in the embodiment of this application, the interconnect pad layer 9 is disposed on the upper bridge chipset region, the lower bridge chipset region, and the substrate power negative electrode copper layer 6-e.

[0067] like Figure 3 As shown in the embodiment of this application, the interconnect substrate 10 is disposed on the interconnect pad layer 9.

[0068] In this embodiment, the upper bridge arm gate signal terminal 11, the upper bridge arm source signal terminal 12, the lower bridge arm gate signal terminal 2, and the lower bridge arm source signal terminal 3 are respectively connected to the driving regions of the MOSFET power chips 7 in the upper and lower bridge chipsets through corresponding signal connectors 8 to form driving paths; the DC positive power electrode terminal 5 is respectively connected to the DC negative power electrode terminal 4 through the power copper layer, chipset, interconnect pad layer 9, and interconnect substrate 10 on the substrate 6 to form power paths; and the driving paths and power paths have no overlapping areas in space.

[0069] like Figure 4 As shown, in one possible embodiment, the upper bridge gate signal copper layer 6-a1, the upper bridge source signal copper layer 6-b1, and the upper bridge drain power copper layer 6-c are all disposed on the right side of the substrate 6 and extend along the length direction of the substrate 6. The lower bridge gate signal copper layer 6-a2, the lower bridge source signal copper layer 6-b2, and the lower bridge drain power copper layer 6-d are all disposed on the left side of the substrate 6 and extend along the length direction of the substrate 6. The substrate power negative copper layer 6-e is disposed in the region between the upper bridge drain power copper layer 6-c and the lower bridge drain power copper layer 6-d.

[0070] like Figure 3 As shown, in one possible embodiment, the temperature sensor 1 is disposed at the lower left corner of the substrate 6.

[0071] like Figure 3 and Figure 4As shown, in one possible embodiment, one end of the lower bridge arm gate signal terminal 2 is connected to the lower bridge gate signal copper layer 6-a2 of the substrate. One end of the lower bridge arm source signal terminal 3 is connected to the lower bridge source signal copper layer 6-b2 of the substrate. One end of the DC negative power electrode terminal 4 is connected to the power negative copper layer 6-e of the substrate. One end of the DC positive power electrode terminal 5 is connected to the upper bridge drain power copper layer 6-c of the substrate. Furthermore, the lower bridge arm gate signal terminal 2, the lower bridge arm source signal terminal 3, the DC negative power electrode terminal 4, and the DC positive power electrode terminal 5 are all located at the first end of the substrate 6.

[0072] like Figure 8 As shown, in one possible embodiment, the upper bridge chipset includes four MOSFET power chips 7, which are sequentially and spaced apart on the upper bridge drain power copper layer 6-c of the substrate. The lower bridge chipset includes four MOSFET power chips 7, which are sequentially and spaced apart on the lower bridge drain power copper layer 6-d of the substrate.

[0073] like Figure 8 As shown, in one possible embodiment, the signal connector 8 includes an upper bridge gate bonding wire 8-a1 connecting the upper bridge gate signal copper layer 6-a1 of the substrate and the MOSFET power chip 7, a lower bridge gate bonding wire 8-a2 connecting the lower bridge gate signal copper layer 6-a2 of the substrate and the MOSFET power chip 7, an upper bridge source bonding wire 8-b1 connecting the upper bridge source signal copper layer 6-b1 of the substrate and the MOSFET power chip 7, and a lower bridge source bonding wire 8-b2 connecting the lower bridge source signal copper layer 6-b2 of the substrate and the MOSFET power chip 7.

[0074] like Figure 9 As shown, in one possible embodiment, the interconnect layer 9 includes an upper bridge source power interconnect layer 9-a disposed on each upper bridge chip group, two upper and lower bridge power interconnect layers 9-b disposed on the lower bridge drain power copper layer 6-d of the substrate, a lower bridge source power interconnect layer 9-c disposed on each lower bridge chip group, and four lower bridge and DC negative interconnect layers 9-d disposed on the power negative copper layer 6-e of the substrate.

[0075] like Figure 5 , Figure 6 and Figure 10 As shown, in one possible embodiment, the interconnect substrate 10 includes an interconnect copper layer 10-b, an insulating ceramic sheet 10-a, and a signal shielding copper layer 10-c, which are sequentially stacked. The interconnect copper layer 10-b includes a first portion 10-b1 and a second portion 10-b2. The first portion 10-b1 covers all the lower bridge source power interconnect pad layers 9-c and all the lower bridge and DC negative interconnect pad layers 9-d; the second portion 10-b2 covers all the upper bridge source power interconnect pad layers 9-a and all the upper and lower bridge power interconnect pad layers 9-b.

[0076] like Figure 4 As shown, in one possible embodiment, one end of the upper bridge arm gate signal terminal 11 is connected to the upper bridge gate signal copper layer 6-a1 on the substrate. One end of the upper bridge arm source signal terminal 12 is connected to the upper bridge source signal copper layer 6-b1 on the substrate. One end of the upper bridge arm drain signal terminal 13 is connected to the upper bridge drain power copper layer 6-c on the substrate. One end of the output power electrode terminal 14 is connected to the lower bridge drain power copper layer 6-d on the substrate. Furthermore, the upper bridge arm gate signal terminal 11, upper bridge arm source signal terminal 12, upper bridge arm drain signal terminal 13, and output power electrode terminal 14 are all located at the second end of the substrate 6.

[0077] like Figure 8 and Figure 10 As shown in this embodiment, in the MOSFET power semiconductor module, the driving path 17 (the driving path is the chip control signal path, generally a small current) includes a gate path and a source path. The gate path includes an upper bridge gate path and a lower bridge gate path, which are symmetrically arranged at 180° with the center as the origin. The source path includes an upper bridge source path and a lower bridge source path, which are symmetrically arranged at 180° with the center as the origin. The specific details of each path are as follows:

[0078] Upper bridge gate path: from the upper bridge arm gate signal terminal 11 through the upper bridge gate signal copper layer 6-a1 on the substrate and the upper bridge gate binding wire 8-a1 to the gate region of the MOSFET power chip 7 in the upper bridge chipset.

[0079] Upper bridge source path: from the upper bridge arm source signal terminal 12 through the upper bridge source signal copper layer 6-b1 on the substrate and the upper bridge source binding wire 8-b1 to the Kelvin source region of the MOSFET power chip 7 in the upper bridge chipset.

[0080] Lower bridge gate path: from the lower bridge arm gate signal terminal 2 through the lower bridge gate signal copper layer 6-a2 on the substrate and the lower bridge gate bonding wire 8-a2 to the gate region of the MOSFET power chip 7 in the lower bridge chipset.

[0081] Lower bridge source path: from the source signal terminal 3 through the lower bridge source signal copper layer 6-b2 on the substrate and the lower bridge source bonding wire 8-b2 to the Kelvin source region of the MOSFET power chip 7 in the lower bridge chipset.

[0082] In this embodiment, the upper bridge gate path, upper bridge source path, lower bridge gate path, and lower bridge source path are basically the same, which reduces the difference in driving parasitic parameters.

[0083] like Figure 9 and 10As shown in this embodiment, the power path 16 (high current path) in the MOSFET power semiconductor module is as follows:

[0084] From the DC positive power electrode terminal 5, through the upper bridge drain power copper layer 6-c, upper bridge chipset, upper bridge source power interconnect layer 9-a, the second part 10-b2 of interconnect copper layer 10-b, upper and lower bridge power interconnect layer 9-b (i.e. lower bridge drain power interconnect layer), lower bridge drain power copper layer 6-d, lower bridge chipset, lower bridge source power interconnect layer 9-c, the first part 10-b1 of interconnect copper layer 10-b, lower bridge and DC negative interconnect layer 9-d, and the substrate power negative copper layer 6-e to the DC negative power electrode terminal 4.

[0085] In this embodiment, the drive path and power path have no spatial overlap area, which greatly reduces gate switching oscillation caused by mutual electromagnetic interference.

[0086] In this embodiment, the commutation loop in the power path is significantly reduced compared to existing solutions. For example, the power path at the chip drain or drain front end, and the power interconnection path between the upper and lower bridges are reduced, resulting in faster commutation. Simultaneously, when the upper and lower bridges are interconnected on the upper substrate, the current paths exhibit reverse cancellation (the number of "opposite current paths" increases throughout the power path, and the magnetic fields generated by opposite currents cancel each other out), thereby reducing loop inductance, lowering switching losses, reducing turn-off spikes, and significantly improving module performance.

[0087] In this embodiment, the MOSFET power chip 7 is interconnected with the substrate 6 by soldering with soldering material. The temperature sensor 1, lower bridge arm gate signal terminal 2, lower bridge arm source signal terminal 3, DC negative power electrode terminal 4, DC positive power electrode terminal 5, upper bridge arm gate signal terminal 11, upper bridge arm source signal terminal 12, upper bridge arm drain signal terminal 13, and output power electrode terminal 14 are electrically interconnected with the substrate 6 by soldering with soldering material. The gate / source signals of the MOSFET power chip 7 are interconnected with the gate / source terminals via gate / source signal bonding lines. The electrical interconnection between the upper and lower bridge arms of the MOSFET power chip 7 is achieved through interconnect pad layers 9 and the interconnect substrate 10. The MOSFET power chip 7 is interconnected with the interconnect pad layers 9 by soldering with soldering material. The interconnect pad layers 9 and the interconnect substrate 10 are interconnected by soldering with soldering material.

[0088] In one possible embodiment, the lower bridge arm gate signal terminal 2, the lower bridge arm source signal terminal 3, the DC negative power electrode terminal 4, the DC positive power electrode terminal 5, the upper bridge arm gate signal terminal 11, the upper bridge arm source signal terminal 12, the upper bridge arm drain signal terminal 13, and the output power electrode terminal 14 are distributed around the substrate 6 and satisfy a certain electrical clearance.

[0089] In one possible embodiment, when the interconnect pad layer 9 is electrically connected to the interconnect substrate 10, it is connected to the interconnect copper layer 10-b of the interconnect substrate 10.

[0090] like Figure 7 As shown, in one possible embodiment, all components must meet electrical clearance and creepage distance requirements when interconnected. Signal connector 8 must meet electrical clearance requirements when bonded. Various portions of the power chip region 15 must meet electrical clearance and creepage distance requirements.

[0091] like Figure 11 As shown, in one possible embodiment, in order to ensure good heat dissipation of the MOSFET power semiconductor module, a heat dissipation structure 18 is provided on the back of the MOSFET power semiconductor module.

[0092] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A MOSFET power semiconductor module, characterized by, The application relates to a power module, comprising: a substrate (6) provided with an upper bridge chip set area, a substrate power negative copper layer (6-e) and a lower bridge chip set area from one side to the other side in sequence, wherein the upper bridge chip set area comprises a substrate upper bridge gate signal copper layer (6-a1), a substrate upper bridge source signal copper layer (6-b1) and a substrate upper bridge drain power copper layer (6-c), and the lower bridge chip set area comprises a substrate lower bridge gate signal copper layer (6-a2), a substrate lower bridge source signal copper layer (6-b2) and a substrate lower bridge drain power copper layer (6-d); a plurality of power electrode terminals, comprising a direct-current negative power electrode terminal (4), a direct-current positive power electrode terminal (5) and an output power electrode terminal (14) connected with the substrate power negative copper layer (6-e), the substrate upper bridge drain power copper layer (6-c) and the substrate lower bridge drain power copper layer (6-d) respectively; a plurality of signal terminals, comprising an upper bridge arm gate signal terminal (11), an upper bridge arm source signal terminal (12), a lower bridge arm gate signal terminal (2) and a lower bridge arm source signal terminal (3) connected with the substrate upper bridge gate signal copper layer (6-a1), the substrate upper bridge source signal copper layer (6-b1), the substrate lower bridge gate signal copper layer (6-a2) and the substrate lower bridge source signal copper layer (6-b2) respectively; an upper bridge chip set comprising a plurality of MOSFET power chips (7) arranged on the substrate upper bridge drain power copper layer (6-c) respectively; a lower bridge chip set comprising a plurality of MOSFET power chips (7) arranged on the substrate lower bridge drain power copper layer (6-d) respectively; a signal connecting piece (8) for connecting the substrate upper bridge gate signal copper layer (6-a1), the substrate upper bridge source signal copper layer (6-b1), the substrate lower bridge gate signal copper layer (6-a2) and the substrate lower bridge source signal copper layer (6-b2) with the driving areas of the corresponding MOSFET power chips (7); an interconnection pad high layer (9) arranged on the upper bridge chip set area, the lower bridge chip set area and the substrate power negative copper layer (6-e); an interconnection substrate (10) arranged on the interconnection pad high layer (9); wherein the upper bridge arm gate signal terminal (11), the upper bridge arm source signal terminal (12), the lower bridge arm gate signal terminal (2) and the lower bridge arm source signal terminal (3) are connected with the driving areas of the MOSFET power chips (7) in the upper bridge chip set and the lower bridge chip set through corresponding signal connecting pieces (8) to form driving paths; the direct-current positive power electrode terminal (5) is connected with the direct-current negative power electrode terminal (4) through the power copper layer on the substrate (6), the chip set, the interconnection pad high layer (9) and the interconnection substrate (10) to form a power path; and the driving paths and the power path have no cross-over and re-pasting areas in space.

2. The MOSFET power semiconductor module according to claim 1, characterized in that The signal connecting piece (8) comprises: an upper bridge gate binding wire (8-a1) connecting the substrate upper bridge gate signal copper layer (6-a1) and the MOSFET power chip (7). The lower bridge gate signal copper layer (6-a2) of the connection substrate is connected with the lower bridge gate bonding wire (8-a2) of the MOSFET power chip (7); The upper bridge source signal copper layer (6-b1) of the connection substrate is connected with the upper bridge source bonding wire (8-b1) of the MOSFET power chip (7); The lower bridge source signal copper layer (6-b2) of the connection substrate is connected with the lower bridge source bonding wire (8-b2) of the MOSFET power chip (7).

3. The MOSFET power semiconductor module according to claim 2, characterized in that The driving path comprises a gate path, and the gate path comprises an upper bridge gate path and a lower bridge gate path, and the upper bridge gate path and the lower bridge gate path are symmetrically arranged at 180° with the center as the origin; The upper bridge gate path is from the upper bridge arm gate signal terminal (11) to the gate region of the MOSFET power chip (7) in the upper bridge chip set through the upper bridge gate signal copper layer (6-a1) of the substrate, the upper bridge gate bonding wire (8-a1); The lower bridge gate path is from the lower bridge arm gate signal terminal (2) to the gate region of the MOSFET power chip (7) in the lower bridge chip set through the lower bridge gate signal copper layer (6-a2) of the substrate, the lower bridge gate bonding wire (8-a2).

4. The MOSFET power semiconductor module according to claim 3, characterized in that The driving path further comprises a source path, and the source path comprises an upper bridge source path and a lower bridge source path, and the upper bridge source path and the lower bridge source path are symmetrically arranged at 180° with the center as the origin; The upper bridge source path is from the upper bridge arm source signal terminal (12) to the Kelvin source region of the MOSFET power chip (7) in the upper bridge chip set through the upper bridge source signal copper layer (6-b1) of the substrate, the upper bridge source bonding wire (8-b1); The lower bridge source path is from the lower bridge arm source signal terminal (3) to the Kelvin source region of the MOSFET power chip (7) in the lower bridge chip set through the lower bridge source signal copper layer (6-b2) of the substrate, the lower bridge source bonding wire (8-b2).

5. The MOSFET power semiconductor module according to claim 1, wherein The interconnection pad high layer (9) comprises an upper bridge source power interconnection pad high layer (9-a) arranged on each upper bridge chip set, two upper and lower bridge power interconnection pad high layers (9-b) arranged on the lower bridge drain power copper layer (6-d) of the substrate, a lower bridge source power interconnection pad high layer (9-c) arranged on each lower bridge chip set, and four lower bridge and DC negative interconnection pad high layers (9-d) arranged on the power negative copper layer (6-e) of the substrate; The interconnection substrate (10) comprises an interconnection copper layer (10-b), an insulating ceramic sheet (10-a) and a signal shielding copper layer (10-c) arranged in sequence, the interconnection copper layer (10-b) is divided into a first part (10-b1) capable of covering all the lower bridge source power interconnection pad high layers (9-c) and all the lower bridge and DC negative interconnection pad high layers (9-d), and a second part (10-b2) capable of covering all the upper bridge source power interconnection pad high layers (9-a) and all the upper and lower bridge power interconnection pad high layers (9-b).

6. The MOSFET power semiconductor module of claim 2, wherein, The power path is from the DC positive power electrode terminal (5) through the upper bridge drain power copper layer (6-c) on the substrate, the upper bridge chip set, the upper bridge source power interconnection pad high layer (9-a), the second part (10-b2) of the interconnection copper layer (10-b), the upper and lower bridge power interconnection pad high layer (9-b), the lower bridge drain power copper layer (6-d) under the substrate, the lower bridge chip set, the lower bridge source power interconnection pad high layer (9-c), the first part (10-b1) of the interconnection copper layer (10-b), the lower bridge and DC negative interconnection pad high layer (9-d), the power negative copper layer (6-e) on the substrate to the DC negative power electrode terminal (4).

7. The MOSFET power semiconductor module of claim 1, wherein, The upper bridge chip set comprises four MOSFET power chips (7) arranged on the upper bridge drain power copper layer (6-c) on the substrate in sequence at intervals. The lower bridge chip set comprises four MOSFET power chips (7) arranged on the lower bridge drain power copper layer (6-d) on the substrate in sequence at intervals.

8. The MOSFET power semiconductor module of claim 1, wherein, The upper bridge gate signal copper layer (6-a1), the upper bridge source signal copper layer (6-b1) and the upper bridge drain power copper layer (6-c) on the substrate are arranged on one side of the substrate (6) and extend along the length direction of the substrate (6). The lower bridge gate signal copper layer (6-a2), the lower bridge source signal copper layer (6-b2) and the lower bridge drain power copper layer (6-d) on the substrate are arranged on the other side of the substrate (6) and extend along the length direction of the substrate (6).

9. An electric machine controller characterized by: The MOSFET power semiconductor module according to any one of claims 1 to 8 is adopted.

10. An automobile characterized by comprising: The motor controller according to claim 9 is adopted.

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