Semiconductor light-emitting structure and preparation method thereof

Abstract

The invention provides a semiconductor light-emitting structure and a preparation method thereof. The semiconductor light-emitting structure comprises a semiconductor substrate layer; a lower confinement layer on the semiconductor substrate layer; the lower waveguide layer, the active layer, the upper waveguide layer and the upper limiting layer are located on the side, away from the semiconductor substrate layer, of part of the lower limiting layer and stacked in sequence; the insulating epitaxial layer is positioned on one side, deviating from the semiconductor substrate layer, of part of the lower limiting layer and is positioned on two sides of the lower waveguide layer, the active layer, the upper waveguide layer and the upper limiting layer in the slow axis direction; the first isolation groove and the second isolation groove penetrate through the upper limiting layer from the insulating epitaxial layer on one side of the slow axis direction from the upper limiting layer along the slow axis direction and extend into the insulating epitaxial layer on the other side of the slow axis direction, and the first isolation groove is located on one side, deviating from the rear cavity surface, of the second isolation groove.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor light-emitting structure and a preparation method thereof. Background Art

[0002] Semiconductor light-emitting devices are devices that use certain semiconductor materials as working materials to produce stimulated emission. Their working principle is: through a certain excitation method, a particle population inversion of non-equilibrium carriers is achieved between the energy bands (conduction band and valence band) of the semiconductor material, or between the energy bands of the semiconductor material and the energy levels of impurities (acceptor or donor). When a large number of electrons in the particle population inversion state recombine with holes, stimulated emission occurs. Semiconductor light-emitting devices are widely used due to their small size and high electro-optical conversion efficiency.

[0003] Quantum cascade laser is an important semiconductor light-emitting device. Its spectral range covers the mid-infrared to far-infrared band. It can be used in trace gas detection, free-space optical communication and many other aspects, and has broad market application prospects. Summary of the invention

[0004] Therefore, the technical problem to be solved by the present invention is how to improve the power and efficiency of a semiconductor light-emitting structure, thereby providing a semiconductor light-emitting structure and a method for preparing the same.

[0005] The present application provides a semiconductor light-emitting structure, comprising: a semiconductor substrate layer; a lower limiting layer located on the semiconductor substrate layer; a lower waveguide layer, an active layer, an upper waveguide layer and an upper limiting layer stacked in sequence and located on a side of a portion of the lower limiting layer away from the semiconductor substrate layer; the lower waveguide layer, the active layer, the upper waveguide layer and the upper limiting layer having a front cavity surface and a rear cavity surface opposite to each other in the cavity length direction; an insulating epitaxial layer located on a side of a portion of the lower limiting layer away from the semiconductor substrate layer and on both sides of the lower waveguide layer, the active layer, the upper waveguide layer and the upper limiting layer in the slow axis direction ; A first isolation groove and a second isolation groove, both of which extend along the slow axis direction from the insulating epitaxial layer on one side of the upper restriction layer in the slow axis direction, pass through the upper restriction layer and extend to the insulating epitaxial layer on the other side of the upper restriction layer in the slow axis direction, and the first isolation groove is located on the side of the second isolation groove away from the rear cavity surface; in the cavity length direction, the spacing distance from the first isolation groove to the front cavity surface is much smaller than the spacing distance from the first isolation groove to the rear cavity surface, and the spacing distance from the second isolation groove to the rear cavity surface is much smaller than the spacing distance from the second isolation groove to the front cavity surface.

[0006] Optionally, it further includes: a first insulating filling layer and a second insulating filling layer; wherein the first insulating filling layer is located in the first isolation trench, and the second insulating filling layer is located in the second isolation trench.

[0007] Optionally, the absolute value of the difference between the refractive index of the first insulating filling layer and the refractive index of the upper limiting layer is less than or equal to 0.03; the absolute value of the difference between the refractive index of the second insulating filling layer and the refractive index of the upper limiting layer is less than or equal to 0.03.

[0008] Optionally, the material of the upper limiting layer includes Si-doped InP; the material of the first insulating filling layer includes Fe-doped InP; and the material of the second insulating filling layer includes Fe-doped InP.

[0009] Optionally, the first isolation groove extends in the fast axis direction into the upper confinement layer and does not extend into the upper waveguide layer; or, the first isolation groove extends in the fast axis direction into the upper confinement layer and the upper waveguide layer and does not extend into the active layer; wherein the second isolation groove extends in the fast axis direction into the upper confinement layer and does not extend into the upper waveguide layer; or, the second isolation groove extends in the fast axis direction into the upper confinement layer and the upper waveguide layer and does not extend into the active layer.

[0010] Optionally, the depth dimension of the first isolation groove in the fast axis direction is 1 μm to 6 μm; the depth dimension of the second isolation groove in the fast axis direction is 1 μm to 6 μm.

[0011] Optionally, the width of the first isolation groove in the cavity length direction is 10 μm to 20 μm; the width of the second isolation groove in the cavity length direction is 10 μm to 20 μm.

[0012] Optionally, the spacing distance between the first isolation groove and the front cavity surface in the cavity length direction is 100 μm to 200 μm; the spacing distance between the second isolation groove and the front cavity surface in the cavity length direction is 100 μm to 200 μm.

[0013] Optionally, it also includes: a front electrode layer, which is located on the side of the upper limiting layer, the first insulating filling layer and the second insulating filling layer away from the upper waveguide layer.

[0014] Optionally, it also includes: a first insulating dielectric layer, located between the front cavity surface and the first insulating filling layer and between the front electrode layer and the upper limiting layer; and a second insulating dielectric layer, located between the rear cavity surface and the second insulating filling layer and between the front electrode layer and the upper limiting layer.

[0015] Optionally, the active layer includes a first part and a second part, the first part is located between the front cavity surface and the first isolation groove along the cavity length direction, and the second part is located between the rear cavity surface and the second isolation groove along the cavity length direction; wherein, the size of the first part at one end of the front cavity surface in the slow axis direction is larger than the size of the end of the first part away from the front cavity surface along the cavity length direction in the slow axis direction; the size of the second part at one end of the rear cavity surface in the slow axis direction is larger than the size of the end of the second part away from the rear cavity surface along the cavity length direction in the slow axis direction.

[0016] Optionally, the size of the first part along the slow axis increases from the first isolation groove to the front cavity surface along the cavity length direction; the size of the second part along the slow axis increases from the second isolation groove to the rear cavity surface along the cavity length direction.

[0017] Optionally, the size of the first part at one end of the front cavity surface in the slow axis direction is 15μm~25μm; the size of the first part at the end away from the front cavity surface along the cavity length direction in the slow axis direction is 8μm~12μm; the size of the second part at one end of the rear cavity surface in the slow axis direction is 15μm~25μm; the size of the second part at the end away from the rear cavity surface along the cavity length direction in the slow axis direction is 8μm~12μm.

[0018] The present application also provides a method for preparing a semiconductor light-emitting structure, comprising: providing a semiconductor substrate layer; forming a lower limiting layer on the semiconductor substrate layer; forming a lower waveguide layer, an active layer, an upper waveguide layer and an upper limiting layer stacked in sequence on a side of a portion of the lower limiting layer away from the semiconductor substrate layer; the lower waveguide layer, the active layer, the upper waveguide layer and the upper limiting layer have front cavity surfaces and rear cavity surfaces that are opposite in the cavity length direction; forming an insulating epitaxial layer, the insulating epitaxial layer being located on a side of a portion of the lower limiting layer away from the semiconductor substrate layer and being located on the lower waveguide layer, the active layer, the upper waveguide layer and the upper limiting layer. On both sides of the slow axis direction; a first isolation groove and a second isolation groove are formed, and the first isolation groove and the second isolation groove both extend along the slow axis direction from the upper restriction layer in the insulating epitaxial layer on one side of the slow axis direction, pass through the upper restriction layer and extend to the upper restriction layer in the insulating epitaxial layer on the other side of the slow axis direction, and the first isolation groove is located on the side of the second isolation groove away from the rear cavity surface; in the cavity length direction, the spacing distance from the first isolation groove to the front cavity surface is much smaller than the spacing distance from the first isolation groove to the rear cavity surface, and the spacing distance from the second isolation groove to the rear cavity surface is much smaller than the spacing distance from the second isolation groove to the front cavity surface.

[0019] Optionally, the method further includes: forming a first insulating filling layer in the first isolation trench; and forming a second insulating filling layer in the second isolation trench.

[0020] Optionally, the material of the upper limiting layer includes Si-doped InP; the material of the first insulating filling layer includes Fe-doped InP; and the material of the second insulating filling layer includes Fe-doped InP.

[0021] Optionally, it also includes: forming a first insulating dielectric layer on the side of the upper limiting layer between the front cavity surface and the first insulating filling layer facing away from the active layer, and forming a second insulating dielectric layer on the side of the upper limiting layer between the back cavity surface and the second insulating filling layer facing away from the active layer; forming a front electrode layer on the side of the upper limiting layer, the first insulating dielectric layer, the second insulating dielectric layer, the first insulating filling layer and the second insulating filling layer facing away from the upper waveguide layer.

[0022] Optionally, forming an active layer includes forming a first part and a second part, the first part is located between the front cavity surface and the first isolation groove along the cavity length direction, and the second part is located between the rear cavity surface and the second isolation groove along the cavity length direction; wherein a size of the first part at one end of the front cavity surface in the slow axis direction is larger than a size of the first part at an end of the cavity length away from the front cavity surface in the slow axis direction; a size of the second part at one end of the rear cavity surface in the slow axis direction is larger than a size of the second part at an end of the cavity length away from the rear cavity surface in the slow axis direction.

[0023] The technical solution of the present invention has the following beneficial effects: The semiconductor light-emitting structure provided by the technical solution of the present invention is provided with a first isolation groove and a second isolation groove, and the first isolation groove and the second isolation groove both penetrate the upper confinement layer along the slow axis direction. Even if the electron mobility of the upper confinement layer is high, due to the provision of the first isolation groove and the second isolation groove, when current is injected into the interior of the semiconductor light-emitting structure, it is difficult for the electrons to expand in the cavity length direction through the upper confinement layer, thereby reducing the injection current value of the semiconductor light-emitting structure near the front cavity surface and the rear cavity surface. The reduction in the injection current value can effectively suppress the electrical heating near the front cavity surface and the rear cavity surface, thereby reducing the temperature of the front cavity surface and the rear cavity surface, increasing the catastrophic optical damage threshold of the cavity surface, and thus improving the power and efficiency upper limit of the semiconductor light-emitting structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 It is a schematic diagram of the three-dimensional structure of a quantum cascade laser in the related art; Figure 2 for Figure 1 Schematic diagram of the cross section in the cavity surface direction x and the fast axis direction z; Figure 3 A schematic diagram of the three-dimensional structure of a semiconductor light-emitting structure provided in one embodiment of the present application; Figure 4 for Figure 3 Schematic diagram of the cross section in the cavity surface direction x and the fast axis direction z; Figure 5 A top view of a partial structure of a semiconductor light emitting structure provided by another embodiment of the present application; Figure 6 A schematic diagram of a process for preparing a semiconductor light-emitting structure provided in one embodiment of the present application; Figures 7 to 14 A structural schematic diagram of a process for preparing a semiconductor light-emitting structure provided in one embodiment of the present application. DETAILED DESCRIPTION

[0026] A quantum cascade laser such as Figure 1 and Figure 2 shown. Figure 1 Schematic diagram of the three-dimensional structure of the quantum cascade laser. Figure 2 yes Figure 1 A schematic cross-sectional view in the cavity length direction x and the fast axis direction z. The quantum cascade laser comprises: a semiconductor substrate layer 100; a lower confinement layer 110 located on the semiconductor substrate layer 100; a lower waveguide layer 120, an active layer 130, an upper waveguide layer 140 and an upper confinement layer 150 stacked in sequence on the side of the lower confinement layer 110 away from the semiconductor substrate layer 100; the lower waveguide layer 120, the active layer 130, the upper waveguide layer 140 and the upper confinement layer 150 having a front cavity surface and a rear cavity surface opposite to each other in the cavity length direction x; an insulating epitaxial layer 160, located on the side of the lower confinement layer 110 away from the semiconductor substrate layer 100 and on both sides of the lower waveguide layer 120, the active layer 130, the upper waveguide layer 140 and the upper confinement layer 150 in the slow axis direction y; an antireflection film 170 located on the front cavity surface; and a reflective film 180 located on the rear cavity surface. Reference Figure 2 The reflective film 180 includes a first isolation film 180a, a main reflective film 180b and a second isolation film 180c which are sequentially stacked in the cavity length direction. The semiconductor light emitting structure also includes: a front electrode layer 190 located on the side of the upper confinement layer 150 away from the upper waveguide layer 140; and a back electrode layer 200 located on the side of the semiconductor substrate layer 100 away from the lower confinement layer 110.

[0027] However, current quantum cascade lasers can meet basic performance requirements, but still have many shortcomings.

[0028] On this basis, the embodiment of the present application provides a semiconductor light-emitting structure to improve the power and efficiency of the semiconductor light-emitting structure.

[0029] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0031] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0032] refer to Figure 3 , an embodiment of the present invention provides a semiconductor light emitting structure, comprising: Semiconductor substrate layer 1; A lower confinement layer 2 located on the semiconductor substrate layer 1; A lower waveguide layer 3, an active layer 4, an upper waveguide layer 5 and an upper limit layer 6 are sequentially stacked on a side of a portion of the lower limit layer 2 away from the semiconductor substrate layer 1; the lower waveguide layer 3, the active layer 4, the upper waveguide layer 5 and the upper limit layer 6 have a front cavity surface and a rear cavity surface opposite to each other in the cavity length direction x; The insulating epitaxial layer 7 is located on the side of the lower confinement layer 2 away from the semiconductor substrate layer 1 and on both sides of the lower waveguide layer 3, the active layer 4, the upper waveguide layer 5 and the upper confinement layer 6 in the slow axis direction y; The first isolation groove 8a and the second isolation groove 8b extend along the slow axis direction y from the insulating epitaxial layer 7 on one side of the upper restriction layer 6 in the slow axis direction y, pass through the upper restriction layer 6 and extend to the insulating epitaxial layer 7 on the other side of the upper restriction layer 6 in the slow axis direction y. The first isolation groove 8a is located on the side of the second isolation groove 8b away from the rear cavity surface. In the cavity length direction x, the spacing distance from the first isolation groove 8a to the front cavity surface is much smaller than the spacing distance from the first isolation groove 8a to the rear cavity surface, and the spacing distance from the second isolation groove 8b to the rear cavity surface is much smaller than the spacing distance from the second isolation groove 8b to the front cavity surface.

[0033] In the cavity length direction x, the spacing distance between the first isolation groove 8a and the front cavity surface is much smaller than the spacing distance between the first isolation groove 8a and the rear cavity surface, which also means that the first isolation groove 8a is close to the front cavity surface. In the cavity length direction x, the spacing distance between the second isolation groove 8b and the rear cavity surface is much smaller than the spacing distance between the second isolation groove 8b and the front cavity surface, which also means that the second isolation groove 8b is close to the rear cavity surface.

[0034] In this embodiment, a first isolation groove 8a and a second isolation groove 8b are provided, and the first isolation groove 8a and the second isolation groove 8b both penetrate the upper confinement layer 6 along the slow axis direction. Even if the electron mobility of the upper confinement layer 6 is high, due to the provision of the first isolation groove 8a and the second isolation groove 8b, when current is injected into the interior of the semiconductor light-emitting structure, it is difficult for the electrons to expand in the cavity length direction through the upper confinement layer 6, thereby reducing the injection current value of the semiconductor light-emitting structure near the front cavity surface and the rear cavity surface. The reduction of the injection current value can effectively suppress the electrical heating near the front cavity surface and the rear cavity surface, thereby reducing the temperature of the front cavity surface and the rear cavity surface, and increasing the catastrophic optical damage threshold of the cavity surface, thereby improving the power and efficiency upper limit of the semiconductor light-emitting structure.

[0035] Figure 3 The middle and lower waveguide layers 3, the active layer 4, the upper waveguide layer 5 and the upper confinement layer 6 constitute a ridge structure. Figure 3 The semiconductor light emitting structure has a ridge structure as an example. It can be seen that both the first isolation groove 8a and the second isolation groove 8b penetrate the ridge structure along the slow axis direction y.

[0036] In other embodiments, the semiconductor light emitting structure has a plurality of ridge structures along the slow axis direction y.

[0037] In this embodiment, the semiconductor light-emitting structure is an edge-emitting semiconductor laser as an example for explanation, such as a quantum cascade edge-emitting semiconductor laser, and the quantum cascade edge-emitting semiconductor laser includes a mid-infrared quantum cascade edge-emitting semiconductor laser. Further, this embodiment takes a mid-infrared quantum cascade edge-emitting semiconductor laser with a lasing wavelength of 9 μm as an example. The quantum cascade edge-emitting semiconductor laser of this embodiment uses electrons as carriers, and the mobility of electrons is much higher than that of holes. Therefore, the first isolation groove 8a and the second isolation groove 8b are both extended along the slow axis direction y from the upper confinement layer 6 in the insulating epitaxial layer 7 on one side of the slow axis direction y, through the upper confinement layer 6 and extend to the upper confinement layer 6 in the insulating epitaxial layer 7 on the other side of the slow axis direction y, so as to effectively block the electrons from expanding in the cavity length direction.

[0038] In other embodiments, the semiconductor light emitting structure may not be a quantum cascade edge emitting semiconductor laser.

[0039] In this embodiment, the semiconductor substrate layer 1 is an InP substrate layer. It should be noted that in other embodiments, the semiconductor substrate layer can also be made of other materials.

[0040] In one embodiment, the material of the lower confinement layer 2 is InP doped with conductive ions. Based on the characteristics of the mid-infrared quantum cascade edge-emitting semiconductor laser, the lower confinement layer 2 is made of InP doped with conductive ions. In a specific embodiment, the conductive ions doped in the lower confinement layer 2 are, for example, Si ions.

[0041] In a specific embodiment, the doping concentration of the conductive ions in the lower confinement layer 2 is 2×10 16 atom / cm 3 In one embodiment, the thickness of the lower limiting layer 2 is 4 micrometers, which is only used as an example.

[0042] In one embodiment, the material of the lower waveguide layer 3 is In doped with conductive ions. p Ga (1-p) As,p is greater than zero and less than 1. In a specific embodiment, the conductive ions doped into the lower waveguide layer 3 are, for example, Si ions.

[0043] In a specific embodiment, the doping concentration of the conductive ions in the lower waveguide layer 3 is 2×10 16 atom / cm 3 In one embodiment, the thickness of the lower waveguide layer 3 is 0.1 micrometers, which is only used as an example.

[0044] In one embodiment, the active layer 4 is a superlattice structure, and the active layer 4 includes a plurality of stacked sub-active layer groups, wherein the sub-active layer groups include a first sub-active layer unit to an M-th sub-active layer unit stacked sequentially from bottom to top, M is an integer greater than or equal to 2, and any m-th sub-active layer unit includes an m-th lower sub-active layer and an m-th upper sub-active layer stacked from bottom to top, m is an integer greater than or equal to 1 and less than or equal to M, and the material of the m-th lower sub-active layer is In a Ga (1-a) As, the material of the mth upper active layer is In b Al (1-b) As.

[0045] In a specific embodiment, the thickness of the active layer 4 is 2 micrometers, which is only used as an example.

[0046] In one embodiment, the material of the upper waveguide layer 5 is In doped with conductive ions. p Ga (1-p) In one embodiment, the conductive ions doped in the upper waveguide layer 5 are, for example, Si ions.

[0047] In a specific embodiment, the doping concentration of the conductive ions in the upper waveguide layer 5 is 2×10 16 atom / cm 3 In one embodiment, the thickness of the upper waveguide layer 5 is 0.1 micrometers. This is just an example. In one embodiment, the material of the upper confinement layer 6 is InP doped with conductive ions. In one embodiment, the conductive ions doped in the upper confinement layer 6 are, for example, Si ions.

[0048] In a specific embodiment, the doping concentration of the conductive ions in the upper confinement layer 6 is 2×10 16 atom / cm 3 In one embodiment, the thickness of the upper limiting layer 6 is 5 micrometers, which is only used as an example.

[0049] In one embodiment, the material of the insulating epitaxial layer 7 is InP doped with Fe. The insulating epitaxial layer 7 is non-conductive, and the carriers in the active layer 4 will not pass through the insulating epitaxial layer 7.

[0050] In one embodiment, the semiconductor light emitting structure further includes: a contact layer (not shown) located on the surface of the upper confinement layer 6 facing away from the upper waveguide layer 5. In one embodiment, the contact layer is an InP contact layer, and the contact layer is doped with conductive ions, and the doping concentration of the conductive ions in the contact layer is greater than the doping concentration of the conductive ions in the upper confinement layer 6.

[0051] refer to Figure 4 , Figure 4 yes Figure 3 A schematic cross-sectional view in the cavity length direction x and the fast axis direction z. The semiconductor light-emitting structure also includes: a first insulating filling layer 9a and a second insulating filling layer 9b; wherein the first insulating filling layer 9a is located in the first isolation groove 8a, and the second insulating filling layer 9b is located in the second isolation groove 8b. Since the first isolation groove 8a and the second isolation groove 8b are filled with air when they are not filled, and the refractive index of the air is very different from the refractive index of the upper limiting layer 6, the light field distribution at the location of the first isolation groove 8a and the second isolation groove 8b and the light field distribution at the location of the upper limiting layer 6 far away from the first isolation groove 8a and the second isolation groove 8b will be significantly different, thereby affecting the optical transmission of the light field along the cavity length direction x. Based on this, this embodiment fills the first insulating filling layer 9a in the first isolation groove 8a and the second insulating filling layer 9b in the second isolation groove 8b, and the refractive index difference between the first insulating filling layer 9a and the upper limiting layer 6 is reduced, and the refractive index difference between the second insulating filling layer 9b and the upper limiting layer 6 is reduced. This can optimize the distribution of the light field, reduce the impact on the optical transmission of the light field along the cavity length direction x, improve the performance of the semiconductor light-emitting structure, and further improve the power and efficiency of the semiconductor light-emitting structure.

[0052] In one embodiment, the absolute value of the difference between the refractive index of the first insulating filling layer 9a and the refractive index of the upper confinement layer 6 is less than or equal to 0.03; the absolute value of the difference between the refractive index of the second insulating filling layer 9b and the refractive index of the upper confinement layer 6 is less than or equal to 0.03. The smaller the difference between the refractive index of the first insulating filling layer 9a and the refractive index of the upper confinement layer 6, and the smaller the difference between the refractive index of the second insulating filling layer 9b and the refractive index of the upper confinement layer 6, the stronger the effect of reducing the influence on the optical transmission of the light field along the cavity length direction x.

[0053] In this embodiment, the material of the upper limiting layer 6 includes InP doped with Si; the material of the first insulating filling layer 9a includes InP doped with Fe; and the material of the second insulating filling layer 9b includes InP doped with Fe. The first insulating filling layer 9a and the second insulating filling layer 9b have good electrical insulation and thermal conductivity properties, and can simultaneously ensure the heat dissipation capacity and optical confinement effect of the semiconductor light-emitting structure; at the same time, since the difference between the refractive index of the first insulating filling layer 9a and the refractive index of the upper limiting layer 6 is very small, and the difference between the refractive index of the second insulating filling layer 9b and the refractive index of the upper limiting layer 6 is very small, the influence on the optical transmission of the light field along the cavity length direction x is effectively reduced.

[0054] In this embodiment, the first isolation groove 8a extends into the upper confinement layer 6 in the fast axis direction z and does not extend into the upper waveguide layer 5. Specifically, the first isolation groove 8a is located in a partial thickness of the upper confinement layer 6, or the first isolation groove 8a penetrates the upper confinement layer 6 and the bottom surface of the first isolation groove 8a is located at the interface between the upper confinement layer 6 and the upper waveguide layer 5.

[0055] In another embodiment, the first isolation groove 8a extends into the upper confinement layer 6 and the upper waveguide layer 5 in the fast axis direction z and does not extend into the active layer 4. Specifically, the first isolation groove 8a penetrates the upper confinement layer 6 and the bottom surface of the first isolation groove 8a is located in the upper waveguide layer 5, or the first isolation groove 8a penetrates the upper confinement layer 6 and the upper waveguide layer 5 and the bottom surface of the first isolation groove 8a is located at the interface between the upper waveguide layer 5 and the active layer 4.

[0056] When the first isolation groove 8a extends into the upper confinement layer 6 in the fast axis direction z and does not extend into the upper waveguide layer 5; or, when the first isolation groove 8a extends into the upper confinement layer 6 and the upper waveguide layer 5 in the fast axis direction z and does not extend into the active layer 4, since the first isolation groove 8a does not extend into the active layer 4, etching loss to the active layer 4 is avoided.

[0057] In this embodiment, the second isolation groove 8b extends into the upper confinement layer 6 in the fast axis direction z and does not extend into the upper waveguide layer 5. Specifically, the second isolation groove 8b is located in a partial thickness of the upper confinement layer 6, or the second isolation groove 8b penetrates the upper confinement layer 6 and the bottom surface of the second isolation groove 8b is located at the interface between the upper confinement layer 6 and the upper waveguide layer 5.

[0058] In another embodiment, the second isolation groove 8b extends into the upper confinement layer 6 and the upper waveguide layer 5 in the fast axis direction z and does not extend into the active layer 4. Specifically, the second isolation groove 8b penetrates the upper confinement layer 6 and the bottom surface of the second isolation groove 8b is located in the upper waveguide layer 5, or the second isolation groove 8b penetrates the upper confinement layer 6 and the upper waveguide layer 5 and the bottom surface of the second isolation groove 8b is located at the interface between the upper waveguide layer 5 and the active layer 4.

[0059] When the second isolation groove 8b extends into the upper confinement layer 6 in the fast axis direction z and does not extend into the upper waveguide layer 5; or, when the second isolation groove 8b extends into the upper confinement layer 6 and the upper waveguide layer 5 in the fast axis direction z and does not extend into the active layer 4, since the second isolation groove 8b does not extend into the active layer 4, etching loss to the active layer 4 is avoided.

[0060] In one embodiment, the depth dimension of the first isolation groove 8a in the fast axis direction z is 1 μm to 6 μm, for example, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm or 6 μm. If the depth dimension of the first isolation groove 8a in the fast axis direction z is less than 1 μm, the restriction on the extension of electrons in the upper confinement layer 6 along the cavity length direction has certain limitations, and the degree of improving the catastrophic optical damage threshold of the cavity surface is small; if the depth dimension of the first isolation groove 8a in the fast axis direction z is greater than 6 μm, the probability of the first isolation groove 8a extending to the upper waveguide layer 5 and the active layer 4 is large, and the refractive index difference between the upper waveguide layer 5 and the active layer 4 and the first insulating filling layer 9a filled in the first isolation groove 8a is large, thereby affecting the transmission of the light field. Therefore, the depth dimension of the first isolation groove 8a in the fast axis direction z is 1 μm to 6 μm, which can take into account the above performance at the same time. In a specific embodiment, preferably, the depth dimension of the first isolation groove 8a in the fast axis direction z is 5.5 μm.

[0061] In one embodiment, the depth dimension of the second isolation groove 8b in the fast axis direction z is 1 μm to 6 μm, for example, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm or 6 μm. If the depth dimension of the second isolation groove 8b in the fast axis direction z is less than 1 μm, the restriction on the extension of electrons in the upper confinement layer 6 along the cavity length direction has certain limitations, and the degree of improving the catastrophic optical damage threshold of the cavity surface is small; if the depth dimension of the second isolation groove 8b in the fast axis direction z is greater than 6 μm, the probability of the second isolation groove 8b extending to the upper waveguide layer 5 and the active layer 4 is large, and the refractive index difference between the upper waveguide layer 5 and the active layer 4 and the second insulating filling layer 9b filled in the second isolation groove 8b is large, thereby affecting the transmission of the light field. Therefore, the depth dimension of the second isolation groove 8b in the fast axis direction z is 1 μm to 6 μm, which can take into account the above performance at the same time. Preferably, the depth dimension of the second isolation groove 8b in the fast axis direction z is 5.5 μm.

[0062] In one embodiment, the width of the first isolation groove 8a in the cavity length direction x is 10μm~20μm, for example, 10μm, 13μm, 15μm, 17μm or 20μm. If the width of the first isolation groove 8a in the cavity length direction x is less than 10μm, the injected current has the risk of bypassing the first isolation groove 8a along the cavity length direction x to reach the cavity surface, and there is a situation where the local position has a weak restriction on the expansion of electrons along the cavity length direction x, and the degree of improving the catastrophic optical damage threshold of the cavity surface is small; if the width of the first isolation groove 8a in the cavity length direction x is greater than 20μm, on the one hand, the process time required for etching the first isolation groove 8a and growing the first insulating filling layer 9a is long, and on the other hand, it is not conducive to the increase in the length of the region where the current is injected into the interior of the semiconductor light-emitting structure along the cavity length direction x, and the degree of improving the power of the semiconductor light-emitting structure is limited. Therefore, the width of the first isolation groove 8a in the cavity length direction x is 10μm~20μm, which can take into account the above performance at the same time.

[0063] In one embodiment, the width of the second isolation groove 8b in the cavity length direction x is 10μm~20μm, for example, 10μm, 13μm, 15μm, 17μm or 20μm. If the width of the second isolation groove 8b in the cavity length direction x is less than 10μm, the injected current has the risk of bypassing the second isolation groove 8b along the cavity length direction x to reach the cavity surface, and there is a situation where the local position has a weak restriction on the expansion of electrons along the cavity length direction x, and the degree of improving the catastrophic optical damage threshold of the cavity surface is small; if the width of the second isolation groove 8b in the cavity length direction x is greater than 20μm, on the one hand, the process time required for etching the second isolation groove 8b and growing the second insulating filling layer 9b is long, and on the other hand, it is not conducive to the increase in the length of the region where the current is injected into the interior of the semiconductor light-emitting structure along the cavity length direction x, and the degree of improving the power of the semiconductor light-emitting structure is limited. Therefore, the width of the second isolation groove 8b in the cavity length direction x is 10μm~20μm, which can take into account the above performance at the same time.

[0064] In one embodiment, the spacing distance between the first isolation groove 8a and the front cavity surface in the cavity length direction x is 100μm~200μm, for example, 100μm, 130μm, 150μm, 180μm or 200μm. If the spacing distance between the first isolation groove 8a and the front cavity surface in the cavity length direction x is less than 100μm, the degree of improvement of the restriction effect on the expansion of electrons along the cavity length direction x is small; if the spacing distance between the first isolation groove 8a and the front cavity surface in the cavity length direction x is greater than 200μm, it is not conducive to the increase of the length of the region for injecting current into the interior of the semiconductor light-emitting structure along the cavity length direction x, and the degree of improving the power of the semiconductor light-emitting structure is limited. Therefore, the spacing distance between the first isolation groove 8a and the front cavity surface in the cavity length direction x is 100μm~200μm, which can take into account the above performance at the same time.

[0065] In one embodiment, the spacing distance between the second isolation groove 8b and the front cavity surface in the cavity length direction x is 100μm~200μm, for example, 100μm, 130μm, 150μm, 180μm or 200μm. If the spacing distance between the second isolation groove 8b and the front cavity surface in the cavity length direction x is less than 100μm, the degree of improvement of the restriction effect on the expansion of electrons along the cavity length direction x is small; if the spacing distance between the second isolation groove 8b and the front cavity surface in the cavity length direction x is greater than 200μm, it is not conducive to the increase in the length of the region where the current is injected into the interior of the semiconductor light-emitting structure along the cavity length direction x, and the degree of improvement in the power of the semiconductor light-emitting structure is limited. Therefore, the spacing distance between the second isolation groove 8b and the front cavity surface in the cavity length direction x is 100μm~200μm, which can take into account the above performance at the same time.

[0066] In this embodiment, the first isolation groove 8a and the second isolation groove 8b are symmetrically distributed along the cavity length direction x, that is, the first isolation groove 8a and the second isolation groove 8b have the same depth dimension in the fast axis direction z, the first isolation groove 8a and the second isolation groove 8b have the same width dimension in the cavity length direction x, and the spacing distance between the first isolation groove 8a and the front cavity surface in the cavity length direction x and the spacing distance between the second isolation groove 8b and the rear cavity surface in the cavity length direction x are the same. This is conducive to simplifying the process.

[0067] In other embodiments, the first isolation trench 8 a and the second isolation trench 8 b may be designed asymmetrically along the cavity length direction x.

[0068] refer to Figure 4 The semiconductor light-emitting structure also includes: a front electrode layer 10, located on the side of the upper limiting layer 6, the first insulating filling layer 9a and the second insulating filling layer 9b away from the upper waveguide layer 5; and a back electrode layer 11 located on the side of the semiconductor substrate layer 1 away from the lower limiting layer 2.

[0069] When the semiconductor light emitting structure includes a contact layer, the first isolation trench 8a and the second isolation trench 8b further penetrate the contact layer along the fast axis direction, wherein the first insulating filling layer and the second insulating filling layer further penetrate the contact layer along the fast axis direction.

[0070] In this embodiment, the semiconductor light emitting structure further includes: a first insulating dielectric layer 12a, located between the front cavity surface and the first insulating filling layer 9a and between the front electrode layer 10 and the upper limiting layer 6; and a second insulating dielectric layer 12b, located between the rear cavity surface and the second insulating filling layer 9b and between the front electrode layer 10 and the upper limiting layer 6. In this way, the current of the front electrode layer 10 will not be injected into the upper limiting layer 6 between the front cavity surface and the first insulating filling layer 9a and the upper limiting layer 6 between the rear cavity surface and the second insulating filling layer 9b.

[0071] When the semiconductor light-emitting structure includes a contact layer, the first insulating medium layer 12a is located between the front cavity surface and the first insulating filling layer 9a and between the front electrode layer 10 and the contact layer, and the second insulating medium layer 12b is located between the rear cavity surface and the second insulating filling layer 9b and between the front electrode layer 10 and the contact layer.

[0072] In other embodiments, the first insulating medium layer and the second insulating medium layer may not be provided.

[0073] Continue to refer Figure 4 The semiconductor light emitting structure further includes: an anti-reflection film 13 located on the front cavity surface; and an anti-reflection film 14 located on the rear cavity surface.

[0074] In one embodiment, the material of the anti-reflection film 13 is Y2O3, Al2O3 or ZrO2. In this embodiment, the material of the anti-reflection film is Y2O3.

[0075] In one embodiment, the anti-reflection film 14 includes a main reflection film 14a, a first isolation film 14b located on one side of the main reflection film 14a along the cavity length direction x, and a second isolation film 14c located on the other side of the main reflection film 14a along the cavity length direction x. In one embodiment, the material of the main reflection film 14a is Au; the material of the first isolation film 14b is Y2O3; and the material of the second isolation film 14c is Y2O3.

[0076] In one embodiment, the electrical isolation capability of the first isolation film 14b and the second isolation film 14c is improved, the dimension of the first isolation film 14b along the cavity length direction x is greater than or equal to 200nm, for example, 200nm or 250nm, and the dimension of the second isolation film 14c along the cavity length direction x is greater than or equal to 200nm, for example, 200nm or 250nm.

[0077] Another embodiment of the present invention further provides a semiconductor light emitting structure, which is different from the above embodiment in that: Figure 5 The active layer 4 includes a first portion 4a and a second portion 4b, wherein the first portion 4a is located between the front cavity surface and the first isolation groove 8a along the cavity length direction x, and the second portion 4b is located between the rear cavity surface and the second isolation groove 8b along the cavity length direction x. The active layer 4 also includes a third portion 4c, which is located between the first isolation groove 8a and the second isolation groove 8b along the cavity length direction x.

[0078] The lower waveguide layer 3 includes a first lower waveguide portion, a second lower waveguide portion, and a third lower waveguide portion. The first lower waveguide portion is disposed opposite to the first portion 4a in the fast axis direction z, the second lower waveguide portion is disposed opposite to the second portion 4b in the fast axis direction z, and the third lower waveguide portion is disposed opposite to the third portion 4c in the fast axis direction z. The upper waveguide layer 5 includes a first upper waveguide portion, a second upper waveguide portion, and a third upper waveguide portion. The first upper waveguide portion is disposed opposite to the first portion 4a in the fast axis direction z, the second upper waveguide portion is disposed opposite to the second portion 4b in the fast axis direction z, and the third upper waveguide portion is disposed opposite to the third portion 4c in the fast axis direction z. The upper confinement layer 6 includes a first upper confinement portion, a second upper confinement portion, and a third upper confinement portion. The first upper confinement portion is disposed opposite to the first portion 4a in the fast axis direction z, the second upper confinement portion is disposed opposite to the second portion 4b in the fast axis direction z, and the third upper confinement portion is disposed opposite to the third portion 4c in the fast axis direction z.

[0079] In this embodiment, the size of the first part 4a at one end of the front cavity surface in the slow axis direction y is greater than the size of the end of the first part 4a away from the front cavity surface along the cavity length direction x in the slow axis direction y; the size of the second part 4b at one end of the back cavity surface in the slow axis direction y is greater than the size of the end of the second part 4b away from the back cavity surface along the cavity length direction x in the slow axis direction y. Through such a design, under the premise that the output power of the front cavity surface light of the semiconductor light-emitting structure is determined, since the size of the first part 4a at one end of the front cavity surface in the slow axis direction y is larger, the optical power density of the front cavity surface will be reduced, thereby reducing the optical power absorption density of the front cavity surface, and suppressing the temperature rise phenomenon caused by the absorption of optical power on the front cavity surface. Under the premise that the output power of the front cavity surface light of the semiconductor light-emitting structure is determined, since the size of the second part 4b at one end of the back cavity surface in the slow axis direction y is larger, the optical power density of the back cavity surface will be reduced, thereby reducing the optical power absorption density of the back cavity surface, and suppressing the temperature rise phenomenon caused by the absorption of optical power on the back cavity surface. Therefore, the catastrophic optical damage threshold of the cavity surface is further suppressed, thereby further improving the power and efficiency of the semiconductor light-emitting structure.

[0080] In one embodiment, the size of the third portion 4c in the slow axis direction y remains unchanged along the cavity length direction. Exemplarily, the size of the third portion 4c in the slow axis direction y is equal to the size of the end of the first portion 4a in the slow axis direction y away from the front cavity surface along the cavity length direction x, and the size of the third portion 4c in the slow axis direction y is equal to the size of the end of the second portion 4b in the slow axis direction y away from the rear cavity surface along the cavity length direction x.

[0081] In this embodiment, the semiconductor light-emitting structure further includes: an anti-reflection film 13 located on the front cavity surface; and an anti-reflection film 14 located on the rear cavity surface. The description of the anti-reflection film 13 and the anti-reflection film 14 refers to the aforementioned embodiment. Although the thickness of the first isolation film 14b and the thickness of the second isolation film 14c are both relatively large, the size setting of the second part 4b compensates for the influence of the thickness of the first isolation film 14b and the thickness of the second isolation film 14c on the optical power absorption of the rear cavity surface, reducing the probability of catastrophic optical damage to the cavity surface of the rear cavity surface. The size setting of the first part 4a compensates for the influence of the material of the anti-reflection film 13 on the optical power absorption of the rear cavity surface, reducing the probability of catastrophic optical damage to the cavity surface of the front cavity surface.

[0082] In this embodiment, the probability of catastrophic optical damage to the front cavity surface is reduced by setting the size of the first portion 4a. Therefore, there is no need to limit the size of the anti-reflection film 13 along the cavity length direction to reduce the probability of catastrophic optical damage to the front cavity surface. In this way, the size range of the anti-reflection film 13 along the cavity length direction x can be selected within a wider range, and the reflectivity of the front cavity surface can be effectively adjusted.

[0083] In one embodiment, along the cavity length direction x from the first isolation groove 8a to the front cavity surface, the size of the first part 4a along the slow axis direction y increases; along the cavity length direction x from the second isolation groove 8b to the rear cavity surface, the size of the second part 4b along the slow axis direction increases. The first part 4a smoothly transitions from the first isolation groove 8a to the front cavity surface along the cavity length direction x, and the second part 4b smoothly transitions from the second isolation groove 8b to the rear cavity surface along the cavity length direction x, which is beneficial to improving the stability of the cavity surface, and the process operation is simple and convenient.

[0084] In one embodiment, the size of the first portion 4a at one end of the front cavity surface in the slow axis direction y is 15 μm to 25 μm, for example, 15 μm, 20 μm or 25 μm; the size of the end of the first portion 4a away from the front cavity surface along the cavity length direction x in the slow axis direction y is 8 μm to 12 μm, for example, 8 μm, 10 μm or 12 μm. In this embodiment, preferably, the size of the first portion 4a at one end of the front cavity surface in the slow axis direction y is 20 μm; the size of the end of the first portion 4a away from the front cavity surface along the cavity length direction x in the slow axis direction y is 10 μm.

[0085] In one embodiment, the size of the second portion 4b at one end of the rear cavity surface in the slow axis direction y is 15 μm to 25 μm, for example, 15 μm, 20 μm or 25 μm; the size of the end of the second portion 4b away from the rear cavity surface along the cavity length direction x in the slow axis direction y is 8 μm to 12 μm, for example, 8 μm, 10 μm or 12 μm. In this embodiment, preferably, the size of the second portion 4b at one end of the rear cavity surface in the slow axis direction y is 20 μm; the size of the end of the second portion 4b away from the rear cavity surface along the cavity length direction x in the slow axis direction y is 10 μm.

[0086] In one embodiment, the size of the third portion 4c in the slow axis direction y is 8 μm-12 μm, for example, 8 μm, 10 μm or 12 μm. In this embodiment, preferably, the size of the third portion 4c in the slow axis direction y is 10 μm.

[0087] The other contents of this embodiment that are the same as those of the aforementioned embodiment will not be described in detail.

[0088] The present invention further provides a semiconductor light emitting structure, which is composed of all the features of the aforementioned embodiments, that is, a combination of the aforementioned embodiments.

[0089] Another embodiment of the present invention further provides a method for preparing a semiconductor light emitting structure, referring to Figure 6 ,include: S1: providing a semiconductor substrate layer; S2: forming a lower confinement layer on the semiconductor substrate layer; S3: forming a lower waveguide layer, an active layer, an upper waveguide layer and an upper confinement layer stacked in sequence on a side of a portion of the lower confinement layer away from the semiconductor substrate layer; the lower waveguide layer, the active layer, the upper waveguide layer and the upper confinement layer have a front cavity surface and a rear cavity surface opposite to each other in the cavity length direction; S4: forming an insulating epitaxial layer, wherein the insulating epitaxial layer is located on a side of a portion of the lower confinement layer away from the semiconductor substrate layer, and is located on both sides of the lower waveguide layer, the active layer, the upper waveguide layer and the upper confinement layer in the slow axis direction; S5: forming a first isolation trench and a second isolation trench, wherein both the first isolation trench and the second isolation trench extend along the slow axis direction from the insulating epitaxial layer on one side of the upper restriction layer in the slow axis direction, pass through the upper restriction layer and extend to the insulating epitaxial layer on the other side of the upper restriction layer in the slow axis direction, and the first isolation trench is located on the side of the second isolation trench away from the rear cavity surface; in the cavity length direction, the spacing distance from the first isolation trench to the front cavity surface is much smaller than the spacing distance from the first isolation trench to the rear cavity surface, and the spacing distance from the second isolation trench to the rear cavity surface is much smaller than the spacing distance from the second isolation trench to the front cavity surface.

[0090] The method for preparing the semiconductor light-emitting structure also includes: forming a front electrode layer on the side of the upper limiting layer, the first insulating filling layer and the second insulating filling layer facing away from the upper waveguide layer; and forming a first insulating dielectric layer and a second insulating dielectric layer, the first insulating dielectric layer being located between the front cavity surface and the first insulating filling layer and between the front electrode layer and the upper limiting layer; the second insulating dielectric layer being located between the rear cavity surface and the second insulating filling layer and between the front electrode layer and the upper limiting layer.

[0091] Reference below Figures 7 to 14 , the preparation process of the semiconductor light-emitting structure in this embodiment is introduced in detail.

[0092] refer to Figure 7 , providing a semiconductor substrate layer 1; forming an initial lower confinement layer 2a on the semiconductor substrate layer 1; and sequentially forming a stacked initial lower waveguide layer 3a, an initial active layer 4a, an initial upper waveguide layer 5a and an initial upper confinement layer 6a on the side of the initial lower confinement layer 2a away from the semiconductor substrate layer 1.

[0093] In one embodiment, the method further includes: forming an initial contact layer on a side of the initial upper confinement layer 6a facing away from the initial upper waveguide layer 5a.

[0094] refer to Figure 8 , the initial upper confinement layer 6a, the initial upper waveguide layer 5a, the initial active layer 4a, the initial lower waveguide layer 3a and part of the initial lower confinement layer 2a are etched to form the initial lower waveguide layer 3a into the lower waveguide layer 3, the initial active layer 4a into the active layer 4, the initial upper waveguide layer 5a into the upper waveguide layer 5, the initial upper confinement layer 6a into the upper confinement layer 6, and the initial lower confinement layer 2a into the lower confinement layer 2.

[0095] In some embodiments, the method further includes: etching the initial contact layer so that the initial contact layer forms a contact layer, and the contact layer is located on a side of the upper confinement layer 6 away from the upper waveguide layer 5 .

[0096] For the material description, doping concentration description and thickness description of the lower waveguide layer 3, the upper confinement layer 6, the lower confinement layer 2, the active layer 4 and the upper waveguide layer 5, refer to the description of the previous embodiment. For the description of the contact layer, refer to the description of the previous embodiment.

[0097] In this embodiment, the process of etching the initial upper confinement layer 6a, the initial upper waveguide layer 5a, the initial active layer 4a, the initial lower waveguide layer 3a and part of the initial lower confinement layer 2a includes a dry etching process and a wet etching process or a combination of both.

[0098] Figure 8 The middle and lower waveguide layers 3, the active layer 4, the upper waveguide layer 5 and the upper confinement layer 6 constitute a ridge structure. Figure 8In the figure, one ridge structure is provided along the slow axis direction y as an illustration. In other embodiments, the semiconductor light emitting structure has a plurality of ridge structures along the slow axis direction y.

[0099] In other embodiments, the lower waveguide layer 3, the active layer 4, the upper waveguide layer 5, the upper confinement layer 6 and the contact layer constitute a ridge structure.

[0100] Continue to refer Figure 8 , forming an insulating epitaxial layer 7, the insulating epitaxial layer 7 is located on the side of the lower confinement layer 2 away from the semiconductor substrate layer 1, and on both sides of the lower waveguide layer 3, the active layer 4, the upper waveguide layer 5 and the upper confinement layer 6 in the slow axis direction y.

[0101] The process of forming the insulating epitaxial layer 7 is an epitaxial growth process.

[0102] In one embodiment, the material of the insulating epitaxial layer 7 includes InP doped with Fe. The insulating epitaxial layer 7 is non-conductive, and the carriers in the active layer 4 will not pass through the insulating epitaxial layer 7.

[0103] Combined with reference Fig. 9 and Fig.10 , Fig. 9 for Figure 8 Schematic diagram of the three-dimensional structure etched on the basis of Fig.10 for Fig. 9 A schematic cross-sectional view along the cavity length direction x and the fast axis direction z. A first isolation groove 8a and a second isolation groove 8b are formed.

[0104] Both the first isolation groove 8a and the second isolation groove 8b extend along the slow axis direction y from the insulating epitaxial layer 7 on one side of the upper restriction layer 6 in the slow axis direction y, pass through the upper restriction layer 6 and extend to the insulating epitaxial layer 7 on the other side of the upper restriction layer 6 in the slow axis direction y. The first isolation groove 8a is located on the side of the second isolation groove 8b away from the rear cavity surface. In the cavity length direction x, the spacing distance from the first isolation groove 8a to the front cavity surface is much smaller than the spacing distance from the first isolation groove 8a to the rear cavity surface, and the spacing distance from the second isolation groove 8b to the rear cavity surface is much smaller than the spacing distance from the second isolation groove 8b to the front cavity surface.

[0105] In this embodiment, the process of forming the first isolation groove 8a and the second isolation groove 8b includes an etching process. Fig. 9 and Fig.10 The steps of forming the first isolation groove 8a and the second isolation groove 8b include: forming a patterned mask layer 12 on the surface of the upper restriction layer 6 facing away from the semiconductor substrate layer 1; etching a portion of the upper restriction layer 6 using the patterned mask layer 12 as a mask to form the first isolation groove 8a and the second isolation groove 8b.

[0106] The material of the patterned mask layer 12 includes, but is not limited to, silicon dioxide.

[0107] In the present embodiment, the first isolation groove 8a extends into the upper confinement layer 6 in the fast axis direction z and does not extend into the upper waveguide layer 5, and the second isolation groove 8b extends into the upper confinement layer 6 in the fast axis direction z and does not extend into the upper waveguide layer 5. In other embodiments, the first isolation groove extends into the upper confinement layer and the upper waveguide layer in the fast axis direction and does not extend into the active layer, and the second isolation groove extends into the upper confinement layer and the upper waveguide layer in the fast axis direction and does not extend into the active layer.

[0108] Regarding the arrangement description and size definition of the first isolation groove 8 a and the second isolation groove 8 b , reference is made to the description of the aforementioned embodiment.

[0109] When the contact layer is formed, both the first isolation trench 8a and the second isolation trench 8b penetrate the contact layer along the fast axis direction.

[0110] refer to Fig.11 , a first insulating filling layer 9a is formed in the first isolation trench 8a; and a second insulating filling layer 9b is formed in the second isolation trench 8b.

[0111] The second insulating filling layer 9b is formed during the process of forming the first insulating filling layer 9a, thereby simplifying the process.

[0112] When the contact layer is formed, both the first insulating filling layer 9a and the second insulating filling layer 9b penetrate the contact layer along the fast axis direction.

[0113] The process for forming the first insulating filling layer 9a is a metal organic chemical vapor deposition process or a hydride vapor phase epitaxy process. The process for forming the second insulating filling layer 9b is a metal organic chemical vapor deposition process or a hydride vapor phase epitaxy process.

[0114] In one embodiment, the description of the relationship between the refractive index of the first insulating filling layer 9a and the second insulating filling layer 9b and the upper limiting layer 6 refers to the description of the previous embodiment. The description of the materials of the first insulating filling layer 9a and the second insulating filling layer 9b refers to the previous embodiment.

[0115] refer to Fig.12 , and remove the patterned mask layer 12.

[0116] refer to Fig.12 A first insulating dielectric layer 12a is formed on the side of the upper limiting layer 6 between the front cavity surface and the first insulating filling layer 9a away from the active layer 4, and a second insulating dielectric layer 12b is formed on the side of the upper limiting layer 6 between the rear cavity surface and the second insulating filling layer 9b away from the active layer 4.

[0117] The material of the first insulating dielectric layer 12a includes but is not limited to silicon dioxide; the material of the second insulating dielectric layer 12b includes but is not limited to silicon dioxide.

[0118] The positions of the first insulating dielectric layer 12a and the second insulating dielectric layer 12b are described with reference to the above-mentioned embodiment.

[0119] refer to Fig.13 A front electrode layer 10 is formed on the side of the upper limiting layer 6, the first insulating dielectric layer 12a, the second insulating dielectric layer 12b, the first insulating filling layer 9a and the second insulating filling layer 9b away from the upper waveguide layer 5; and a back electrode layer 11 is formed on the side of the semiconductor substrate layer 1 away from the lower limiting layer 2.

[0120] The material of the front electrode layer 10 includes a metal material, such as gold.

[0121] The material of the back electrode layer 11 includes a metal material, such as gold.

[0122] refer to Fig.14 The lower waveguide layer 3, the active layer 4, the upper waveguide layer 5 and the upper limiting layer 6 have a front cavity surface and a rear cavity surface opposite to each other in the cavity length direction x; an anti-reflection film 13 is formed on the front cavity surface; and an anti-reflection film 14 is formed on the rear cavity surface.

[0123] For the structural description and material description of the anti-reflection film 13 , and the structural description and material description of the anti-reflection film 14 , refer to the description of the aforementioned embodiment.

[0124] Before forming the anti-reflection film 13 on the front cavity surface and the anti-reflection film 14 on the back cavity surface, the semiconductor light emitting structure may be cleaved.

[0125] Another embodiment of the present invention further provides a method for preparing a semiconductor light emitting structure, which is different from the above embodiment in that: Figure 5 The active layer 4 is formed by forming a first portion 4a and a second portion 4b, wherein the first portion 4a is located between the front cavity surface and the first isolation groove 8a along the cavity length direction x, and the second portion 4b is located between the rear cavity surface and the second isolation groove 8b along the cavity length direction x. The active layer 4 is formed by forming a third portion 4c, wherein the third portion 4c is located between the first isolation groove 8a and the second isolation groove 8b along the cavity length direction x.

[0126] Among them, the size of the first part 4a at one end of the front cavity surface in the slow axis direction y is greater than the size of the end of the first part 4a away from the front cavity surface along the cavity length direction x in the slow axis direction y; the size of the second part 4b at one end of the rear cavity surface in the slow axis direction y is greater than the size of the end of the second part 4b away from the rear cavity surface along the cavity length direction x in the slow axis direction y.

[0127] The dimension of the third portion 4c in the slow axis direction y is equal to the dimension of the end of the first portion 4a away from the front cavity surface along the cavity length direction x, and is also equal to the dimension of the end of the second portion 4b away from the rear cavity surface along the cavity length direction x.

[0128] Furthermore, along the cavity length direction x from the first isolation groove 8a to the front cavity surface, the size of the first part 4a along the slow axis direction y increases; along the cavity length direction x from the second isolation groove 8b to the rear cavity surface, the size of the second part 4b along the slow axis direction increases.

[0129] Regarding the size of the first part 4a at one end of the front cavity surface in the slow axis direction y, the size of the first part 4a at the end away from the front cavity surface along the cavity length direction x in the slow axis direction y, the size of the second part 4b at one end of the rear cavity surface in the slow axis direction y, the size of the second part 4b at the end away from the rear cavity surface along the cavity length direction x in the slow axis direction y, and the size of the third part 4c in the slow axis direction y, refer to the description of the aforementioned embodiments.

[0130] The other contents of this embodiment that are the same as those of the aforementioned embodiment will not be described in detail.

[0131] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A semiconductor light emitting structure, characterized in that: include: Semiconductor substrate layer; a lower confinement layer located on the semiconductor substrate layer; A lower waveguide layer, an active layer, an upper waveguide layer and an upper limit layer are stacked in sequence on a side of the lower limit layer away from the semiconductor substrate layer; the lower waveguide layer, the active layer, the upper waveguide layer and the upper limit layer have a front cavity surface and a rear cavity surface opposite to each other in the cavity length direction; an insulating epitaxial layer, located on a side of a portion of the lower confinement layer away from the semiconductor substrate layer, and located on both sides of the lower waveguide layer, the active layer, the upper waveguide layer and the upper confinement layer in a slow axis direction; A first isolation trench and a second isolation trench, wherein the first isolation trench and the second isolation trench both extend along the slow axis direction from the insulating epitaxial layer on one side of the upper confinement layer in the slow axis direction, pass through the upper confinement layer and extend to the insulating epitaxial layer on the other side of the upper confinement layer in the slow axis direction, and the first isolation trench is located on the side of the second isolation trench away from the rear cavity surface; in the cavity length direction, the spacing distance from the first isolation trench to the front cavity surface is much smaller than the spacing distance from the first isolation trench to the rear cavity surface, and the spacing distance from the second isolation trench to the rear cavity surface is much smaller than the spacing distance from the second isolation trench to the front cavity surface.

2. The semiconductor light emitting structure according to claim 1, characterized in that: Also includes: A first insulating filling layer and a second insulating filling layer; wherein the first insulating filling layer is located in the first isolation trench, and the second insulating filling layer is located in the second isolation trench.

3. The semiconductor light emitting structure according to claim 2, characterized in that: The absolute value of the difference between the refractive index of the first insulating filling layer and the refractive index of the upper limiting layer is less than or equal to 0.03; the absolute value of the difference between the refractive index of the second insulating filling layer and the refractive index of the upper limiting layer is less than or equal to 0.

03.

4. The semiconductor light emitting structure according to claim 2, characterized in that: The material of the upper confinement layer includes Si-doped InP; the material of the first insulating filling layer includes Fe-doped InP; and the material of the second insulating filling layer includes Fe-doped InP.

5. The semiconductor light emitting structure according to claim 1, characterized in that: The first isolation groove extends into the upper confinement layer in the fast axis direction and does not extend into the upper waveguide layer; or, the first isolation groove extends into the upper confinement layer and the upper waveguide layer in the fast axis direction and does not extend into the active layer; The second isolation groove extends into the upper confinement layer in the fast axis direction but does not extend into the upper waveguide layer; or the second isolation groove extends into the upper confinement layer and the upper waveguide layer in the fast axis direction but does not extend into the active layer.

6. The semiconductor light emitting structure according to claim 1, characterized in that: The depth dimension of the first isolation groove in the fast axis direction is 1 μm to 6 μm; the depth dimension of the second isolation groove in the fast axis direction is 1 μm to 6 μm.

7. The semiconductor light emitting structure according to claim 1, characterized in that: The width of the first isolation groove in the direction of the cavity length is 10 μm to 20 μm; the width of the second isolation groove in the direction of the cavity length is 10 μm to 20 μm.

8. The semiconductor light emitting structure according to claim 1, characterized in that: The spacing distance between the first isolation groove and the front cavity surface in the cavity length direction is 100 μm to 200 μm; the spacing distance between the second isolation groove and the front cavity surface in the cavity length direction is 100 μm to 200 μm.

9. The semiconductor light emitting structure according to claim 2, characterized in that: Also includes: The front electrode layer is located on a side of the upper limiting layer, the first insulating filling layer and the second insulating filling layer away from the upper waveguide layer.

10. The semiconductor light emitting structure according to claim 9, characterized in that: Also includes: A first insulating dielectric layer, located between the front cavity surface and the first insulating filling layer and between the front electrode layer and the upper limiting layer; and a second insulating dielectric layer, located between the rear cavity surface and the second insulating filling layer and between the front electrode layer and the upper limiting layer.

11. The semiconductor light emitting structure according to any one of claims 1 to 10, characterized in that: The active layer comprises a first portion and a second portion, the first portion is located between the front cavity surface and the first isolation groove along the cavity length direction, and the second portion is located between the rear cavity surface and the second isolation groove along the cavity length direction; Among them, the size of the first part at one end of the front cavity surface in the slow axis direction is larger than the size of the first part at the end away from the front cavity surface along the cavity length direction in the slow axis direction; the size of the second part at one end of the rear cavity surface in the slow axis direction is larger than the size of the second part at the end away from the rear cavity surface along the cavity length direction in the slow axis direction.

12. The semiconductor light emitting structure according to claim 11, characterized in that: In the direction from the first isolation groove to the front cavity surface along the cavity length direction, the size of the first part along the slow axis direction increases gradually; In a direction from the second isolation trench to the rear cavity surface along the cavity length direction, a size of the second portion along the slow axis direction increases gradually.

13. The semiconductor light emitting structure according to claim 11, characterized in that: The size of the first part at one end of the front cavity surface in the slow axis direction is 15 μm to 25 μm; the size of the end of the first part away from the front cavity surface along the cavity length direction in the slow axis direction is 8 μm to 12 μm; The size of the second part at one end of the back cavity surface in the slow axis direction is 15 μm to 25 μm; the size of the second part at the end away from the back cavity surface along the cavity length direction in the slow axis direction is 8 μm to 12 μm.

14. A method for preparing a semiconductor light-emitting structure, characterized in that: include: providing a semiconductor substrate layer; forming a lower confinement layer on the semiconductor substrate layer; A lower waveguide layer, an active layer, an upper waveguide layer and an upper limit layer are sequentially stacked on a side of a portion of the lower limit layer away from the semiconductor substrate layer; the lower waveguide layer, the active layer, the upper waveguide layer and the upper limit layer have a front cavity surface and a rear cavity surface that are opposite to each other in the cavity length direction; forming an insulating epitaxial layer, wherein the insulating epitaxial layer is located on a side of the lower confinement layer away from the semiconductor substrate layer and on both sides of the lower waveguide layer, the active layer, the upper waveguide layer and the upper confinement layer in a slow axis direction; A first isolation trench and a second isolation trench are formed, wherein the first isolation trench and the second isolation trench both extend along the slow axis direction from the upper limiting layer in the insulating epitaxial layer on one side of the slow axis direction, pass through the upper limiting layer and extend to the upper limiting layer in the insulating epitaxial layer on the other side of the slow axis direction, and the first isolation trench is located on the side of the second isolation trench away from the rear cavity surface; in the cavity length direction, the spacing distance from the first isolation trench to the front cavity surface is much smaller than the spacing distance from the first isolation trench to the rear cavity surface, and the spacing distance from the second isolation trench to the rear cavity surface is much smaller than the spacing distance from the second isolation trench to the front cavity surface.

15. The method for preparing a semiconductor light emitting structure according to claim 14, characterized in that: Also includes: forming a first insulating filling layer in the first isolation trench; A second insulating filling layer is formed in the second isolation trench.

16. The method for preparing a semiconductor light emitting structure according to claim 15, characterized in that: The material of the upper confinement layer includes Si-doped InP; the material of the first insulating filling layer includes Fe-doped InP; and the material of the second insulating filling layer includes Fe-doped InP.

17. The method for preparing a semiconductor light emitting structure according to claim 15, characterized in that: Also includes: A first insulating dielectric layer is formed on a side of the upper limiting layer facing away from the active layer between the front cavity surface and the first insulating filling layer, and a second insulating dielectric layer is formed on a side of the upper limiting layer facing away from the active layer between the back cavity surface and the second insulating filling layer; A front electrode layer is formed on a side of the upper limiting layer, the first insulating dielectric layer, the second insulating dielectric layer, the first insulating filling layer, and the second insulating filling layer away from the upper waveguide layer.

18. The method for preparing a semiconductor light emitting structure according to claim 14, characterized in that: Forming the active layer includes forming a first portion and a second portion, wherein the first portion is located between the front cavity surface and the first isolation groove along the cavity length direction, and the second portion is located between the rear cavity surface and the second isolation groove along the cavity length direction; Among them, the size of the first part at one end of the front cavity surface in the slow axis direction is larger than the size of the first part at the end away from the front cavity surface along the cavity length direction in the slow axis direction; the size of the second part at one end of the rear cavity surface in the slow axis direction is larger than the size of the second part at the end away from the rear cavity surface along the cavity length direction in the slow axis direction.

Images