Novel audio amplifier circuit

Abstract

The invention discloses a novel audio amplifier circuit, and relates to the field of audio amplifiers, and the circuit comprises a clock generation circuit, a non-overlapping clock circuit, a level shift circuit, a charge pump circuit and an audio drive circuit which are connected in sequence; the clock generation circuit is used for generating a clock signal with a fixed frequency, the clock signal generates two phase clock signals through the non-overlapping clock circuit, and the two phase clock signals generate four shifted clock signals through the level shift circuit. The charge pump circuit generates voltage signals to the audio drive circuit through the four shifted clock signals, and the audio drive circuit generates output voltage to drive the audio loudspeaker. The application can improve the range of the output voltage and save the cost.

Description

Technical Field

[0001] The present application relates to the field of audio amplifiers, and in particular to a novel audio amplifier circuit. Background Art

[0002] Traditional audio amplifier circuits such as Figure 1 As shown, the audio input is amplified by the audio driver circuit and then drives the speaker. The output voltage Out is usually VDD / 2. CL is a DC blocking capacitor to prevent the output voltage Out from having a large DC current to the ground. CL often needs to be very large, ranging from 100uF to 1000uF, so the cost is relatively high. However, if CL is not added, Out will have a large bias current to the ground. Summary of the invention

[0003] The purpose of this application is to provide a novel audio amplifier circuit, which can increase the range of output voltage and save costs.

[0004] To achieve the above-mentioned object, the present application provides a novel audio amplifier circuit, comprising: a clock generation circuit, a non-overlapping clock circuit, a level shift circuit, a charge pump circuit and an audio driving circuit connected in sequence;

[0005] The clock generating circuit is used to generate a clock signal of a fixed frequency. The clock signal generates two-phase clock signals through the non-overlapping clock circuit. The two-phase clock signals generate four shifted clock signals through the level shifting circuit. The charge pump circuit generates a voltage signal to the audio driving circuit through the four shifted clock signals. The audio driving circuit generates an output voltage to drive the audio speaker.

[0006] According to the specific embodiments provided in this application, this application has the following technical effects:

[0007] (1) The novel audio amplifier circuit provided in the present application eliminates the need for CL capacitors, thus reducing costs.

[0008] (1) The novel audio amplifier circuit provided in the present application generates four shifted clock signals through a level shift circuit, so that the charge pump circuit generates a -VCC voltage signal to the audio driving circuit, thereby making the audio driving circuit generate an output voltage ranging from -VCC to VCC, thereby improving the output power. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0010] Figure 1 It is a schematic diagram of the structure of a traditional audio amplifier circuit;

[0011] Figure 2 A schematic diagram of the structure of a novel audio amplifier circuit provided in one embodiment of the present application;

[0012] Figure 3 It is a structural schematic diagram of a clock generating circuit;

[0013] Figure 4 is a timing diagram of the clock signal CK, the phase clock signal CK1, and the phase clock signal CK2;

[0014] Figure 5 is a schematic diagram of the structure of a non-overlapping clock circuit;

[0015] Figure 6 is a schematic diagram of the structure of a level shift circuit;

[0016] Figure 7 is a timing diagram of four shifted clock signals P1-P4;

[0017] Figure 8 is a schematic diagram of the structure of a charge pump circuit;

[0018] Fig. 9 It is a structural diagram of the audio driving circuit. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0020] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0021] In an exemplary embodiment, Figure 2 As shown, a novel audio amplifier circuit is provided, comprising: a clock generating circuit, a non-overlapping clock circuit, a level shifting circuit, a charge pump circuit and an audio driving circuit connected in sequence.

[0022] The clock generating circuit is used to generate a fixed frequency clock signal CK. The clock signal CK generates two phase clock signals CK1 and CK2 through a non-overlapping clock circuit. CK1 and CK2 generate four shifted clock signals P1, P2, P3, and P4 through a level shifting circuit. The charge pump circuit generates a voltage signal -VCC through P1-P4 to the audio driving circuit. The audio driving circuit generates an output voltage Out to drive the audio speaker.

[0023] In a specific embodiment, Figure 3 As shown, the clock generating circuit includes: a current source I1, a capacitor C1, a comparator Comp, a switch tube SW1 and a frequency dividing circuit. The output end of the current source I1 is respectively connected to one end of the capacitor C1, the drain of the switch tube SW and the positive input end of the comparator Comp, the other end of the capacitor C1 and the source of the switch tube SW are both grounded, the inverting input end of the comparator Comp inputs a reference level, the output end of the comparator Comp is respectively connected to the gate of the switch tube SW1 and the input end of the frequency dividing circuit, and the output end of the frequency dividing circuit is connected to the non-overlapping clock circuit.

[0024] When CK is low, I1 will charge C1. When the voltage VIP = VREF, CK becomes high, VIP is pulled low, and then CK becomes high. This process is repeated to generate the clock signal CK. The frequency division circuit is divided by N, and the period T of the clock signal CK is approximately N is the frequency division ratio of the frequency division circuit, c1 is the capacitance value of the capacitor C1, i1 is the current value of the current source I1, and VREF is the reference level.

[0025] In a specific embodiment, Figure 5 As shown, the non-overlapping clock circuit includes: inverter INV1, inverter INV2, inverter INV3, inverter INV4, inverter INV5, inverter INV6, inverter INV7, a first delay unit group, a second delay unit group, a NAND gate NAND1 and a NAND gate NAND2.

[0026] The input end of the inverter INV1 is connected to the output end of the frequency dividing circuit, the output end of the inverter INV1 is respectively connected to the input end of the inverter INV2 and the first input end of the NAND gate NAND1, the second input end of the NAND gate NAND1 is respectively connected to the output end of the inverter INV5 and the input end of the inverter INV6, the output end of the NAND gate NAND1 is connected to the input end of the first delayed unit group, the output end of the first delayed unit group is respectively connected to the input end of the inverter INV3 and the first input end of the NAND gate NAND2 The output end of the inverter INV3 is connected to the input end of the inverter INV4, and the output end of the inverter INV4 is connected to the level shift circuit; the output end of the inverter INV2 is connected to the second input end of the NAND gate NAND2, the output end of the NAND gate NAND2 is connected to the input end of the second delay unit group, the output end of the second delay unit group is connected to the input end of the inverter INV5, the output end of the inverter INV6 is connected to the input end of the inverter INV7, and the output end of the inverter INV7 is connected to the level shift circuit.

[0027] Specifically, the first delay unit group includes: a delay unit DLY1 and a delay unit DLY2, and the second delay unit group includes: a delay unit DLY3 and a delay unit DLY4.

[0028] The output end of the NAND gate NAND1 is connected to the input end of the delay unit DLY1, the output end of the delay unit DLY1 is connected to the input end of the delay unit DLY2, the output end of the delay unit DLY2 is connected to the input end of the inverter INV3 and the first input end of the NAND gate NAND2 respectively. The output end of the NAND gate NAND2 is connected to the input end of the delay unit DLY3, the output end of the delay unit DLY3 is connected to the input end of the delay unit DLY4, and the output end of the delay unit DLY4 is connected to the input end of the inverter INV5.

[0029] The non-overlapping clock circuit generates two-phase clocks CK1 and CK2, which are provided to the charge pump circuit through the level shift circuit. When CK changes from low level to high level, after passing through the delay units DLY1 and DLY2, CK1 changes from low level to high level, and controls NAND2 at the same time. CK passes through the four delay units DLY1, DLY2, DLY3, and DLY4 to generate CK2. When CK changes from high level to low level, after passing through the delay units DLY3 and DLY4, CK2 changes from high level to low level. At the same time, the INV5 output controls NAND1, and CK passes through the four delay units DLY3, DLY4, DLY1, and DLY2 to generate CK1. The timing diagram of CK, CK1, and CK2 is shown in the figure. Figure 4 shown.

[0030] In a specific implementation, Figure 6As shown, the level shift circuit includes: a first level shift circuit and a second level shift circuit.

[0031] The first level shift circuit includes an inverter INV8 , an inverter INV9 , an inverter INV10 , a transistor M1 , a transistor M2 , a transistor M3 , a transistor M4 , a transistor M5 , and a transistor M6 .

[0032] The input end of the inverter INV8 is connected to the output end of the inverter INV4, the output end of the inverter INV8 is respectively connected to the input end of the inverter INV9, the source of the transistor M2 and the gate of the transistor M1, the output end of the inverter INV9 is respectively connected to the input end of the inverter INV10, the gate of the transistor M2 and the source of the transistor M1, and the output end of the inverter INV10 is connected to the charge pump circuit. The drain of the transistor M2 is connected to the drain of the transistor M4, the gate of the transistor M4 and the gate of the transistor M3 are both grounded, the source of the transistor M4 is respectively connected to the drain of the transistor M6 and the gate of the transistor M5, the gate of the transistor M6 is respectively connected to the source of the transistor M3 and the drain of the transistor M5, the source of the transistor M6 is connected to the source of the transistor M5, and the drain of the transistor M3 is respectively connected to the drain of the transistor M1 and the charge pump circuit.

[0033] The second level shift circuit includes an inverter INV11, an inverter INV12, an inverter INV13, an inverter INV14, an inverter INV15, a transistor M7, a transistor M8, a transistor M9, a transistor M10, a transistor M11 and a transistor M12.

[0034] The input end of the inverter INV11 is connected to the output end of the inverter INV7, the output end of the inverter INV11 is respectively connected to the input end of the inverter INV12, the source of the transistor M8 and the gate of the transistor M7, the output end of the inverter INV12 is respectively connected to the input end of the inverter INV13, the gate of the transistor M8 and the source of the transistor M7, and the output end of the inverter INV13 is connected to the charge pump circuit. The drain of transistor M8 is connected to the drain of transistor M10, the gate of transistor M10 and the gate of transistor M9 are both grounded, the source of transistor M10 is respectively connected to the input end of inverter INV14, the drain of transistor M12 and the gate of transistor M11, the gate of transistor M12 is respectively connected to the source of transistor M9, the drain of transistor M11 and the input end of inverter INV15, the source of transistor M12 is respectively connected to the power supply end of inverter INV14, the source of transistor M11 and the power supply end of inverter INV15, the drain of transistor M9 is connected to the drain of transistor M7, and the output end of inverter INV15 is connected to the charge pump circuit.

[0035] The non-overlapping clock output CK1 is sent to the first level shift circuit to generate P1 and P2 to control the switch tubes SW2 and SW3 of the charge pump circuit respectively. CK2 is passed through the first level shift circuit to generate P3 and P4 to control the switch tubes SW4 and SW5 of the charge pump circuit.

[0036] The first level shift circuit: when CK1 is a low level 0, after the inverters INV8, INV9, and INV10, P1 outputs a high level VCC, M1 and M6 are turned off, M2, M3, M4, and M5 are turned on, and P2 outputs a low level -VCC; when CK1 is a high level VCC, after the inverters INV8, INV9, and INV10, P1 outputs a low level 0, M2 and M5 are turned off, M1, M3, M4, and M6 are turned on, and P2 outputs a high level VCC.

[0037] The second level shift circuit: when CK2 is a high level VCC, after passing through the inverters INV11, INV12, and INV13, P3 is a low level 0, M8 and M11 are turned off, M7, M9, M10, and M12 are turned on, and after passing through the inverter INV15, P4 is a low level -VCC; when CK2 is a low level 0, after passing through the inverters INV11, INV12, and INV13, P3 is a high level VCC, M7 and M12 are turned off, M8, M9, M10, and M11 are turned on, and after passing through INV15, P4 is a high level 0.

[0038] In a specific embodiment, Figure 8 As shown, the charge pump circuit includes: a switch tube SW2, a switch tube SW3, a switch tube SW4, a switch tube SW5, a capacitor CF and a capacitor Co.

[0039] The gate of the switch tube SW2 is connected to the output end of the inverter INV10, the drain of the switch tube SW2 is connected to the power supply, the source of the switch tube SW2 is respectively connected to the drain of the switch tube SW4 and one end of the capacitor CF, the gate of the switch tube SW4 is connected to the output end of the inverter INV13, the source of the switch tube SW4 is grounded, the other end of the capacitor CF is respectively connected to the source of the switch tube SW3 and the drain of the switch tube SW5, the gate of the switch tube SW3 is connected to the drain of the transistor M3, the drain of the switch tube SW3 is grounded, the gate of the switch tube SW5 is connected to the output end of the inverter INV15, the source of the switch tube SW5 is connected to one end of the capacitor Co, and the other end of the capacitor Co is grounded.

[0040] like Figure 7As shown in the figure, when P1=0, P2=VCC, SW2 and SW3 will be turned on to charge capacitor CF. At this time, P3=0, P4=-VCC, and SW4 and SW5 will be turned off. When P3=VCC, P4=0, SW4 and SW5 will be turned on, SW2 and SW3 will be turned off, and the charge of CF will be transferred to capacitor Co. As time goes by, Vo=-VCC. The output voltage Out of the audio driver circuit ranges from -VCC to VCC.

[0041] In a specific embodiment, Fig. 9 As shown, the audio driving circuit is a constant static current class AB audio driving circuit. When the positive input voltage of the operational amplifier OP1 is higher than the negative voltage, the voltage Vbp increases, the source voltage of the transistor M15 increases, and the drain voltage of the transistor M13 (i.e., the positive voltage of OP1) decreases. Therefore, the loop composed of OP1, M15, I2, M13, and I7 locks the drain voltage of M13 at 0V. When the positive voltage of the operational amplifier OP2 increases, the voltage Vbn increases, the source voltage of the transistor M14 increases, and the drain voltage of the transistor M16 (i.e., the positive voltage of OP2) decreases. Therefore, the loop composed of OP2, M14, I8, M16, and I3 locks the drain voltage of M16 at 0V. The gate of transistor M18 is grounded. When there is no audio input signal, Out passes through the negative feedback network composed of R2, M17, M19, M20, M21, M22, MP1, and MP2, and the output of Out is clamped at 0V. The gate-source voltage difference of MP2 is VGS_MP2 = VGS_M16 + VGS_M14 - VGS_M22 = VGS_M16. Here, adjusting the transistor size can make VGS_M14 = VGS_M22. The voltage difference between the source and gate of MP1 is VSG_MP1 = VSG_M13 + VSG_M15 - VSG_M21 = VSG_M13. Here, adjusting the transistor size can make VSG_M15 = VSG_M21. In normal static operation, the drain voltage of MP1 and MP2 is 0V, the operating voltage of MP1 and M13 is consistent, and the operating voltage of MP2 and M16 is consistent, so the currents of I7 and I3 can be accurately mirrored. The static current flowing through the power tubes MP1 and MP2 is n2*I / 3 or n1*I7, where: Adjust the parameters so that n2*I3=n1*I7, and the entire AB class drive current is I2+I3+I4+I5+I6+I7+I8+n2*I3, which is a constant value. When the input audio has a signal Vin, through the feedback network composed of C1, operational amplifier OP3, R1, and R2, Out=-R2 / R1*Vin.

[0042] The novel audio amplifier circuit provided by the present application has a charge pump circuit that generates a -VCC voltage, which is supplied to the audio driving circuit, and the output voltage is 0. One end of the audio speaker can be directly grounded by direct current. The output voltage Out of the audio driving circuit ranges from -VCC to VCC.

[0043] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0044] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A novel audio amplifier circuit, characterized in that: include: A clock generation circuit, a non-overlapping clock circuit, a level shift circuit, a charge pump circuit and an audio driving circuit connected in sequence; The clock generating circuit is used to generate a clock signal of a fixed frequency. The clock signal generates two-phase clock signals through the non-overlapping clock circuit. The two-phase clock signals generate four shifted clock signals through the level shifting circuit. The charge pump circuit generates a voltage signal to the audio driving circuit through the four shifted clock signals. The audio driving circuit generates an output voltage to drive the audio speaker.

2. The novel audio amplifier circuit according to claim 1 is characterized in that: The clock generating circuit comprises: a current source I1, a capacitor C1, a comparator Comp, a switch tube SW1 and a frequency dividing circuit; The output end of the current source I1 is respectively connected to one end of the capacitor C1, the drain of the switch tube SW and the non-inverting input end of the comparator Comp, the other end of the capacitor C1 and the source of the switch tube SW are grounded, the reference level is input to the inverting input end of the comparator Comp, the output end of the comparator Comp is respectively connected to the gate of the switch tube SW1 and the input end of the frequency dividing circuit, and the output end of the frequency dividing circuit is connected to the non-overlapping clock circuit.

3. The novel audio amplifier circuit according to claim 2 is characterized in that: The period of the clock signal is T, Wherein, N is the frequency division ratio of the frequency division circuit, c1 is the capacitance value of the capacitor C1, i1 is the current value of the current source I1, and VREF is the reference level.

4. The novel audio amplifier circuit according to claim 2 is characterized in that: The non-overlapping clock circuit includes: an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, an inverter INV6, an inverter INV7, a first delay unit group, a second delay unit group, a NAND gate NAND1 and a NAND gate NAND2; The input end of the inverter INV1 is connected to the output end of the frequency dividing circuit, the output end of the inverter INV1 is respectively connected to the input end of the inverter INV2 and the first input end of the NAND gate NAND1, the second input end of the NAND gate NAND1 is respectively connected to the output end of the inverter INV5 and the input end of the inverter INV6, the output end of the NAND gate NAND1 is connected to the input end of the first delayed unit group, and the output end of the first delayed unit group is respectively connected to the input end of the inverter INV3 and the first input end of the NAND gate NAND2. The output end of the inverter INV3 is connected to the input end of the inverter INV4, and the output end of the inverter INV4 is connected to the level shift circuit; the output end of the inverter INV2 is connected to the second input end of the NAND gate NAND2, and the output end of the NAND gate NAND2 is connected to the input end of the second delay unit group, the output end of the second delay unit group is connected to the input end of the inverter INV5, the output end of the inverter INV6 is connected to the input end of the inverter INV7, and the output end of the inverter INV7 is connected to the level shift circuit.

5. The novel audio amplifier circuit according to claim 4 is characterized in that: The first delay unit group includes: a delay unit DLY1 and a delay unit DLY2, and the second delay unit group includes: a delay unit DLY3 and a delay unit DLY4; The output end of the NAND gate NAND1 is connected to the input end of the delay unit DLY1, the output end of the delay unit DLY1 is connected to the input end of the delay unit DLY2, and the output end of the delay unit DLY2 is respectively connected to the input end of the inverter INV3 and the first input end of the NAND gate NAND2; The output end of the NAND gate NAND2 is connected to the input end of the delay unit DLY3 , the output end of the delay unit DLY3 is connected to the input end of the delay unit DLY4 , and the output end of the delay unit DLY4 is connected to the input end of the inverter INV5 .

6. The novel audio amplifier circuit according to claim 5, characterized in that: The level shift circuit includes: a first level shift circuit and a second level shift circuit.

7. The novel audio amplifier circuit according to claim 6, characterized in that: The first level shift circuit includes: an inverter INV8, an inverter INV9, an inverter INV10, a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5 and a transistor M6; The input end of the inverter INV8 is connected to the output end of the inverter INV4, the output end of the inverter INV8 is respectively connected to the input end of the inverter INV9, the source of the transistor M2 and the gate of the transistor M1, the output end of the inverter INV9 is respectively connected to the input end of the inverter INV10, the gate of the transistor M2 and the source of the transistor M1, and the output end of the inverter INV10 is connected to the charge pump circuit; The drain of the transistor M2 is connected to the drain of the transistor M4, the gate of the transistor M4 and the gate of the transistor M3 are both grounded, the source of the transistor M4 is respectively connected to the drain of the transistor M6 and the gate of the transistor M5, the gate of the transistor M6 is respectively connected to the source of the transistor M3 and the drain of the transistor M5, the source of the transistor M6 is connected to the source of the transistor M5, and the drain of the transistor M3 is respectively connected to the drain of the transistor M1 and the charge pump circuit.

8. The novel audio amplifier circuit according to claim 7, characterized in that: The second level shift circuit includes: an inverter INV11, an inverter INV12, an inverter INV13, an inverter INV14, an inverter INV15, a transistor M7, a transistor M8, a transistor M9, a transistor M10, a transistor M11 and a transistor M12; The input end of the inverter INV11 is connected to the output end of the inverter INV7, the output end of the inverter INV11 is respectively connected to the input end of the inverter INV12, the source of the transistor M8 and the gate of the transistor M7, the output end of the inverter INV12 is respectively connected to the input end of the inverter INV13, the gate of the transistor M8 and the source of the transistor M7, and the output end of the inverter INV13 is connected to the charge pump circuit; The drain of the transistor M8 is connected to the drain of the transistor M10, the gate of the transistor M10 and the gate of the transistor M9 are both grounded, the source of the transistor M10 is respectively connected to the input end of the inverter INV14, the drain of the transistor M12 and the gate of the transistor M11, the gate of the transistor M12 is respectively connected to the source of the transistor M9, the drain of the transistor M11 and the input end of the inverter INV15, the source of the transistor M12 is respectively connected to the power supply end of the inverter INV14, the source of the transistor M11 and the power supply end of the inverter INV15, the drain of the transistor M9 is connected to the drain of the transistor M7, and the output end of the inverter INV15 is connected to the charge pump circuit.

9. The novel audio amplifier circuit according to claim 8, characterized in that: The charge pump circuit includes: a switch tube SW2, a switch tube SW3, a switch tube SW4, a switch tube SW5, a capacitor CF and a capacitor Co; The gate of the switch tube SW2 is connected to the output end of the inverter INV10, the drain of the switch tube SW2 is connected to the power supply, the source of the switch tube SW2 is respectively connected to the drain of the switch tube SW4 and one end of the capacitor CF, the gate of the switch tube SW4 is connected to the output end of the inverter INV13, the source of the switch tube SW4 is grounded, the other end of the capacitor CF is respectively connected to the source of the switch tube SW3 and the drain of the switch tube SW5, the gate of the switch tube SW3 is connected to the drain of the transistor M3, the drain of the switch tube SW3 is grounded, the gate of the switch tube SW5 is connected to the output end of the inverter INV15, the source of the switch tube SW5 is connected to one end of the capacitor Co, and the other end of the capacitor Co is grounded.

10. The novel audio amplifier circuit according to claim 6, characterized in that: The audio driving circuit is a constant static current class AB audio driving circuit.

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