Implementation Method of a Filter Saving Computing Resources Based on FPGA

Abstract

This application relates to the field of digital signal processing and discloses a method for implementing a filter that saves computing resources based on FPGA: reducing redundant calculations by analyzing coefficient symmetry and optimizing the multiplier configuration; designing a timing scheduling model to dynamically schedule resources and avoid calculation conflicts; combining load prediction and real-time scheduling, and dynamically adjusting computing resources according to load changes through an adaptive resource allocation algorithm, effectively improving computing efficiency and reducing power consumption; a system for implementing a filter that saves computing resources based on FPGA: a multiplier resource management module, a load prediction module, and a scheduling optimization module. By combining filter coefficient symmetry analysis, timing scheduling, load prediction, and an adaptive resource allocation algorithm, the present invention optimizes the multiplier configuration, significantly improves the utilization rate of hardware resources and computing efficiency; compared with the prior art, the present invention effectively reduces power consumption, flexibly responds to load fluctuations, ensures the efficient operation of the system, and improves energy efficiency.

Description

Technical Field

[0001] The present invention relates to the field of digital signal processing, and specifically to an implementation method of a filter for saving computing resources based on FPGA. Background Art

[0002] In the prior art, FPGA (Field Programmable Gate Array) is widely used in digital signal processing, especially in filter design. However, traditional digital filter design methods based on FPGA often have the problem of excessive resource consumption. Especially when designing high-precision filters, each filter coefficient usually needs to be processed by an independent multiplier, which leads to excessive consumption of hardware resources. For example, when designing an 8th-order FIR filter, each coefficient is processed separately, resulting in a large number of multipliers needed to execute these operations in parallel. In this way, the number of multipliers is directly proportional to the filter order, and the hardware overhead of the system also increases accordingly.

[0003] On the other hand, filter design in the prior art mostly relies on static hardware resource configuration. This means that the computing tasks and hardware resource allocation are determined at the design stage and cannot be flexibly adjusted according to the change of data flow in actual applications. For example, when the input data flow is low, traditional designs cannot dynamically reduce unnecessary computing tasks, resulting in waste of resources and power consumption. On the contrary, when the data flow increases significantly, the system may not be able to quickly schedule enough computing resources, thus affecting the computing performance and leading to processing delay and real-time problems.

[0004] In addition, most traditional resource scheduling and power consumption optimization methods rely on preset hardware configurations and lack the ability to respond to load fluctuations in real time. This makes it possible that when the system load fluctuates violently, the hardware resources may be misconfigured, resulting in performance degradation or increased power consumption. Existing scheduling strategies often fail to combine the characteristics of the input data flow and real-time load changes. Therefore, when dealing with sudden loads and changes in data flow density, they often cannot achieve the best resource allocation and power consumption optimization effects. This shortcoming further exacerbates the tension of system resources under high load and the waste of resources under low load.

[0005] Therefore, the present invention proposes an implementation method of a filter for saving computing resources based on FPGA to solve the deficiencies of the prior art. Summary of the Invention

[0006] Aiming at the deficiencies of the prior art, the present invention provides an implementation method of a filter for saving computing resources based on FPGA, which solves the problems of excessive hardware resource consumption, insufficient reuse of computing resources, and inability to dynamically adjust resource configuration during load fluctuations in filter design.

[0007] To achieve the above object, the present invention is realized through the following technical solutions: An implementation method of a filter that saves computing resources based on FPGA, comprising the following steps:

[0008] S1. Analyze the symmetry of the filter coefficients, identify the symmetric coefficient part, and reduce redundant multiplication operations through symmetry;

[0009] S2. Based on symmetry, obtain the calculation results of the data in the filter calculation process through a shared calculation path, thereby reducing the number of required multipliers;

[0010] S3. Design a timing scheduling model, analyze the timing characteristics of the input data stream, and dynamically schedule the operation of the multiplier to avoid calculation conflicts and reuse the multiplier;

[0011] S4. Predict the system load according to the change of the input data stream, adjust the multiplier configuration using the load prediction model, and perform resource allocation through the optimal scheduling algorithm;

[0012] S5. Combine load prediction and real-time scheduling, and dynamically adjust the multiplier configuration through the adaptive resource allocation algorithm, so that the system can adjust the computing resources according to the load change.

[0013] Preferably, in the symmetry analysis step, the data of the filter coefficients is calculated through mathematical derivation, and the calculation results are shared through symmetry.

[0014] Preferably, the mathematical derivation step includes:

[0015] Identify the symmetric coefficients in the filter, and since the symmetric coefficients are the same as the identified coefficients, deduce the values of other coefficients by calculating the results of the identified coefficients.

[0016] Preferably, the timing scheduling model controls the multiplier through a scheduling matrix to determine whether it is activated at time , where , and only one multiplier is activated in each clock cycle.

[0017] Preferably, the objective function of the timing scheduling model is:

[0018] ;

[0019] where represents whether the multiplier is activated in the clock cycle . If it is activated, then , otherwise ; is the total number of calculation cycles, that is, the number of clock cycles required for filter calculation; is the number of multipliers used.

[0020] Preferably, the load prediction model is based on the density function of the input data stream and the amount of computation to perform load prediction, and the load prediction formula is:

[0021] ;

[0022] where represents the system load at time , represents the change in the density function of the input data stream at time , is the data traffic transmitted at time ; represents the weighted sum of the total computation amounts of all multipliers at time , is the weighting coefficient used to adjust the impact of the computation amount on the total load, represents the computation amount processed by multiplier at time , is the number of multipliers.

[0023] Preferably, the load prediction model uses the recursive least squares method to recursively predict the system load and predict the load change at future times, providing a basis for subsequent resource scheduling.

[0024] Preferably, the optimal scheduling algorithm dynamically adjusts resource allocation by solving the following optimization problem:

[0025] ;

[0026] where represents the power consumption of multiplier at time ; represents the total number of clock cycles in the filter calculation process; represents the number of multipliers used in the system; represents the total load of the system at time ; represents the maximum load allowed by the system at time .

[0027] Preferably, the adaptive resource allocation algorithm combines load prediction and real-time scheduling. When a change in data traffic is predicted, it dynamically adjusts the multiplier configuration according to the input data traffic and load change, providing sufficient computing resources in high-load situations and reducing the use of computing resources in low-load situations.

[0028] The present invention also provides an implementation system of a filter that saves computing resources based on FPGA, including:

[0029] A multiplier resource management module for dynamically scheduling multiplier resources according to the symmetry analysis of filter coefficients and the timing characteristics of the input data stream;

[0030] A load prediction module for predicting the system load based on the change of input data traffic and adjusting resource allocation according to the load change;

[0031] A scheduling optimization module for dynamically adjusting the multiplier configuration through an optimal scheduling algorithm.

[0032] The present invention provides an implementation method of a filter that saves computing resources based on FPGA. It has the following beneficial effects:

[0033] 1. The present invention adopts a technical solution that combines the symmetry analysis of filter coefficients with timing scheduling. By analyzing the symmetry of filter coefficients and reusing the calculation path, redundant multiplication operations are reduced, achieving the effect of significantly reducing the consumption of hardware resources; compared with the prior art solution of allocating independent multipliers to each coefficient, the present invention avoids repeated calculations by sharing the calculation path, optimizes the utilization of hardware resources, significantly reduces power consumption, and improves system efficiency.

[0034] 2. The present invention combines the timing characteristics of the input data stream and adopts a technical solution of dynamically scheduling multiplier resources. Through real-time scheduling and reuse mechanisms, the utilization efficiency of multipliers is maximized; compared with the static hardware resource configuration solution in the prior art, the present invention can more flexibly adapt to different data traffic changes, avoid multiplier idleness, thereby improving the overall utilization rate of computing resources and reducing unnecessary hardware overhead.

[0035] 3. The present invention uses a technical solution that combines a load prediction model with real-time scheduling optimization, enabling the system to predict future load conditions based on the change of the input data stream and adjust the multiplier configuration accordingly, achieving higher computing performance and lower power consumption; compared with the prior art solutions that rely on static or preset configurations, the present invention can dynamically adjust computing resources according to load changes, solve the problems of excessive or insufficient resources during load fluctuations, and improve the adaptive ability and energy efficiency of the system.

[0036] 4. The present invention introduces an adaptive resource allocation algorithm to automatically adjust the multiplier configuration when the load changes. By real-time monitoring and optimizing the multiplier activation state, the effect of reducing power consumption while ensuring efficient computing is achieved; compared with the prior art solutions with fixed resource allocation, the present invention can respond to the change of the input data stream in real time, flexibly configure computing resources, reduce unnecessary power consumption, and ensure the efficient operation of the system under different load conditions. Brief Description of the Drawings

[0037] Figure 1 is a flowchart of the method of the present invention;

[0038] Figure 2 is a system architecture diagram of the present invention. Detailed Embodiment

[0039] Next, in combination with the accompanying drawings of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0040] Please refer to Figure 1 , the embodiments of the present invention provide a method for implementing a filter that saves computing resources based on FPGA, including the following steps:

[0041] S1. Analyze the symmetry of the coefficients of the filter, identify the symmetric part of the coefficients, and reduce redundant multiplication operations through symmetry;

[0042] In this embodiment, step S1 involves reducing redundant calculations by analyzing the symmetry of the filter coefficients; the symmetry of the filter coefficients is usually an important characteristic in digital filters; by identifying and utilizing this symmetry, the calculation path can be significantly optimized, and the required hardware resources, especially the number of multipliers, can be reduced; this step simplifies the calculation process by identifying the symmetric part, thereby achieving the purpose of saving computing resources.

[0043] Generally, FIR (Finite Impulse Response) filters and IIR (Infinite Impulse Response) filters often have symmetry in their coefficient matrices; in FIR filters with symmetric coefficients, the coefficients of the filter satisfy the following relationship:

[0044] ;

[0045] wherein, is the order of the filter, is the index of the coefficient; through this symmetry relationship, we can deduce that the coefficients in the second half of the filter are the mirror images of the coefficients in the first half, so the multiplication operation results in the second half are redundant.

[0046] Specifically, in traditional filter calculations, assuming we have coefficients, then we need to calculate multiplication operations to process each input data; considering symmetry, actually only the first The product of coefficients, and then The product of coefficients can be obtained by reusing the calculation result of the previous ; In this way, half of the traditional computational amount can be saved.

[0047] For example, consider an 8th-order FIR filter with coefficients , and satisfying the symmetry condition (that is ); Then, we only need to calculate the product of the first 4 coefficients and the input signal , and the rest can be directly obtained by sharing the calculation path;

[0048] For example, in the example of the above 8th-order filter, due to symmetry, we only need to calculate the product of the first 4 coefficients , and the last 4 coefficients can be directly obtained by sharing the calculation path.

[0049] Among them, represents the input data stream at time , is the index of discrete time.

[0050] Specifically, in some embodiments, to achieve this optimization, we can first scan the coefficients of the filter, identify the subset of all symmetric coefficients, and share the calculation paths of these symmetric coefficients; for example, we calculate the product of the first coefficients, and the product of the last coefficients is directly obtained through the already calculated result; by this method, we save the number of multipliers.

[0051] As an option, by introducing a parallel computing structure of hardware, we can achieve the reuse of the calculation of the symmetric coefficient part; for example, in the FPGA hardware design, we can configure the multiplier so that the first half and the second half of the coefficients in the calculation process alternately use the same multiplier, thereby further reducing the consumption of hardware resources.

[0052] In the present invention, as an option, symmetry analysis can be applied to more complex filter designs, including higher-order FIR filters or IIR filters with complex coefficients; for higher-order filters, the reuse strategy of the calculation path can be achieved through more hardware parallelization designs, further reducing the demand for multipliers; by designing a more complex hardware architecture, such as making multiple multipliers work in parallel and using a shared calculation path, more multiplier reuse can be achieved, thereby saving hardware resources and power consumption.

[0053] S2. Based on symmetry, the calculation results of data in the filter calculation process are obtained through a shared calculation path, thereby reducing the number of required multipliers;

[0054] Step S2 in this embodiment further optimizes the filter calculation process and reduces the consumption of hardware resources; specifically, by utilizing the symmetry of the filter coefficients, this step not only reduces the number of multipliers but also further improves the calculation efficiency; the core idea of this step is to avoid repeated calculations for the second half by reusing the calculation results of the first half.

[0055] In the aforementioned step S1, by analyzing the symmetry of the filter coefficients, the calculation amount of the filter has been halved; since the coefficients of many FIR filters are symmetric, that is, they satisfy the relationship, where is the order of the filter, , so we can share the calculation results of these symmetric coefficients in hardware, which can avoid repeated calculations and thus reduce the number of required multipliers.

[0056] Generally, in the filter calculation process, the traditional method requires calculating the product of each coefficient and the input data and then accumulating them; but based on the symmetry analysis, we only need to calculate a part of the filter coefficients, and the calculation results of the other parts can be obtained by reusing the calculation of the first half, thereby reducing the demand for hardware resources; especially when the filter order is relatively high, the advantage of symmetry is more obvious.

[0057] In this embodiment, for a FIR filter with symmetric coefficients, assuming its coefficients are , where is the order of the filter and satisfies the symmetry relationship (that is ), we only need to calculate the multiplication operations of the first coefficients, and the calculation of the last coefficients can be directly obtained by reusing the calculation results of the first coefficients.

[0058] Assume the order of the filter , the coefficients are , and satisfy the symmetry relationship . In the traditional implementation, we need to calculate the products of the coefficients in the front and back parts, that is, 8 multipliers are required, and calculate respectively:

[0059] ;

[0060] In the method of the present invention, we can calculate only the products of the first 4 coefficients and the input data, and the products of the last 4 coefficients can be directly obtained through a shared calculation path; for example, we only need to calculate:

[0061] ;

[0062] Then, through symmetry calculation, we can obtain:

[0063] ;

[0064] By this method of reusing the calculation path, only 4 multipliers are required in the hardware design to complete all calculation tasks; this greatly reduces the consumption of hardware resources and especially saves precious resources in FPGAs.

[0065] In terms of hardware implementation, as an option, we can achieve this shared calculation by reusing the calculation path of the multiplier; for example, using the method of reusing the multiplier with clock cycles, within each clock cycle, the multiplier first calculates the multiplication operations of the first half, and then through the shared calculation path, calculates the multiplication results of the second half; specifically, the calculation of the first 4 coefficients is performed in parallel by 4 multipliers, and the calculation of the last 4 coefficients is carried out by reusing the calculation results of these multipliers in the next clock cycle.

[0066] Specifically, in the FPGA design, we can implement a shared calculation path module in the hardware so that when the first 4 multipliers are calculating, the calculation of the last 4 multipliers can be directly obtained through the calculated results of the multipliers; to further improve the calculation efficiency, the multipliers can complete different parts of the calculation tasks in different time periods through dynamic scheduling.

[0067] In some embodiments, by increasing the parallel calculation, the hardware can configure multiple multipliers to process different data parts; this parallel calculation not only improves the processing speed of the filter but also further optimizes the resource reuse of the multipliers. Especially in filters with higher computational complexity, the total power consumption of the system can be further reduced through parallel calculation.

[0068] As an option, for filters of different orders, the reuse method of the multiplier can be adjusted as needed; for example, filters of lower orders can directly utilize the symmetry to share the calculation path, while filters of higher orders can support more efficient parallel calculation by increasing the number of multipliers, while still maintaining the calculation reuse advantage brought by symmetry.

[0069] S3. Design a timing scheduling model, analyze the timing characteristics of the input data stream, and dynamically schedule the operation of the multiplier to avoid calculation conflicts and reuse the multiplier;

[0070] In this embodiment, the core objective of step S3 is to dynamically schedule the multipliers during the filter calculation process by designing a timing scheduling model. The system reasonably arranges the working states of each multiplier according to the timing characteristics of the input data stream, avoiding multiple multipliers calculating the same data at the same time, thereby ensuring the efficient reuse of multiplier resources, reducing calculation conflicts and waste of hardware resources. This step further optimizes the calculation process on the basis of the aforementioned step S2, maximizes the resource utilization rate, and effectively reduces the hardware power consumption.

[0071] Generally, in the design of digital filters, the input data stream is continuous time series data, and the product of each input data and the filter coefficient depends on the past input data. Therefore, the scheduling of multipliers must take into account the order of the data stream and the dependence of the calculation, which is also the key to the design of the timing scheduling model.

[0072] In this embodiment, to achieve timing scheduling, we designed a scheduling model based on clock cycles. This model represents whether the th multiplier is activated at time by defining a scheduling matrix . The scheduling matrix allows us to control the working states of each multiplier in different time periods, thereby realizing the reuse of multipliers. Specifically, if the multiplier is activated at time , then , otherwise .

[0073] In the present invention, the design of the timing scheduling model follows the following principles:

[0074] Dependence of the data stream: Each data item depends on the previous input data , so the scheduling of multipliers needs to consider the order of the input data.

[0075] Resource reuse: To maximize the utilization rate of multipliers, multipliers can reuse the same data in different time periods. For example, the first 4 coefficients can be calculated with the products of the first 4 moments of the input data, and the calculation of the last 4 coefficients is obtained by reusing the calculation results of the first 4 coefficients.

[0076] In a possible implementation, for an FIR filter of order , the filter output is given by the following formula:

[0077] ;

[0078] where, represents the output of the filter at time , is the order of the filter, is the th coefficient of the filter, is the th data of the filter input; this formula indicates that the filter output is the sum of products of the input data stream and the filter coefficients; therefore, the scheduling of the multipliers must consider the correspondence between the input data and the coefficients at each time.

[0079] Through the timing scheduling model, specifically, the data at each time will be calculated with the data of the previous times; due to the symmetry of the filter coefficients, the calculation of the second half can be obtained by reusing the calculation results of the first half; at this time, the task of the timing scheduling model is to reasonably allocate the work of each multiplier at different times, so that each multiplier can efficiently execute the calculation task and avoid multiple multipliers calculating the same data at the same time.

[0080] For example, assume that the system has 4 multipliers, and each time can handle the multiplication operation of 4 data items; in the calculation of the first half, the multiplier will handle , will handle , and so on; when the calculation of the first 4 coefficients is completed, the multiplier will reuse the calculation results to handle the multiplication operation of the last 4 coefficients; through this timing scheduling, we can ensure that the multiplier resources are reused and avoid calculation conflicts at the same time.

[0081] As an option, in some implementations, the timing scheduling can be further improved in efficiency through an optimization algorithm; for example, adopting a dynamic scheduling algorithm or a prediction scheduling based on historical load information can more precisely control the calculation task allocation at each time, thereby improving the reuse rate of the multipliers and reducing power consumption.

[0082] In some embodiments, a real-time feedback mechanism can be introduced to dynamically adjust the scheduling strategy based on the feedback information during the calculation process; for example, the system can timely adjust the work arrangement of the multipliers according to the real-time calculation delay and load changes; this adaptive scheduling mechanism can maintain the stability and efficiency of the system under different operating conditions.

[0083] S4. Predict the system load according to the change of the input data stream, adjust the multiplier configuration using the load prediction model, and perform resource allocation through the optimal scheduling algorithm;

[0084] In this embodiment, step S4 optimizes the use of multipliers in the FPGA by combining load prediction and an optimal scheduling algorithm, further improving the computational efficiency and power consumption control of the filter system. Specifically, in this step, the system predicts the load of the system based on the changes in the input data stream, adjusts the working configuration of the multipliers, and dynamically allocates resources through the optimal scheduling algorithm. This resource allocation mechanism based on load prediction and real-time scheduling helps to improve the system response speed, reduce power consumption, and balance the use of hardware resources under different load conditions.

[0085] Generally, in a digital filter, the change of the input data stream will directly affect the computational load of the system. For a dynamically changing data stream, the computational requirements of the filter may fluctuate accordingly. To use hardware resources (such as multipliers) more efficiently, it is necessary to accurately predict the load change and adjust the hardware configuration according to the prediction result to avoid overcomputation or resource idleness.

[0086] In this embodiment, we designed a load prediction model to predict the system load by analyzing the changes in the input data stream. This model mainly relies on the density function of the input data stream and the computational amount of the multipliers to estimate the load. Through the formula:

[0087] ;

[0088] Where: represents the system load at time ; represents the density function of the input data stream at time , reflecting the change characteristics of the data flow; is a weighting coefficient used to adjust the influence of data flow changes and computational amount on the system load; represents the total computational amount of all multipliers at time , reflecting the real-time computational requirements of the system; is the number of multipliers used in the system.

[0089] Through this load prediction formula, we can obtain the computational requirements of the system at a certain time , and then estimate how many multipliers need to be enabled and their computational loads.

[0090] In a possible implementation, the calculation of the load prediction model depends on the continuous monitoring of the input data stream. At each moment, the system calculates based on the latest input data stream and the change trend of the historical data stream , estimate the change in data traffic at the next moment; this prediction result is used to guide the working state of the system scheduler multiplier; through this method, the system can timely adjust the resource allocation to adapt to the changing load requirements.

[0091] Load prediction not only depends on the traffic characteristics of the input data stream, but also considers the current computational load of all multipliers in the system; for each multiplier , the system calculates its computational load at time ; , for example, the computational task volume of the multiplier when processing input data; the overall load when the system calculates at time is the weighted sum of the computational loads of all multipliers.

[0092] As an option, the load prediction algorithm can be optimized by methods such as recursive least squares (RLS) or Kalman filtering, enabling it to make more accurate predictions of future load changes on the basis of real-time updates; these algorithms can dynamically adjust the system load according to the real-time feedback at each moment, improve the prediction accuracy, and ensure that the system can respond in a timely manner and adjust the hardware configuration when the data stream fluctuates greatly.

[0093] Based on the load prediction model, step S4 continues to adjust the allocation of hardware resources through the optimal scheduling algorithm; by analyzing the real-time load of the system and the computational requirements of the multipliers, the scheduling algorithm can dynamically adjust the configuration of the multipliers according to the predicted load changes to reasonably allocate the computational resources of the system; the goal of the optimal scheduling algorithm is to minimize the total power consumption of the system and reduce unnecessary resource consumption on the premise of ensuring computational accuracy.

[0094] Specifically, the power consumption of the system can be expressed as:

[0095] ;

[0096] Where: is the power consumption of multiplier at time ; is a constant representing the power consumption of the multiplier per unit of computational load; is the scheduling matrix, indicating whether multiplier is activated at time ; is the computational load of multiplier at time .

[0097] In a possible implementation, by optimizing the scheduling matrix , the system can maximize the utilization rate of multipliers and avoid resource waste; for example, when the computing load is low, the system can save power by turning off some multipliers, while when the load is high, the system will increase the number of active multipliers to improve computing power.

[0098] As an option, in specific implementations, the scheduling algorithm can adopt heuristic algorithms, dynamic programming, or integer linear programming (ILP) methods to solve the optimal scheduling problem; these algorithms can automatically calculate the optimal multiplier configuration under given constraints by modeling the system load and power consumption; by precisely controlling the multiplier activation state at each moment, the optimal scheduling algorithm can ensure power consumption minimization while meeting real-time computing requirements.

[0099] In the present invention, the optimal scheduling is not only to improve computing efficiency but also to effectively reduce power consumption; through reasonable multiplier resource scheduling, the system can flexibly adjust power consumption according to the real-time load; for example, when dealing with low loads, the system reduces unnecessary multiplier activations, thereby reducing power consumption; when the load is high, the system can quickly enable more multipliers to improve processing capacity.

[0100] As an option, an adaptive resource scheduling scheme can be adopted to automatically adjust the usage amount of multipliers when the system load changes; this method can dynamically configure multipliers according to the requirements of real-time computing tasks, thereby ensuring power consumption minimization under various workloads.

[0101] S5. Combine load prediction and real-time scheduling, and dynamically adjust the multiplier configuration through an adaptive resource allocation algorithm, so that the system can adjust computing resources according to load changes;

[0102] Step S5 in this embodiment further improves the adaptive scheduling ability of the system; by combining the load prediction and real-time scheduling mechanisms, the system can dynamically adjust the multiplier configuration based on load changes to achieve more flexible and efficient computing resource allocation; through the adaptive resource allocation algorithm, the system can not only respond to computing requirements when the load changes but also save power to the greatest extent and ensure the completion of computing tasks.

[0103] Generally, in a digital signal processing system, the change of the input data stream directly affects the system load; the fluctuation of data traffic may cause changes in computing requirements. Therefore, how to adjust computing resources, especially the multiplier configuration, through an adaptive algorithm is the key to ensuring the efficient operation of the system; the load prediction model estimates the future computing load by analyzing the change of the input data stream. Combining with the real-time scheduling algorithm, the system can flexibly adjust computing resources at different times, avoid wasting hardware resources when the load is low, and ensure sufficient computing power when the load is high.

[0104] In this embodiment, we adopt a method that combines load prediction with real-time resource scheduling. While adjusting the hardware configuration in real time through an adaptive resource allocation algorithm, we ensure the efficient utilization of resources. The load prediction module estimates the system load based on the characteristics of the input data stream, and the real-time scheduling module dynamically adjusts the working state of the multiplier according to the prediction results, thereby making corresponding adjustments according to the real-time load of the system.

[0105] In the present invention, specifically, the load prediction model uses the characteristics of the input data stream to predict the load situation of the system; the load prediction formula is as follows:

[0106] ;

[0107] Where: represents the system load at time ; represents the density function of the input data stream at time , which reflects the change characteristics of the data flow; is the weighting coefficient, which is used to adjust the influence of data flow changes and the amount of calculation on the system load; represents the total amount of calculation of all multipliers at time , which reflects the real-time calculation requirements of the system; is the number of multipliers used in the system.

[0108] In some embodiments, the system uses a prediction model based on historical data streams, such as the recursive least squares (RLS) or Kalman filtering algorithm. These algorithms can dynamically adjust the accuracy of load prediction. With the real-time feedback of changes in the input data flow, the parameters of the load prediction model are continuously updated to ensure that the system can respond promptly to future calculation requirements.

[0109] For example, when the system predicts that the load will increase, the load prediction model will generate a corresponding warning, and the scheduling system will enable more multipliers in advance to adapt to the high load. When the load prediction value is low, the system will reduce the activation of multipliers, reduce unnecessary resource consumption, and thus save power.

[0110] Through the load prediction in step S4, the system has understood the load situation at the current time and future times. Next, the hardware resources are optimally allocated through the optimal scheduling algorithm. The core goal of the scheduling algorithm is to minimize the total power consumption by dynamically adjusting the working state of each multiplier and ensure the real-time completion of the calculation tasks.

[0111] Specifically, in the optimal scheduling algorithm, the power consumption of the multiplier and the amount of calculation can be obtained through the power consumption of the system in the foregoing steps; it is calculated through the following formula:

[0112] ;

[0113] Wherein: is the time when the power consumption of the multiplier is; is a constant, representing the power consumption of the multiplier under unit computational workload; is a scheduling matrix, indicating whether the multiplier is activated at time ; is the computational workload of the multiplier at time ;

[0114] By adjusting , the system can control the activation state of each multiplier at different times, thereby achieving power consumption optimization and efficient completion of computational tasks; the specific optimization goal is to minimize power consumption while ensuring the real-time requirements of computational tasks at each time; the objective function can be represented by the following constraint conditions:

[0115] ;

[0116] Where is the system load at time , is the maximum load that the system can bear at this time; through this constraint condition, the system avoids overloading and ensures the smooth completion of computational tasks.

[0117] In a possible implementation, the scheduling algorithm uses dynamic programming (DP) or a greedy algorithm for optimization, and uses historical load information and current power consumption estimation to determine the working time of each multiplier, thereby ensuring the minimization of power consumption while completing all computational tasks.

[0118] As an option, the system further optimizes the use of computational resources through dynamic scheduling of multipliers; especially when processing large-scale data, the system can multiplex computational tasks among multiple multipliers, maximizing the utilization of multiplier resources within a clock cycle; for example, at a time when the load is low, the system can combine multiple computational tasks to run on fewer multipliers, thereby reducing the consumption of redundant resources.

[0119] The system arranges tasks within each clock cycle through dynamic timing control, ensuring that each multiplier is activated only when necessary. This dynamic adjustment mechanism can flexibly adapt to changes in the input data stream and ensure the efficient use of hardware resources.

[0120] Specifically, the system not only realizes the dynamic allocation of computing resources through the optimal scheduling algorithm, but also further optimizes the power consumption management through an accurate power consumption control mechanism. For example, when the system predicts a long period of low load, the multiplier can enter the "standby" or "low-power" state. During high load periods, the system will increase the input of computing resources by scheduling more multipliers to ensure that the computing tasks are completed on time.

[0121] In some embodiments, the system further optimizes the power consumption control through real-time monitoring and feedback mechanisms. For example, the system can quickly respond to load changes, adjust the allocation of computing tasks and the activation status of hardware resources, ensuring that the computing accuracy is not affected while optimizing the power consumption.

[0122] Please refer to Figure 2 , a system for implementing a filter that saves computing resources based on FPGA, including:

[0123] A multiplier resource management module, which is responsible for dynamically scheduling multiplier resources according to the symmetry analysis of filter coefficients and the timing characteristics of the input data stream. By analyzing the symmetry of filter coefficients, the module can identify and reuse the calculations of the symmetric part, thus reducing redundant multiplication operations. Combining the timing characteristics of the input data stream, the module further adjusts the activation status of the multiplier according to the changes in the real-time data flow. The multiplier resource management module ensures the maximization of the utilization rate of multipliers during the calculation process, while avoiding unnecessary calculations and resource waste, which is particularly important in applications with limited hardware resources or power-sensitive requirements.

[0124] A load prediction module, which estimates the system load by using a load prediction model through real-time monitoring of the changes in the input data flow. The load prediction module analyzes the density and change trend of the data stream to predict the complexity and resource requirements of future computing tasks. Based on the predicted load changes, the module can timely adjust the configuration of computing resources. Specifically, when it is predicted that the system will face high computing demands, the load prediction module will adjust the resources in advance and activate more multipliers. When the load is low, the module will reduce the activation of resources to save power. The load prediction module can effectively cope with the changes in burst data flow, ensuring the stable operation of the system and optimizing the energy efficiency.

[0125] The scheduling optimization module is responsible for dynamically adjusting the configuration of the multiplier through the optimal scheduling algorithm. The scheduling optimization module combines the output of the load prediction module to adjust the working state of each multiplier in real time. Through the scheduling matrix, the system can flexibly control the activation state of the multiplier in different time periods, thus realizing the reasonable allocation of computing resources. The optimal scheduling algorithm not only optimizes the use of the multiplier, avoids calculation conflicts, but also ensures that sufficient computing resources can be provided in a timely manner under high load and reduces unnecessary power consumption under low load. The scheduling optimization module is the key for the system to achieve efficient and low-power operation, which can ensure the timely completion of computing tasks and save hardware resources to the greatest extent.

[0126] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An implementation method of a filter that saves computing resources based on FPGA, characterized in that, It includes the following steps: S1. Analyze the symmetry of the filter coefficients, identify the coefficient symmetry part, and reduce redundant multiplication operations through symmetry; S2. Based on symmetry, obtain the calculation results of the data in the filter calculation process through a shared calculation path, thereby reducing the number of required multipliers; S3. Design a timing scheduling model, analyze the timing characteristics of the input data stream, and dynamically schedule the operation of the multipliers to avoid calculation conflicts and reuse the multipliers; The timing scheduling model controls whether the multiplier i is activated at time t through the scheduling matrix S(t, i), where S(t, i) ∈ {0, 1}, and only one multiplier is activated within each clock cycle; The objective function of the timing scheduling model is: Among them, S(t, i) represents whether the multiplier i is activated within the clock cycle t. If it is activated, then S(t, i) = 1; otherwise, S(t, i) = 0; T is the total number of calculation cycles, that is, the number of clock cycles required for filter calculation; N is the number of multipliers used; S4. Predict the system load according to the change of the input data stream, use the load prediction model to adjust the multiplier configuration, and perform resource allocation through the optimal scheduling algorithm; The load prediction model performs load prediction based on the density function f(x t ) and the computational amount (i, t). The load prediction formula is as follows: Among them, L(t) represents the system load at time t, and f(x t ) represents the change in the density function of the input data stream at time t. x t is the data traffic transmitted at time t; represents the weighted sum of the total computation amounts of all multipliers at time t. α is a weighting coefficient used to adjust the impact of the computation amount on the total load. Computation amount(i, t) represents the computation amount processed by multiplier i at time t, and N is the number of multipliers; The optimal scheduling algorithm dynamically adjusts the resource allocation by solving the following optimization problem: Among them, P(i, t) represents the power consumption of the multiplier i at time t; T represents the total number of clock cycles in the filter calculation process; N represents the number of multipliers used in the system; L(t) represents the total load of the system at time t; maximum load(t) represents the maximum allowable load of the system at time t; S5. Combine load prediction and real-time scheduling, and dynamically adjust the multiplier configuration through the adaptive resource allocation algorithm, so that the system can adjust the computing resources according to the load change.

2. The implementation method of a filter based on FPGA that saves computing resources according to claim 1, characterized in that, The symmetry analysis step calculates the data of the filter coefficients through mathematical derivation, and the data shares the calculation results through symmetry.

3. The implementation method of a filter based on FPGA that saves computing resources according to claim 2, characterized in that, The mathematical derivation step includes: Identify the symmetric coefficients in the filter. Since the symmetric coefficients are the same as the identified coefficients, the values of other coefficients are deduced by calculating the results of the identified coefficients.

4. The implementation method of a filter based on FPGA that saves computing resources according to claim 1, characterized in that, The load prediction model uses the recursive least squares method to recursively predict the system load and predict the load change at future times, providing a basis for subsequent resource scheduling.

5. The implementation method of a filter based on FPGA for saving computing resources according to claim 1, characterized in that The adaptive resource allocation algorithm combines load prediction and real-time scheduling. When it predicts a change in data traffic, it dynamically adjusts the multiplier configuration according to the input data traffic and load change, providing sufficient computing resources in high-load situations and reducing the use of computing resources in low-load situations.

6. An implementation system of a filter that saves computing resources based on FPGA, which is applied to the implementation method of a filter that saves computing resources based on FPGA described in any one of claims 1-5, characterized in that, It includes: A multiplier resource management module for dynamically scheduling multiplier resources according to the symmetry analysis of filter coefficients and the timing characteristics of the input data stream; A load prediction module for predicting the system load based on the change of the input data traffic and adjusting the resource allocation according to the load change; A scheduling optimization module for dynamically adjusting the multiplier configuration through the optimal scheduling algorithm.

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