High-speed CMOS logic addressable latch

Abstract

The invention discloses a high-speed CMOS (Complementary Metal Oxide Semiconductor) logic addressable latch, which comprises 40 transistors, 2 phase inverters and 14 nodes, and not only can recover all SNUs (Single Node Units), but also can recover all MNUs (Multi Node Units); the number of transistors required by the latch is only 40, so that the minimum hardware overhead is ensured while the high-reliability fault-tolerant capability is provided; the number of sensitive nodes of the latch is only 12, and the probability that the sensitive nodes are bombarded by radiation particles is reduced due to fewer sensitive nodes; the locker can realize recovery fault tolerance of all SNUs and MNUs only by relying on a fault-tolerant ring on a circuit level, so that any placement and optimization technology on a layout level is not needed, the minimization of the layout area is ensured, and the complexity of reinforcement design is reduced; the recovery fault tolerance ensures that an output node does not enter a high resistance state, so that a holding circuit does not need to be added to maintain an output value, and meanwhile, the influence of leakage current on output and the problem of short-circuit power consumption possibly caused when overturning is unrecoverable are also avoided.

Description

Technical Field

[0001] The invention relates to the technical field of latches, in particular to a high-speed CMOS logic addressable latch. Background Art

[0002] With the continuous development of the economy and society, integrated circuits have played an important role in many areas of social life. From satellites and giant machines that are vital to national security and lifeline to consumer electronics that are vital to personal life experience, digital circuits play an irreplaceable role.

[0003] The existing latch SNU cannot be restored, so the node will be in a floating high-impedance state throughout the latching period. Affected by the leakage current under the nano-integrated circuit process, the value stored in the node can be easily changed by charging and discharging. Therefore, we propose a high-speed CMOS logic addressable latch to solve the above-mentioned problems. Summary of the invention

[0004] The object of the present invention is to provide a high-speed CMOS logic addressable latch to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A high-speed CMOS logic addressable latch, comprising:

[0007] 40 transistors, including: TN1-TN 16 ,TP1-TP 20 , 2 NMOS transistors and 2 PMOS transistors that form 2 inverters; TP 16 -TP 19 There are 4 pass transistors;

[0008] 2 inverters, including: I1 and I2, used to provide the clock CLK and the inverse signal CLK of the input D respectively N and D N ;

[0009] 14 nodes, including M1-M8, F1, F2, F5, F6, F 12 and Q, and the 14 nodes include 12 sensitive nodes.

[0010] As a further solution of the present invention: the lock is in a transmission mode when the clock CLK is at a low level, wherein CLK=0; and is in a latching mode when the clock CLK is at a high level, wherein CLK=1.

[0011] As a further solution of the present invention: when Q=0, M3-M5, M7, M8, F1, F2, F5, F6, F9 and Q are sensitive nodes.

[0012] As a further solution of the present invention: the drain terminals of the two NMOS transistors are coupled to the clock terminal through the PMOS transistor, and the source terminals of the two NMOS transistors are coupled to another group of clock terminals through another group of PMOS transistors.

[0013] As a further solution of the present invention: the drain end of the PMOS transistor is connected to the power supply voltage, the source end of the PMOS transistor is connected to the drain end of the NMOS transistor, the gate of the PMOS transistor is coupled to the clock end, the drain end of another group of PMOS transistors is connected to the power supply voltage, the source end of another group of PMOS transistors is connected to the drain end of the NMOS transistor, and the gate is coupled to the clock end.

[0014] As a further solution of the present invention: a group of NMOS transistors includes: a group of first PMOS transistors, the gate of the first PMOS transistor is connected to the input end of the NMOS transistor, the source end of the first PMOS transistor is connected to the output end of the NMOS transistor, and the drain end of the first PMOS transistor is connected to the drain end of the NMOS transistor.

[0015] As a further solution of the present invention: another group of NMOS transistors includes: a group of second PMOS transistors, the gate of the second PMOS transistor is connected to the input end of the other group of NMOS transistors, the source end of the second PMOS transistor is connected to the output end of the other group of NMOS transistors, and the drain end of the second PMOS transistor is connected to the drain end of the other group of NMOS transistors.

[0016] As a further solution of the present invention: an input end of a group of the inverters is coupled to the first output end, and an output end of the inverter is coupled to the second output end.

[0017] As a further solution of the present invention: the input end of another group of inverters is coupled to the second output end, and the output end of the inverter is coupled to the first output end.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] The high-speed CMOS logic addressable latch can not only restore all SNUs, but also restore all MNUs. At the same time, the number of transistors required for the latch is only 40, which ensures that the hardware overhead is minimized while providing high reliability fault tolerance. The number of sensitive nodes of the latch is only 12, and fewer sensitive nodes reduce the probability of being bombarded by radiation particles. At the same time, the latch can achieve recovery fault tolerance in all SNUs and MNUs only by relying on the fault tolerance loop at the circuit level, so no placement and optimization technology at the layout level is required, which ensures the minimization of the layout area and reduces the complexity of the reinforcement design. Recovery fault tolerance ensures that the output node will not enter the high-impedance state, so there is no need to add a holding circuit to maintain the output value, and it also avoids the influence of leakage current on the output and the short-circuit power consumption problem that may be caused when the flip is irreversible. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the structure of the high-speed CMOS logic addressable latch in the present invention. DETAILED DESCRIPTION

[0021] In one embodiment, Figure 1 As shown, a high-speed CMOS logic addressable latch comprises:

[0022] 40 transistors, including: TN1-TN 16 ,TP1-TP 20 , 2 NMOS transistors and 2 PMOS transistors that form 2 inverters; TP 16 -TP 19 There are four pass transistors, whose main function is to transfer the input D to the internal nodes M1 and M5 in the transfer mode, and to transfer D N To internal nodes M2 and M6; by TP 20 and TN 16 The transmission gate composed of TP3-TP transmits the D signal to the output Q; 15 and TN 13 -TN 15 The clock-controlled C unit formed can effectively shield the impact of internal node flipping on output Q; the remaining transistors form a fault-tolerant latch loop of the circuit, which can effectively restore the nodes where SNU and MNU occur, ensuring the correctness of the Q latch value; the output node Q is not connected to any internal node, thereby ensuring that the flip occurring at node Q will not affect its internal nodes;

[0023] 2 inverters, including: I1 and I2, used to provide the clock CLK and the inverse signal CLK of the input D respectively N and D N ;

[0024] 14 nodes, including M1-M8, F1, F2, F5, F6, F 12 and Q, and the 14 nodes include 12 sensitive nodes;

[0025] The lock is in transmission mode when the clock CLK is at a low level, where CLK = 0; it is in latching mode when the clock CLK is at a high level, where CLK = 1;

[0026] When the clock CLK = 0, the constructed latch enters the transmission mode. At this time, TP 20 and TN 16 The transmission gate is opened, and the input signal D is directly transmitted to the output Q; at the same time, TP 16 -TP 19 is turned on, input signals D and D N Force the values ​​stored in the internal nodes M1, M5, M2 and M6 to change, and turn on or off the transistors directly and indirectly driven by these nodes, thereby establishing a correct fault-tolerant feedback protection loop;

[0027] When the clock CLK = 1, the constructed latch enters the latch mode. At this time, TP 16 -TP 20 and TN 16 Closed, TP 15 and TN 13 is turned on, and the clocked C unit chooses whether to connect output Q to VDD or GND, depending on the value stored in the internal node.

[0028] When Q=0, M3-M5, M7, M8, F1, F2, F5, F6, F9 and Q are sensitive nodes;

[0029] The drain terminals of the two NMOS transistors are coupled to the clock terminal through the PMOS transistors, and the source terminals of the two NMOS transistors are coupled to another group of clock terminals through another group of PMOS transistors;

[0030] The drain of the PMOS transistor is connected to the power supply voltage, the source of the PMOS transistor is connected to the drain of the NMOS transistor, the gate of the PMOS transistor is coupled to the clock terminal, the drain of another group of PMOS transistors is connected to the power supply voltage, the source of another group of PMOS transistors is connected to the drain of the NMOS transistor, and the gate is coupled to the clock terminal;

[0031] A group of NMOS transistors includes: a group of first PMOS transistors, the gate of the first PMOS transistor is connected to the input end of the NMOS transistor, the source of the first PMOS transistor is connected to the output end of the NMOS transistor, and the drain of the first PMOS transistor is connected to the drain of the NMOS transistor; another group of NMOS transistors includes: a group of second PMOS transistors, the gate of the second PMOS transistor is connected to the input end of the other group of NMOS transistors, the source of the second PMOS transistor is connected to the output end of the other group of NMOS transistors, and the drain of the second PMOS transistor is connected to the drain of the other group of NMOS transistors;

[0032] An input terminal of one set of inverters is coupled to the first output terminal, and an output terminal of the inverters is coupled to the second output terminal; an input terminal of another set of inverters is coupled to the second output terminal, and an output terminal of the inverters is coupled to the first output terminal;

[0033] To simulate radiation-induced current, dual double-exponential current sources were used for fault injection: one dual double-exponential current source was used to inject current to simulate SNUS; two dual double-exponential current sources were used to inject current at two sensitive nodes simultaneously to simulate MNU caused by charge sharing effect;

[0034] In the first and third clock cycles, when the clock CLK=0 and the input D changes from high level to low level, the nodes M1, M3, M5, M7 and the output Q all change from high level to low level, and the nodes M2, M4, M6, and M8 change from low level to high level; when the clock CLK=1, the latch enters the latch mode and latches the value to be held. At this time, the value of the output Q has nothing to do with the input D and is always maintained at a high level;

[0035] In the second clock cycle, when the clock CLK=0 and the input D changes from low level to high level, the nodes M2, M4, M6, M8 and the output Q all change from low level to high level, and the nodes M1, M3, M5, and M7 change from high level to low level; when the clock CLK=1, the latch enters the latch mode and latches the low level. During this period, the change of the input D signal will not affect the latched value of the output Q;

[0036] During the period of 25-45ns, fault injection is performed on the internal single nodes M1, M3, M4, M5, M7 and M8 respectively to make them flip, and these SNUs can be recovered;

[0037] During the period of 16-185ns, MNU faults are injected, and these MNUs can be quickly recovered. In addition, the MNU recovery results between internal nodes and output Q also prove that SNU occurring at output Q can also be recovered;

[0038] Since all SNUs and MNUs can be restored to fault tolerance, the output Q will not enter a high-impedance state, so there is no need to add a holding circuit to maintain the value of the output Q; at the same time, it also avoids the impact of leakage current on the output Q and the short-circuit power consumption problem that may be caused when the flip cannot be restored.

[0039] The present invention can not only restore all SNUs, but also restore all MNUs; at the same time, the number of transistors required by the latch is only 40, which ensures that the hardware overhead is minimized while providing high reliability fault tolerance; the number of sensitive nodes of the latch is only 12, and fewer sensitive nodes reduce the probability of being bombarded by radiation particles; at the same time, the latch can realize the recovery fault tolerance of all SNUs and MNUs only by relying on the fault tolerance ring at the circuit level, so no placement and optimization technology at the layout level is required, which ensures the minimization of the layout area and reduces the complexity of the reinforcement design; the recovery fault tolerance ensures that the output node will not enter the high impedance state, so there is no need to add a holding circuit to maintain the output value, and at the same time, it also avoids the influence of leakage current on the output and the short-circuit power consumption problem that may be caused when the flip is unrecoverable.

[0040] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A high-speed CMOS logic addressable latch, characterized in that: include: 40 transistors, including: TN1-TN 16 ,TP1-TP 20 , 2 NMOS transistors and 2 PMOS transistors that form 2 inverters; TP 16 -TP 19 There are 4 pass transistors; 2 inverters, including: I1 and I2, used to provide the clock CLK and the inverse signal CLK of the input D respectively N and D N ; 14 nodes, including M1-M8, F1, F2, F5, F6, F 12 and Q, and the 14 nodes include 12 sensitive nodes.

2. A high-speed CMOS logic addressable latch according to claim 1, characterized in that: The lock is in a transmission mode when the clock CLK is at a low level, wherein CLK=0; and in a latching mode when the clock CLK is at a high level, wherein CLK=1.

3. A high-speed CMOS logic addressable latch according to claim 1, characterized in that: When Q=0, M3-M5, M7, M8, F1, F2, F5, F6, F9 and Q are sensitive nodes.

4. A high-speed CMOS logic addressable latch according to claim 1, characterized in that: The drain terminals of the two NMOS transistors are coupled to the clock terminal through the PMOS transistor, and the source terminals of the two NMOS transistors are coupled to another group of clock terminals through another group of PMOS transistors.

5. A high-speed CMOS logic addressable latch according to claim 1, characterized in that: The drain end of the PMOS transistor is connected to the power supply voltage, the source end of the PMOS transistor is connected to the drain end of the NMOS transistor, the gate of the PMOS transistor is coupled to the clock end, the drain end of another group of PMOS transistors is connected to the power supply voltage, the source end of another group of PMOS transistors is connected to the drain end of the NMOS transistor, and the gate is coupled to the clock end.

6. A high-speed CMOS logic addressable latch according to claim 1, characterized in that: The group of NMOS transistors includes: a group of first PMOS transistors, the gate of the first PMOS transistor is connected to the input end of the NMOS transistor, the source end of the first PMOS transistor is connected to the output end of the NMOS transistor, and the drain end of the first PMOS transistor is connected to the drain end of the NMOS transistor.

7. A high-speed CMOS logic addressable latch according to claim 6, characterized in that: The other group of NMOS transistors includes: a group of second PMOS transistors, the gate of the second PMOS transistor is connected to the input end of the other group of NMOS transistors, the source end of the second PMOS transistor is connected to the output end of the other group of NMOS transistors, and the drain end of the second PMOS transistor is connected to the drain end of the other group of NMOS transistors.

8. A high-speed CMOS logic addressable latch according to claim 1, characterized in that: An input terminal of a group of the inverters is coupled to the first output terminal, and an output terminal of the inverters is coupled to the second output terminal.

9. A high-speed CMOS logic addressable latch according to claim 1, characterized in that: The input terminal of another group of inverters is coupled to the second output terminal, and the output terminal of the inverter is coupled to the first output terminal.

Images