Semiconductor device and method of manufacturing the same

Abstract

Disclosed herein is a semiconductor device and a method of manufacturing the same. A method of manufacturing a semiconductor device can include providing a substrate, etching the substrate from a first side to form at least one vertical pillar having a first end and a second end, forming at least one gate line on a gate dielectric layer formed on a sidewall of the at least one vertical pillar, forming a first p-type region at the first end of the at least one vertical pillar, forming a storage member connecting the first p-type region, removing a portion of the substrate at a second side of the substrate opposite the first side to expose the second end of the at least one vertical pillar, forming a second p-type region made of at least p-type SiGe at the second end of the at least one vertical pillar, and forming a bit line connected to the second p-type region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device and a manufacturing process thereof. The semiconductor device can be a vertical gate dynamic random access memory (DRAM) device. BACKGROUND

[0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar processes and manufacturing technology become challenging and costly. As a result, the storage density for planar memory cells approaches an upper limit. Three-dimensional (3D) memory architectures can be employed to address the density limitations in planar memory cells by using vertical gate transistors. SUMMARY

[0003] Aspects of the present disclosure provide a method of manufacturing a semiconductor device. The method can include: providing a substrate; etching the substrate from a first side of the substrate to form at least one vertical pillar having a first end and a second end opposite the first end; forming at least one gate line on a gate dielectric layer formed on a sidewall of the at least one vertical pillar; forming a first p-type region at the first end of the at least one vertical pillar; forming a storage member connecting the first p-type region; removing a portion of the substrate at a second side of the substrate to expose the second end of the at least one vertical pillar, the second side of the substrate being opposite the first side of the substrate; forming a second p-type region at the second end of the at least one vertical pillar, the second p-type region being made of at least p-type silicon germanium (SiGe); and forming a bit line connected to the second p-type region at the second end of the at least one vertical pillar.

[0004] In an embodiment, forming the second p-type region further includes: performing a rapid thermal anneal process with an anneal temperature less than 500 °C.

[0005] In an embodiment, forming the second p-type region further includes: epitaxially growing p-type SiGe on the at least one vertical pillar.

[0006] In an embodiment, forming the second p-type region further includes: depositing p-type SiGe into the at least one vertical pillar.

[0007] In an embodiment, the first p-type region has a dopant concentration higher than 10 19 atoms / cm 3 .

[0008] In an embodiment, the second p-type region has a dopant concentration higher than 10 19 atoms / cm 3 .

[0009] In embodiments, the at least one gate line and the bit line are formed such that they are perpendicular to each other.

[0010] In embodiments, the second p-type region is made of p-type SiGe.

[0011] In embodiments, the gate line is also encapsulated by an oxide layer.

[0012] In embodiments, the storage element is a capacitor.

[0013] Aspects of the disclosure provide a semiconductor device. The semiconductor device can include at least one vertical pillar having a first end and a second end opposite the first end, at least one gate line on a gate dielectric layer formed on a sidewall of the at least one vertical pillar, a first p-type region at the first end of the at least one vertical pillar, a storage element connected with the first p-type region, a second p-type region at the second end of the at least one vertical pillar, the second p-type region including at least p-type silicon germanium (SiGe), and a bit line connected with the second p-type region at the second end of the at least one vertical pillar.

[0014] Aspects of the disclosure provide a memory system including a semiconductor device to store data. BRIEF DESCRIPTION OF DRAWINGS

[0015] Various embodiments of the disclosure presented as examples will be described in detail with reference to the following drawings, in which like reference numerals refer to like elements, and in which:

[0016] Figure 1 A side view of a cross-section of a memory device 100 according to embodiments of the disclosure is shown.

[0017] Figures 2A-2I A manufacturing process to form a DRAM array having vertical transistors 219 according to embodiments of the disclosure is shown.

[0018] Figure 2J A top view of a substrate 200 is shown.

[0019] Figure 3 A flowchart of a manufacturing process 300 to form a DRAM array having vertical transistors 219 according to embodiments of the disclosure is shown.

[0020] Figure 4 A block diagram of an exemplary system 400 having a memory system according to embodiments of the disclosure is shown. DETAILED DESCRIPTION

[0021] Transistors are used as switching or selection devices in memory cells of some memory devices, such as DRAM, phase change memory (PCM), and ferroelectric DRAM (FRAM). Conventional planar transistors commonly used in existing memory cells typically have a horizontal structure with a buried word line in a substrate and a bit line above the substrate. Because the source and drain of the planar transistor are disposed at different locations, this increases the area occupied by the transistor. The design of the planar transistor also complicates the layout of the interconnect structures (e.g., word lines and bit lines) coupled to the memory cell, for example, limiting the pitch of the word lines and / or bit lines, thereby increasing manufacturing complexity and reducing production yield. Furthermore, because the bit line and storage element (e.g., a capacitor or PCM element) are disposed on the same side of the planar transistor (above the transistor and substrate), the bit line process margin is limited by the storage element, and the coupling capacitance between the bit line and storage element (e.g., capacitor) is increased. As saturated drain current continues to increase, planar transistors can also suffer from higher leakage current, which is not desirable for performance of the memory device.

[0022] On the other hand, as the number of memory cells continues to increase, in order to maintain the same chip size, the size of the components (e.g., transistors, word lines, and / or bit lines) in the memory cell array needs to continue to decrease so that the efficiency of the memory cell array is not significantly reduced.

[0023] To address one or more of the foregoing issues, a vertical transistor is introduced to replace the conventional planar transistor as the switching and selection device in the memory cell array of a memory device (e.g., DRAM, PCM, and FRAM). Compared to the planar transistor, the vertically arranged transistor (i.e., the drain and source are overlapping in a plan view) can reduce the area of the transistor and simplify the layout of the interconnect structures (e.g., metal lines of the word lines and bit lines), which can reduce manufacturing complexity and improve yield. The vertical structure of the transistor also allows the bit line and storage element (e.g., capacitor) to be disposed on opposite sides of the transistor in the vertical direction (e.g., one above the transistor and one below the transistor), so that the process margin of the bit line can be increased, and the coupling capacitance between the bit line and storage element can be reduced.

[0024] In an example, a process of fabricating a vertical structure of a transistor of a memory device includes forming a source including an n-type doped region at a top end of the vertical transistor and forming a storage element (e.g., a capacitor) in contact with the source. A drain including an n-type doped region is then formed at a bottom end of the transistor for connection to a bit line. In this way, the vertical transistor can have similar characteristics as a planar transistor of n-type. However, to activate the n-type doped region in the drain located at the bottom end of the transistor, a high temperature anneal process is required, such as a rapid thermal anneal employing an anneal temperature higher than 750 °C. The high temperature anneal process can damage the capacitor that has already been formed on the top end of the transistor. This will result in potential performance degradation in the memory device. The present disclosure introduces a solution of replacing the n-type doped region with a p-type doped region. More specifically, a p-type silicon germanium (SiGe) is used to form a p-type doped region in the vertical transistor that is connected to the bit line.

[0025] Figure 1 A side view of a cross-section of a memory device 100 is shown in accordance with an embodiment of the present disclosure. The memory device 100 includes a plurality of vertical transistors 101, a gate line 103, a storage element 107, and a bit line 109. Each vertical transistor 101 includes a semiconductor body 102 connected to a gate structure (e.g., a gate dielectric layer and a gate layer) and including a source and a drain. The source can be located at a first end of the vertical transistor 101. The source can include a first p-type doped region 104. The first p-type doped region 104 can be a highly doped p-type region. The first p-type doped region 104 can be connected to a first lightly doped drain (LDD) region 105. The drain can be located at a second end of the vertical transistor 101. The drain can include a second p-type doped region 108. The second p-type region can be a highly doped p-type region. The second p-type doped region can be connected to a second LDD region 109. In an embodiment, the LDD regions 105 and 109 can have a dopant concentration lower than 10 19 atoms / cm 3 In an embodiment, the highly doped regions 104 and 108 can have a dopant concentration higher than 10 19 atoms / cm 3 .

[0026] Each vertical transistor 101 can be connected to a storage 107 at a source (e.g., first p-type doped region 104). Each vertical transistor 101 can have a gate structure that includes a gate dielectric layer 106 and a gate layer. The gate dielectric layer 106 is between the gate layer and the semiconductor body 102. A gate line 103 can be formed by connecting the gate layers of each vertical transistor 101 in a row. The gate line 103 can be surrounded by an oxide 111 (e.g., silicon dioxide) to provide insulation. The gate line 103 can also be referred to as a word line. A bit line 110 can be connected to a drain at a second p-type doped region 108. The gate line 103 and the bit line 110 can be formed in a manner that is perpendicular to each other. The storage 107 can include any device capable of storing binary data (e.g., 0 and 1), including but not limited to: capacitors for DRAM cells and FRAM cells, and PCM elements for PCM cells. In embodiments, the vertical transistor 101 controls selection and / or state switching of the respective storage 107 coupled to the vertical transistor 101.

[0027] Figures 2A-2I A flowchart illustrating a manufacturing process 300 of forming a DRAM array having vertical transistors 219 (shown in Figure 2I ) is shown. Figures 2A-2I A side view of a cross-section of a DRAM array is shown. Figure 3 A flowchart illustrating a manufacturing process 300 of forming a DRAM array having vertical transistors 219 (shown in

[0028] At S310 in Figure 3 and as shown in Figure 2A , a substrate 200 can be provided that can be made of silicon. Other materials such as germanium, gallium arsenide, indium phosphide, etc. can also be used as the substrate material. The substrate 200 can have a first side 201 and a second side 202.

[0029] At S320 in Figure 3 and as shown in Figure 2B , a semiconductor body 203 can be formed by etching the substrate 200. The semiconductor body 203 can have a first end 204 and a second end 205. In embodiments, the etching process can include providing a mask material having a pattern on the first side 201 of the substrate 200, and then performing an etching method to remove a desired amount of the substrate 200 according to the mask pattern. In response to the etching process, a trench 206 and the semiconductor body 203 are formed.

[0030] Figure 2JA top view of the substrate 200 is shown. The semiconductor body 203 (vertical transistors 203A-203I) can have a solid shape of a circular pillar. Other shapes, such as square pillars and rectangular pillars, can also be formed depending on the desired mask pattern in the embodiment.

[0031] At S330 in Figure 3 and as shown in Figure 2C , a gate line 207 can be formed in the trench 206 and coupled to a gate dielectric layer 209 of the vertical transistor 219 (shown in Figure 2I ) at the side of the semiconductor body 203. The gate structure can include a gate layer and the gate dielectric layer 209. The gate dielectric layer is between the gate layer and the semiconductor body 203. The gate line 207 is formed by connecting the gate layers of multiple vertical transistors 219. For example, the gate line 207 is formed in the y direction (as shown in Figure 2J ) to couple and connect to the column of the semiconductor bodies 203A, 203B, 203C, 203D, and 203E located in the y direction. An oxide fill 208 can be filled into the trench 206 to encapsulate the gate line 207. The gate structure of the vertical transistor can be formed in a manner suitable for the memory device. For example, a gate-all-around (GAA) transistor can have a gate structure formed to surround (e.g., surround and contact) all sides of the semiconductor body 203 in a top view. For another example, a multi-gate transistor can have a gate structure that contacts multiple sides (e.g., three sides) of the semiconductor body 203.

[0032] At S340 in Figure 3 and as shown in Figure 2DAs shown, a source region, including a first p-type doped region 210, is formed at the first end 204 of the semiconductor body 203. The first p-type doped region 210 can be connected to a first lightly doped drain (LDD) region 211. For example, the first p-type doped region 210 can be formed by etching away the semiconductor body 203 from the first end 204, and then a layer of semiconductor material (e.g., SiGe) can be formed by deposition or epitaxial growth on the semiconductor body 203, followed by doping with a p-type dopant and annealing. For example, the first p-type doped region 210 and the first LDD region 211 can be formed in a similar manner, with the LDD region 211 being formed first, followed by the first p-type doped region 210. For example, the first p-type doped region 210 can be formed by epitaxial growth of p-type SiGe on the semiconductor body 203 from the first end 204. The first LDD region 211 can be grown first, followed by the first p-type doped region 210. For example, the first p-type doped region 210 can be formed by depositing p-type SiGe directly on the semiconductor body 203 from the first end 204. The first LDD region 211 can be deposited first, followed by the first p-type doped region 210.

[0033] In embodiments, the first p-type doped region 210 can be doped by diffusion. In embodiments, the first p-type doped region 210 can be doped by ion implantation. In embodiments of the present disclosure, the first p-type doped region 210 can be doped using a p-type dopant such as boron. However, other p-type dopants from the group III elements can also be used. In embodiments, the first LDD region 211 can be a region having a dopant concentration substantially below 10 19 atoms / cm 3 According to aspects of the present disclosure, the p-type doped region 210 needs to be a highly doped region having a dopant concentration above 10 19 atoms / cm 3 In embodiments, the first LDD region 211 can be an optional region. For example, the semiconductor body 203 can have only the first p-type doped region 210 at the first end 204.

[0034] According to the present disclosure, a dopant activation process is performed after the dopant impurity atoms are diffused or implanted into the semiconductor body 203 to form the first p-type doped region 210. The dopant activation process converts the dopant impurity atoms from a relatively inactive state to an electrically active state. The dopant activation process includes applying a high temperature anneal, such as a rapid thermal anneal. For doped SiGe, the anneal temperature required to activate the dopant depends on the dopant material. For example, p-type SiGe will only require an anneal temperature of 500°C or less. N-type SiGe will require an anneal temperature of 750°C or more.

[0035] At S350 in Figure 3 and as shown in Figures 2E-2F , a storage 214 is formed at the first end 204 of the semiconductor body 203. The storage 214 is electrically connected to the first p-type doped region 210. In embodiments, an optional pillar structure 213 can be formed from the first p-type doped region 210. For example, as shown in Figure 2E , the pillar structure 213 can be formed by removing a thin layer 212 of the substrate 200 at the top side 201. The storage 214 can then be formed on the pillar structure 213 and electrically connected to the first p-type doped region 210. In embodiments, the storage 214 can be formed directly on the first p-type doped region 210 and electrically connected to the first p-type doped region 210. The storage 214 can include any device capable of storing binary data (e.g., 0 and 1), including but not limited to: capacitors for DRAM cells and FRAM cells, and PCM elements for PCM cells.

[0036] At S360 in Figure 3 and as shown in Figure 2G , a portion 215 of the substrate 200 at the second side 202 can be removed to expose the second end 205 of the semiconductor body 203.

[0037] At S370 in Figure 3 and as shown in Figure 2H , a drain region including a second p-type doped region 216 is formed at the second end 205 of the semiconductor body 203. The second p-type doped region 216 can be connected to a second LDD region 217. For example, the second p-type doped region 216 and the second LDD region 217 can be formed by etching away the semiconductor body 204 from the second end 205. A layer of semiconductor material (e.g., SiGe) can be formed by depositing or epitaxially growing on the semiconductor body 203, followed by doping with a p-type dopant and annealing. For example, the second p-type doped region 216 and the second LDD region 217 can be formed in a similar manner, with the second LDD region 217 first, followed by the second p-type region 216. For example, the second p-type doped region 216 can be formed by epitaxially growing p-type SiGe on the semiconductor body 203 from the second end 205. The second LDD region 217 can be grown first, followed by the second p-type doped region. For example, the second p-type doped region 216 can be formed by depositing p-type SiGe directly on the semiconductor body 203 from the second end 205. The second LDD region 217 can be deposited first, followed by the second p-type doped region 216.

[0038] In an embodiment, the second p-type doped region 216 can be doped by diffusion. In an embodiment, the second p-type doped region 216 can be doped by ion implantation. In an embodiment, the second p-type doped region 216 can be doped using a p-type dopant such as boron. However, other p-type dopants from group III elements can also be used. In an embodiment, the second LDD region 217 can have a generally lower than 10-1 19 atoms / cm 3 The region with the highest dopant concentration. According to aspects of this disclosure, the second p-type doped region 216 needs to have a dopant concentration higher than 10. 19 atoms / cm 3 The dopant concentration is p-type SiGe. In an embodiment, the second LDD region 217 can be an optional region. For example, the semiconductor body 203 may have only a second p-type doped region 216 at the second end 205.

[0039] According to this disclosure, after dopant impurity atoms are diffused or implanted into the semiconductor body 203 to form a second p-type doped region 216, a dopant activation process is performed. The dopant activation process converts the dopant impurity atoms from a relatively inactive state to an electrically active state. The dopant activation process includes applying high-temperature annealing, such as rapid thermal annealing. The annealing temperature required to activate the dopant depends on the dopant material. For example, doping p-type SiGe will only require an annealing temperature of 500°C or less. Other dopant materials will require an annealing temperature of 750°C or greater. As... Figure 2F As shown, a memory device 214 is formed at the first end 204 of the semiconductor body 203. An annealing temperature of 500°C or less for doping the second p-type doped region 216 of p-type SiGe can prevent damage to the memory device 214.

[0040] exist Figure 3 At S380 in the middle and as Figure 2I As shown, bit line 218 can be formed, and bit line 218 is connected to the drain region. Bit line 218 is formed in the x-direction (e.g., Figure 2I and Figure 2J As shown), to be coupled and connected to rows of semiconductor bodies 203 (semiconductor bodies 203A, 203F, 203G, 203H and 203I) located in the y direction. Process 300 can proceed to S399 and terminate at S399.

[0041] Figure 4A block diagram of an exemplary system 400 having a memory system according to embodiments of the present disclosure is shown. The system 400 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game controller, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other appropriate electronic device having a memory device therein.

[0042] As shown, the system 400 can include a host 408 and a memory system 402. The memory system 402 can have one or more memory devices 404 and a memory controller 406. The host 408 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 408 can be configured to send or receive data to or from the one or more memories 404. Figure 4

[0043] The one or more memories 404 can be memory devices disclosed in the present disclosure, for example, the one or more memories 404 can include the memory device 100 provided by the present disclosure. As disclosed in detail below, the one or more memories 404 (e.g., a DRAM device) can have a vertical transistor structure using at least p-type SiGe for bit line connections at a drain region.

[0044] In embodiments, the memory controller 406 is coupled to the one or more memories 404 and the host 408, and is configured to control the one or more memories 404. The memory controller 406 can manage data stored in the one or more memories 404, and communicate with the host 408. The memory controller 406 is configured to control the one or more memories 404 to perform a programming method provided by any embodiment of the present disclosure.

[0045] In embodiments, the memory controller 406 is designed for operation in main memory used as an instruction and data storage device when a program is executed by an electronic device (e.g., a personal computer, a digital camera, a mobile phone, a tablet, etc.). The memory controller 406 can be configured to control operations of the memory device 404, such as read, erase, and program operations. The memory controller 406 can also be configured to manage various functions regarding data stored or to be stored in the memory device 404.

[0046] The memory controller 406 can communicate with an external device (e.g., the host 408) according to a specific communication protocol.

[0047] ​The memory controller 406 and one or more memories 404 can be integrated into various types of memory devices, e.g., included in the same package (e.g., DDR SDRAM). The memory system 402 can be implemented and packaged into different types of end electronic devices.

[0048] While aspects of the disclosure have been described in connection with the various embodiments described, it is to be understood that the disclosure is not limited to the specific embodiments disclosed. On the contrary, it is intended to cover various modifications, alternatives, and equivalents. Accordingly, the disclosure as set forth herein is intended to be illustrative not limiting. Changes can be made without departing from the scope of the claims as set forth below.

Claims

1. A method for manufacturing a semiconductor device, comprising: Provide substrate; The substrate is etched from a first side to form at least one vertical pillar having a first end and a second end opposite to the first end; At least one gate line is formed on the gate dielectric layer, the gate dielectric layer being formed on the sidewall of the at least one vertical pillar; A first p-shaped region is formed at the first end of the at least one vertical column; Forming a storage device that connects to the first p-type region; A portion of the substrate located on the second side of the substrate is removed to expose the second end of the at least one vertical pillar, the second side of the substrate being opposite to the first side of the substrate; A second p-type region is formed at the second end of the at least one vertical column, the second p-type region being made of at least p-type silicon germanium (SiGe); as well as A bit line is formed that connects to the second p-type region located at the second end of the at least one vertical column.

2. The method according to claim 1, wherein, The formation of the second p-type region also includes: The hot annealing process is performed at an annealing temperature of less than 500°C.

3. The method according to claim 1, wherein, The formation of the second p-type region also includes: The p-type silicon-germanium is epitaxially attached to the at least one vertical pillar.

4. The method according to claim 1, wherein, The formation of the second p-type region also includes: The p-type silicon-germanium is deposited onto the at least one vertical pillar.

5. The method according to claim 1, wherein, The first p-type region has a value higher than 10. 19 atoms / cm 3 The dopant concentration.

6. The method according to claim 1, wherein, The second p-type region has a value higher than 10. 19 atoms / cm 3 The dopant concentration.

7. The method according to claim 1, wherein, The at least one gate line and the bit line are formed such that they are perpendicular to each other.

8. The method according to claim 1, wherein, The at least one gate line is encapsulated by an oxide layer.

9. The method according to claim 1, wherein, The storage device is a capacitor.

10. A semiconductor device, comprising: At least one vertical column, the at least one vertical column having a first end and a second end opposite to the first end; At least one gate line is located on a gate dielectric layer, the gate dielectric layer being formed on the sidewall of the at least one vertical pillar; A first p-shaped region, the first p-shaped region being located at the first end of the at least one vertical column; A storage device, wherein the storage device is connected to the first p-type region; The second p-type region is located at the second end of the at least one vertical pillar, and the second p-type region includes at least p-type silicon germanium (SiGe). as well as Bit line, the bit line being connected to the second p-type region located at the second end of the at least one vertical column.

11. The semiconductor device according to claim 10, wherein, The first p-type region has a value higher than 10. 19 atoms / cm 3 The dopant concentration.

12. The semiconductor device according to claim 10, wherein, The second p-type region has a value higher than 10. 19 atoms / cm 3 The dopant concentration.

13. The semiconductor device according to claim 10, wherein, The gate line and the bit line are formed such that they are perpendicular to each other.

14. The semiconductor device according to claim 10, wherein, The gate line is encapsulated by an oxide layer.

15. The semiconductor device according to claim 10, wherein, The storage device is a capacitor.

16. A memory system, comprising: A semiconductor device configured to store data, and comprising: At least one vertical column, the at least one vertical column having a first end and a second end opposite to the first end; At least one gate line is located on a gate dielectric layer, the gate dielectric layer being formed on the sidewall of the at least one vertical pillar; A first p-shaped region, the first p-shaped region being located at the first end of the at least one vertical column; A storage device, wherein the storage device is connected to the first p-type region; A second p-type region, located at the second end of the at least one vertical pillar, comprising at least p-type silicon-germanium (SiGe); and Bit lines, the bit lines being connected to the second p-type region located at the second end of the at least one vertical pillar; and A memory controller coupled to the semiconductor device and configured to control the semiconductor device via the at least one gate line and the bit line.

17. The memory system according to claim 16, wherein, The at least one gate line and the bit line are perpendicular to each other.

18. The memory system according to claim 16, wherein, The storage device is a capacitor.

19. The memory system according to claim 16, wherein, The first p-type region has a value higher than 10. 19 atoms / cm 3 The dopant concentration.

20. The memory system of claim 16, wherein, The second p-type region has a value higher than 10. 19 atoms / cm 3 The dopant concentration.

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