Semiconductor device and method for manufacturing the same

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the same. In the semiconductor device, a first HKMG transistor having a first threshold voltage forms a first memory cell, and a second HKMG transistor having a second threshold voltage forms a second memory cell. The difference between the first and second threshold voltages allows the first and second memory cells to form different conduction states, enabling 0 / 1 state readout. The fabrication of the first and second HKMG transistors is compatible with the HKMG process and can be formed together with other devices on the HKMG process platform, helping to increase the integration density of the semiconductor device and reduce process complexity. Furthermore, the first and second HKMG transistors do not employ a floating gate structure, resulting in a lower operating voltage and compatibility with the processes of low-voltage devices (such as logic devices).

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] EEPROM (Electrically Erasable Programmable Read-Only Memory) is a semiconductor memory device that can be rewritten multiple times electronically. Current EEPROM devices use a floating-gate tunnel oxide transistor structure to form the memory cell. An external strong electric field enables bidirectional electron flow between the drain and floating gate, thereby controlling the memory cell.

[0003] In addition, with the development of manufacturing technology and the reduction of critical dimensions, the HKMG (high dielectric constant gate dielectric and metal gate) process has the advantages of reducing gate dielectric leakage current and avoiding polysilicon gate depletion effect, and has now been applied to CMOS integrated circuit manufacturing.

[0004] However, the above-mentioned structure of the EEPROM device makes it difficult to be compatible with the HKMG process, which increases the process difficulty and reduces the integration density. Moreover, since the control gate needs to be connected to a high voltage (usually not less than 12V) during writing to form a strong positive electric field between the floating gate and the drain to allow electrons to pass from the drain through the tunnel oxide layer into the floating gate, the existing EEPROM device structure is also incompatible with low-voltage device processes. Summary of the Invention

[0005] In order to solve the problem that current memory devices using a floating gate tunnel oxide layer transistor structure are incompatible with the HKMG process and the low voltage device process, the present invention provides a semiconductor device and a method for manufacturing the semiconductor device.

[0006] In one aspect, the present invention provides a semiconductor device, comprising:

[0007] a substrate comprising a first conductivity type doped region;

[0008] at least one first HKMG transistor having a first threshold voltage, formed on a surface of a corresponding first conductivity type doped region, wherein a gate and a source / drain region of the first HKMG transistor are of the second conductivity type; and

[0009] at least one second HKMG transistor having a second threshold voltage, formed on a surface of a corresponding first conductivity type doped region, wherein a gate of the second HKMG transistor has the first conductivity type and a source and drain region has the second conductivity type;

[0010] The first HKMG transistor forms a first storage unit, the second HKMG transistor forms a second storage unit, and the first storage unit and the second storage unit form different conduction states according to the difference between the first threshold voltage and the second threshold voltage, thereby realizing 0 / 1 state reading.

[0011] Optionally, the substrate has a first conductivity type doping or a second conductivity type doping, and the first conductivity type doping region is formed by the substrate or by a well region formed in the substrate.

[0012] Optionally, the difference between the first threshold voltage and the second threshold voltage is (1±x)V, where x is a value greater than 0 and less than 1.

[0013] Optionally, the first threshold voltage is lower than the second threshold voltage.

[0014] Optionally, the gate of the first HKMG transistor includes a second conductivity type work function adjustment layer and an electrode material layer stacked on the second conductivity type work function adjustment layer.

[0015] Optionally, the gate of the second HKMG transistor includes a first conductivity type work function adjustment layer and an electrode material layer stacked on the first conductivity type work function adjustment layer.

[0016] Optionally, at least one pair of adjacent first HKMG transistors and second HKMG transistors shares the same first conductivity type doping region.

[0017] Optionally, at least one pair of adjacent first HKMG transistors and second HKMG transistors share the same source and drain region; or at least one pair of adjacent first HKMG transistors and second HKMG transistors do not share the same source and drain region.

[0018] Optionally, the semiconductor device further includes a logic transistor formed on the surface of the substrate, and the logic transistor has an HKMG gate structure.

[0019] In another aspect, the present invention provides a method for manufacturing a semiconductor device, the method comprising:

[0020] providing a substrate, the substrate comprising a first conductivity type doped region; and

[0021] At least one first HKMG transistor and at least one second HKMG transistor are formed on the surface of the first conductivity type doped region, wherein the gate and source / drain regions of the first HKMG transistor are of the second conductivity type, and the gate and source / drain regions of the second HKMG transistor are of the first conductivity type and the source / drain regions are of the second conductivity type. The first HKMG transistor has a first threshold voltage and forms a first memory cell, and the second HKMG transistor has a second threshold voltage and forms a second memory cell. The first memory cell and the second memory cell have different conduction states according to a difference between the first threshold voltage and the second threshold voltage, thereby realizing 0 / 1 state readout.

[0022] Optionally, forming at least one first HKMG transistor and at least one second HKMG transistor on the surface of the first conductive type doped region includes:

[0023] forming a first dummy gate and a second dummy gate on the surface of the first conductive type doped region, respectively, and forming sidewalls, corresponding source and drain regions, and an interlayer dielectric layer on both sides of the first dummy gate and the second dummy gate, wherein the upper surface of the interlayer dielectric layer is flush with the upper surfaces of the first dummy gate and the second dummy gate;

[0024] removing the first dummy gate and forming a first groove at the location of the first dummy gate;

[0025] forming a first gate dielectric layer and a second conductive type work function adjustment layer on the inner wall of the first groove and filling the inner wall with electrode material, wherein the first gate dielectric layer comprises a high dielectric constant material;

[0026] performing a planarization process to expose the upper surface of the interlayer dielectric layer, wherein the remaining conductive material in the first groove and the second conductive type work function adjustment layer form the gate of the first HKMG transistor, and the source and drain regions on both sides of the first groove serve as the source and drain regions of the first HKMG transistor;

[0027] removing the second dummy gate and forming a second groove at the location of the second dummy gate;

[0028] forming a second gate dielectric layer and a first conductive type work function adjustment layer on an inner wall of the second groove and filling the inner wall with an electrode material, wherein the second gate dielectric layer comprises a high dielectric constant material; and

[0029] A planarization process is performed to expose the upper surface of the interlayer dielectric layer. The remaining conductive material in the second groove and the first conductive type work function adjustment layer form the gate of the second HKMG transistor. The source and drain regions on both sides of the second groove serve as the source and drain regions of the second HKMG transistor.

[0030] In the semiconductor device and method for fabricating the semiconductor device provided by the present invention, a first HKMG transistor having a first threshold voltage forms a first memory cell, and a second HKMG transistor having a second threshold voltage forms a second memory cell. The difference between the first and second threshold voltages allows the first and second memory cells to have different conduction states, enabling 0 / 1 state readout. The fabrication of the first and second HKMG transistors is compatible with the HKMG process and can be formed together with other devices on the HKMG process platform, helping to increase the integration density of the semiconductor device and reduce process complexity. Furthermore, the first and second HKMG transistors do not employ a floating gate structure, resulting in a lower operating voltage and compatibility with processes for low-voltage devices (such as logic devices). BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 FIG. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.

[0032] Figure 2 FIG. 4 is a schematic structural diagram of a semiconductor device according to another embodiment of the present invention.

[0033] Figure 3 FIG. 1 is a plan view of a first storage unit and a second storage unit in one embodiment of the present invention.

[0034] Figure 4 FIG. 4 is a circuit diagram of a first storage unit and a second storage unit in one embodiment of the present invention.

[0035] Figure 5 It is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0036] Figures 6A to 6E It is a cross-sectional schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The semiconductor device and manufacturing method of the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the drawings in the specification are in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly illustrate the purpose of the embodiments of the present invention. It should be noted that the order of the steps in the method presented herein is not necessarily the only order in which these steps are performed. Some of the steps described may be omitted and / or some other steps not described herein may be added to the method.

[0038] The following first refers to Figures 1 to 4 A semiconductor device according to an embodiment of the present invention will be described.

[0039] Reference Figure 1 and Figure 2 In an embodiment of the present invention, the semiconductor device includes a substrate 100, and the substrate 100 includes a first conductive type doped region.

[0040] Substrate 100 may be a silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a Group III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate), or may be other substrate materials known to those skilled in the art for supporting semiconductor devices. In the following description, substrate 100 is, for example, a silicon substrate. Certain dopant ions may be implanted into substrate 100 to adjust electrical parameters according to design requirements, and isolation structures (e.g., shallow trench isolation (STI) and / or deep trench isolation (DTI)) may be formed within substrate 100.

[0041] The substrate 100 may have a first conductive type doping or a second conductive type doping. In one embodiment, the first conductive type doping region is formed by the substrate 100 having the first conductive type doping. However, the first conductive type doping region may also be formed by a well region (such as Figure 1 and Figure 2 The P-well (PW) shown is formed.

[0042] like Figure 1 and Figure 2 As shown, the semiconductor device further includes at least one first HKMG transistor 10 and at least one second HKMG transistor 20, wherein the first HKMG transistor 10 has a first threshold voltage (Vth1) and the second HKMG transistor 20 has a second threshold voltage (Vth2). "HKMG" indicates that the first HKMG transistor 10 and the second HKMG transistor 20 utilize a gate dielectric layer comprising a high-k dielectric material (high k, where k represents a dielectric constant) and a metal gate structure.

[0043] The first conductivity type may be P-type or N-type, with P-type and N-type being opposite. In the case where the substrate 100 is a silicon substrate, the dopant used to form the N-type doping includes, for example, phosphorus (P) or arsenic (As), and the dopant used to form the P-type doping includes, for example, boron (B) or boron difluoride (BF2).

[0044] like Figure 1 As shown, in one embodiment, at least one pair of adjacent first HKMG transistors 10 and second HKMG transistors 20 may share the same P-well (i.e., share the same first conductivity type doped region), i.e., at least one pair of adjacent first HKMG transistors 10 and second HKMG transistors 20 are formed on the same P-well surface. In another embodiment, the first HKMG transistor 10 and second HKMG transistor 20 are formed on different P-well surfaces.

[0045] The first HKMG transistor 10 and the second HKMG transistor 20 each include a gate and source / drain regions (eg, Figure 1 and Figure 2 A first gate dielectric layer 111 may be provided between the gate of the first HKMG transistor 10 and the substrate 100, and a second gate dielectric layer 113 may be provided between the gate of the second HKMG transistor 20 and the substrate 100. The first gate dielectric layer 111 and the second gate dielectric layer 113 may include, for example, a high-k dielectric material. The high-k dielectric material has a dielectric constant greater than that of silicon oxide. The high-k dielectric material may include, for example, Al2O3, Ta2O5, ZrO2, LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Si3N4, TiO2, and at least one of oxynitrides.

[0046] like Figure 1 As shown, in one embodiment, at least one pair of adjacent first HKMG transistors 10 and second HKMG transistors 20 share the same source and drain region. As an example, the first HKMG transistor 10 and the second HKMG transistor 20 share a drain region. However, the present invention is not limited thereto. Figure 2 As shown, in some other embodiments, the source and drain regions of at least one pair of adjacent first HKMG transistors 10 and second HKMG transistors 20 are not shared, and are isolated by a shallow trench isolation (STI) structure.

[0047] The conductivity type of the source and drain regions of the first HKMG transistor 10 and the second HKMG transistor 20 is opposite to that of the first conductivity type doped region, that is, the second conductivity type. Figure 1 and Figure 2 As shown, taking the case where the first conductivity type is P-type and the second conductivity type is N-type as an example, the first HKMG transistor 10 and the second HKMG transistor 20 are N-channel transistors, and the source and drain regions are N-type doped. In another embodiment, the first conductivity type is N-type and the second conductivity type is P-type, the first HKMG transistor 10 and the second HKMG transistor 20 are P-channel transistors, and the source and drain regions are P-type doped.

[0048] In the embodiment of the present invention, the gate conductivity types of the first HKMG transistor 10 and the second HKMG transistor 20 are different. The gate of the first HKMG transistor 10 ( Figure 1 and Figure 2 Indicated as “NMG”) is, for example, an N-type, and the gate of the second HKMG transistor 20 ( Figure 1 and Figure 2Expressed as "PMG"), for example, it is of P type. As an example, the gate of the first HKMG transistor 10 may include an N-type work function adjustment layer and an electrode material layer stacked on the N-type work function adjustment layer, and the gate of the second HKMG transistor 20 may include a P-type work function adjustment layer and an electrode material layer stacked on the P-type work function adjustment layer. By selecting the N-type work function adjustment layer and the P-type work function adjustment layer, the gate conduction types and work functions of the first HKMG transistor 10 and the second HKMG transistor 20 can be made different, so that the threshold voltages are different. The N-type work function adjustment layer is, for example, TiAl, the P-type work function adjustment layer is, for example, TiN, and the electrode material layer includes, for example, Al.

[0049] In this embodiment, the gate of the second HKMG transistor 20 formed on the surface of the first conductive type doped region is of the second conductive type, which is the same as the conductive type of the first conductive type doped region. The second threshold voltage (Vth2) of the second HKMG transistor 20 is greater than the first threshold voltage (Vth1) of the first HKMG transistor 10, that is, Vth1 < Vth2. As an example, the difference between the first threshold voltage and the second threshold voltage is (1 ± x)V, where x is a value greater than 0 and less than 1, that is, the difference between the first threshold voltage and the second threshold voltage is, for example, about 1V.

[0050] In the embodiment of the present invention, by using the threshold voltage difference between the first HKMG transistor 10 and the second HKMG transistor 20, the first storage unit is formed by the first HKMG transistor 10, and the second storage unit is formed by the second HKMG transistor 20, and the ROM (Read Only Memory) function can be realized. The first storage unit and the second storage unit can form different conduction states according to the difference between the first threshold voltage and the second threshold voltage, so as to realize the readout of the 0 / 1 state (referring to the binary symbols 0 and 1).

[0051] Refer to Figure 3 and Figure 4In one embodiment, the drain terminal (D) of the first HKMG transistor 10 and the gate terminal of the second HKMG transistor 20 are shared and connected, so that the drain terminal voltage and the gate terminal voltage are the same. For example, the gate voltage and the drain terminal voltage are both VDD, and VDD is, for example, 0.8V to 1.2V. The first HKMG transistor 10 and the second HKMG transistor 20 jointly form a storage bit; wherein the first storage unit formed by the first HKMG transistor 10 has a first state reading point N1 (i.e., Node1) located at the source terminal (S) of the first HKMG transistor 10, and the first state reading point N1 is used to read 1, for example. The second storage unit formed by the second HKMG transistor 20 has a second state reading point N2 (i.e., Node2) located at the source terminal of the second HKMG transistor 20, and the second state reading point N2 is used to read 0, for example. The corresponding reading point can be selected as needed. Because the first threshold voltage (Vth1) of the first HKMG transistor 10 is lower than the second threshold voltage (Vth2) of the second HKMG transistor 20, when the gate voltage VDD is greater than Vth1 and less than Vth2, the first HKMG transistor 10 is turned on while the second HKMG transistor 20 is turned off. By detecting the source current or voltage of the first HKMG transistor 10, a first state signal (e.g., 1) can be obtained. When the gate voltage VDD is greater than Vth2, both the first HKMG transistor 10 and the second HKMG transistor 20 are turned on. By detecting the source current or voltage of the second HKMG transistor 20, a second state signal (e.g., 0) can be obtained.

[0052] However, the present invention is not limited to Figure 3 and Figure 4 In the illustrated embodiment, for example, in another embodiment, the source and drain terminals of the first HKMG transistor 10 and the second HKMG transistor 20 are independently controlled, and the gate terminals can also be independently controlled. When reading a signal, the drain terminals and gate terminals of the first HKMG transistor 10 and the second HKMG transistor 20 can be connected to VDD. The source voltage or current of the first HKMG transistor 10 and the second HKMG transistor 20 can be detected at the corresponding gate voltage to obtain the corresponding status signal.

[0053] The first HKMG transistor 10 and the second HKMG transistor 20 can be formed using an HKMG process, making them compatible with the HKMG process without requiring additional process steps. Therefore, they can be integrated on the same substrate 100 with other devices fabricated using the HKMG process platform. As an example, in one embodiment, in addition to the first HKMG transistor 10 and the second HKMG transistor 20, the semiconductor device may also include a logic transistor formed on the surface of the substrate 100. The logic transistor may, for example, employ an HKMG gate structure, but is not limited thereto. The logic transistor may also employ a non-HKMG gate structure, such as a gate oxide layer and a polysilicon gate formed on the gate oxide layer. Furthermore, the first HKMG transistor 10 and the second HKMG transistor 20 do not employ a floating gate structure, resulting in a lower operating voltage and compatibility with low-voltage device processes. The semiconductor device may be, for example, a semiconductor chip or module. This high compatibility helps increase the integration density of semiconductor devices and reduce process complexity.

[0054] An embodiment of the present invention further relates to a method for manufacturing a semiconductor device, which can be used to manufacture the semiconductor device described in the above embodiment.

[0055] Reference Figure 5 and Figure 6A According to an embodiment of the present invention, first, step S1 is performed to provide a substrate 100, wherein the substrate 100 includes a first conductivity type doped region. The substrate 100 is, for example, a silicon substrate. The substrate 100 may have a first conductivity type doping region or a second conductivity type doping region. The first conductivity type doped region may be formed by the substrate 100, or the first conductivity type doped region may be formed by a well region formed in the substrate 100. As an example, the first conductivity type is P-type, and the first conductivity type doped region is a P-well (PW) formed in the substrate 100.

[0056] According to an embodiment of the present invention, step S2 is then performed to form at least one first HKMG transistor and at least one second HKMG transistor on the surface of the first conductivity type doped region, wherein the gate and source / drain regions of the first HKMG transistor are of the second conductivity type, and the gate and source / drain regions of the second HKMG transistor are of the first conductivity type and the source / drain regions are of the second conductivity type. The first HKMG transistor has a first threshold voltage and forms a first storage cell, and the second HKMG transistor has a second threshold voltage and forms a second storage cell. The first storage cell and the second storage cell have different conduction states according to the difference between the first threshold voltage and the second threshold voltage, thereby realizing 0 / 1 state readout.

[0057] As an example, step S2 may include the following process.

[0058] First, refer to Figure 6A , respectively forming a first dummy gate DG1 and a second dummy gate DG2 on the surface of the corresponding first conductive type doping region, and forming sidewalls SP, source and drain regions (such as Figure 6A The first conductive type doped region is illustratively a P-well (PW), and the first dummy gate DG1 and the second dummy gate DG2 are formed on the surface of the same P-well. The first dummy gate DG1 and the second dummy gate DG2 are, for example, polysilicon, and an oxide layer may be formed between them and the substrate 100.

[0059] Afterwards, refer to Figure 6B The second dummy gate DG2 is protected by a mask (not shown), and the first dummy gate DG1 is removed by etching to form a first groove T1 at the location of the first dummy gate DG1. The oxide layer under the first dummy gate DG1 can also be removed.

[0060] Next, refer to Figure 6C A first gate dielectric layer 111 and a second conductive type work function adjustment layer 113 are formed on the inner wall of the first groove T1, and an electrode material 115 is filled. Then, a planarization process is performed to expose the upper surface of the interlayer dielectric layer 120. The remaining electrode material 115 and the second conductive type work function adjustment layer 113 in the first groove T1 form the gate of the first HKMG transistor 10. The source and drain regions on both sides of the gate are the source and drain regions of the first HKMG transistor 10. The gate of the first HKMG transistor 10 and the source and drain regions on both sides thereof have the second conductivity type (e.g., N-type). Figure 6C The gate of the first HKMG transistor 10 is represented by "NMG". The first gate dielectric layer 111 includes a high-k dielectric material. The second conductive type work function adjustment layer 113 is, for example, an N-type work function adjustment layer, such as TiAl. The electrode material 115 includes, for example, Al.

[0061] Afterwards, refer to Figure 6D A mask (not shown) is used to protect the gate of the first HKMG transistor 10, and the second dummy gate DG2 is removed by etching, forming a second groove T2 at the location of the second dummy gate DG2. The oxide layer under the second dummy gate DG2 can also be removed.

[0062] Next, refer to Figure 6EA second gate dielectric layer 112 and a first conductive type work function adjustment layer 114 are formed on the inner wall of the second groove T2, and an electrode material 116 is filled. A planarization process is then performed to expose the upper surface of the interlayer dielectric layer 120. The remaining conductive material in the second groove T2 and the first conductive type work function adjustment layer 114 form the gate of the second HKMG transistor 20. The source and drain regions on both sides of the gate serve as the source and drain regions of the second HKMG transistor 20. The gate of the second HKMG transistor 20 has a first conductivity type (e.g., P-type). Figure 6E The source and drain regions of the second HKMG transistor 20 are of the second conductivity type, denoted by PMG. The second gate dielectric layer 112 comprises a high-k dielectric material. The first conductivity type work function adjustment layer 114 is, for example, a P-type work function adjustment layer, such as TiN. The electrode material 116 comprises, for example, Al.

[0063] The first HKMG transistor 10 and the second HKMG transistor 20 formed by the above process have different gate conductivity types and, consequently, different work functions. The first HKMG transistor 10 and the second HKMG transistor 20 have different threshold voltages, forming a first memory cell and a second memory cell, respectively. By utilizing the difference in threshold voltages between the first HKMG transistor 10 and the second HKMG transistor 20, the first memory cell and the second memory cell can have different conduction states, thereby enabling 0 / 1 state readout. In embodiments of the present invention, the fabrication of the first HKMG transistor 10 and the second HKMG transistor 20 is compatible with the HKMG process. The first HKMG transistor 10 and the second HKMG transistor 20 can be formed together with other devices on the HKMG process platform, thereby increasing the integration density of semiconductor devices and reducing process complexity. Furthermore, the first HKMG transistor 10 and the second HKMG transistor 20 do not employ a floating gate structure, resulting in a lower operating voltage and compatibility with processes for low-voltage devices (such as logic devices).

[0064] It should be noted that the embodiments in this specification are described in a progressive manner, and each part focuses on the differences from other embodiments. The relevant parts can be understood by reference.

[0065] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A semiconductor device, characterized in that: include: a substrate comprising a first conductivity type doped region; At least one first HKMG transistor having a first threshold voltage is formed on a surface of a corresponding first conductivity type doped region, wherein a gate and a source / drain region of the first HKMG transistor are of the second conductivity type; as well as at least one second HKMG transistor having a second threshold voltage, formed on a surface of a corresponding first conductivity type doped region, wherein a gate of the second HKMG transistor has the first conductivity type and a source and drain region has the second conductivity type; The first HKMG transistor forms a first storage unit, the second HKMG transistor forms a second storage unit, and the first storage unit and the second storage unit form different conduction states according to the difference between the first threshold voltage and the second threshold voltage, thereby realizing 0 / 1 state reading.

2. The semiconductor device according to claim 1, wherein The substrate has a first conductivity type doping or a second conductivity type doping, and the first conductivity type doping region is formed by the substrate or by a well region formed in the substrate.

3. The semiconductor device according to claim 1, wherein The difference between the first threshold voltage and the second threshold voltage is (1±x)V, where x is a value greater than 0 and less than 1.

4. The semiconductor device according to claim 1, wherein The first threshold voltage is lower than the second threshold voltage.

5. The semiconductor device according to claim 1, wherein The gate of the first HKMG transistor includes a second conductive type work function adjusting layer and an electrode material layer stacked on the second conductive type work function adjusting layer.

6. The semiconductor device according to claim 1, wherein The gate of the second HKMG transistor includes a first conductive type work function adjustment layer and an electrode material layer stacked on the first conductive type work function adjustment layer.

7. The semiconductor device according to claim 1, wherein At least one pair of adjacent first HKMG transistors and second HKMG transistors shares the same first conductive type doping region.

8. The semiconductor device according to claim 1, wherein At least one pair of adjacent first HKMG transistors and second HKMG transistors share the same source and drain region; or at least one pair of adjacent first HKMG transistors and second HKMG transistors do not share the same source and drain region.

9. The semiconductor device according to any one of claims 1 to 8, wherein The invention also includes a logic transistor formed on the surface of the substrate, wherein the logic transistor has an HKMG gate structure.

10. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising a first conductivity type doped region; as well as At least one first HKMG transistor and at least one second HKMG transistor are formed on the surface of the first conductivity type doped region, wherein the gate and source / drain regions of the first HKMG transistor are of the second conductivity type, and the gate and source / drain regions of the second HKMG transistor are of the first conductivity type and the source / drain regions are of the second conductivity type. The first HKMG transistor has a first threshold voltage and forms a first memory cell, and the second HKMG transistor has a second threshold voltage and forms a second memory cell. The first memory cell and the second memory cell have different conduction states according to a difference between the first threshold voltage and the second threshold voltage, thereby realizing 0 / 1 state readout.

11. The production method according to claim 10, characterized in that: Forming at least one first HKMG transistor and at least one second HKMG transistor on the surface of the first conductive type doped region includes: forming a first dummy gate and a second dummy gate on the surface of the first conductive type doped region, respectively, and forming sidewalls, corresponding source and drain regions, and an interlayer dielectric layer on both sides of the first dummy gate and the second dummy gate, wherein the upper surface of the interlayer dielectric layer is flush with the upper surfaces of the first dummy gate and the second dummy gate; removing the first dummy gate and forming a first groove at the location of the first dummy gate; forming a first gate dielectric layer and a second conductive type work function adjustment layer on the inner wall of the first groove and filling the inner wall with electrode material, wherein the first gate dielectric layer comprises a high dielectric constant material; performing a planarization process to expose the upper surface of the interlayer dielectric layer, wherein the remaining conductive material in the first groove and the second conductive type work function adjustment layer form the gate of the first HKMG transistor, and the source and drain regions on both sides of the first groove serve as the source and drain regions of the first HKMG transistor; removing the second dummy gate and forming a second groove at the location of the second dummy gate; forming a second gate dielectric layer and a first conductive type work function adjustment layer on an inner wall of the second groove and filling the inner wall with an electrode material, wherein the second gate dielectric layer comprises a high dielectric constant material; and A planarization process is performed to expose the upper surface of the interlayer dielectric layer. The remaining conductive material in the second groove and the first conductive type work function adjustment layer form the gate of the second HKMG transistor. The source and drain regions on both sides of the second groove serve as the source and drain regions of the second HKMG transistor.

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