High performance p-type two-dimensional transistor based on zonedoping and preparation method thereof

Abstract

The application discloses a high-performance p-type two-dimensional transistor based on partition doping and a preparation method thereof, and mainly solves the problem that a high-performance p-type two-dimensional transistor cannot be realized in the prior art. The scheme comprises the following steps: an insulating substrate, a two-dimensional material channel layer, two-dimensional material source-drain contact parts located on both ends of the channel layer and source-drain electrodes located on the two-dimensional material source-drain contact parts respectively, a gate dielectric layer located on the two-dimensional material channel layer and the source-drain electrodes, and a gate electrode located on the gate dielectric; the p-type heavily doped source-drain contact parts of the two-dimensional material in the two-dimensional transistor and the lightly doped / undoped channel layer of the two-dimensional material are prepared separately, then the two parts are laminated in alignment, p-type partition doping of the two-dimensional transistor is realized, and thickness control is simultaneously realized. The application can effectively improve the conductive performance of the device while keeping the gate control capability of the two-dimensional transistor.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and further relates to high-performance two-dimensional transistor technology, specifically a high-performance p-type two-dimensional transistor based on partitioned doping and its fabrication method, which can be used to fabricate high-performance p-type two-dimensional field-effect transistors. Background Technology

[0002] With the development of semiconductor device manufacturing technology, traditional silicon-based transistors have encountered a series of problems when shrinking to the nanometer scale, such as short-channel effects, increased power consumption, and difficulties in thermal management. These problems have constrained further miniaturization and performance improvement of transistors. Two-dimensional field-effect transistors (FETs) use two-dimensional semiconductor materials as channel materials. Utilizing the atomic-level thickness of two-dimensional materials, device size can be further reduced without sacrificing switching performance, thus breaking through the miniaturization limits of silicon-based transistors. Two-dimensional semiconductor materials, especially transition metal dichalcogenides such as molybdenum disulfide and tungsten diselenide, possess many superior properties as channel materials for FETs. Their atomic-level thickness and excellent electrical properties can significantly reduce leakage current and quiescent power consumption in the channel, making them ideal for low-power devices. Simultaneously, two-dimensional materials also exhibit good mobility, enabling fast switching and efficient signal transmission at low voltages, suitable for high-speed circuit applications. Furthermore, two-dimensional semiconductor materials possess excellent mechanical flexibility and transparency, making them widely applicable in flexible electronics, wearable devices, and other fields, providing more possibilities for the diversity of future electronic products. These characteristics of two-dimensional semiconductor materials make them promising candidates for next-generation electronic devices, especially high-efficiency, low-power nanoelectronic devices.

[0003] As Moore's Law approaches its limits, there is an urgent need for novel semiconductor materials with comprehensive and superior performance. While two-dimensional materials meet many of the performance requirements for novel semiconductor materials, there are still many problems that need to be solved.

[0004] Research on p-type two-dimensional transistors is relatively lagging due to the inherent properties of two-dimensional materials and the Fermi level pinning effect. Existing two-dimensional semiconductor materials, such as transition metal dichalcogenides, mostly exhibit intrinsic n-type conductivity, making two-dimensional materials with excellent p-type characteristics scarce. Furthermore, the Fermi level pinning effect makes it difficult to tune the Schottky barrier when metals are in contact with two-dimensional materials, which significantly limits the realization of p-type two-dimensional transistors. The ideal CMOS-compatible mass production method for p-type two-dimensional transistors is p-type doping of the two-dimensional material. However, the common p-type doping method for two-dimensional transistors currently used in academia mainly involves uniform doping with dopant during the growth of the two-dimensional material. P-type two-dimensional transistors prepared using this uniform doping method suffer from severe gate control problems, making it difficult to turn off the transistor.

[0005] In silicon-based field-effect transistors (FETs), partitioned doping techniques can effectively optimize device performance. By controlling the doping concentration in different regions of the transistor channel, precise control of the electric field distribution can be achieved, thereby significantly improving carrier mobility, reducing source-drain resistance, and mitigating short-channel effects. However, compared to the atomically thin structure of silicon-based two-dimensional materials, the ion implantation doping methods commonly used in silicon-based devices cause severe lattice damage to the two-dimensional material during the process, destroying its inherent structural integrity and electrical properties, leading to severe degradation of the two-dimensional transistor's performance. Therefore, conventional partitioned doping techniques using ion implantation are difficult to apply to two-dimensional materials.

[0006] Currently, research on two-dimensional transistors still lacks a partitioned doping technique that can effectively improve their conductivity while maintaining their gate control performance. This technological bottleneck limits the large-scale fabrication of high-performance two-dimensional transistors, especially high-performance p-type devices, making it difficult to meet the growing demand for high-performance two-dimensional transistors. Summary of the Invention

[0007] The purpose of this invention is to address the shortcomings of existing technologies by proposing a high-performance p-type two-dimensional transistor based on partitioned doping and its fabrication method, thus solving the problem of the difficulty in achieving high-performance p-type two-dimensional transistors using existing technologies. First, the heavily p-type doped source / drain contact portions of the two-dimensional material in the two-dimensional transistor, and the lightly doped / undoped channel layer of the two-dimensional material are fabricated separately. Then, the two portions are aligned and laminated to achieve p-type partitioned doping of the two-dimensional transistor, while simultaneously achieving thickness control. This invention can effectively improve the conductivity of the device while maintaining the gate control capability of the two-dimensional transistor.

[0008] To achieve the above objectives, the technical solution of the present invention includes the following:

[0009] A high-performance p-type two-dimensional transistor based on partitioned doping includes: an insulating substrate 1, a two-dimensional material channel layer 2, a two-dimensional material source contact portion 3 and a two-dimensional material drain contact portion 4 located above the two ends of the channel layer, and a source electrode 5 and a drain electrode 6 located above the two, respectively, a gate dielectric layer 7 located above the two-dimensional material channel layer and the source and drain electrodes, and a gate electrode 8 located above the gate dielectric.

[0010] The two-dimensional material channel layer 2 is made of one of the two-dimensional semiconductor materials, and is either undoped or lightly doped; the two-dimensional semiconductor material includes at least tungsten diselenide and molybdenum diselenide;

[0011] The two-dimensional material source contact portion 3 and the two-dimensional material drain contact portion 4 are made of the same material as the two-dimensional material channel layer 2, and are heavily doped.

[0012] Furthermore, the thickness of the two-dimensional material channel layer (2) is 2 to 4 layers; the thickness of the two-dimensional material source contact portion (3) and the two-dimensional material drain contact portion (4) is the same, both being 2 to 4 layers.

[0013] Furthermore, the substrate is any one of the insulating substrate materials of SiO2 / Si, sapphire, and diamond; the gate dielectric is any one of the insulating dielectric layers of aluminum oxide, aluminum nitride, or silicon nitride; the gate electrode is Ni / Au, Pd / Au, or Pt / Au metal; and the source electrode and drain electrode are both Pd / Au or Pt / Au or metals compatible with the electrical properties of two-dimensional materials.

[0014] A method for fabricating a high-performance p-type two-dimensional transistor based on partitioned doping includes the following steps:

[0015] §1: Select the target substrate, and use acetone, isopropanol and deionized water to ultrasonically clean its surface, and then blow it dry with nitrogen to obtain a clean insulating substrate.

[0016] §2: Two-dimensional material source / drain contact portions and two-dimensional material channel layers are respectively fabricated and doped on sapphire substrates a and b. The doping is achieved by one of two different doping methods, substitutional doping and surface charge transfer doping, depending on actual needs, as detailed below:

[0017] ① Substitutional doping method: By using liquid phase epitaxy-assisted chemical vapor deposition, appropriate dopants are added during the growth process to grow lightly doped two-dimensional materials and heavily doped two-dimensional materials of different thicknesses on two cleaned sapphire substrates a and b, respectively.

[0018] ② Surface charge transfer doping method: Two-dimensional materials are grown on two cleaned sapphire substrates a and b by chemical vapor deposition. The two-dimensional material on substrate b is treated with nitride to obtain heavily doped two-dimensional material, while the two-dimensional material on substrate a is not treated.

[0019] §3: Transferring two-dimensional material films grown on sapphire substrate a to an insulating substrate using PMMA-assisted transfer method;

[0020] §4: The two-dimensional material transferred on the substrate is coated with adhesive, pre-baked, photolithographically etched, and developed. Then, isolation regions are etched out for arraying the two-dimensional material to obtain the two-dimensional material channel layer of the transistor.

[0021] §5: The heavily doped two-dimensional material on the sapphire substrate b obtained in step §2 is used to obtain patterned source and drain contact portions of the two-dimensional material to be transferred by photolithography and etching;

[0022] §6: Using the PDMS-assisted transfer method, the two-dimensional material source and drain contact parts to be transferred after etching on the sapphire substrate b are moved to their relative positions under an optical microscope by using the xy platform, and after alignment and lamination, they are transferred to the two-dimensional material channel layer (2) at both ends to obtain the two-dimensional material source contact parts and two-dimensional material drain contact parts (4) at both ends of the channel layer.

[0023] §7: Source and drain electrode metals are deposited on the surfaces of the source and drain contacts of the two-dimensional material through photolithography and electron beam evaporation. After the metals are deposited, the source and drain electrodes are formed through a lift-off process.

[0024] §8; On the surface of the two-dimensional material channel layer, source electrode and drain electrode, any one of aluminum oxide, aluminum nitride and silicon nitride insulating dielectric layers is deposited by atomic layer-by-layer or by magnetron sputtering as a gate dielectric layer;

[0025] §9: The gate electrode is fabricated on the surface of the gate dielectric layer to be etched by photolithography, electron beam evaporation deposition of gate metal and lift-off process;

[0026] §10: The area above the source and drain electrodes is patterned by photolithography, and then the gate dielectric layer is etched to expose the source and drain electrodes, thus completing the fabrication of the device.

[0027] Compared with the prior art, the present invention has the following advantages:

[0028] First, based on the common doped two-dimensional field-effect transistor, this invention designs a partitioned doping method, that is, the source and drain contact parts of the two-dimensional material are heavily doped separately, while the channel layer of the two-dimensional material is not doped or lightly doped. Then, the source and drain contact parts of the two-dimensional material are aligned and laminated on both ends of the two-dimensional material channel layer. This realizes the partitioned doping of the two-dimensional transistor, which enhances the conductivity while avoiding the channel part being degenerately doped, thus preventing the transistor from being unable to turn off, and improving the gate control capability of the transistor.

[0029] Secondly, this invention employs two doping methods: surface charge transfer doping and substitutional doping. Surface charge transfer doping is easier to implement and does not introduce lattice disorder that reduces carrier mobility, but it has poor controllability. Substitutional doping, on the other hand, can achieve different doping concentrations and corresponding electrical properties by adjusting different chemical proportions and reaction parameters during the preparation process. Compared to traditional ion implantation partitioning doping, the doping method used in this invention does not damage two-dimensional materials, is controllable, and is easier to implement.

[0030] Third, because the two-dimensional material in the transistor obtained by the partitioned doping method of this invention has a thick-thin-thick structure, that is, the source and drain contact portions at both ends are thick while the gate control channel portion in the middle is thin, this structure can improve the gate control capability of the two-dimensional transistor, and at the same time realize the individual control of the thickness of the channel portion that plays the role of gate control in the two-dimensional transistor, so as to fabricate transistors with different electrical performance according to the requirements; compared with the traditional method of thinning the channel portion of the transistor by direct etching, this invention avoids the uncontrollable damage to the two-dimensional material caused by etching.

[0031] Fourth, since the present invention uses chemical vapor deposition to prepare two-dimensional material thin films, compared with mechanical exfoliation, it can grow large-area, uniform two-dimensional material thin films. Furthermore, the number of layers and crystal quality of the two-dimensional material can be controlled by adjusting parameters such as gas flow rate, reaction temperature, and time, so as to batch prepare two-dimensional material field-effect transistors with different electrical properties.

[0032] Fifth, this invention uses PMMA wet transfer to achieve the transfer of two-dimensional material thin film layers, which can achieve uniform transfer on a large area substrate, effectively reducing mechanical damage to the molybdenum disulfide film during the transfer process, and helping to obtain higher quality films. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the device structure of the high-performance p-type two-dimensional transistor in this invention;

[0034] Figure 2 This is a schematic diagram illustrating the implementation process of the preparation method in this invention. Detailed implementation method:

[0035] The present invention will now be further described with reference to the accompanying drawings.

[0036] Example 1: Refer to Figure 1 The present invention proposes a high-performance p-type two-dimensional transistor based on partitioned doping, comprising: an insulating substrate 1, a two-dimensional material channel layer 2, a two-dimensional material source contact portion 3 and a two-dimensional material drain contact portion 4 located above the two ends of the channel layer, and a source electrode 5 and a drain electrode 6 located above the two, respectively, a gate dielectric layer 7 located above the two-dimensional material channel layer and the source and drain electrodes, and a gate electrode 8 located above the gate dielectric.

[0037] The aforementioned two-dimensional material channel layer 2 is made of one of the two-dimensional semiconductor materials, and is either undoped or lightly doped; the two-dimensional semiconductor material includes tungsten diselenide, molybdenum diselenide, molybdenum disulfide, etc.; the thickness is 2 to 4 layers;

[0038] The thickness of the two-dimensional material source contact portion 3 and the two-dimensional material drain contact portion 4 are the same. The materials used are the same as those used in the two-dimensional material channel layer 2, and they are heavily doped.

[0039] In this embodiment, the substrate 1 is any one of SiO2 / Si, sapphire, diamond, or other insulating substrate materials; the gate dielectric is any one of insulating dielectric layers such as alumina, aluminum nitride, and silicon nitride, preferably with a thickness of 10-50 nm; the gate electrodes are all made of metals such as Ni / Au, Pd / Au, and Pt / Au, preferably with a thickness of 5 / 25 nm; the source and drain electrodes are all made of Pd / Au or Pt / Au or other metals that can be adapted to the p-type electrical properties of two-dimensional materials, preferably with a thickness of 5 / 25 nm.

[0040] Example 2: Refer to Figure 2 The present invention proposes a method for fabricating a high-performance p-type two-dimensional transistor based on partitioned doping, which specifically includes the following steps:

[0041] Step §1: Select the target substrate, and use acetone, isopropanol and deionized water to ultrasonically clean its surface, and then blow it dry with nitrogen to obtain a clean insulating substrate.

[0042] Step §2: Two-dimensional material source / drain contact portions and two-dimensional material channel layers are respectively fabricated and doped on sapphire substrates a and b. The doping is achieved by one of two different doping methods, substitutional doping and surface charge transfer doping, depending on actual needs, as detailed below:

[0043] ① Substitutional doping method: Using liquid phase epitaxy-assisted chemical vapor deposition, appropriate dopants are added during the growth process to grow lightly doped two-dimensional materials and heavily doped two-dimensional materials of different thicknesses on two cleaned sapphire substrates a and b, respectively. The steps are as follows:

[0044] 1a) Select the appropriate reaction precursor and doping solution according to the type of two-dimensional material to be grown and the type of doping. Mix the metal precursor in the reaction precursor with the doping solution. The mixing ratio is determined according to the doping intensity.

[0045] 1b) Spin-coat the mixed solution onto the sapphire substrate according to the reaction requirements, and place other reaction precursors in the high-temperature zone or low-temperature zone of the tube furnace according to their type;

[0046] 1c) After spin-coating the mixed solution, place the clean sapphire substrate a used for growing lightly doped two-dimensional material films away from the high-temperature zone, set the working gas, keep the gas flow constant during the deposition process, and heat up at a rate of 15-20℃ / min until the set working temperature is reached. Then, control the reaction time according to the required two-dimensional material film thickness to obtain the lightly doped two-dimensional material film to be transferred.

[0047] 1d) Place the clean sapphire substrate b, which has been spin-coated with a mixed solution for growing heavily doped two-dimensional material films, away from the high-temperature zone, set the working gas, heat up to the set working temperature, and control the reaction time according to the required thickness to obtain the heavily doped two-dimensional material film to be transferred.

[0048] ② Surface charge transfer doping method: Two-dimensional materials are grown on two cleaned sapphire substrates a and b by chemical vapor deposition. The two-dimensional material on substrate b is treated with nitride to obtain heavily doped two-dimensional material, while the two-dimensional material on substrate a is not treated.

[0049] In this embodiment, a two-dimensional material is grown on two cleaned sapphire substrates a and b using chemical vapor deposition in this step, as follows:

[0050] 2a) Select the reaction precursors according to the type of two-dimensional material thin film to be grown, and place the different types of reaction precursors in the high-temperature zone and low-temperature zone of the tube furnace according to their reaction requirements.

[0051] 2b) Place the clean substrates a and b used for growing two-dimensional material films in an area a few centimeters away from the high-temperature sample to facilitate film growth;

[0052] 2c) Set the working gas and keep the gas flow constant during the deposition process. Increase the temperature at a rate of 15-20℃ / min until the set working temperature is reached. Then, control the reaction time according to the required thickness of the two-dimensional material film to obtain the two-dimensional material film to be transferred.

[0053] In this embodiment, the nitrogen oxide treatment involves exposing a sapphire substrate with two-dimensional materials grown on it to a stream of nitric oxide gas at 175°C for 4 hours.

[0054] Step §3: Transfer the two-dimensional material film grown on sapphire substrate a to an insulating substrate using PMMA-assisted transfer. The process is as follows: First, spin-coat PMMA onto the surface of the layer to be transferred and cure it on a hot plate at 90-120℃; then immerse the sample in the solution required for substrate separation for two hours to separate the PMMA-transfer layer from its substrate; next, transfer the separated floating PMMA-transfer layer to the target substrate, cure it, remove the PMMA by immersion in acetone, clean it with IPA, and finally dry it with nitrogen.

[0055] Step §4: The two-dimensional material transferred on the substrate is coated with adhesive, pre-baked, photolithographically etched, and developed. Then, isolation regions are etched out for arraying the two-dimensional material to obtain the two-dimensional material channel layer of the transistor.

[0056] Step §5: The heavily doped two-dimensional material on the sapphire substrate b obtained in Step §2 is used to obtain the patterned source and drain contact portions of the two-dimensional material to be transferred by photolithography and etching;

[0057] Step §6: Using the PDMS-assisted transfer method, the two-dimensional material source and drain contact portions etched on the sapphire substrate b are transferred to the two-dimensional material channel layer at both ends by moving their relative positions under an optical microscope using an xy platform, followed by alignment and lamination, thus obtaining the two-dimensional material source and drain contact portions at both ends of the channel layer.

[0058] The PDMS-assisted transfer method involves using a PDMS mold to pick up the etched two-dimensional material source / drain contact portion on the sapphire substrate b. The relative positions of these contacts are moved using an xy platform and aligned with the bottom two-dimensional material channel layer under an optical microscope. Finally, a motor-controlled manipulator is used to gradually push the two-dimensional material source / drain contact portion towards the bottom two-dimensional material channel layer along the z-axis, so that the two-dimensional material source / drain contact portion contacts the two-dimensional material channel layer.

[0059] Step §7: Deposit source and drain electrode metals on the surfaces of the two-dimensional material source contact portion and the two-dimensional material drain contact portion by photolithography and electron beam evaporation. After the metal is deposited, the source electrode and drain electrode are formed by a lift-off process.

[0060] Step §8: On the surface of the two-dimensional material channel layer, source electrode and drain electrode, any one of aluminum oxide, aluminum nitride and silicon nitride insulating dielectric layers is deposited by atomic layer-by-layer or by magnetron sputtering as a gate dielectric layer.

[0061] In this embodiment, the atomic layer-by-layer deposition in this step specifically involves pre-depositing a seed layer according to deposition requirements, cleaning the sample, setting the deposition temperature, ensuring good chamber vacuum, starting the ALD system, introducing the working gas, and controlling the deposition time according to the required gate dielectric layer thickness to deposit the gate dielectric layer to be etched on the two-dimensional material channel layer. Magnetron sputtering involves heating the substrate to a set temperature, using the appropriate target and working gas according to the type of encapsulation protective layer, and growing the gate dielectric layer to be etched on the substrate or two-dimensional material channel layer using the magnetron sputtering system at the reaction chamber temperature and controlling the sputtering time according to the required thickness.

[0062] Step §9: The gate electrode is fabricated on the surface of the gate dielectric layer to be etched by photolithography, electron beam evaporation deposition of gate metal, and lift-off process;

[0063] Step §10: Pattern the area above the source and drain electrodes using photolithography, and then etch the gate dielectric layer to expose the source and drain electrodes, thus completing the fabrication of the device.

[0064] Example 3: The overall implementation steps of the transistor fabrication method proposed in this example are the same as in Example 2. A specific example is provided to further describe the fabrication process of this invention: the substrate is SiO2 / Si, the gate dielectric layer is 50nm aluminum nitride, the two-dimensional material is tungsten diselenide, the channel layer has two layers, the source / drain contact portion has two layers, the doping method is substitutional doping via liquid-phase epitaxy-assisted chemical vapor deposition with the addition of a niobium-based solution, and the source / drain electrode metal is Pt / Au.

[0065] Step 1: Pretreatment of transistor substrate 1.

[0066] 200nm / 625μm SiO2 / Si was selected as the transistor substrate 1. The substrate 1 was ultrasonically cleaned for 5 minutes each in acetone solution, isopropanol and deionized water, and then dried with nitrogen gas.

[0067] Step 2: Two-dimensional material source / drain contact portions and two-dimensional material channel layers are prepared and doped on sapphire substrates a and b, respectively.

[0068] 2.1) Sapphire substrates a and b were ultrasonically cleaned with acetone for 20 minutes. After cleaning, the substrates were rinsed with deionized water 2 to 3 times, then immersed in deionized water for ultrasonic cleaning for 15 minutes. Finally, the substrates treated above were dried with nitrogen.

[0069] 2.2) The metal precursor is composed of a molybdenum-based solution and an appropriate amount of niobium-based solution. The tungsten-based solution is composed of ammonium metatungstate and sodium hydrate in deionized water at a volume ratio of 1:4. The niobium-doped solution is obtained by mixing 0.01 g of ammonium niobate oxalate hydrate with 10 mL of deionized water. The metal precursor is spin-coated onto the surface of sapphire substrate a. The sapphire substrate a is placed in a quartz boat in the high-temperature zone with the substrate surface facing upwards. The selenium source is high-purity selenium powder, which is placed in the low-temperature zone of the furnace tube near the outlet.

[0070] 2.3) Set up an argon-hydrogen mixture with argon and hydrogen flow rates of 100 sccm and 10 sccm, respectively. Maintain a constant gas flow during the deposition process. Turn on the tube furnace and set the heating rate to 15℃ / min to heat the high-temperature zone to 800℃ and the selenium powder zone to 375℃. After the temperature reaches the set value, maintain a constant temperature for about 15 minutes to grow a lightly doped tungsten diselenide film to be transferred on the surface of substrate a.

[0071] 2.4) A niobium-doped solution is obtained by mixing 10 mL of deionized water with 0.1 g of niobium ammonium oxalate hydrate. An appropriate amount of the niobium-doped solution is mixed with the same molybdenum-based solution as described in 2.2) above to obtain a metal precursor. The metal precursor is spin-coated onto the surface of sapphire substrate b. The sapphire substrate b is placed in a quartz boat in the high-temperature zone with the substrate surface facing upward. High-purity selenium powder is used as the selenium source. The high-purity selenium powder is placed in the low-temperature zone of the furnace tube near the outlet.

[0072] 2.5) Set up an argon-hydrogen mixture with argon and hydrogen flow rates of 100 sccm and 10 sccm, respectively. Maintain a constant gas flow during deposition. Turn on the tube furnace and set the heating rate to 15℃ / min to heat the high-temperature zone to 800℃ and the selenium powder zone to 375℃. After the temperature reaches the set value, maintain a constant temperature for about 15 minutes to grow the heavily doped tungsten diselenide film to be transferred on substrate b.

[0073] 2.6) After the reaction is complete, turn off the heating and keep the argon gas flowing until the system cools down to room temperature naturally.

[0074] Step 3: Transfer the two-dimensional material on the sapphire substrate a to the insulating substrate 1.

[0075] 3.1) Drop a small amount of PMMA solution evenly onto the surface of the WSe2 / sapphire substrate, spin coat at 4000 rpm for 1 minute using a spin coater, and then dry on a hot plate at 100°C for 10 minutes to cure the PMMA layer.

[0076] 3.2) Dissolve 55g of KOH solute in 300ml of deionized water and stir continuously until the solute is completely dissolved and the solution becomes a colorless and odorless liquid. Then immerse the sample in the prepared KOH solution for two hours to allow the PMMA-WSe2 layer to gradually separate from the substrate.

[0077] 3.3) Rinse the PMMA-WSe2 layer in deionized water. Using tweezers or other auxiliary tools, gently lift the PMMA / WSe2 film floating on the water surface and slowly place it on the target substrate. Use a glass rod or scraper to gently press and remove air bubbles between the PMMA / WSe2 film and the substrate to ensure full contact and adhesion. Let it stand for several hours to allow the film to fully adhere to the substrate.

[0078] 3.4) Soak the sample in acetone to remove PMMA, then wash with IPA, and finally dry with nitrogen.

[0079] Step 4: Array the two-dimensional material on the insulating substrate 1 by photolithography and etching.

[0080] The two-dimensional material surface transferred to substrate 1 is coated with photoresist, photolithographically etched, and developed to pattern the area to be etched; the process conditions are set with gas flow rate, reaction pressure, and RF power of 10 sccm, 30 mTorr, and 50 W, respectively, and etching time of about 3 min. Oxygen plasma is used to etch tungsten diselenide to obtain isolation regions to array tungsten diselenide and form the two-dimensional material channel layer 2 of the transistor.

[0081] Step 5: Pattern the two-dimensional material on the sapphire substrate b using photolithography and etching.

[0082] The two-dimensional material surface on the sapphire substrate b is patterned with a resist, photolithography, and development to form the area to be etched; the two-dimensional material on the sapphire substrate b is etched using the same method as in step 4 to form the source-drain contact portion of the two-dimensional material to be transferred.

[0083] Step 6: Align and transfer the patterned two-dimensional material on the sapphire substrate b to the surface of the two-dimensional material channel layer 2 to obtain the two-dimensional material source contact portion 3 and the two-dimensional material drain contact portion 4.

[0084] The etched and patterned two-dimensional material source / drain contact portion to be transferred is picked up from the sapphire substrate b using a PDMS mold. Its position is moved by using an xy platform and aligned with the two-dimensional material channel layer on the substrate 1 under an optical microscope. Finally, the two-dimensional material source / drain contact portion is gradually pushed towards the two-dimensional material channel layer on the z-axis using a motor-controlled manipulator, so that the two-dimensional material source / drain contact portion contacts the two-dimensional material channel layer and is transferred to the two-dimensional material channel layer, forming the two-dimensional material source contact portion 3 and the two-dimensional material drain contact portion 4.

[0085] Step 7: Fabricate source and drain electrodes 4 and 5.

[0086] 7.1) Coat the sample surface with photoresist, expose, and develop to form the source / drain contact area for the metal to be deposited;

[0087] 72) Mount the sample on the sample stage of the vapor deposition system and ensure that the sample surface is aligned with the target placement area;

[0088] 7.3) Select Pt as the target material and set the evaporation rate to [value missing]. To ensure the uniformity and adhesion of the Pt layer, the vacuum pump was turned on to evaporate to a high vacuum. The electron beam current was then gradually increased to begin depositing the Pt layer. After depositing to a thickness of 5 nm in the source-drain contact area, the electron beam was turned off to stop the deposition. The target material was then changed to Au, and the deposition rate was set to [value missing]. An Au layer with a thickness of 25 nm is then deposited on the contact area between the source and drain electrodes.

[0089] 7.4) After the vapor deposition is completed, let the sample cool in the chamber for a few minutes, then slowly release the gas to restore the pressure to normal, take out the sample, put it into acetone for stripping, remove the excess metal layer, and form the source electrode 4 and the drain electrode 5.

[0090] Step 8: Aluminum nitride is magnetron sputtered as the gate dielectric layer 7 on the surface of the two-dimensional material channel layer and the source / drain electrodes.

[0091] 8.1) In the magnetron sputtering system, aluminum nitride is used as the target material, and argon and nitrogen are set as working gases with flow rates of 20 sccm and 5 sccm, respectively. The working gas pressure, sputtering power and sputtering temperature are 3 mTorr, 100 W and 300 °C, respectively.

[0092] 8.2) Install the aluminum nitride target on the target position of the magnetron sputtering equipment, and start the vacuum pump until the cavity reaches 10 °C. - 6 After the vacuum level is below Torr, nitrogen and argon are introduced, the flow rate is adjusted to the target working pressure and kept stable before sputtering begins. The sputtering time is about 10 minutes. A 50 nm thick aluminum nitride film is deposited on the two-dimensional material channel layer and the source and drain electrode surfaces as the gate dielectric layer 7.

[0093] 8.3) After cooling the sample to room temperature in the vacuum chamber, introduce nitrogen gas to bring the chamber back to atmospheric pressure, open the chamber and remove the sample.

[0094] Step 9: Fabricate the gate electrode 8.

[0095] 9.1) Coating photoresist on the surface of the gate dielectric layer 7, exposing and developing it to form the gate region of the metal to be deposited;

[0096] 9.2) Mount the sample on the sample stage of the vapor deposition system and ensure that the sample surface is aligned with the target placement area;

[0097] 9.3) Select Pd as the target material and set the evaporation rate to [value missing]. To ensure the uniformity and adhesion of the Pd layer, the vacuum pump was turned on to evaporate to a high vacuum. The electron beam current was then gradually increased to begin depositing the Pd layer. After depositing to a thickness of 5 nm in the gate region, the electron beam was turned off to stop the deposition. The target material was then changed to Au, and the deposition rate was set to [value missing]. An Au layer with a thickness of 25 nm is then deposited on the contact area between the source and drain electrodes.

[0098] 9.4) After the vapor deposition is completed, allow the sample to cool in the chamber for a few minutes, then slowly release the gas to restore the pressure to normal, remove the sample, place it in acetone for stripping, remove the excess metal layer to form the gate electrode, and complete the entire device fabrication process.

[0099] Step 10: Etch the gate dielectric layer 7 to expose the source and drain electrodes.

[0100] Photoresist is coated on the sample surface, and the area to be etched is exposed and developed.

[0101] Aluminum nitride was etched using CF4 plasma at a CF4 gas flow rate of 30 sccm, auxiliary gas Ar and O2 gas flow rates of 10 sccm and 2 sccm respectively, reaction pressure and RF power of 10 mTorr and 100 W respectively, and etching time of about 10 min. The source and drain electrodes were exposed after etching.

[0102] After etching, remove the photoresist and clean the sample with acetone and IPA, then blow dry with nitrogen to ensure no residue remains on the surface.

[0103] Example 4: The overall implementation steps of the transistor fabrication method proposed in this example are the same as in Example 2. A specific example is provided to further describe the fabrication process of this invention: the substrate is sapphire, the gate dielectric layer is 30nm aluminum nitride, the two-dimensional material is molybdenum diselenide, the channel layer has 4 layers, the source / drain contact portion has 4 layers, the doping method is surface charge transfer doping with oxynitride treatment, and the source / drain electrode metal is Pd / Au.

[0104] Step a: Pretreatment of transistor substrate 1.

[0105] Sapphire was selected as the insulating substrate for the transistor. The substrate was ultrasonically cleaned for 5 minutes each in acetone solution, isopropanol and deionized water, and then dried with nitrogen.

[0106] Step b: Two-dimensional material source / drain contact portions and two-dimensional material channel layers are prepared and doped on sapphire substrates a and b, respectively.

[0107] b1) Ultrasonically clean sapphire substrates a and b with acetone for 20 minutes. After cleaning, rinse with deionized water 2-3 times, then immerse in deionized water and ultrasonically clean for 15 minutes. Finally, use nitrogen to dry the substrates treated above.

[0108] b2) The molybdenum source is MoO3, and the selenium source is high-purity selenium powder. The MoO3 powder is placed in a quartz boat in the high-temperature zone, and the high-purity selenium powder is placed in the low-temperature zone of the furnace tube near the outlet. The cleaned sapphire substrates a and b are placed with their surfaces facing up in an area a few centimeters away from the MoO3 powder to facilitate the growth of MoSe2.

[0109] b3) Set up an argon-hydrogen mixture with argon and hydrogen gas flow rates of 100 sccm and 10 sccm, respectively. Maintain a constant gas flow during the deposition process. Turn on the tube furnace and set the heating rate to 15℃ / min. Heat the MoO3 powder area to 800℃ and the selenium powder area to 300℃. After the temperature reaches the set value, maintain a constant temperature for about 10 minutes. At this time, the selenium vapor reacts with MoO3 on the substrate to generate molybdenum diselenide and grow the molybdenum diselenide film to be transferred.

[0110] b4) After the reaction is complete, turn off the heating and keep argon gas flowing until the system cools naturally to room temperature to avoid the oxidation of molybdenum diselenide at high temperatures;

[0111] b5) Expose sapphire substrate b, on which molybdenum diselenide has been grown, to a stream of nitric oxide gas at 175°C for 4 hours; substrate a is left untreated.

[0112] Step c: Transfer the two-dimensional material on the sapphire substrate a to the insulating substrate 1.

[0113] c1) A small amount of PMMA solution is evenly dropped onto the surface of the MoSe2 / sapphire substrate, and then spin-coated at 4000 rpm for 1 minute using a spin coater. The PMMA layer is then cured by drying on a hot plate at 100°C for 10 minutes.

[0114] c2) Dissolve 55g of KOH solute in 300ml of deionized water and stir continuously until the solute is completely dissolved and the solution becomes a colorless and odorless liquid. Then immerse the sample in the prepared KOH solution for two hours to allow the PMMA-MoSe2 layer to gradually separate from the substrate.

[0115] c3) Rinse the PMMA-MoSe2 layer in deionized water. Using tweezers or other auxiliary tools, gently lift the PMMA / MoSe2 film floating on the water surface and slowly place it on the target substrate. Use a glass rod or scraper to gently press and remove air bubbles between the PMMA / MoSe2 film and the substrate to ensure full contact and adhesion. Let it stand for several hours to allow the film to fully adhere to the substrate.

[0116] c4) Soak the sample in acetone to remove PMMA, then wash with IPA, and finally dry with nitrogen.

[0117] Step d: Array the two-dimensional material on the insulating substrate 1 by photolithography and etching.

[0118] The two-dimensional material surface transferred to substrate 1 is coated with adhesive, photolithographically patterned, and developed to pattern the area to be etched. The process conditions are set as follows: gas flow rate, reaction pressure, and RF power are 10 sccm, 30 mTorr, and 50 W, respectively, and the etching time is about 3 min. Oxygen plasma is used to etch molybdenum diselenide to obtain the isolation region and array the molybdenum diselenide to form the two-dimensional material channel layer 2 of the transistor.

[0119] Step e: Pattern the two-dimensional material on the sapphire substrate b using photolithography and etching.

[0120] The two-dimensional material surface on the sapphire substrate b is patterned with a resist, photolithography, and development to form the area to be etched; the two-dimensional material on the sapphire substrate b is etched using the same method as in step 4 to form the source-drain contact portion of the two-dimensional material to be transferred.

[0121] Step f: Align and transfer the patterned two-dimensional material on the sapphire substrate b to the surface of the two-dimensional material channel layer 2 to obtain the two-dimensional material source contact portion 3 and the two-dimensional material drain contact portion 4.

[0122] The etched and patterned two-dimensional material source / drain contact portion to be transferred is picked up from the sapphire substrate b using a PDMS mold. Its position is moved by using an xy platform and aligned with the two-dimensional material channel layer on the substrate 1 under an optical microscope. Finally, the two-dimensional material source / drain contact portion is gradually pushed towards the two-dimensional material channel layer on the z-axis using a motor-controlled manipulator, so that the two-dimensional material source / drain contact portion contacts the two-dimensional material channel layer and is transferred to the two-dimensional material channel layer, forming the two-dimensional material source contact portion 3 and the two-dimensional material drain contact portion 4.

[0123] Step g: Fabricate source and drain electrodes 4 and 5

[0124] g1) Coating photoresist on the sample surface, exposing and developing it to form the source and drain contact area of ​​the metal to be deposited;

[0125] g2) Mount the sample on the sample stage of the vapor deposition system and ensure that the sample surface is aligned with the target placement area;

[0126] g3) Select Pd as the target material and set the evaporation rate to [value missing]. To ensure the uniformity and adhesion of the Pd layer, the vacuum pump was turned on to evaporate to a high vacuum. The electron beam current was then gradually increased to begin depositing the Pd layer. After depositing to a thickness of 5 nm in the source-drain contact area, the electron beam was turned off to stop the deposition. The target material was then changed to Au, and the deposition rate was set to [value missing]. An Au layer with a thickness of 25 nm is then deposited on the contact area between the source and drain electrodes.

[0127] g4) After the vapor deposition is completed, let the sample cool in the chamber for a few minutes, then slowly release the gas to restore the pressure to normal, take out the sample, put it into acetone for peeling, remove the excess metal layer, and form the source electrode 4 and the drain electrode 5.

[0128] Step h: Aluminum nitride is used as the gate dielectric layer 7 by magnetron sputtering on the two-dimensional material channel layer and the source / drain electrode surface.

[0129] h1) In a magnetron sputtering system, aluminum nitride is used as the target material, and argon and nitrogen are set as working gases with gas flow rates of 20 sccm and 5 sccm, respectively. The working gas pressure, sputtering power and sputtering temperature are 3 mTorr, 100 W and 300 °C, respectively. An aluminum nitride film is sputtered on substrate 1 as the bottom layer 2 of the encapsulation protective layer.

[0130] h2) Install the aluminum nitride target on the target position of the magnetron sputtering equipment, and start the vacuum pump until the cavity reaches 10 °C. - 6 After the vacuum level is below Torr, nitrogen and argon are introduced, the flow rate is adjusted to the target working pressure and kept stable before sputtering begins. The sputtering time is about 6 minutes, and a 30 nm thick aluminum nitride film is deposited on the sample surface as the gate dielectric layer 7.

[0131] h3) After cooling the sample to room temperature in the vacuum chamber, nitrogen gas is introduced to bring the chamber back to atmospheric pressure, the chamber is opened and the sample is removed.

[0132] Step i: Fabricate the gate electrode 8.

[0133] i1) Coating photoresist on the surface of the gate dielectric layer 7, exposing and developing it to form the gate region of the metal to be deposited;

[0134] i2) Mount the sample on the sample stage of the vapor deposition system and ensure that the sample surface is aligned with the target placement area;

[0135] i3) Select Pd as the target material and set the evaporation rate to [value missing]. To ensure the uniformity and adhesion of the Pd layer, the vacuum pump was turned on to evaporate to a high vacuum. The electron beam current was then gradually increased to begin depositing the Pd layer. After depositing to a thickness of 5 nm in the source-drain contact area, the electron beam was turned off to stop the deposition. The target material was then changed to Au, and the deposition rate was set to [value missing]. An Au layer with a thickness of 25 nm is then deposited on the contact area between the source and drain electrodes.

[0136] i4) After the vapor deposition is completed, let the sample cool in the chamber for a few minutes, then slowly release the gas to restore the pressure to normal, take out the sample, put it into acetone for peeling, remove the excess metal layer to form the gate electrode, and complete the fabrication process of the entire device.

[0137] Step j: Etch the gate dielectric layer 7 to expose the source and drain electrodes.

[0138] Photoresist is coated on the sample surface, and the area to be etched is exposed and developed.

[0139] Aluminum nitride was etched using CF4 plasma at a CF4 gas flow rate of 30 sccm, auxiliary gas Ar and O2 gas flow rates of 10 sccm and 2 sccm respectively, reaction pressure and RF power of 10 mTorr and 100 W respectively, and etching time of about 6 min. The source and drain electrodes were exposed after etching.

[0140] After etching, remove the photoresist and clean the sample with acetone and IPA, then blow dry with nitrogen to ensure no residue remains on the surface.

[0141] Example 5: The overall implementation steps of the transistor fabrication method proposed in this example are the same as in Example 2. A specific example is provided to further describe the fabrication process of this invention: the substrate is diamond, the gate dielectric layer is 50nm silicon nitride, the two-dimensional material is molybdenum diselenide, the channel layer has 4 layers, the source / drain contact portion has 4 layers, the doping method is surface charge transfer doping with oxynitride treatment, and the source / drain electrode metal is Pd / Au.

[0142] Step A: Pretreatment of transistor substrate 1.

[0143] Diamond was selected as the insulating substrate 1 for the transistor. The substrate was ultrasonically cleaned for 5 minutes each in acetone solution, isopropanol and deionized water, and then dried with nitrogen.

[0144] Step B: Two-dimensional material source / drain contact portions and two-dimensional material channel layers are prepared and doped on sapphire substrates a and b, respectively.

[0145] B1) Sapphire substrates a and b were ultrasonically cleaned with acetone for 20 minutes. After cleaning, they were rinsed with deionized water 2-3 times, then immersed in deionized water for ultrasonic cleaning for 15 minutes. Finally, nitrogen was used to dry the substrates treated above.

[0146] B2) The molybdenum source is MoO3, and the selenium source is high-purity selenium powder. The MoO3 powder is placed in a quartz boat in the high-temperature zone, and the high-purity selenium powder is placed in the low-temperature zone of the furnace tube near the outlet. The cleaned sapphire substrates a and b are placed with their surfaces facing up in an area a few centimeters away from the MoO3 powder to facilitate the growth of MoSe2.

[0147] B3) Set up an argon-hydrogen mixture with argon and hydrogen gas flow rates of 100 sccm and 10 sccm, respectively. Maintain a constant gas flow during the deposition process. Turn on the tube furnace and set the heating rate to 15℃ / min to heat the MoO3 powder area to 800℃ and the selenium powder area to 300℃. After the temperature reaches the set value, maintain a constant temperature for about 10 minutes. At this time, the selenium vapor reacts with MoO3 on the substrate to generate molybdenum diselenide and grow the molybdenum diselenide film to be transferred.

[0148] B4) After the reaction is complete, turn off the heating and keep argon gas flowing until the system cools naturally to room temperature to avoid the oxidation of molybdenum diselenide at high temperatures;

[0149] B5) Sapphire substrate b with molybdenum diselenide grown on it was exposed to a stream of nitric oxide gas at 175°C for 4 hours; substrate a was left untreated.

[0150] Step C: Transfer the two-dimensional material on the sapphire substrate a to the insulating substrate 1.

[0151] C1) A small amount of PMMA solution is evenly dropped onto the surface of the MoSe2 / sapphire substrate, and then spin-coated at 4000 rpm for 1 minute using a spin coater. The PMMA layer is then cured by drying on a hot plate at 100°C for 10 minutes.

[0152] C2) Dissolve 55g of KOH solute in 300ml of deionized water and stir continuously until the solute is completely dissolved and the solution becomes a colorless and odorless liquid. Then immerse the sample in the prepared KOH solution for two hours to allow the PMMA-MoSe2 layer to gradually separate from the substrate.

[0153] C3) Rinse the PMMA-MoSe2 layer in deionized water. Using tweezers or other auxiliary tools, gently lift the PMMA / MoSe2 film floating on the water surface and slowly place it on the target substrate. Use a glass rod or scraper to gently press and remove air bubbles between the PMMA / MoSe2 film and the substrate to ensure full contact and adhesion. Let it stand for several hours to allow the film to fully adhere to the substrate.

[0154] C4) Soak the sample in acetone to remove PMMA, then wash with IPA, and finally dry with nitrogen.

[0155] Step D: The two-dimensional material on the insulating substrate 1 is arrayed by photolithography and etching.

[0156] The two-dimensional material surface transferred to substrate 1 is coated with adhesive, photolithographically patterned, and developed to pattern the area to be etched. The process conditions are set as follows: gas flow rate, reaction pressure, and RF power are 10 sccm, 30 mTorr, and 50 W, respectively, and the etching time is about 3 min. Oxygen plasma is used to etch molybdenum diselenide to obtain the isolation region and array the molybdenum diselenide to form the two-dimensional material channel layer 2 of the transistor.

[0157] Step E: Pattern the two-dimensional material on the sapphire substrate b using photolithography and etching.

[0158] The two-dimensional material surface on the sapphire substrate b is patterned with a resist, photolithography, and development to form the area to be etched; the two-dimensional material on the sapphire substrate b is etched using the same method as in step 4 to form the source-drain contact portion of the two-dimensional material to be transferred.

[0159] Step F: Align and transfer the patterned two-dimensional material on the sapphire substrate b to the surface of the two-dimensional material channel layer 2 to obtain the two-dimensional material source contact portion 3 and the two-dimensional material drain contact portion 4.

[0160] The etched and patterned two-dimensional material source / drain contact portion to be transferred is picked up from the sapphire substrate b using a PDMS mold. Its position is moved by using an xy platform and aligned with the two-dimensional material channel layer on the substrate 1 under an optical microscope. Finally, the two-dimensional material source / drain contact portion is gradually pushed towards the two-dimensional material channel layer on the z-axis using a motor-controlled manipulator, so that the two-dimensional material source / drain contact portion contacts the two-dimensional material channel layer and is transferred to the two-dimensional material channel layer, forming the two-dimensional material source contact portion 3 and the two-dimensional material drain contact portion 4.

[0161] Step G: Fabricate source and drain electrodes 4 and 5

[0162] G1) Coating photoresist on the sample surface, exposing and developing it to form the source and drain contact area of ​​the metal to be deposited;

[0163] G2) Mount the sample on the sample stage of the vapor deposition system and ensure that the sample surface is aligned with the target placement area;

[0164] G3) Select Pd as the target material and set the evaporation rate to... To ensure the uniformity and adhesion of the Pd layer, the vacuum pump was turned on to evaporate to a high vacuum. The electron beam current was then gradually increased to begin depositing the Pd layer. After depositing to a thickness of 5 nm in the source-drain contact area, the electron beam was turned off to stop the deposition. The target material was then changed to Au, and the deposition rate was set to [value missing]. An Au layer with a thickness of 25 nm is then deposited on the contact area between the source and drain electrodes.

[0165] After the vapor deposition is completed (G4), allow the sample to cool in the chamber for a few minutes, then slowly release the gas to restore the pressure to normal, remove the sample, and place it in acetone for stripping. After removing the excess metal layer, the source electrode 4 and the drain electrode 5 are formed.

[0166] Step H: Silicon nitride is used as the gate dielectric layer 7 by magnetron sputtering on the two-dimensional material channel layer and the source / drain electrode surface.

[0167] H1) Under process conditions of 20W power, 5sccm gas flow rate, and approximately 10 minutes, the substrate surface was pretreated with low-power oxygen plasma to further improve the adhesion of the silicon nitride film.

[0168] H2) Mount the high-purity silicon target onto the cathode and ensure good contact with the magnetron sputtering system. Start the vacuum pump and evacuate the cavity to 10°C. -6 After reaching a high vacuum of Torr, argon and nitrogen are introduced as working gases, with a flow rate of 15 sccm for both argon and nitrogen, and the working pressure is maintained at 3 mTorr.

[0169] H3) After heating the sapphire substrate 1 to 300 degrees Celsius, a 50 nm thick silicon nitride thin film was deposited as the gate dielectric layer 7 under the process conditions of sputtering power of 150 W and sputtering time of 10 min.

[0170] After H4 deposition is completed, the sample is cooled to room temperature in the vacuum chamber, nitrogen gas is introduced to bring the chamber back to atmospheric pressure, the chamber is opened, and the sample is removed.

[0171] Step I: Fabricate the gate electrode 8.

[0172] I1) Photoresist is coated on the surface of the gate dielectric layer 7, exposed, and developed to form the gate region of the metal to be deposited;

[0173] I2) Mount the sample on the sample stage of the vapor deposition system and ensure that the sample surface is aligned with the target placement area;

[0174] I3) Select Pd as the target material and set the evaporation rate to... To ensure the uniformity and adhesion of the Pd layer, the vacuum pump was turned on to evaporate to a high vacuum. The electron beam current was then gradually increased to begin depositing the Pd layer. After depositing to a thickness of 5 nm in the source-drain contact area, the electron beam was turned off to stop the deposition. The target material was then changed to Au, and the deposition rate was set to [value missing]. An Au layer with a thickness of 25 nm is then deposited on the contact area between the source and drain electrodes.

[0175] I4) After the vapor deposition is completed, let the sample cool in the chamber for a few minutes, then slowly release the gas to restore the pressure to normal, take out the sample, put it into acetone for stripping, remove the excess metal layer to form the gate electrode, and complete the fabrication process of the entire device.

[0176] Step J: Etch the gate dielectric layer 7 to expose the source and drain electrodes.

[0177] Photoresist is coated on the sample surface, and the area to be etched is exposed and developed.

[0178] Silicon nitride was etched using CF4 plasma at a CF4 gas flow rate of 30 sccm, auxiliary gas Ar and O2 gas flow rates of 10 sccm and 2 sccm respectively, reaction pressure and RF power of 10 mTorr and 100 W respectively, and etching time of about 10 min. The source and drain electrodes were exposed after etching.

[0179] After etching, remove the photoresist and clean the sample with acetone and IPA, then blow dry with nitrogen to ensure no residue remains on the surface.

[0180] Unless otherwise specified, the preparation methods used in the above specific embodiments are conventional methods; the reagents and materials used are commercially available unless otherwise specified. Parts of this invention not described in detail are common knowledge to those skilled in the art.

[0181] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and detail without departing from the principles and results of the present invention. For example, in addition to SiO2, sapphire, and diamond, other insulating substrate materials can be used for the insulating substrate; in addition to aluminum oxide, aluminum nitride, and silicon nitride, hafnium oxide and gallium oxide can be used for the gate dielectric layer; in addition to Pt / Au or Pd / Au, other metals compatible with the p-type electrical properties of two-dimensional materials can be used for the source / drain metal electrodes; in addition to oxynitride treatment, oxygen plasma treatment and ozone treatment can be used for surface charge transfer doping, but the time-related effects of the treatment and device aging performance need to be considered. However, these modifications and changes based on the concept of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A high-performance p-type two-dimensional transistor based on partitioned doping, characterized in that, include: An insulating substrate (1), a two-dimensional material channel layer (2), a two-dimensional material source contact portion (3) and a two-dimensional material drain contact portion (4) located above the two ends of the channel layer, and a source electrode (5) and a drain electrode (6) located above the two, a gate dielectric layer (7) located above the two-dimensional material channel layer and the source electrode and drain electrode, and a gate electrode (8) located above the gate dielectric layer. The two-dimensional material channel layer (2) is made of one of the two-dimensional semiconductor materials and is either undoped or lightly doped; the two-dimensional semiconductor material includes at least tungsten diselenide and molybdenum diselenide. The two-dimensional material source contact portion (3) and the two-dimensional material drain contact portion (4) are made of the same material as the two-dimensional material channel layer (2), and are heavily doped.

2. The transistor according to claim 1, characterized in that: The thickness of the two-dimensional material channel layer (2) is 2 to 4 layers; The thickness of the two-dimensional material source contact portion (3) and the two-dimensional material drain contact portion (4) is the same, both being 2 to 4 layers.

3. The transistor according to claim 1, characterized in that, The substrate (1) is made of any one of the insulating substrate materials, such as SiO2 / Si, sapphire, or diamond; the gate dielectric layer (7) is made of any one of the insulating dielectric layers, such as aluminum oxide, aluminum nitride, or silicon nitride; the gate electrode (8) is made of Ni / Au, Pd / Au, or Pt / Au metal; the source electrode (5) and drain electrode (6) include Pd / Au and Pt / Au.

4. A method for fabricating a high-performance p-type two-dimensional transistor based on partitioned doping, characterized in that, Includes the following steps: §1: Select the target substrate, and use acetone, isopropanol and deionized water to ultrasonically clean its surface, and then blow it dry with nitrogen to obtain a clean insulating substrate (1). §2: Two-dimensional material source / drain contact portions and two-dimensional material channel layers are respectively fabricated and doped on sapphire substrates a and b. The doping is achieved by one of two different doping methods, substitutional doping and surface charge transfer doping, depending on actual needs, as detailed below: ① Substitutional doping method: By using liquid phase epitaxy-assisted chemical vapor deposition, appropriate dopants are added during the growth process to grow lightly doped two-dimensional materials and heavily doped two-dimensional materials of different thicknesses on two cleaned sapphire substrates a and b, respectively. ② Surface charge transfer doping method: Two-dimensional materials are grown on two cleaned sapphire substrates a and b by chemical vapor deposition. The two-dimensional material on substrate b is treated with nitride to obtain heavily doped two-dimensional material, while the two-dimensional material on substrate a is not treated. §3: Transfer of two-dimensional material films grown on sapphire substrate a to insulating substrate (1) using PMMA-assisted transfer method; §4: The two-dimensional material transferred on the substrate (1) is coated, pre-baked, photolithographically etched, and developed, and then an isolation region is etched out for arraying the two-dimensional material to obtain the two-dimensional material channel layer (2) of the transistor; §5: The heavily doped two-dimensional material on the sapphire substrate b obtained in step §2 is used to obtain patterned source and drain contact portions of the two-dimensional material to be transferred through photolithography and etching; §6: Using the PDMS-assisted transfer method, the two-dimensional material source and drain contact parts to be transferred after etching on the sapphire substrate b are moved to their relative positions under an optical microscope by using an xy platform, and after alignment and lamination, they are transferred to the two-dimensional material channel layer (2) at both ends to obtain the two-dimensional material source contact parts (3) and two-dimensional material drain contact parts (4) at both ends of the channel layer. §7: Source and drain electrode metals are deposited on the surface of the two-dimensional material source contact portion (3) and the two-dimensional material drain contact portion (4) by photolithography and electron beam evaporation. After the metals are deposited, the source electrode (5) and drain electrode (6) are formed by a stripping process. §8; On the surface of the two-dimensional material channel layer (2), source electrode (5) and drain electrode (6), any one of aluminum oxide, aluminum nitride and silicon nitride insulating dielectric layers is deposited by atomic layer-by-layer or by magnetron sputtering as a gate dielectric layer (7); §9: The gate electrode (8) is prepared on the surface of the gate dielectric layer (7) to be etched by photolithography, electron beam evaporation deposition of gate metal and lift-off process; §10: The area above the source electrode (5) and drain electrode (6) is patterned by photolithography, and then the gate dielectric layer is etched to expose the source and drain electrodes, thus completing the fabrication of the device.

5. The method according to claim 4, characterized in that: The substitutional doping method described in step ① includes the following steps: 1a) Select the appropriate reaction precursor and doping solution according to the type of two-dimensional material to be grown and the type of doping. Mix the metal precursor in the reaction precursor with the doping solution. The mixing ratio is determined according to the doping intensity. 1b) Spin-coat the mixed solution onto the sapphire substrate according to the reaction requirements, and place other reaction precursors in the high-temperature zone or low-temperature zone of the tube furnace according to their type; 1c) After spin-coating the mixed solution, place the clean sapphire substrate a used for growing lightly doped two-dimensional material films away from the high-temperature zone, set the working gas, keep the gas flow constant during the deposition process, and heat at a rate of 15-20 °C / min until the set working temperature is reached. Then, control the reaction time according to the required two-dimensional material film thickness to obtain the lightly doped two-dimensional material film to be transferred. 1d) Place the clean sapphire substrate b, which has been spin-coated with a mixed solution for growing heavily doped two-dimensional material films, away from the high-temperature zone, set the working gas, heat up to the set working temperature, and control the reaction time according to the required thickness to obtain the heavily doped two-dimensional material film to be transferred.

6. The method according to claim 4, characterized in that: Step ② describes growing two-dimensional materials on two cleaned sapphire substrates a and b using chemical vapor deposition. The steps include the following: 2a) Select the reaction precursor according to the type of two-dimensional material thin film to be grown, and prepare the reaction precursor according to its reaction requirements. Different types of materials are placed in the high-temperature zone and low-temperature zone of the tube furnace, respectively; 2b) Place the clean substrates a and b used for growing two-dimensional material films in an area a few centimeters away from the high-temperature sample to facilitate film growth; 2c) Set the working gas and keep the gas flow constant during the deposition process. Increase the temperature at a rate of 15-20 °C / min until the set working temperature is reached. Then, control the reaction time according to the required thickness of the two-dimensional material film to obtain the two-dimensional material film to be transferred.

7. The method according to claim 4, characterized in that: The nitrogen oxide treatment in step ② involves exposing the sapphire substrate on which the two-dimensional material has been grown to a stream of nitric oxide gas at 175°C for 4 hours.

8. The method according to claim 4, characterized in that: The PMMA-assisted transfer method in step §3 is implemented as follows: Spin-coat PMMA onto the surface of the layer to be transferred and cure it on a hot plate at 90-120°C. The sample was immersed in the solution required for substrate separation for two hours to allow the PMMA-to-be-transferred layer to adhere to its substrate. Separation; The separated floating PMMA-to-transfer layer was transferred to the target substrate and cured. The PMMA was removed by soaking in acetone, then cleaned with IPA, and finally dried with nitrogen.

9. The method according to claim 4, characterized in that: The PDMS-assisted transfer method in step §6 involves using a PDMS mold to pick up the etched two-dimensional material source / drain contact portion on the sapphire substrate b, moving their relative positions using an xy platform, aligning them with the bottom two-dimensional material channel layer under an optical microscope, and finally using a motor-controlled manipulator to gradually push the two-dimensional material source / drain contact portion towards the bottom two-dimensional material channel layer on the z-axis, so that the two-dimensional material source / drain contact portion contacts the two-dimensional material channel layer.

10. The method according to claim 4, characterized in that: The atomic layer-by-layer deposition described in step §8 involves pre-depositing a seed layer to meet deposition requirements, cleaning the sample, setting the deposition temperature, ensuring good vacuum in the chamber, starting the ALD system, introducing the working gas, and controlling the deposition time according to the required gate dielectric layer thickness to deposit the gate dielectric layer to be etched on the two-dimensional material channel layer. The magnetron sputtering described in step §8 involves heating the substrate to a set temperature, using the appropriate target and working gas according to the type of encapsulation protective layer, and using the magnetron sputtering system to grow the gate dielectric layer to be etched on the substrate or two-dimensional material channel layer at the reaction chamber temperature and controlling the sputtering time according to the required thickness.

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