Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device has an active region and a terminal region surrounding the active region, and comprises: a base region located in the active region and on the second surface of the semiconductor substrate of the first conductivity type; a plurality of annular sub-regions which are located in the terminal region and on the second surface of the substrate and are spaced apart from each other; the insulating layer is positioned in the terminal area, is positioned on one side, far away from the substrate, of the plurality of annular sub-areas and is provided with a plurality of insulating layer openings; the first conductive layer is located in the active region and the terminal region and located on the side, away from the substrate, of the base region and the insulating layer. The plurality of annular sub-regions include a first annular sub-region, and the first annular sub-region is in contact with the base region. The first annular sub-region includes a plurality of annular structures in contact with each other, each annular structure corresponding to one insulating layer opening. Each ring structure contacts the first conductive layer through a corresponding insulating layer opening. The base region, the annular sub-region, and the annular structure have a second conductivity type.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor device having an active region and a terminal region surrounding the active region and a manufacturing method thereof. Background Art

[0002] In existing semiconductor devices, taking ultra-fast diodes (ultra-fast diodes / hyper-fast diodes) as an example, when ultra-fast diodes are turned off at high speed and high DC voltage, dynamic avalanche breakdown may occur. The current distribution and electric field distribution inside the diode become uneven, resulting in current concentration, which can easily cause the device to burn out. Current filaments and high electric field peaks may appear at the pn junction and the bottom nn+ junction, and the diode may be damaged. The ultra-fast diode of the prior art shown in Figure 1 has the above problems.

[0003] Others such as Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and Insulated-gate bipolar transistor (IGBT) also have the same problem.

[0004] Therefore, it is necessary to provide an improved semiconductor device to solve the above technical problems. Summary of the invention

[0005] In a first aspect of the present disclosure, a semiconductor device is disclosed, which has an active area and a terminal area surrounding the active area, and the semiconductor device includes: a semiconductor substrate of a first conductivity type, the semiconductor substrate including a first surface and a second surface opposite to each other; a base region of a second conductivity type, which is located in the active area and located on the second surface of the semiconductor substrate; a plurality of annular sub-regions of the second conductivity type, which are located in the terminal area and located on the second surface of the semiconductor substrate and are spaced apart from each other; an insulating layer, which is located in the terminal area and located on a side of the plurality of annular sub-regions away from the semiconductor substrate; wherein the insulating layer is provided with a first insulating layer opening; a first conductive layer, which is located in the active area and the terminal area, and is located between the base area and the insulating layer; layer away from the side of the semiconductor substrate; wherein the multiple annular sub-regions include a first annular sub-region; the first annular sub-region is in contact with the base region; the first conductive layer includes a first portion, and a plurality of second portions surrounding the first portion and located in the terminal region, wherein the first portion is spaced apart from the plurality of second portions, and extends from a portion of the active region, across the boundary between the active region and the terminal region, to a portion of the terminal region, wherein the plurality of second portions are spaced apart from each other; the first annular sub-region includes a plurality of annular structures of the second conductivity type in contact with each other, and a first annular structure in contact with the base region among the base region and the plurality of annular structures contacts the first portion through an opening in the first insulating layer.

[0006] In some embodiments, the insulating layer is also provided with a plurality of second insulating layer openings; each second part of the first conductive layer corresponds to a second insulating layer opening, and each second part corresponds to a respective corresponding, different second insulating layer opening; the other annular structures except the first annular structure respectively contact the corresponding second part through their respective corresponding second insulating layer openings.

[0007] In some embodiments, the first conductivity type is n-type; the second conductivity type is p-type; the semiconductor substrate is an n-type region, the base region is a p-type region, the multiple annular sub-regions are multiple p-type annular sub-regions, the first annular sub-region is a first p-type annular sub-region, and the annular structure is a p-type annular structure.

[0008] In some embodiments, the multiple p-type ring sub-regions are all ring-shaped and are arranged around the p-type region; among any two adjacent p-type ring structures, the p-type ring structure far away from the p-type region is arranged around the p-type ring structure close to the p-type region; the orthographic projections of any two adjacent p-type ring structures on the n-type region overlap with each other, so that each p-type ring structure includes an overlapping area and a non-overlapping area; the orthographic projection is a projection of the p-type ring structure formed on the surface of the n-type region perpendicular to the surface of the n-type region; the depth of each p-type ring structure in the non-overlapping area is greater than the depth of each p-type ring structure in the overlapping area.

[0009] In some embodiments, the multiple p-type ring sub-regions also include a plurality of second p-type ring sub-regions spaced apart from each other and arranged around the first p-type ring sub-region, the plurality of second p-type ring sub-regions being arranged sequentially along a direction from the active area to the terminal area; and the plurality of second p-type ring sub-regions respectively contact corresponding second portions through corresponding second insulation layer openings among the plurality of second insulation layer openings.

[0010] In some embodiments, in a plane perpendicular to the surface of the n-type region and parallel to the direction from the active region to the terminal region, any two adjacent p-type ring structures form a recess in the contact region, and the recess is recessed in a direction away from the n-type region.

[0011] In some embodiments, the doping concentration of the plurality of p-type ring structures is different from the doping concentration of the plurality of second p-type ring sub-regions; and / or the doping depth of the plurality of p-type ring structures is different from the doping depth of the plurality of second p-type ring sub-regions.

[0012] In some embodiments, a doping depth of the plurality of p-type ring sub-regions is greater than a doping depth of the p-type region.

[0013] In some embodiments, the plurality of p-type ring structures includes two or three p-type ring structures.

[0014] In some embodiments, an orthographic projection of a p-type ring structure in contact with the p-type region on the n-type region overlaps with an orthographic projection of the p-type region on the n-type region, wherein the orthographic projection is a projection of the p-type ring structure formed on the surface of the n-type region perpendicular to the surface of the n-type region.

[0015] In some embodiments, a doping concentration and a doping depth of a portion of the p-type ring structure in the overlapping region are respectively smaller than a doping concentration and a doping depth of other portions of the p-type ring structure.

[0016] In another aspect of the present disclosure, a method for forming a semiconductor device is disclosed, wherein the semiconductor device has an active area and a terminal area surrounding the active area, and the method comprises: providing a semiconductor substrate of a first conductivity type, the semiconductor substrate comprising a first surface and a second surface opposite to each other; forming a base region of a second conductivity type on the second surface of the semiconductor substrate, which is located in the active area; forming a plurality of annular sub-regions of the second conductivity type on the second surface of the semiconductor substrate, which are located in the terminal area and are spaced apart from each other; forming an insulating layer on a side of the plurality of annular sub-regions away from the semiconductor substrate, which is located in the terminal area and is provided with a first insulating layer opening; forming a first conductive layer on a side of the base region and the insulating layer away from the semiconductor substrate, which is located in the terminal area; The source region and the terminal region; wherein, forming the plurality of annular sub-regions comprises: forming a first annular sub-region; the first annular sub-region is in contact with the base region; forming the first conductive layer comprises forming a first portion, and forming a plurality of second portions located in the terminal region and surrounding the first portion and spaced apart from each other, wherein the first portion is formed to be spaced apart from the plurality of second portions, and extends from a portion of the active region, across the boundary between the active region and the terminal region, to a portion of the terminal region; forming the first annular sub-region comprises: forming a plurality of annular structures of the second conductive type in contact with each other, and a first annular structure in contact with the base region among the base region and the plurality of annular structures contacts the first portion through an opening in the first insulating layer.

[0017] In some embodiments, the insulating layer is also provided with a plurality of second insulating layer openings; each second part of the first conductive layer corresponds to a second insulating layer opening, and each second part corresponds to a respective corresponding, different second insulating layer opening; the other annular structures except the first annular structure respectively contact the corresponding second part through their respective corresponding second insulating layer openings.

[0018] In some embodiments, the first conductivity type is n-type; the second conductivity type is p-type; the semiconductor substrate is an n-type region, the base region is a p-type region, the multiple annular sub-regions are multiple p-type annular sub-regions, the first annular sub-region is a first p-type annular sub-region, and the annular structure is a p-type annular structure.

[0019] In some embodiments, forming the multiple p-type ring sub-regions also includes: forming a plurality of second p-type ring sub-regions spaced apart from each other; the plurality of second p-type ring sub-regions are arranged sequentially along a direction from the active area to the terminal area, and are spaced apart from the first p-type ring sub-region; wherein forming the first p-type ring sub-region and forming the plurality of second p-type ring sub-regions are carried out simultaneously.

[0020] In some embodiments, forming the plurality of p-type ring sub-regions comprises: coating a photoresist layer on the second surface of the n-type region and forming a photoresist pattern, using the photoresist pattern as a mask, forming a plurality of p-type ring layers and a plurality of second p-type ring sub-layers by ion implantation, wherein adjacent p-type ring layers are spaced apart by a first spacing; adjacent second p-type ring sub-layers are spaced apart by a second spacing, wherein the first spacing is smaller than the second spacing; removing the photoresist pattern; subjecting the plurality of p-type ring layers and the plurality of second p-type ring sub-layers to high temperature treatment to further diffuse the implanted ions to form The plurality of p-type ring structures and the plurality of second p-type ring sub-regions are formed so that the orthographic projections of any two adjacent p-type ring structures on the n-type region overlap with each other, so that each p-type ring structure includes an overlapping region and a non-overlapping region, the orthographic projection is a projection of the p-type ring structure formed on the surface of the n-type region perpendicular to the surface of the n-type region; and the orthographic projections of any two adjacent second p-type ring sub-regions on the n-type region do not overlap with each other; and the depth of a portion of each p-type ring structure in the non-overlapping region is greater than the depth of a portion of each p-type ring structure in the overlapping region.

[0021] In some embodiments, forming the multiple p-type ring sub-regions includes: coating a photoresist layer on the second surface of the n-type region and forming a photoresist pattern, using the photoresist pattern as a mask to form multiple p-type ring layers by ion implantation, and adjacent p-type ring layers are spaced apart by a first spacing; removing the photoresist pattern; subjecting the multiple p-type ring layers to high-temperature treatment to further diffuse the implanted ions to form multiple p-type ring structures, so that the orthographic projections of any two adjacent p-type ring structures on the n-type region overlap with each other, so that each p-type ring structure includes an overlapping area and a non-overlapping area, and the orthographic projection is a projection of the p-type ring structure formed on the surface of the n-type region perpendicular to the surface of the n-type region; the depth of each p-type ring structure in the non-overlapping area is greater than the depth of each p-type ring structure in the overlapping area. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0023] Figure 1a It is a top view of the structure of a semiconductor device in the prior art.

[0024] Figure 1b For along Figure 1a Cross-sectional view along line AA'.

[0025] Figure 2a The diagram is a top view of a structure of a semiconductor device according to an embodiment of the present disclosure.

[0026] Figure 2b For along Figure 2a Cross-sectional view along line BB'.

[0027] Figure 2c A top view of another structure of a semiconductor device provided according to an embodiment of the present disclosure.

[0028] Figure 2d A cross-sectional view of another structure of a semiconductor device provided according to an embodiment of the present disclosure.

[0029] Figure 3a FIG. 1 is a top view of another structure of a semiconductor device provided according to an embodiment of the present disclosure.

[0030] Figure 3b For along Figure 3a Cross-sectional view along line CC'.

[0031] Figure 4 The present invention is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0032] Figure 5a to Figure 5e Cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0033] Figure 6 The specific flow of step S3 of the method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0034] Figures 7a to 7d The cross-sectional view shows the steps of forming a plurality of p-type ring-shaped sub-regions on the second surface of the semiconductor substrate in step S3 of the method for manufacturing a conductor device according to an embodiment of the present disclosure.

[0035] Figure 8 The specific flow of step S3 of the method for manufacturing a semiconductor device according to an alternative embodiment of the present disclosure is shown.

[0036] Fig. 9 The p-type ring sub-region according to an embodiment of the present disclosure is shown along Figure 2b The doping profile of the dashed line LL'.

[0037] Fig.10 The p-type ring sub-region according to an embodiment of the present disclosure is shown along Figure 3b The doping profile of the middle dashed line MM'.

[0038] Fig.11 The relationship between voltage drop and current of a semiconductor device according to an embodiment of the present disclosure is shown.

[0039] Fig.12The relationship between the blocking voltage and the leakage current of the semiconductor device according to the embodiment of the present disclosure is shown.

[0040] Fig.13a Show Figure 1b The electric field distribution of a semiconductor device in the prior art is shown.

[0041] Fig.13b Show Figure 2b Schematic diagram of an electric field distribution of a semiconductor device according to an embodiment of the present disclosure.

[0042] Fig.13c Show Figure 3b Schematic diagram of an electric field distribution of a semiconductor device according to an embodiment of the present disclosure.

[0043] Fig.14a Show Figure 1b The current density distribution of a semiconductor device in the prior art is shown.

[0044] Fig.14b Show Figure 2b Schematic diagram of a current density distribution of a semiconductor device according to an embodiment of the present disclosure.

[0045] Fig.14c Show Figure 3b Schematic diagram of a current density distribution of a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0047] Figure 1a It is a top view of the structure of a semiconductor device in the prior art. Figure 1b For along Figure 1a The cross-sectional view of the line AA' in FIG. Figure 1a and Figure 1b As shown, the semiconductor device is divided into an active area AA and a terminal area TA surrounding the active area AA. The semiconductor device includes:

[0048] 1) A semiconductor substrate of a first conductivity type, for example, an n-type semiconductor substrate, which can be used as Figure 1a The n-type region 1 of the semiconductor device shown;

[0049] 2) a contact region of the first conductivity type, for example, an n+ type diffusion layer 2 in contact with the n type region, which is located on the first surface of the semiconductor substrate;

[0050] 3) a base region of a second conductivity type, for example, a p-type region 4, which is located in the active area AA and on a second surface of the n-type region 1 opposite to the first surface;

[0051] 4) A plurality of annular sub-regions of the second conductivity type, for example Figure 1a The multiple p-type ring-shaped sub-regions 5 shown are located in the terminal area TA and on the second surface of the n-type region 1 and are spaced apart from each other;

[0052] 5) an insulating layer 6, which is located in the terminal area TA and on a side of the plurality of p-type ring-shaped sub-regions 5 away from the n-type region 1, wherein the insulating layer 6 is provided with a plurality of insulating layer openings 10;

[0053] 6) a first conductive layer 7, which covers the active area AA and the terminal area TA on the second surface of the n-type region 1 and is located on a side of the p-type region 4 and the insulating layer 6 away from the n-type region 1;

[0054] 7) wherein the plurality of p-type ring-shaped sub-regions 5 include a p-type ring-shaped sub-region in contact with the p-type region 4; each p-type ring-shaped sub-region corresponds to an insulating layer opening 10; the plurality of p-type ring-shaped sub-regions 5 correspond to respective corresponding, different insulating layer openings 10; the plurality of p-type ring-shaped sub-regions 5 contact the first conductive layer 7 through the corresponding insulating layer openings 10.

[0055] The semiconductor device also includes the following layers:

[0056] a) a second conductive layer 3, which is located on a side of the n+ type diffusion layer 2 away from the n type region 1;

[0057] b) a passivation layer 8 , which is located on a side of the first conductive layer 7 away from the n-type region 1 ; in some embodiments, the passivation layer 8 covers the entire terminal region TA.

[0058] c) a channel stop region 9 , which is located in the termination region TA and on the second side of the n-type region 1 and is spaced apart from the plurality of p-type ring sub-regions 5 .

[0059] In existing semiconductor devices, taking ultrafast diodes as an example, when ultrafast diodes are turned off at high speed and high DC voltage, dynamic avalanche breakdown may occur. The current distribution and electric field distribution inside the diode become uneven, resulting in current concentration, which can easily cause the device to burn out. Current filaments and high electric field peaks may appear at the pn junction and the bottom nn+ junction, and the diode may be damaged.

[0060] In order to solve the above technical problems in the prior art, the present disclosure provides a semiconductor device. Figure 2a The diagram is a top view of a structure of a semiconductor device according to an embodiment of the present disclosure. Figure 2b For along Figure 2a In the embodiment of the present disclosure, Figure 1a and Figure 1b The structure of the semiconductor device shown is different from that of Figure 2a and Figure 2b As shown, the multiple p-type ring sub-regions 5 include a first p-type ring sub-region 51. The first p-type ring sub-region 51 is in contact with the p-type region 4. The first p-type ring sub-region 51 includes a plurality of p-type ring structures 11 in contact with each other, each p-type ring structure 11 corresponds to an insulating layer opening 10; each p-type ring structure 11 corresponds to a respective, different insulating layer opening 10; and the plurality of p-type ring structures 11 contact the first conductive layer 7 through the corresponding insulating layer openings 10. Typically, the first conductive type is n-type, and the second conductive type is p-type. Alternatively, the first conductive type is p-type, and the second conductive type is n-type. In the embodiments of the present disclosure, the first conductive type is n-type and the second conductive type is p-type as an example for explanation.

[0061] In some embodiments, the first conductive layer 7 is used as an anode of the semiconductor device. In some embodiments, the second conductive layer 3 is used as a cathode of the semiconductor device. In some embodiments, a pn junction is formed at the interface between the plurality of p-type ring-shaped sub-regions 5 and the n-type region 1, and a pn junction is formed at the interface between the p-type region 4 and the n-type region 1 (the pn junction is not shown in the figure).

[0062] In some embodiments, the first conductive layer 7 can be made of metal, non-metal or alloy material. For example, the first conductive layer 7 can be made of aluminum silicon alloy. In some embodiments, the second conductive layer 3 can have a single layer or a multilayer structure. For example, the second conductive layer 3 can have a three-layer structure consisting of titanium, nickel and copper. In other embodiments, the second conductive layer 3 can be made of metal materials such as titanium, nickel or silver. In some embodiments, the passivation layer 8 can be made of polyimide or silicon nitride.

[0063] In some embodiments, Figure 2aAs shown, the plurality of p-type ring sub-regions 5 are all ring-shaped and are arranged around the p-type region 4. The p-type ring structure 11 adjacent to the p-type region 4 is arranged around the p-type region 4. Of any two adjacent p-type ring structures 11, the p-type ring structure 11 away from the p-type region 4 is arranged around the p-type ring structure 11 close to the p-type region 4. The orthographic projections of any two adjacent p-type ring structures 11 on the n-type region 1 overlap with each other, so that each p-type ring structure 11 includes an overlapping area OA and a non-overlapping area NOA. The orthographic projection refers to the projection of the p-type ring structure 11 formed on the surface of the n-type region 1 perpendicular to the surface of the n-type region 1. The depth h1 of each p-type ring structure 11 in the non-overlapping area NOA is greater than the depth h2 of each p-type ring structure 11 in the overlapping area OA. In this way, the first p-type ring sub-region 51 constitutes a lateral doping ring.

[0064] In some embodiments of the present disclosure, Figure 2b As shown, the depth h2 of each p-type ring structure 11 in the overlap area OA varies continuously, and its minimum value is related to the overlap degree of the two p-type ring structures 11. In some embodiments of the present disclosure, the depth h2 of each p-type ring structure 11 in the overlap area OA is in the range of 0 to h1.

[0065] exist Figure 2a and Figure 2b In the embodiment shown, the first p-type ring sub-region 51 includes two p-type ring structures 11 contacting each other. Figure 2a As shown, the orthographic projections of the two p-type ring structures 11 on the n-type region 1 overlap each other, so that each p-type ring structure 11 includes an overlapping area OA and a non-overlapping area NOA. The depth of each p-type ring structure 11 in the non-overlapping area NOA is greater than the depth of each p-type ring structure 11 in the overlapping area OA. In some embodiments, Figure 2a As shown, the channel stop region 9 is arranged around the plurality of p-type ring-shaped sub-regions 5 .

[0066] In the embodiment of the present disclosure, an orthographic projection refers to a projection formed on the surface of another object (e.g., n-type region 1) by irradiating an object (e.g., p-type ring structure 11) with light. In the embodiment of the present disclosure, the orthographic projections of two p-type ring structures 11 on the n-type region 1 overlap each other. Based on this, it can be known that the direction of light is from the p-type ring structure 11 to the n-type region 1, thereby obtaining the orthographic projection of the p-type ring structure 11, and this orthographic projection is on the surface of the n-type region 1. Adjacent p-type ring structures 11 correspond to two orthographic projections, and these two orthographic projections overlap each other, thereby illustrating the situation that adjacent p-type ring structures 11 overlap each other.

[0067] In the embodiment of the present disclosure, the p-type ring structure 11 is formed by a process such as ion implantation. In two adjacent p-type ring structures 11 formed by a process such as ion implantation, the implanted ions in one p-type ring structure 11 diffuse into the other p-type ring structure 11, and the implanted ions in the other p-type ring structure 11 diffuse into the one p-type ring structure 11, that is, the positive projections of the two adjacent p-type ring structures 11 on the n-type region 1 overlap, so that each p-type ring structure 11 includes an overlapping area OA and a non-overlapping area NOA. That is, each p-type ring structure 11 includes an overlapping area OA that overlaps with the adjacent p-type ring structure 11, and a non-overlapping area NOA that does not overlap with the adjacent p-type ring structure 11.

[0068] In the embodiment of the present disclosure, the material of the insulating layer 6 is oxide, for example, silicon oxide (eg, thermal silicon oxide or silicon oxide deposition).

[0069] In the embodiments of the present disclosure, Figure 2b As shown, the depth of each p-type ring structure 11 in the non-overlapping area NOA refers to the size of the portion in a direction perpendicular to the surface of the n-type region 1. The depth of each p-type ring structure 11 in the overlapping area OA refers to the size of the portion in a direction perpendicular to the surface of the n-type region 1.

[0070] In the embodiment of the present disclosure, the plurality of p-type ring-shaped sub-regions 5 are all ring-shaped, for example, Figure 2a As shown, the plurality of p-type ring sub-regions 5 are square rings. However, the present disclosure is not limited thereto. Alternatively, the plurality of p-type ring sub-regions 5 are ring structures of other shapes, such as polygonal ring structures such as circular rings and hexagonal rings.

[0071] In the embodiments of the present disclosure, Figure 2bAs shown, the first conductive layer 7 includes a first portion 12, and a plurality of second portions 13 located in the terminal area TA and surrounding the first portion 12 and spaced apart from the first portion 12 and each other, wherein the first portion 12 extends from a portion of the active area AA, across the boundary between the active area AA and the terminal area TA, to a portion of the terminal area TA; each second portion 13 corresponds to an insulating layer opening 10; each second portion 13 corresponds to a respective corresponding, different insulating layer opening 10; the first p-type ring structure 11 in contact with the p-type region 4 among the p-type region 4 and the plurality of p-type ring structures 11 contacts (for example, directly contacts) the first portion 12 through the same insulating layer opening 10 (that is, the first insulating layer opening) closest to the p-type region 4 among the plurality of insulating layer openings 10, and the other plurality of p-type ring structures 11 contact (for example, directly contacts) the corresponding second portion 13 through the corresponding insulating layer opening 10 (that is, the second insulating layer opening). In the embodiment of the present disclosure, the first portion 12 and the plurality of second portions 13 are used as metal field plates.

[0072] In the embodiments of the present disclosure, Figure 2a and Figure 2b As shown, the multiple p-type ring sub-regions 5 also include a plurality of second p-type ring sub-regions 52 spaced apart from each other and arranged around the first p-type ring sub-region 51, the plurality of second p-type ring sub-regions 52 are arranged sequentially along the direction from the active area AA to the terminal area TA, and the plurality of second p-type ring sub-regions 52 respectively contact the corresponding second portions 13 through corresponding insulating layer openings 10 (i.e., second insulating layer openings) among the multiple insulating layer openings 10.

[0073] In the present disclosure, the length of the first p-type annular sub-region 51 and the length of each second p-type annular sub-region 52 are not limited. The length of the first p-type annular sub-region 51 refers to the size of the first p-type annular sub-region 51 in the direction from the active area AA to the terminal area TA. The length of the second p-type annular sub-region 52 refers to the size of the second p-type annular sub-region 52 in the direction from the active area AA to the terminal area TA. In the embodiment of the present disclosure, the length of the first p-type annular sub-region 51 may be equal to or may not be equal to the length of each second p-type annular sub-region 52. Figure 2b As shown, the channel stop region 9 is in contact with a second portion 13 through an insulating layer opening.

[0074] In some embodiments, each p-type ring sub-region 5 is a continuously formed ring region (eg Figure 2a In an alternative embodiment, each p-type ring sub-region 5 is a discontinuous ring region (such as Figure 2c In some embodiments, each p-type ring structure 11 is a continuously formed ring region (such as Figure 2a In an alternative embodiment, each p-type ring structure 11 is a discontinuous ring region (such as Figure 2c In some embodiments, each second p-type ring sub-region 52 is a continuously formed ring region (such as Figure 2a In an alternative embodiment, each second p-type ring sub-region 52 is a discontinuous ring region (eg Figure 2c ), that is, each second p-type ring sub-region 52 includes a plurality of portions spaced apart from each other.

[0075] Figure 2c The figure only shows an example of a discontinuous annular region, as long as the various parts of each p-type annular structure 11 and the various parts of each second p-type annular sub-region 52 respectively constitute an annular region as a whole.

[0076] Figure 2d A cross-sectional view of another structure of a semiconductor device provided according to an embodiment of the present disclosure. In an embodiment of the present disclosure, the insulating layer 6 may be provided with only one first insulating layer opening 10, without providing a plurality of second insulating layer openings. That is, the insulating layer 6 is configured so that the plurality of second p-type ring sub-regions 52 are electrically insulated from the first conductive layer 7. Among the p-type region 4 and the plurality of p-type ring structures 11, the first p-type ring structure 11 in contact with the p-type region 4 contacts (e.g., directly contacts) the first portion 12 through the first insulating layer opening 10, and the other plurality of p-type ring structures 11 do not contact the second portion 13. Figure 2d In the embodiment shown, the plurality of second portions 13 of the first conductive layer 7 are floating. Figure 2d As shown, the channel stop region 9 is electrically insulated from the first conductive layer 7 .

[0077] In the embodiments of the present disclosure, Figure 2b As shown, in a plane perpendicular to the surface of the n-type region 1 and parallel to the direction from the active region AA to the terminal region TA (ie, in Figure 2b In the cross section shown in the figure, any two adjacent p-type ring structures 11 form a recess RE in the area where they contact each other, and the recess RE is recessed in the direction away from the n-type region 1. The recess RE is caused by the overlap of the two p-type ring structures 11, that is, the recess RE is located in the overlapping area OA.

[0078] In the embodiment of the present disclosure, the first conductive layer 7 forms an ohmic contact with multiple p-type annular sub-regions 5, multiple p-type annular structures 11, and p-type region 4. In the embodiment of the present disclosure, multiple p-type annular sub-regions 5, multiple p-type annular structures 11, and p-type region 4 are heavily doped, which is conducive to forming an ohmic contact. Specifically, among the p-type region 4 and the multiple p-type annular structures 11, the p-type annular structure 11 in contact with the p-type region 4 forms an ohmic contact with the first portion 12 through the same insulating layer opening 10 closest to the p-type region 4 among the multiple insulating layer openings 10, and the other multiple p-type annular structures 11 form an ohmic contact with the corresponding second portion 13 through the corresponding insulating layer openings 10. Multiple second p-type annular sub-regions 52 form ohmic contacts with the corresponding second portion 13 through the corresponding insulating layer openings 10.

[0079] In the embodiment of the present disclosure, the n-type region 1 can be any suitable material, such as silicon, etc. In the embodiment of the present disclosure, the substrate dopant of the p-type region 4, the plurality of p-type ring structures 11 and the plurality of second p-type ring sub-regions 52 can be any suitable material, such as boron, aluminum, etc. That is, the p-type region 4, the plurality of p-type ring structures 11 and the plurality of second p-type ring sub-regions 52 are formed by implanting boron or aluminum ions in the n-type region 1. In the embodiment of the present disclosure, the n+ type diffusion layer 2 is formed by implanting phosphorus ions, arsenic ions or antimony ions in the n-type region 1.

[0080] In an optional embodiment of the present disclosure, the doping concentration of the plurality of p-type ring structures 11 may be the same as or different from the doping concentration of the plurality of second p-type ring sub-regions 52. In an embodiment of the present disclosure, the doping depth of the plurality of p-type ring structures 11 may be the same as or different from the doping depth of the plurality of second p-type ring sub-regions 52.

[0081] In the embodiment of the present disclosure, the doping concentration of each p-type ring structure 11 can be 1E15 cm -3 To 1E20cm -3 In the embodiment of the present disclosure, the doping concentration of each second p-type ring sub-region 52 may be within the range of 1E15 cm -3 to 1E20 cm -3 within the range.

[0082] In an embodiment of the present disclosure, the doping depth of each p-type ring structure 11 may be in the range of 2 μm to 50 μm. In an embodiment of the present disclosure, the doping depth of each second p-type ring sub-region 52 may be in the range of 2 μm to 50 μm.

[0083] In the embodiments of the present disclosure, Figure 2a and Figure 2bAs shown, it is only schematically shown that the multiple p-type ring sub-regions 5 include two second p-type ring sub-regions 52. However, the present disclosure is not limited thereto. In other embodiments, the multiple p-type ring sub-regions 5 may also include other numbers of second p-type ring sub-regions 52. In the embodiments of the present disclosure, there is no restriction on the number of the multiple p-type ring structures 11 of the first p-type ring sub-region 51. There is also no restriction on the number of the second p-type ring sub-regions 52. In an alternative embodiment, the multiple second p-type ring sub-regions 52 may not be included, but only one first p-type ring sub-region 51 may be included, which is distributed in the entire terminal area TA.

[0084] In the embodiments of the present disclosure, Figure 2b As shown, the doping depth of the plurality of p-type ring-shaped sub-regions 52 is greater than the doping depth of the p-type region 4 .

[0085] In the embodiment of the present disclosure, the doping concentration of the p-type region 4 may be 1E15 cm -3 to 1E20 cm -3 In the embodiment of the present disclosure, the doping depth of the p-type region 4 may be in the range of 2 μm to 50 μm.

[0086] In the embodiments of the present disclosure, Figure 2a and Figure 2b As shown, the orthographic projection of the p-type ring structure 11 in contact with the p-type region 4 on the n-type region 1 overlaps with the orthographic projection of the p-type region 4 on the n-type region 1 , where the orthographic projection refers to the projection of the p-type ring structure 11 formed on the surface of the n-type region 1 perpendicular to the surface of the n-type region 1 .

[0087] In the embodiments of the present disclosure, Figure 2a and Figure 2b As shown, the doping concentration and doping depth of the p-type ring structure 11 in the overlapping area OA are respectively smaller than the doping concentration and doping depth of other parts of the p-type ring structure 11 .

[0088] exist Figure 2a and Figure 2b In the semiconductor device in the illustrated embodiment, the first p-type ring sub-region 51 includes two p-type ring structures 11 in contact with each other, each p-type ring structure 11 corresponds to an insulating layer opening 10; each p-type ring structure 11 corresponds to a respective, different insulating layer opening 10. The multiple p-type ring structures 11 contact the first conductive layer 7 through the corresponding insulating layer openings 10. In this way, the electric field and current distribution and carrier distribution of the semiconductor device of the present disclosure are more uniform, the current concentration phenomenon is improved, the ability of the semiconductor device of the present disclosure to prevent dynamic avalanche breakdown is improved, and the durability of the semiconductor device of the present disclosure is improved.

[0089] For semiconductor devices provided according to the embodiments of the present disclosure, such as ultra-fast diodes (ultra-fast diodes / hyper-fast diodes), metal-oxide-semiconductor field effect transistors (Metal-Oxide-Semiconductor Field Effect Transistors, MOSFETs) and insulated-gate bipolar transistors (Insulated-gate bipolar transistors, IGBTs), their durability is greatly improved and they have better reverse recovery behavior when in a reverse recovery state.

[0090] Figure 3a FIG. 1 is a top view of another structure of a semiconductor device provided according to an embodiment of the present disclosure. Figure 3b For along Figure 3a In the embodiment of the present disclosure, Figure 2a and Figure 2b The structure of the semiconductor device shown is different from that of Figure 3a and Figure 3b As shown, the first p-type ring sub-region 51 includes three p-type ring structures 11 contacting each other, and each p-type ring structure 11 corresponds to an insulating layer opening 10. Each p-type ring structure 11 corresponds to a respective, different insulating layer opening 10. The multiple p-type ring structures 11 contact the first conductive layer 7 through the corresponding insulating layer openings 10.

[0091] In another aspect, the present disclosure provides a method of manufacturing a semiconductor device. Figure 4 The present invention is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 5a to Figure 5e Cross-sectional views showing respective steps of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 5a to Figure 5e Shown Figure 2a and Figure 2b The embodiment shown in the figure is an example of a cross-sectional view of each step of a method for manufacturing a semiconductor device. Figure 4 As shown, the method for manufacturing a semiconductor device according to an embodiment of the present disclosure includes the following steps:

[0092] S1, such as Figure 5a As shown, a semiconductor substrate 1 of a first conductivity type (eg, Figure 2a The n-type semiconductor substrate shown can be used as Figure 1a The semiconductor device shown has an n-type region 1), wherein the semiconductor substrate 1 comprises a first surface and a second surface opposite to each other;

[0093] S2, such as Figure 5bAs shown, a contact region of a first conductivity type is formed on a first surface of the n-type region 1, for example, it is an n+ type diffusion layer 2 in contact with the n-type region 1;

[0094] In an embodiment of the present disclosure, the semiconductor device has an active area AA and a terminal area TA surrounding the active area AA. In an embodiment of the present disclosure, the n-type region 1 can be any suitable material, for example, a semiconductor substrate of n-type doped silicon, etc. In an embodiment of the present disclosure, the n+ type diffusion layer 2 is formed by further implanting phosphorus ions, arsenic ions or antimony ions in the n-type region 1.

[0095] S3, such as Figure 5c As shown, a base region of the second conductivity type is formed on the second surface of the n-type region 1, for example, a p-type region 4, which is located in the active area AA; a plurality of annular sub-regions of the second conductivity type are formed on the second surface of the n-type region 1, for example, Figure 2a The multiple p-type ring-shaped sub-regions 5 shown are located in the terminal area TA and are spaced apart from each other.

[0096] In an embodiment of the present disclosure, a plurality of p-type ring sub-regions 5 and a p-type region 4 are formed by implanting boron or aluminum ions in a semiconductor substrate such as an n-type region 1. In an embodiment of the present disclosure, the step of forming an n+ type diffusion layer 2 on the first surface of the n-type region 1 (i.e., step S2) may be performed before or after the step of forming a p-type region 4 on the second surface of the n-type region 1 and forming a plurality of p-type ring sub-regions 5 on the second surface of the n-type region 1 (i.e., step S3). In the step of forming a p-type region 4 on the second surface of the n-type region 1 and forming a plurality of p-type ring sub-regions 5 on the second surface of the n-type region 1 (i.e., step S3), the p-type region 4 and the plurality of p-type ring sub-regions 5 may be formed simultaneously or at different times, and this is not limited.

[0097] S4, such as Figure 5d As shown, an insulating layer 6 is formed on one side of the plurality of p-type ring-shaped sub-regions 5 away from the n-type region 1 , which is located in the terminal area TA and has a plurality of insulating layer openings 10 .

[0098] In the embodiment of the present disclosure, the plurality of insulating layer openings 10 are formed by patterning and etching processes. In the embodiment of the present disclosure, the material of the insulating layer 6 is oxide, for example, silicon oxide (eg, thermal silicon oxide or silicon oxide deposition).

[0099] S5, such as Figure 5e As shown, a first conductive layer 7 is formed on the side of the p-type region 4 and the insulating layer 6 away from the n-type region 1 , and is located in the active area AA and the terminal area TA.

[0100] In the embodiment of the present disclosure, a conductive layer material (eg, aluminum silicon alloy) is coated on the side of the p-type region 4 and the insulating layer 6 away from the n-type region 1 by a sputtering process, and the conductive layer material is patterned, etched, and sintered to form a first conductive layer 7.

[0101] In the embodiment of the present disclosure, forming a plurality of p-type ring sub-regions 5 includes forming a first p-type ring sub-region 51. The first p-type ring sub-region 51 contacts the p-type region 4. Forming the first p-type ring sub-region 51 includes forming a plurality of p-type ring structures 11 contacting each other, each p-type ring structure 11 corresponding to an insulating layer opening 10. Each p-type ring structure 11 corresponds to a respective, different insulating layer opening 10; the plurality of p-type ring structures 11 contact the first conductive layer 7 through the corresponding insulating layer opening 10.

[0102] In an embodiment of the present disclosure, forming a plurality of p-type ring sub-regions 5 also includes forming a plurality of second p-type ring sub-regions 52 spaced apart from each other and arranged around the first p-type ring sub-region 51, the plurality of second p-type ring sub-regions 52 being arranged sequentially along a direction from the active area AA to the terminal area TA; and the plurality of second p-type ring sub-regions 52 respectively contact corresponding second portions 13 through corresponding insulating layer openings 10 among the plurality of insulating layer openings 10.

[0103] In the embodiment of the present disclosure, the first p-type ring sub-region 51 and the plurality of second p-type ring sub-regions 52 may be formed simultaneously or at different times, which is not limited.

[0104] In an alternative embodiment, the insulating layer 6 may be provided with only one first insulating layer opening 10, without providing a plurality of second insulating layer openings. That is, the insulating layer 6 is provided so that the plurality of second p-type ring sub-regions 52 are electrically insulated from the first conductive layer 7. The first p-type ring structure 11 in contact with the p-type region 4 and the plurality of p-type ring structures 11 contacts (e.g., directly contacts) the first portion 12 through the first insulating layer opening 10, and the other plurality of p-type ring structures 11 do not contact the second portion 13.

[0105] Figure 6 The specific process of forming a plurality of p-type ring-shaped sub-regions on the second surface of the n-type region in step S3 of the method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown. Figures 7a to 7d The cross-sectional view shows the steps of forming a plurality of p-type ring-shaped sub-regions on the second surface of the semiconductor substrate in step S3 of the method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figures 7a to 7d Shown Figure 2a and Figure 2b Taking the embodiment shown in the figure as an example, a cross-sectional view of each step of forming a plurality of p-type ring-shaped sub-regions on the second surface of the n-type region in step S3 of the method for manufacturing a semiconductor device. Figure 6 As shown, in the embodiment of the present disclosure, the step of forming a plurality of p-type ring-shaped sub-regions 5 on the second surface of the n-type region 1 includes the following steps:

[0106] S31, such as Figure 7a As shown, a photoresist layer is coated on the second surface of the n-type region 1 and a photoresist pattern 01 is formed.

[0107] S32, such as Figure 7b As shown, the photoresist pattern 01 is used as a mask, and an ion implantation method (such as Figure 7b As shown, marked as II), a plurality of p-type ring layers 02 and a plurality of second p-type ring sublayers 03 are formed, and adjacent p-type ring layers 02 are spaced apart by a first spacing d1; adjacent second p-type ring sublayers 03 are spaced apart by a second spacing d2, wherein the first spacing d1 is smaller than the second spacing d2; and adjacent p-type ring layers 02 and second p-type ring sublayers 03 are also spaced apart by a second spacing d2.

[0108] In the embodiment of the present disclosure, the step of forming the p-type region 4 on the second surface of the n-type region 1 in step S3 includes the following steps: In step S32, as Figure 7b As shown, while forming a plurality of p-type ring layers 02 and a plurality of second p-type ring sub-layers 03 , a p-type layer 04 is formed by ion implantation using the photoresist pattern 01 as a mask, and adjacent p-type ring layers 02 are spaced apart from the p-type layer 04 .

[0109] S33, such as Figure 7c As shown, the photoresist pattern 01 is removed;

[0110] S34, such as Figure 7d As shown, a plurality of p-type ring layers 02 and a plurality of second p-type ring sub-layers 03 are subjected to high temperature treatment to further diffuse the implanted ions to form a plurality of p-type ring structures 11 and a plurality of second p-type ring sub-regions 52, so that the orthographic projections of any two adjacent p-type ring structures 11 on the n-type region 1 overlap each other, so that each p-type ring structure 11 includes an overlapping region OA and a non-overlapping region NOA; the orthographic projection is a projection of the p-type ring structure 11 formed on the surface of the n-type region 1 perpendicular to the surface of the n-type region 1, and the orthographic projections of any two adjacent second p-type ring sub-regions 52 on the n-type region 1 do not overlap each other. The orthographic projections of the adjacent second p-type ring sub-regions 52 and the p-type ring structure 11 on the n-type region 1 do not overlap each other; the depth of each p-type ring structure 11 in the non-overlapping region NOA is greater than the depth of each p-type ring structure 11 in the overlapping region OA. In this way, the first p-type ring sub-region 51 constitutes a lateral variable doping ring.

[0111] In an embodiment of the present disclosure, the first spacing d1 satisfies the following condition: 0 < d1 < 2×X0, where X0 represents the depth of each p-type ring structure 11 in the non-overlapping region NOA. Preferably, the first spacing d1 is 0.5×X0, 1.0×X0, or 1.5×X0. In an embodiment of the present disclosure, the second spacing d2 satisfies the following condition: d2 > 2×X0. Thus, in forming a plurality of p-type ring sub-regions 5 through the above steps S31 to S34, the positive projections of any two adjacent p-type ring structures 11 on the n-type region 1 overlap each other, while the positive projections of any two adjacent second p-type ring sub-regions 52 on the n-type region 1 do not overlap each other. The positive projections of the adjacent second p-type ring sub-regions 52 and the p-type ring structures 11 on the n-type region 1 do not overlap each other.

[0112] In an embodiment of the present disclosure, during the high-temperature treatment process, the maximum temperature can be 1150 °C, 1175 °C, 1200 °C, or 1250 °C, etc.; the duration at the maximum temperature can be 60 minutes, 120 minutes,..., or 900 minutes. The maximum temperature and the duration can be determined according to actual needs, and there is no limitation thereto.

[0113] In an embodiment of the present disclosure, the step of forming the p-type region 4 on the second surface of the n-type region 1 in step S3 includes the following steps: In step S34, as Figure 7d shown, while performing high-temperature treatment on the plurality of p-type ring layers 02 and the plurality of second p-type ring sub-layers 03, the p-type layer 04 is subjected to high-temperature treatment to further diffuse the implanted ions to form the p-type region 4. Among them, the positive projection of the p-type ring structure 11 in contact with the p-type region 4 on the n-type region 1 overlaps the positive projection of the p-type region 4 on the n-type region 1, and the positive projection is the projection formed on the surface of the n-type region 1 with the p-type ring structure 11 perpendicular to the surface of the n-type region 1.

[0114] In an embodiment of the present disclosure, the number of the plurality of p-type ring structures 11 in the first p-type ring sub-region 51 is not limited. The number of the second p-type ring sub-regions 52 is also not limited. In an alternative embodiment, the plurality of second p-type ring sub-regions 52 may not be included, and only one first p-type ring sub-region 51 may be included, which is distributed in the entire terminal region TA.

[0115] Figure 8 Illustrates the specific process of forming a plurality of p-type ring sub-regions on the second surface of the n-type region in step S3 of the method for manufacturing a semiconductor device according to an alternative embodiment of the present disclosure. As Figure 8 shown, in an embodiment of the present disclosure, the step of forming a plurality of p-type ring sub-regions 5 on the second surface of the n-type region 1 includes the following steps:

[0116] S31 ′, coating a photoresist layer on the second surface of the n-type region 1 and forming a photoresist pattern.

[0117] S32 ′, using the photoresist pattern as a mask, forming a plurality of p-type ring layers by ion implantation, wherein adjacent p-type ring layers are spaced apart by a first interval d1 .

[0118] S33', removing the photoresist pattern.

[0119] S34', subjecting the plurality of p-type ring layers to high temperature treatment to further diffuse the injected ions to form a plurality of p-type ring structures 11, so that the orthographic projections of any two adjacent p-type ring structures 11 on the n-type region 1 overlap with each other, so that each p-type ring structure 11 includes an overlapping area OA and a non-overlapping area NOA; the orthographic projection is a projection of the p-type ring structure 11 formed on the surface of the n-type region 1 perpendicular to the surface of the n-type region 1; the depth of each p-type ring structure 11 in the non-overlapping area NOA is greater than the depth of each p-type ring structure 11 in the overlapping area OA.

[0120] In the embodiment of the present disclosure, after the step of forming the first conductive layer 7 on the side of the p-type region 4 and the insulating layer 6 away from the n-type region 1 (i.e., step S6), the method further includes: forming a second conductive layer 3 located on the side of the n+ type diffusion layer 2 away from the n-type region 1; forming a passivation layer 8 located on the side of the first conductive layer 7 away from the n-type region 1. In the embodiment of the present disclosure, after the step of forming the p-type region 4 on the second side of the n-type region 1 and forming a plurality of p-type ring sub-regions 5 on the second side of the n-type region 1 (i.e., step S3), the method further includes: forming a channel stop region 9 located in the terminal area TA and on the second side of the n-type region 1, and spaced apart from the plurality of p-type ring sub-regions 5. In some embodiments, the channel stop region 9 is disposed around the plurality of p-type ring sub-regions 5.

[0121] The electric field, current distribution and carrier distribution of the semiconductor device manufactured by the method provided by the embodiment of the present disclosure are more uniform, the current concentration phenomenon is improved, the ability of the semiconductor device of the present disclosure to prevent dynamic avalanche breakdown is improved, and the durability of the semiconductor device of the present disclosure is improved.

[0122] Fig. 9 The p-type ring sub-region 5 according to the embodiment of the present disclosure is shown along Figure 2b The doping distribution of the dashed line LL' is shown in Figure 1. Fig. 9 As shown, the horizontal axis represents the distance along the dotted line LL' in μm; the vertical axis represents the doping distribution in cm -3 The doping distribution of the two p-type ring structures 11 in the first p-type ring sub-region 51 is marked in the dotted frame. Fig. 9The doping distributions of the two p-type ring structures 11 of the plurality of second p-type ring sub-regions 52 and the first p-type ring sub-region 51 are shown. At the overlapping region OA of the p-type ring structures 11 that are in contact with each other, the doping distribution of the portion of each p-type ring structure 11 in the non-overlapping region NOA is significantly greater than the doping distribution of the portion of each p-type ring structure 11 in the overlapping region OA. The doping distribution of each second p-type ring sub-region 52 is substantially the same as the doping distribution of the portion of each p-type ring structure 11 in the non-overlapping region NOA.

[0123] Fig.10 The p-type ring sub-region 5 according to the embodiment of the present disclosure is shown along Figure 3b The doping profile of the dashed line MM' is similar to Fig. 9 , Fig.10 The horizontal axis represents the distance along the dotted line LL' in μm, and the vertical axis represents the doping distribution in cm -3 The doping distribution of the three p-type ring structures 11 in the first p-type ring sub-region 51 is marked in the dotted box. Fig.10 The doping distributions of the three p-type ring structures 11 of the plurality of second p-type ring sub-regions 52 and the first p-type ring sub-region 51 are shown. At the overlapping region OA of the p-type ring structures 11 that are in contact with each other, the doping distribution of the portion of each p-type ring structure 11 in the non-overlapping region NOA is significantly greater than the doping distribution of the portion of each p-type ring structure 11 in the overlapping region OA. The doping distribution of each second p-type ring sub-region 52 is substantially the same as the doping distribution of the portion of each p-type ring structure 11 in the non-overlapping region NOA.

[0124] Fig.11 The relationship between voltage drop and current of a semiconductor device according to an embodiment of the present disclosure is shown. Fig.12 FIG. 2 shows the relationship between the blocking voltage and the leakage current of the semiconductor device according to the embodiment of the present disclosure. Fig.11 As shown in the figure, the horizontal axis represents the voltage drop and the vertical axis represents the current. When the voltage drop reaches the range of 0.8 to 1V, the current suddenly changes from 0A to 150A. Fig.12 As shown in the figure, the horizontal axis represents the blocking voltage and the vertical axis represents the leakage current. When the blocking voltage is 1400V, the leakage current suddenly increases.

[0125] Fig.13a Show Figure 1b The electric field distribution of a semiconductor device in the prior art is shown. Fig.13b Show Figure 2b Schematic diagram of an electric field distribution of a semiconductor device according to an embodiment of the present disclosure. Fig.13c Show Figure 3b Schematic diagram of an electric field distribution of a semiconductor device according to an embodiment of the present disclosure. Fig.14a Show Figure 1b The current density distribution of a semiconductor device in the prior art is shown. Fig.14b Show Figure 2b Schematic diagram of a current density distribution of a semiconductor device according to an embodiment of the present disclosure. Fig.14c Show Figure 3b The current density distribution of the semiconductor device according to the embodiment of the present disclosure is shown in FIG. Figures 13a to 13c as well as Figures 14a to 14c As shown, the abscissa Y and the ordinate X represent the distance in the direction from the active area AA to the terminal area TA and the distance in the direction perpendicular to the surface of the n-type region 1, respectively; the current density is represented by the depth of the color, the darker the color, the greater the current density.

[0126] In a semiconductor device according to the prior art, as Fig.14a As shown, the current density is large, resulting in current concentration, which can easily cause the semiconductor device to burn out. In the semiconductor device according to the embodiment of the present disclosure, as shown in FIG. Fig.14b and Fig.14c As shown, the current is distributed into two areas and the current distribution is more uniform, thereby reducing the current density, thereby improving the current concentration phenomenon and avoiding the burning of semiconductor devices.

[0127] According to the embodiment of the present disclosure, each p-type ring structure 11 in the semiconductor device has a variable doping distribution in the non-overlapping area NOA and the overlapping area OA, so that the first p-type ring sub-region 51 constitutes a laterally variable doping ring, thereby improving the electric field distribution and current density distribution of the semiconductor device, thereby improving the durability of the semiconductor device and enabling the semiconductor device to have better reverse recovery behavior when in a reverse recovery state.

[0128] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

[0129] Reference numerals list

[0130]

[0131]

Claims

1. A semiconductor device having an active region and a terminal region surrounding the active region, the semiconductor device comprising: A semiconductor substrate of a first conductivity type, the semiconductor substrate comprising a first surface and a second surface opposite to each other; A base region of a second conductivity type, located in the active region and on the second surface of the semiconductor substrate; A plurality of annular sub-regions of the second conductivity type, which are located in the terminal region and on the second surface of the semiconductor substrate and are spaced apart from each other; an insulating layer, which is located in the terminal region and on a side of the plurality of annular sub-regions away from the semiconductor substrate; wherein the insulating layer is provided with a first insulating layer opening; A first conductive layer, which is located in the active region and the terminal region, and is located on a side of the base region and the insulating layer away from the semiconductor substrate; Wherein, the plurality of annular sub-regions include a first annular sub-region; the first annular sub-region is in contact with the base region; The first conductive layer includes a first portion, and a plurality of second portions surrounding the first portion and located in the terminal region, wherein the first portion is spaced apart from the plurality of second portions and extends from a portion of the active region, across a boundary between the active region and the terminal region, to a portion of the terminal region, wherein the plurality of second portions are spaced apart from each other; The first annular sub-region includes a plurality of annular structures of the second conductivity type contacting each other, and a first annular structure contacting the base region among the base region and the plurality of annular structures contacts the first portion through the first insulating layer opening.

2. The semiconductor device according to claim 1, wherein The insulating layer is also provided with a plurality of second insulating layer openings; Each second portion of the first conductive layer corresponds to a second insulating layer opening, and each second portion corresponds to a respective, different second insulating layer opening; The other annular structures except the first annular structure contact the corresponding second portion through their corresponding second insulating layer openings.

3. The semiconductor device according to claim 2, wherein: The first conductivity type is n-type; The second conductivity type is p-type; The semiconductor substrate is an n-type region, the base region is a p-type region, the multiple annular sub-regions are multiple p-type annular sub-regions, the first annular sub-region is a first p-type annular sub-region, and the annular structure is a p-type annular structure.

4. The semiconductor device according to claim 3, wherein: The plurality of p-type annular sub-regions are all annular and are arranged around the p-type region; Among any two adjacent p-type ring structures, the p-type ring structure far away from the p-type region is arranged around the p-type ring structure close to the p-type region; The orthographic projections of any two adjacent p-type ring structures on the n-type region overlap with each other, so that each p-type ring structure includes an overlapping region and a non-overlapping region; the orthographic projection is a projection of the p-type ring structure formed on the surface of the n-type region perpendicular to the surface of the n-type region; A depth of each p-type ring structure in a portion of the non-overlapping region is greater than a depth of each p-type ring structure in a portion of the overlapping region.

5. The semiconductor device according to claim 3, wherein: The plurality of p-type ring sub-regions further include a plurality of second p-type ring sub-regions spaced apart from each other and arranged around the first p-type ring sub-region, the plurality of second p-type ring sub-regions being arranged in sequence along a direction from the active region to the terminal region; and The plurality of second p-type ring sub-regions respectively contact the corresponding second portions through corresponding second insulating layer openings among the plurality of second insulating layer openings.

6. The semiconductor device according to claim 5, wherein: In a plane perpendicular to the surface of the n-type region and parallel to the direction from the active region to the terminal region, any two adjacent p-type ring structures form a recess in the contacting region, and the recess is recessed in a direction away from the n-type region.

7. The semiconductor device according to claim 5, wherein: The doping concentration of the plurality of p-type ring structures is different from the doping concentration of the plurality of second p-type ring sub-regions; and / or The doping depths of the plurality of p-type ring structures are different from the doping depths of the plurality of second p-type ring sub-regions.

8. The semiconductor device according to claim 3, wherein: The doping depths of the plurality of p-type ring-shaped sub-regions are greater than the doping depth of the p-type region.

9. The semiconductor device according to claim 3, wherein: The plurality of p-type ring structures include two or three p-type ring structures.

10. The semiconductor device according to any one of claims 3 to 9, wherein: The orthographic projection of the p-type ring structure in contact with the p-type region on the n-type region overlaps with the orthographic projection of the p-type region on the n-type region, wherein the orthographic projection is a projection of the p-type ring structure formed perpendicular to the surface of the n-type region on the surface of the n-type region.

11. The semiconductor device according to claim 4, wherein: The doping concentration and doping depth of the p-type ring structure in the overlapping region are respectively smaller than the doping concentration and doping depth of other portions of the p-type ring structure.

12. A method of forming a semiconductor device, wherein: The semiconductor device has an active area and a termination area surrounding the active area, and the method includes: Providing a semiconductor substrate of a first conductivity type, the semiconductor substrate comprising a first surface and a second surface opposite to each other; forming a base region of a second conductivity type on the second surface of the semiconductor substrate, the base region being located in the active region; Forming a plurality of annular sub-regions of the second conductivity type on the second surface of the semiconductor substrate, which are located in the terminal region and spaced apart from each other; Forming an insulating layer on a side of the plurality of annular sub-regions away from the semiconductor substrate, the insulating layer being located in the terminal region and provided with a first insulating layer opening; Forming a first conductive layer on a side of the base region and the insulating layer away from the semiconductor substrate, the first conductive layer being located in the active region and the terminal region; Wherein, forming the plurality of annular sub-regions comprises: forming a first annular sub-region; the first annular sub-region is in contact with the base region; Forming the first conductive layer includes forming a first portion, and forming a plurality of second portions located in the terminal region and surrounding the first portion and spaced apart from each other, wherein the first portion is formed to be spaced apart from the plurality of second portions and extends from a portion of the active region, across a boundary between the active region and the terminal region, to a portion of the terminal region; Forming the first annular sub-region includes: forming a plurality of annular structures of the second conductivity type contacting each other; A first ring structure among the base region and the plurality of ring structures that contacts the base region contacts the first portion through an opening of the first insulating layer.

13. The method according to claim 12, wherein: The insulating layer is also provided with a plurality of second insulating layer openings; Each second portion of the first conductive layer corresponds to a second insulating layer opening, and each second portion corresponds to a respective, different second insulating layer opening; The other annular structures except the first annular structure contact the corresponding second portion through their corresponding second insulating layer openings.

14. The method according to claim 13, wherein: The first conductivity type is n-type; The second conductivity type is p-type; The semiconductor substrate is an n-type region, the base region is a p-type region, the multiple annular sub-regions are multiple p-type annular sub-regions, the first annular sub-region is a first p-type annular sub-region, and the annular structure is a p-type annular structure.

15. The method according to claim 14, wherein: Forming the plurality of p-type ring sub-regions further includes: forming a plurality of second p-type ring sub-regions spaced apart from each other; the plurality of second p-type ring sub-regions are sequentially arranged along a direction from the active region to the terminal region and spaced apart from the first p-type ring sub-region; The forming of the first p-type ring sub-region and the forming of the plurality of second p-type ring sub-regions are performed simultaneously.

16. The method according to claim 15, wherein: Forming the plurality of p-type ring sub-regions comprises: coating a photoresist layer on the second surface of the n-type region and forming a photoresist pattern, Using the photoresist pattern as a mask, forming a plurality of p-type ring layers and a plurality of second p-type ring sublayers by ion implantation, wherein adjacent p-type ring layers are spaced apart by a first spacing; adjacent second p-type ring sublayers are spaced apart by a second spacing, wherein the first spacing is smaller than the second spacing; removing the photoresist pattern; The plurality of p-type ring layers and the plurality of second p-type ring sub-layers are subjected to high temperature treatment to further diffuse the implanted ions to form a plurality of p-type ring structures and the plurality of second p-type ring sub-regions, so that the orthographic projections of any two adjacent p-type ring structures on the n-type region overlap with each other, so that each p-type ring structure includes an overlapping region and a non-overlapping region, the orthographic projection being a projection of the p-type ring structure formed on the surface of the n-type region perpendicular to the surface of the n-type region; and the orthographic projections of any two adjacent second p-type ring sub-regions on the n-type region do not overlap with each other; A depth of each p-type ring structure in a portion of the non-overlapping region is greater than a depth of each p-type ring structure in a portion of the overlapping region.

17. The method according to claim 14, wherein: Forming the plurality of p-type ring sub-regions comprises: coating a photoresist layer on the second surface of the n-type region and forming a photoresist pattern, Using the photoresist pattern as a mask, forming a plurality of p-type ring layers by ion implantation, wherein adjacent p-type ring layers are spaced apart by a first spacing; removing the photoresist pattern; The plurality of p-type ring layers are subjected to high temperature treatment to further diffuse the implanted ions to form a plurality of p-type ring structures, so that the orthographic projections of any two adjacent p-type ring structures on the n-type region overlap with each other, so that each p-type ring structure includes an overlapping region and a non-overlapping region, and the orthographic projection is a projection of the p-type ring structure formed on the surface of the n-type region perpendicular to the surface of the n-type region; A depth of each p-type ring structure in a portion of the non-overlapping region is greater than a depth of each p-type ring structure in a portion of the overlapping region.

Images