Design and preparation method of metasurface heterogeneous integrated silicon-based EUV detector

Abstract

The invention discloses a metasurface heterogeneous integrated silicon-based EUV detector design and a preparation method thereof, and the detector is based on the metasurface light field regulation and control capability and the graphene / silicon heterogeneous integrated ultra-shallow junction characteristic, a silicon nanometer column is etched on an SOI through photoetching, a full-dry-method transfer technology is adopted to transfer single-layer graphene to the top of the silicon nanometer column to achieve heterogeneous integration, and the metasurface heterogeneous integrated silicon-based EUV detector is obtained. A Schottky barrier structure unit is obtained, and the key challenge of development of a silicon-based EUV detector (namely, how to realize efficient detection of an EUV wave band with extremely low transmission depth and simultaneously complete effective extraction of light field (wavefront) information) is overcome. According to the invention, an integrated scheme of EUV wavefront information and a direct'optical-electric 'detection function is developed, a device prototype approaching a theoretical performance limit is obtained, a foundation is laid for developing a novel EUV wavefront detection system, and the method has important significance for developing key parts of the novel EUV detection system.

Description

Technical Field

[0001] The present invention belongs to the field of micro-nano manufacturing technology, and specifically relates to a design of an ultra-surface heterogeneous integrated silicon-based EUV detector and a preparation method thereof. Background Art

[0002] Silicon-based extreme ultraviolet (EUV, 5-100nm) photodetectors are widely used in equipment systems such as synchrotron radiation and free electron lasers. The EUV wavefront detector, which has efficient detection capabilities in the 13.5nm band, is a key sensor element of the workpiece stage measurement and control subsystem in the EUV lithography machine, and is used for EUV beam imaging quality detection and wafer positioning. Existing commercial silicon-based EUV detectors are mostly co-packaged with a fluorescent layer and a silicon-based CCD sensor or implemented using "PureB" technology. The former uses the top fluorescent layer to convert the incident EUV band into visible light, and then uses the bottom CCD to indirectly realize photoelectric detection. It has high requirements for packaging technology and density, material and process compatibility, and has high technical barriers and preparation costs. Moreover, the response time of such systems is usually difficult to achieve picosecond (ps) accuracy, which becomes one of the key factors restricting the workpiece stage's "overlay accuracy" from breaking through 0.5nm (TSMCNXE: 3400BEUV lithography machine overlay accuracy ~1.8nm); the latter is based on the "pureboron (PureB)" process, and obtains an "ultra-shallow junction" with a junction depth of ~10nm, which can achieve direct detection in the 13.5nm band and a faster response speed. However, the preparation is also complicated, and in order to improve the response time and detection efficiency, the area of ​​the device is often large (to expand the depletion region width), which is not conducive to high-density pixel integration. In addition, in order to measure and analyze the deformation information (such as aberrations and astigmatism) of the EUV beam after modulation by the lens group, an additional integrated package Hartmann or Shack-Hartmann structure (usually a 2D hole array) will be formed on the top of the above-mentioned detector to form a "wavefront detector", which poses higher challenges to the preparation process and alignment accuracy. Carrying out the manufacturability design of super-surface heterogeneous integrated silicon-based EUV detectors, exploring the integrated integration scheme of EUV wavefront information and direct "photo-electric" detection functions, and developing supporting high-precision integration and preparation technologies are of great significance to the development of key components of new EUV detection systems. Summary of the invention

[0003] The purpose of the present invention is to propose a design of a super-surface heterogeneous integrated silicon-based EUV detector and its preparation method. A "super-shallow junction" Schottky barrier super-surface with a "junction depth" of nearly 0 is formed by heterogeneous integration of a single-layer graphene and silicon. Adjusting the doping concentration of the silicon layer can flexibly control the width of the depletion region in the silicon layer, thereby optimizing the effective absorption and efficient "light-to-electricity" direct conversion of the 13.5nm EUV band (the transmission depth is only 0-30nm); and the super-structured single-layer graphene can also absorb the incident EUV band, stimulate the generation of "hot carriers", cross the Schottky barrier to become part of the photocurrent, and improve the overall device detection performance (quantum efficiency and photoelectric responsivity). The preparation process of the present invention is simple, and solves the problem of how to achieve efficient "light-to-electricity" direct conversion detection in the EUV band with extremely low transmission depth and simultaneously complete the effective extraction of light field (wavefront) information.

[0004] The method for preparing the ultra-surface heterogeneous integrated silicon-based EUV detector proposed in the present invention comprises the following specific steps:

[0005] (1) Pretreatment of SOI substrate: Soak the SOI substrate in acetone for 15 min, then ultrasonically clean it in 60°C IPA solution for 5 min, and then take it out and blow dry it with N2;

[0006] (2) Preparation of Si nano-pillar array: After pretreatment, the SOI substrate is uniformly coated with photoresist on the front side, dried at 100°C for 90 seconds, and then electron beam lithography is used to form a photoresist circular array structure. On the front side of the substrate, the photoresist is used as a mask and HBr is used as an etching gas to form a Si nano-pillar array super surface structure by dry etching; the photoresist is spin-coated on the front side of the substrate, and the "photolithography-etching" process is cyclically performed to remove the Si and SiO2 at the edge to obtain a peripheral step structure;

[0007] (3) Gate epitaxy: Spin-coat photoresist on the substrate surface, remove the peripheral photoresist by photolithography and development, then epitaxially grow a layer of Si by MOCVD, and then soak it in acetone solution for 10 seconds to lift off the surface photoresist to obtain the gate structure;

[0008] (4) Manufacturing shallow trench isolation: Spin-coat a layer of photoresist on the substrate surface and define the pattern by photolithography development. Use the photoresist as a mask to form a trench structure by dry etching. Then, deposit SiO2 by CVD. After the deposition is completed, soak it in acetone solution for 10 seconds to lift off the surface photoresist. The trench is densely filled with SiO2 to form an isolation structure.

[0009] (5) Source and drain epitaxy: Spin a layer of photoresist on the substrate surface and define the pattern by photolithography and development. Then, use MOCVD to epitaxially grow an N-type SiC high-density epitaxial layer. After the growth is completed, soak it in acetone solution for 10 seconds to lift off the surface photoresist to form heavily doped source and drain electrodes.

[0010] (6) “Gr / Si heterojunction” supersurface integration: Based on the all-dry transfer technology, a single-layer graphene is transferred to the top of the silicon nanopillar, and the single-layer graphene is conformally integrated with the Si nanopillar (the sidewalls and the top are tightly combined) to form a “Gr / Si heterojunction” structure, obtaining a Schottky barrier superstructure unit. Then, a layer of TaBO film is deposited on the surface of the single-layer graphene using an ion beam plating process as an anti-reflection layer, finally forming a TaBO / Graphene / Si nanopillars supersurface structure;

[0011] (7) Back thinning: Spin-coat a layer of photoresist on the back of the substrate, use the photoresist as a mask to remove the back Si layer by wet etching (KOH and IPA mixed solution) process, put it in ultra-clean water to rinse and remove the etching solution after etching, then put it in HF solution to remove a certain SiO2 layer, put it in ultra-clean water to rinse and remove the etching solution after etching, and finally dry it;

[0012] (8) Fabrication of back reflector: An ion beam plating process is used to deposit a Mo / Si multilayer film structure on the thinned area on the back side of the substrate to form a back Mo / Si reflector structure.

[0013] Furthermore, the photoresist in step (1) can be various photoresist materials such as PMMA, SU8, HSQ, ZEP, ARP, UV5, etc.

[0014] Furthermore, the lithography technique described in step (1) may be optical lithography or electron beam lithography;

[0015] Furthermore, the etching process described in step (4) can be dry etching or wet etching;

[0016] Furthermore, the transfer technology described in step (6) may adopt a fully dry transfer technology or a multi-step wet process;

[0017] Furthermore, the wet etching in step (7) is performed by step etching, first etching away the excess Si layer, and then etching away a certain thickness of the buried oxide layer;

[0018] A super-surface heterogeneous integrated silicon-based EUV detector is prepared by the above steps, wherein the detector structure is, from top to bottom: a TaBO anti-reflection layer (ARC), a single-layer graphene, a Si nano-pillar array, an isolation layer, and a back Mo / Si reflector.

[0019] Furthermore, the reflector adopts a Mo / Si multilayer film structure.

[0020] Furthermore, weak P-type doping is used inside the channel of the Si nano-pillar array.

[0021] As described above, the design of a super-surface heterogeneous integrated silicon-based EUV detector and its preparation method of the present invention have the following beneficial effects:

[0022] (1) The silicon nanopillar array structure increases the "specific surface area" of the Gr / Si heterostructure and combines the optical trapping effect of the metasurface to enhance the absorption and photoelectric conversion capabilities of the photosensitive unit for incident light;

[0023] (2) Conformal integration of single-layer graphene and silicon nanopillars to construct Schottky barriers, achieve full depletion of silicon nanopillars and the bottom thin layer, thereby reducing the dark current of the device while increasing the equivalent width of the depletion region, achieving the suppression of heterojunction capacitance, and then reducing the RC constant and improving the response time (detection speed) of the device to meet the application in high-speed and high-frequency detection scenarios;

[0024] (3) By utilizing the powerful electromagnetic wave parameter control capability of the metasurface, the EUV light field information (such as wavefront information) detection function is simultaneously implanted into the detector when it is working. That is, by utilizing the metasurface composed of a single-layer Gr / Si "ultra-shallow junction", the EUV wavefront information and "light-to-electricity" direct conversion detection functions are integrated;

[0025] (4) The detector uses a fully depleted SOI substrate to form a transistor architecture, and places a "Gr / Si heterojunction" photodiode unit at the transistor gate position, which can use the transistor's transconductance characteristics (Id-Vg exponential relationship characteristics) to internally amplify the photocurrent of the gate photodiode, further improving the photoelectric conversion capability (responsivity and quantum efficiency) of the entire detection architecture;

[0026] (5) A TaBO anti-reflection layer (ARC) can be deposited on the top of the "Gr / Si heterojunction" metasurface to reduce the detector's reflection of the 13.5nm EUV band. At the same time, the Mo / Si reflector structure deposited on the back of the photosensitive area will reflect the EUV light that passes through the thin silicon channel layer (~30nm) back again, enhancing the absorption characteristics of the metasurface photosensitive unit and further enhancing the device's quantum efficiency and photoelectric response. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 The energy band structure of a single-layer graphene and a P-type silicon channel, and the energy band diagram of the Schottky barrier formed when the two are in contact;

[0028] Figure 2Schematic diagram of SOI substrate structure, the three-layer structure is Si, SiO2, Si;

[0029] Figure 3 The present invention is a method for preparing a super-surface heterogeneously integrated silicon-based EUV detector, and a schematic diagram of the structure of the silicon nano-pillar array prepared in the specific step (2);

[0030] Figure 4 A method for preparing a super-surface heterogeneously integrated silicon-based EUV detector, a schematic diagram of the structure of the gate formed by epitaxy in the specific step (3);

[0031] Figure 5 A method for preparing an ultra-surface heterogeneously integrated silicon-based EUV detector, wherein in the specific step (4), a groove is etched to deposit SiO2 to form a schematic diagram of a shallow trench isolation structure;

[0032] Figure 6 A method for preparing a super-surface heterogeneously integrated silicon-based EUV detector, a schematic diagram of the structure of epitaxially forming heavily doped source and drain electrodes in the specific step (5);

[0033] Figure 7 The present invention is a method for preparing an ultra-surface heterogeneously integrated silicon-based EUV detector, wherein in the specific step (6), a single-layer graphene is transferred by using a "full dry transfer technology" to conformally form a "Gr / Si heterojunction" structure with a Si nano-pillar array structure;

[0034] Figure 8 The method for preparing a super-surface heterogeneously integrated silicon-based EUV detector is a schematic diagram of the structure after back thinning by a wet etching process in the specific step (7);

[0035] Fig. 9 The present invention is a method for preparing a super-surface heterogeneous integrated silicon-based EUV detector, wherein in the specific step (8), a multi-layer Mo / Si thin film is deposited by an ion beam deposition coating process to form a reflector structure schematic diagram;

[0036] Fig.10 The present invention is a method for preparing an ultra-surface heterogeneously integrated silicon-based EUV detector, wherein the specific step (9) is a schematic diagram of a structure in which a multi-layer Mo / Si film is deposited using an ion beam deposition coating process. DETAILED DESCRIPTION

[0037] In order to better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention is clearly and completely described below in conjunction with the accompanying drawings. It should be clear that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] A super-surface heterogeneous integrated silicon-based EUV detector, wherein the detector structure is, from top to bottom, TaBO anti-reflection layer (ARC), single-layer graphene, Si nano-pillar array, isolation layer, and reflector.

[0039] Furthermore, the reflector adopts a Mo / Si multilayer film structure.

[0040] Furthermore, weak P-type doping is used inside the channel of the Si nano-pillar array.

[0041] A method for preparing a super-surface heterogeneous integrated silicon-based EUV detector, the preparation steps are as follows:

[0042] (1) Spin-coating a photoresist on an SOI substrate and exposing the photoresist film using a photolithography technique;

[0043] (2) After development, the SOI substrate is etched using a dry etching technique with the photoresist as a mask to obtain a silicon nanopillar array structure;

[0044] (3) epitaxially growing a gate structure using MOCVD;

[0045] (4) Using photolithography and etching processes to define the pattern, filling the shallow trench with deposited oxide to form shallow trench isolation (STI);

[0046] (5) epitaxially growing highly doped source and drain electrodes by MOCVD;

[0047] (6) Based on the dry transfer technology, a single layer of graphene is transferred to the top of the silicon nanopillar and a layer of TaBO film is deposited by ion beam coating process;

[0048] (7) Thinning the back of the device using a wet etching process;

[0049] (8) Use ion beam plating process to deposit the back Mo / Si reflector.

[0050] Furthermore, the photoresist in step (1) can be various photoresist materials such as PMMA, SU8, HSQ, ZEP, ARP, UV5, etc.

[0051] Furthermore, the lithography technique described in step (1) may be optical lithography or electron beam lithography;

[0052] Furthermore, the etching process described in step (4) can be dry etching or wet etching;

[0053] Furthermore, the transfer technology described in step (6) may adopt a fully dry transfer technology or a multi-step wet process;

[0054] Furthermore, the wet etching in step (7) is performed by step etching, first etching away the excess Si layer, and then etching away a certain thickness of the buried oxide layer;

[0055] Example 1: A super-surface heterogeneous integrated silicon-based EUV detector

[0056] Step 1: Clean the SOI wafer. Soak the SOI wafer in acetone for 15 minutes, then ultrasonically clean it in 60°C IPA solution for 5 minutes, and blow dry it with N2.

[0057] Step 2: Spin-coat a 200nm layer of ARP6200 photoresist on the SOI substrate, and then perform multiple exposure-development-dry etching based on the electron beam exposure system and plasma etching equipment to obtain a silicon nano-column array structure.

[0058] Step 3: Use MOCVD to epitaxially grow a layer of Si gate on the edge, then use shallow trench isolation process, use Si3N4 as a hard mask, photoetch a shallow trench structure, then use PECVD to deposit SiO2 in the trench as an isolation layer, and then use chemical mechanical polishing to flatten the SiO2.

[0059] Step 4: Use MOCVD to epitaxially grow an N-type SiC high-crystal epitaxial layer, which serves as the source and drain of the device respectively.

[0060] Step 5: Based on the all-dry transfer technology, the PDMS template is used as a "carrier" and covered on the graphene to obtain a graphene / PDMS stacked structure, which is transferred to the top of the silicon nanopillar, and the PDMS is released to achieve the common integration of graphene and silicon nanopillars, obtain a Schottky barrier superstructure unit, and then deposit a layer of TaBO film as an anti-reflection layer.

[0061] Step 6: Use a wet etching process to thin the back of the device, use a KOH solution to etch to the buried oxide layer, and then use an HF solution to etch away a certain amount of SiO2.

[0062] Step 7: Using ion beam deposition (IBD) technology, a multi-layer Mo / Si thin film structure is deposited on the back of the device as a reflector;

[0063] The specific embodiments and their working principles and preparation methods described above further illustrate the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above description is not intended to limit the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a super-surface heterogeneous integrated silicon-based EUV detector, characterized in that: The specific steps are as follows: (1) Pretreatment of SOI substrate: Soak the SOI substrate in acetone, then ultrasonically clean it in 60°C IPA solution, and then take it out and blow dry it with N2; (2) Preparation of Si nano-pillar array: After the pretreatment, the SOI substrate is uniformly coated with photoresist on the front side, and after drying at 100°C, electron beam lithography is used to form a photoresist circular array structure; on the front side of the substrate, the photoresist is used as a mask and HBr is used as an etching gas to form a Si nano-pillar array super surface structure by dry etching; photoresist is spin-coated on the front side of the substrate, and the "photolithography-etching" process is cyclically performed to remove Si and SiO2 at the edge to obtain a peripheral step structure; (3) Gate epitaxy: Spin-coat photoresist on the substrate surface, remove the peripheral photoresist by photolithography and development, then epitaxially grow a layer of Si by MOCVD, and then soak it in acetone solution for 10 seconds to strip off the surface photoresist to obtain the gate structure; (4) Manufacturing shallow trench isolation: Spin-coat a layer of photoresist on the substrate surface and define the pattern by photolithography development. Use the photoresist as a mask to form a trench structure by dry etching. Then, deposit SiO2 by CVD. After the deposition is completed, soak it in acetone solution for 10 seconds to strip off the surface photoresist. The trench is densely filled with SiO2 to form an isolation structure. (5) Source and drain epitaxy: Spin a layer of photoresist on the substrate surface and define the pattern by photolithography and development. Then, use MOCVD to epitaxially grow an N-type SiC high-density epitaxial layer. After the growth is completed, soak it in acetone solution for 10 seconds to strip off the surface photoresist to form heavily doped source and drain electrodes. (6) "Gr / Si heterojunction" supersurface integration: Based on the all-dry transfer technology, a single-layer graphene is transferred to the top of the silicon nanopillar. The single-layer graphene and the Si nanopillar are conformally integrated into a "Gr / Si heterojunction" structure to obtain a Schottky barrier superstructure unit. Then, a layer of TaBO film is deposited on the surface of the single-layer graphene by ion beam plating as an anti-reflection layer, finally forming a TaBO / Graphene / Si nanopillars supersurface structure; (7) Back thinning: Spin-coat a layer of photoresist on the back of the substrate, use the photoresist as a mask to remove the back Si layer by wet etching process, rinse in ultra-clean water to remove the etching solution after etching, then place in HF solution to remove a certain SiO2 layer, rinse in ultra-clean water to remove the etching solution after etching, and finally dry; (8) Fabrication of back reflector: An ion beam plating process is used to deposit a Mo / Si multilayer film structure on the thinned area on the back side of the substrate to form a back Mo / Si reflector structure.

2. The method for preparing a super-surface heterogeneous integrated silicon-based EUV detector according to claim 1, characterized in that: The photoresist described in step (2) is PMMA, SU8, HSQ, ZEP, ARP, or UV5 photoresist material.

3. The method for preparing a super-surface heterogeneous integrated silicon-based EUV detector according to claim 1, characterized in that: The photolithography in step (2) is optical photolithography or electron beam photolithography.

4. The method for preparing a super-surface heterogeneous integrated silicon-based EUV detector according to claim 1, characterized in that: The etching process described in step (4) is dry etching or wet etching.

5. The method for preparing a super-surface heterogeneous integrated silicon-based EUV detector according to claim 1, characterized in that: The transfer technology described in step (6) adopts a fully dry transfer technology using a multi-step wet process.

6. The method for preparing a super-surface heterogeneous integrated silicon-based EUV detector according to claim 1, characterized in that: The wet etching described in step (7) should be carried out in steps, first etching away the excess Si layer, and then etching away a certain thickness of the buried oxide layer.

7. The ultra-surface heterogeneous integrated silicon-based EUV detector prepared by the method for preparing an ultra-surface heterogeneous integrated silicon-based EUV detector according to claim 1, characterized in that: The detector structure is as follows from top to bottom: TaBO anti-reflection layer, single-layer graphene, Si nano-pillar array, isolation layer, and back Mo / Si reflector.

8. The super-surface heterogeneous integrated silicon-based EUV detector according to claim 7, characterized in that: The reflector adopts a Mo / Si multilayer film structure.

9. The super-surface heterogeneous integrated silicon-based EUV detector according to claim 7, characterized in that: The Si nano-pillar array channel is weakly doped with P-type doping.

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