Display device and electronic device

Abstract

The invention provides a display device and an electronic device. The display device may include: a first pixel; a second pixel; a first data line electrically connected to the first pixel; a second data line electrically connected to the second pixel and electrically insulated from the first data line; a first signal wiring electrically connected to the first data line; a second signal wiring electrically connected to the second data line; and a connection wiring electrically connecting the second data line to the second signal wiring. The connection wiring may include a first portion and a second portion. The second portion may be directly connected to the first portion, may overlap the first pixel, may overlap the first data line, and may be inclined with respect to each of the first data line and the second data line in a plan view of the display device.

Description

[0001] This application is a divisional application of application No. 201910826892.3, entitled “Display Device”, filed with the State Intellectual Property Office of China on September 3, 2019.

[0002] The technical field relates to a display device. Background Art

[0003] The display device may include a pixel circuit, a driver for driving the pixel circuit, and a wiring electrically connecting the driver to the pixel circuit. The pixel circuit may be arranged in a display area of ​​the display device. The driver may be arranged in a non-display area adjacent to the display area. The wiring may extend from the non-display area to the display area. Summary of the invention

[0004] Embodiments may relate to a fan-out structure disposed in a display area of ​​a display device to optimize space utilization of the display device.

[0005] According to some embodiments, a display device includes: a display substrate on which data lines are arranged, the data lines including a first data line arranged in a first area of ​​a display area and a second data line arranged in a second area of ​​the display area; a signal wiring including a first signal wiring connected to the first data line and a second signal wiring connected to the second data line; and a connection wiring connecting the second data line to the second signal wiring. The first data line and the second data line extend in a first direction, the second area is arranged adjacent to the first area in a second direction intersecting the first direction, and the connection wiring has a fan-out structure in the display area.

[0006] The display substrate may include a non-display area surrounding the display area. The non-display area may include a third area disposed adjacent to the first area of ​​the display area in the first direction and a fourth area disposed adjacent to the second area of ​​the display area in the second direction.

[0007] The non-display area may include a bent portion and the signal wiring may be disposed in the bent portion.

[0008] A width of the bent portion in the second direction may be smaller than a width of the display area in the second direction.

[0009] The connection wiring may be connected to the second signal wiring through the first contact hole located in the third region.

[0010] The connection wiring may be connected to the second data line through a second contact hole located in the fourth region.

[0011] The connection wiring may include a first extending portion extending from the non-display area toward the display area in a first direction, and a second extending portion extending from an end of the first extending portion toward the non-display area in an inclined direction between the first and second directions.

[0012] The first signal wiring may be made of the same conductive layer as the second signal wiring.

[0013] The connection wiring may be disposed at a predetermined distance from the first data line along the second direction in a plan view of the display device.

[0014] The connection wiring may overlap the first data line in some regions in the thickness direction.

[0015] The connection wiring may be at least any one of aluminum (Al) and a stacked layer of Ti—Al—Ti.

[0016] The second signal wiring may be connected to the connection wiring through a third signal wiring and the third signal wiring is made of the same conductive layer as the first data line.

[0017] The first organic insulating layer may be provided between the connection wiring and the data line.

[0018] The first organic insulating layer may have a thickness of 15000 Å.

[0019] The first organic insulating layer may be any one of polyacrylic resin and polyimide resin.

[0020] The display device may further include a second organic insulating layer on the conductive layer in which the connection wiring is provided.

[0021] An inorganic insulating layer may be provided between the connection wiring and the data line.

[0022] The data line may be provided on the conductive layer in which the connection wiring is provided.

[0023] The display device may further include a second organic insulating layer on the conductive layer in which the data line is disposed.

[0024] The connection wiring may include at least any one of copper (Cu) and molybdenum (Mo).

[0025] Embodiments may relate to a display device. The display device may include: a first pixel; a second pixel; a first data line electrically connected to the first pixel; a second data line electrically connected to the second pixel and electrically insulated from the first data line; a first signal wiring electrically connected to the first data line; a second signal wiring electrically connected to the second data line; and a connection wiring electrically connecting the second data line to the second signal wiring. The connection wiring may include a first portion and a second portion. The second portion may be directly connected to the first portion, may overlap the first pixel, may overlap the first data line, and may be inclined relative to each of the first data line and the second data line in a plan view of the display device.

[0026] The second portion may form an acute angle with respect to the first portion in a plan view of the display device.

[0027] The edge of the second portion may be directly connected to the edge of the first portion and may extend at an acute angle with respect to the edge of the first portion in a plan view of the display device.

[0028] The display device may include a third pixel. The first portion may overlap the third pixel.

[0029] The connection wiring may be connected to the second signal wiring through the first contact hole. The connection wiring may be connected to the second data line through the second contact hole. A portion of the first data line may be located between the first contact hole and the second contact hole in a plan view of the display device.

[0030] The connection wiring may be connected to the second signal wiring through the first contact hole. The first contact hole may be located outside the display area of ​​the display device in the length direction of the first portion. The first pixel and the second pixel may be located in the display area of ​​the display device.

[0031] The connection wiring may be connected to the second data line through the second contact hole. The second contact hole may be located outside the display area of ​​the display device in the length direction of the second portion.

[0032] The first pixel and the second pixel may be located in a display area of ​​the display device. The non-display area of ​​the display device may be adjacent to the display area of ​​the display device. A boundary between the display area of ​​the display device and the non-display area of ​​the display device may intersect both the first portion and the second portion in a plan view of the display device.

[0033] The material of the first signal wiring may be the same as that of the second signal wiring.

[0034] The first portion of the connection wiring may be parallel to the first data line in a plan view of the display device. The second portion of the connection wiring may cross the first data line in a plan view of the display device.

[0035] The first portion of the connection wiring may overlap the first data line. An edge of the first portion of the connection wiring may be parallel to an edge of the first data line.

[0036] The connection wiring may be formed of at least one of aluminum (Al) and titanium (Ti).

[0037] The second signal wiring may be connected to the connection wiring through the third signal wiring. A material of the third signal wiring may be the same as that of the first data line.

[0038] The display device may include a first organic insulating layer disposed between the connection wiring and each of the first and second data lines.

[0039] The first organic insulating layer may have a thickness of at least 15000Å.

[0040] The first organic insulating layer may be formed of at least one of polyacrylic resin and polyimide resin.

[0041] The display device may include a second organic insulating layer covering the connection wiring.

[0042] The display device may include an inorganic insulating layer disposed between the connection wiring and the first data line.

[0043] The first data line may be provided between the connection wiring and the pixel electrode of the first pixel in a direction perpendicular to a plane of the pixel electrode of the first pixel.

[0044] The display device may include an organic insulating layer covering the first data line.

[0045] The connection wiring may include at least one of copper (Cu) and molybdenum (Mo). BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 is a plan view / layout diagram of a display device according to an embodiment.

[0047] Figure 2 is a schematic partial cross-sectional view of a display device according to an embodiment.

[0048] Figure 3 is a plan view / layout diagram of signal routing extending through a panel bending area according to an embodiment.

[0049] Figure 4 is a plan view / layout view of signal wiring of a display panel according to an embodiment.

[0050] Figure 5 According to the embodiment Figure 4 Magnified view of area A.

[0051] Figure 6According to the embodiment Figure 4 Magnified view of area B.

[0052] Figure 7 According to the embodiment Figure 4 Magnified view of area C.

[0053] Figure 8 According to the embodiment Figure 4 Magnified view of area B.

[0054] Fig. 9 is an equivalent circuit diagram of a pixel of a display device according to an embodiment.

[0055] Fig.10 is a timing diagram of driving signals of the display device according to the embodiment.

[0056] Fig.11 is a plan view of a pixel overlapped with an inclined portion of a connection wiring according to an embodiment.

[0057] Fig.12 According to the embodiment Fig.11 A cross-sectional view taken along line II'.

[0058] Fig.13 is a plan view of a pixel overlapped with a vertical portion of a connection wiring according to an embodiment.

[0059] Fig.14 According to the embodiment Fig.13 A cross-sectional view taken along line II-II'.

[0060] Fig.15 According to the embodiment Fig.11 A cross-sectional view taken along line II'.

[0061] Fig.16 According to the embodiment Fig.11 A cross-sectional view taken along line II'.

[0062] Fig.17 According to the embodiment Fig.11 A cross-sectional view taken along line II'. DETAILED DESCRIPTION

[0063] The exemplary embodiments are described with reference to the accompanying drawings. Actual embodiments are not limited to the exemplary embodiments and may be implemented in various forms.

[0064] Although the terms "first", "second", etc. can be used here to describe various elements, these elements should not be limited to these terms. These terms can be used to distinguish one element from another element. Therefore, without departing from the teachings of one or more embodiments, the first element can be referred to as the second element. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used here to distinguish different classes or groups of elements. For simplicity, the terms "first", "second", etc. can respectively represent "first type (or first group)", "second type (or second group)", etc.

[0065] When a first element is referred to as being "on" a second element, the first element may be directly on the second element or one or more intervening elements may be present between the first and second elements. When a first element is referred to as being "directly on" a second element, no intervening elements are intended to be present between the first and second elements (except for environmental elements such as air).

[0066] For ease of description, spatially relative terms such as "below", "below", "below", "above", "on", etc. may be used here to describe the relationship of one element or feature to another (other) element or feature as shown in the drawings. In addition to the orientation depicted in the drawings, spatially relative terms may include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements described as "below" or "below" other elements or features will then be positioned as "above" the other elements or features. Therefore, the term "below" may include both "above" and "below". The device may be positioned otherwise (rotated 90 degrees or at other orientations) and the spatially relative descriptors used here may be interpreted accordingly.

[0067] The same reference numerals may be used for the same elements. The term "contacting" may mean "directly contacting"; the term "connecting" may mean "electrically connected". Conductive components in the same conductive layer / conductive components of the same conductive layer may include one or more of the same materials and / or be formed from one or more of the same materials by one or more of the same process steps.

[0068] Figure 1 is a plan view / layout diagram of the display device 1 according to the embodiment. Figure 2 is a schematic partial cross-sectional view of the display device 1 according to the embodiment. Figure 3 is a layout diagram of signal wirings SL extending through the panel bending area BD according to an embodiment.

[0069] exist Figure 1 In the plan view of , for ease of description, the up-down direction and the left-right direction are defined. The up-down direction is the vertical direction or the pixel column direction, and the left-right direction is the horizontal direction or the pixel row direction. The directions mentioned in the embodiments may be relative directions and the embodiments are not limited to the mentioned directions.

[0070] Reference Figures 1 to 3 , the display device 1 is a device for displaying moving images or still images. The display device 1 can be used in portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs). The display device 1 can be used in at least one of a television, a notebook computer, a monitor, a billboard, and the Internet of Things. For example, the display device 1 may include an organic light-emitting display, a liquid crystal display, a plasma display, a field emission display, an electrophoretic display, an electrowetting display, a quantum dot light-emitting display, or a micro-light-emitting diode (LED) display. An organic light-emitting display is described as an example of the display device 1, but the embodiment is not limited to an organic light-emitting display.

[0071] The display device 1 may include a display panel 10. The display panel 10 may include a flexible substrate including a flexible polymer material such as polyimide. The display panel 10 may be bent, curved, folded, or rolled.

[0072] The display panel 10 may include a main region MR and a panel bending region BD connected to one side of the main region MR. The display panel 10 may further include a sub-region SR connected to the panel bending region BD and overlapping the main region MR in a direction perpendicular to the image display surface of the display panel 10 after the panel bending region BD has been bent.

[0073] A portion of the display panel 10 including pixels for displaying an image is defined as a display area DA of the display device 1, and a portion of the display panel 10 not including pixels is defined as a non-display area NDA of the display device 1. The display area DA of the display panel 10 is disposed in the main region MR. The remaining portion except the display area DA is the non-display area NDA of the display panel 10. In an embodiment, an edge portion surrounding the display area DA in the main region MR, the entire panel bending area BD, and the entire sub-region SR may be (a portion of) the non-display area NDA. In an embodiment, the panel bending area BD and / or the sub-region SR may include pixels and may be a portion of the display area DA.

[0074] The main region MR may have a shape substantially similar to the planar shape of the display device 1. The main region MR may have a flat surface for displaying an image. In an embodiment, a curved / bent edge of the main region MR may be configured to display one or more images.

[0075] The display area DA of the display panel 10 may be disposed in the center of the main region MR. The display area DA may include a plurality of pixels. Each pixel may include a light-emitting layer and a circuit layer for controlling the amount of light emitted from the light-emitting layer. The circuit layer may include display wiring, display electrodes, and at least one transistor. The light-emitting layer may include an organic light-emitting material. The light-emitting layer may be sealed by an encapsulation layer. The display area DA may have a substantially rectangular shape, for example, a rectangular shape with rounded corners. The display area DA may also have one or more other shapes, such as one or more of other polygonal shapes, circular shapes, and elliptical shapes.

[0076] The display area DA may or may not include the curved or bent edge of the main region MR.

[0077] The non-display area NDA may be located around the display area DA in the main region MR. The non-display area NDA of the main region MR may extend from the outer boundary of the display area DA to the edge of the display panel 10. A signal wiring SL or a driving circuit for transmitting a signal to the display area DA may be provided in the non-display area NDA of the main region MR. The outermost black matrix may be provided in the non-display area NDA of the main region MR.

[0078] The panel bending area BD is connected to the main area MR. For example, the panel bending area BD may be connected to one side of the main area MR. The horizontal width of the panel bending area BD may be smaller than the horizontal width of the main area MR. The panel bending area BD of the display panel 10 may be bent with a curvature in a direction opposite to the display surface. The panel bending area BD may have a constant radius of curvature. The panel bending area BD may also have different radii of curvature in different sections. When the panel bending area BD of the display panel 10 is bent, the surface of the display panel 10 is flipped. That is, the upward-facing surface of the display panel 10 may be made to face outward and then face downward by the panel bending area BD.

[0079] The sub-region SR extends from the panel bending region BD. The sub-region SR may extend parallel to the main region MR after bending is completed. The sub-region SR may overlap the main region MR in the thickness direction of the display panel 10. The sub-region SR may overlap the non-display area NDA on the edge of the main region MR and may also overlap the display area DA of the main region MR.

[0080] The horizontal width of the sub region SR may be equal to the horizontal width of the panel bending region BD.

[0081] The driver chip 20 may be disposed on the sub-region SR of the display panel 10. The driver chip 20 may include an integrated circuit for driving the display panel 10. In an embodiment, the integrated circuit may be a data driver integrated circuit that generates and provides a data signal. The driver chip 20 may be mounted on the display panel 10 and in the sub-region SR. The driver chip 20 may be mounted on a surface of the display panel 10 that is the same surface as the display surface. However, as described above, because the panel bending region BD is bent and turned over, the surface of the display panel 10 on which the driver chip 20 is mounted may be made to face downward in the thickness direction. Therefore, the upper surface of the driver chip 20 may face downward.

[0082] The driving chip 20 may be attached to the display panel 10 through an anisotropic conductive film or through ultrasonic bonding. The horizontal width of the driving chip 20 may be smaller than the horizontal width of the display panel 10. The driving chip 20 may be disposed at the center of the sub-region SR in the horizontal direction and the left and right edges of the driving chip 20 may be spaced apart from the left and right edges of the sub-region SR, respectively.

[0083] A pad (also called "pad") PAD may be provided at an end of the sub region SR of the display panel 10 and the display driving board 30 may be connected to the pad PAD. The display driving board 30 may be a flexible printed circuit board or a film.

[0084] The signal wiring SL may be arranged in the sub-region SR, the panel bending region BD, and the main region MR. The signal wiring SL may extend from the sub-region SR to the main region MR via the panel bending region BD. Some signal wirings SL (e.g., first power wirings and second power wirings) may extend from the end of the sub-region SR to the panel bending region BD without passing through the driver chip 20 and may extend to the main region MR. Other signal wirings SL (e.g., data lines DL) may extend from the end of the sub-region SR to the panel bending region BD via the driver chip 20 and may extend to the main region MR. The signal wiring SL passing through the driver chip 20 may form a fan-out structure that expands wider from the sub-region SR and / or the panel bending region BD toward the main region MR to substantially cover the main region MR that is wider than the driver chip 20. The signal wiring SL that does not pass through the driver chip 20 may extend outside the signal wiring SL that passes through the driver chip 20.

[0085] Because the signal wiring SL passing through the panel bending area BD is bent according to the bending of the display panel 10, the signal wiring SL passing through the panel bending area BD is subjected to bending stress. The bending stress may cause cracking or breakage of the signal wiring SL. To prevent this, the signal wiring SL passing through the panel bending area BD may be made of a more flexible material. The signal wiring SL passing through the panel bending area BD may include a plurality of wiring layers that are electrically connected and vertically contacted. The signal wiring SL passing through the panel bending area BD may have a multi-path structure; even if one of the wiring layers is damaged, the signal can still be transmitted through another wiring layer electrically connected to the wiring layer.

[0086] The contact regions CT1 and CT2 may be disposed adjacent to the panel bending region BD. For example, the first contact region CT1 may be disposed in the sub-region SR and adjacent to the panel bending region BD or at a boundary between the sub-region SR and the panel bending region BD, and the second contact region CT2 may be disposed in the main region MR and adjacent to the panel bending region BD or at a boundary between the panel bending region BD and the main region MR.

[0087] When the signal wiring SL passes through the first contact region CT1 and the second contact region CT2, the signal wiring SL passing through at least a portion of the panel bending region BD may be transferred to a different wiring layer. Figure 3 , Figure 4 and Figure 6 The signal wiring SL may include a first signal wiring SL1 located in the sub-region SR and made of (or located at) a first wiring layer and may include a second signal wiring SL2 located in the panel bending region BD and made of (or located at) a second wiring layer.

[0088] Figure 4 is a plan view / layout diagram of the signal wirings SL of the display panel 10 according to the embodiment. Figure 5 According to the embodiment Figure 4 Magnified view of area A. Figure 6 According to the embodiment Figure 4 Magnified view of area B. Figure 7 According to the embodiment Figure 4 Magnified view of area C.

[0089] Reference Figures 4 to 7 The display device 1 may include data lines DL, connection wirings BR, and signal wirings SL. The data lines DL, connection wirings BR, and signal wirings SL may be arranged symmetrically with respect to a reference axis (not shown) extending in the first direction DR1 and passing through the center of the region of the display device 1 .

[0090] The data lines DL may extend in the first direction DR1 and may be arranged in the second direction DR2 at predetermined intervals. Each of the data lines DL may extend in the first direction DR1 across the display area DA.

[0091] The data line DL may include a first data line DL_A directly connected to the signal wiring SL and may include second data lines DL_B and DL_C connected to the signal wiring SL through a connection wiring BR. The first data line DL_A may be disposed in a region of the display area DA that is consistent with the width of the driving chip 20 in the second direction DR2. The second data lines DL_B and DL_C may be disposed in a region of the display area DA that is outside the driving chip 20 in the second direction DR2. That is, the second data lines DL_B and DL_C may be disposed on the left and right sides of the first data line DL_A.

[0092] The connection wiring BR may electrically connect some of the data lines DL to some of the signal wirings SL. The connection wiring BR may be provided in a layer different from a layer in which the data lines DL are provided and may be insulated from the data lines DL by an insulating layer.

[0093] The connection wiring BR may be disposed in the display area DA in a fan-out structure. The horizontal width of the display panel 10 may be greater than the horizontal width of the driving chip 20. The connection wiring BR may form a fan-out structure that expands wider from the display area DA toward the non-display area NDA to connect to the second data lines DL_B and DL_C.

[0094] A portion of the connection wiring BR may extend in the space between the first data lines DL_A in the first direction DR1 and may be arranged at regular intervals in the second direction DR2. The connection wiring BR may extend more from the left end toward the center relative to the driving chip 20 in the first direction DR1 and may extend more from the right end toward the center relative to the driving chip 20 in the first direction DR1.

[0095] The connection wiring BR located at the center relative to the driving chip 20 may extend obliquely toward the data line DL set on the left side among the second data lines DL_B. The connection wiring BR located on the left side relative to the driving chip 20 may extend obliquely toward the data line DL set on the right side among the second data lines DL_B. The connection wiring BR located at the center relative to the driving chip 20 may extend obliquely toward the data line DL set on the right side among the second data lines DL_C. The connection wiring BR located on the right side relative to the driving chip 20 may extend obliquely toward the data line DL set on the left side among the second data lines DL_C. The connection wiring BR may collectively form an arrow shape in a plan view of the display panel 10.

[0096] The display area DA includes a plurality of pixels electrically connected to the data lines DL. The display area DA may have a substantially rectangular planar shape and / or another shape.

[0097] The display area DA may have four sides, i.e., an upper side, a lower side, a left side, and a right side, and may have four corners disposed between adjacent sides. The upper side and the lower side may be parallel to each other, and the left side and the right side may be parallel to each other. The upper side and the lower side may extend perpendicularly to the left side and the right side, but the angle where the upper side and the lower side meet the left side and the right side may not be a right angle, for example, it may be an oblique angle. The internal angle of each corner may be greater than 90 degrees. Each corner may be in a shape similar to an inclined straight line, but may also have a rounded, curved shape.

[0098] Reference Figure 5 , the corner where the left and lower sides of the display area DA meet may have a rounded, curved shape. The connection wiring BR and the data line DL may be connected to each other outside the display area DA through the contact hole CNT. When the display area DA has a rounded, curved corner, the intervals between directly adjacent contact holes CNT (the connection wiring BR and the data line DL are connected through the contact hole CNT) may be equal in the second direction DR2, but the intervals may gradually increase in the first direction DR1 toward the edge of the display panel 10 (e.g., the left edge of the display panel 10).

[0099] Since the connection wiring BR and the data line DL are connected through the contact hole CNT in the non-display area NDA, an undesired coupling with other conductors may not occur.

[0100] Reference Figure 6 and Figure 7 , the driving chip 20 may be disposed in the sub-region SR and the first signal wirings SL1 electrically connected to the driving chip 20 may extend in the first direction DR1 at equal intervals in the sub-region SR. The first signal wirings SL1 may be located in the same wiring layer as the driving chip 20. The first signal wirings SL1 may include a metal such as copper (Cu), molybdenum (Mo), or an alloy.

[0101] The second signal wirings SL2 may contact some of the first signal wirings SL1 through the contact holes CNT in the first contact region CT1. The second signal wirings SL2 may extend in the first direction DR1 at equal intervals in the panel bending region BD.

[0102] The first data lines DL_A may contact some of the first signal wirings SL1 through the contact holes CNT in the first contact region CT1. The first data lines DL_A may extend from the panel bending region BD to the main region MR along the first direction DR1 at equal intervals.

[0103] The first data line DL_A and the second signal wiring SL2 may be located in the same wiring layer and may include a flexible material such as aluminum (Al) and / or may include a stack structure of titanium-aluminum-titanium (Ti—Al—Ti).

[0104] The connection wiring BR may contact the second signal wiring SL2 through the contact hole CNT in the second contact area CT2 located in the non-display area NDA. A portion of the connection wiring BR may extend in the first direction DR1 in the non-display area NDA and extend to a specific position in the display area DA. The connection wiring BR may be bent leftward and / or downward at a specific position in the display area DA. A portion of the connection wiring BR may extend obliquely from the specific position. The connection wiring BR may be located in a wiring layer different from the wiring layer of the second signal wiring SL2 and may include a flexible material such as aluminum (Al) and / or may include a stacked structure of titanium-aluminum-titanium (Ti-Al-Ti).

[0105] Figure 8 According to the embodiment Figure 4 Magnified view of area B.

[0106] Reference Figure 8 , a portion of the first data line DL_1 may overlap a portion of the connection wiring BR in some portions of the main region MR.

[0107] A portion of the first data line DL_1 may extend from the sub-region SR to the panel bending region BD in parallel with the second signal wiring SL2 and the connection wiring BR. The pitch of each first data line DL_1 may be defined as the sum of the width of the first data line DL_1 and the gap between two directly adjacent data lines. When the pitch of each first data line DL_1 has a small value, a portion of the first data line DL_1 may overlap with a portion of the connection wiring BR at a specific position from the non-display area NDA to the display area DA, and an edge of the portion of the first data line DL_1 is parallel to an edge of the portion of the connection wiring BR.

[0108] The connection wiring BR may be disposed in a layer different from the layer in which the first data line DL_1 is disposed and may be insulated from the first data line DL_1 by an insulating layer. The insulating layer may include an organic insulating material such as a polyacrylic resin or a polyimide resin. The organic insulating layer may have a thickness of at least about 15000Å; therefore, undesired bonding caused by overlapping of the connection wiring BR and the first data line DL_1 may be minimized or prevented.

[0109] The substrate 110 (see Fig.12 ) are electrically connected to the data line DL.

[0110] Fig. 9 is an equivalent circuit diagram of a pixel PX of the display device 1 according to the embodiment.

[0111] Reference Fig. 9 , the display device 1 includes a plurality of pixels PX capable of displaying an image according to an image signal; the display device 1 includes a plurality of signal lines GWn, GIn, EM, GI(n+1), DL, and ELVDD connected to the pixels PX (for ease of description, a signal line and a signal transmitted through the signal line may be represented by the same reference numeral, for example, a first scanning signal line GWn and a scanning signal GWn transmitted through the first scanning signal line GWn). One pixel PX may include a capacitor Cst, at least one light emitting diode ED, and a plurality of transistors T1, T2, T3, T4, T5, T6, and T7 connected to the signal lines GWn, GIn, EM, GI(n+1), DL, and ELVDD. The signal lines GWn, GIn, EM, GI(n+1), DL, and ELVDD may include a plurality of scanning lines GWn, GIn, and GI(n+1), a plurality of control lines EM, a plurality of data lines DL, and a plurality of driving voltage lines ELVDD.

[0112] The scan lines GWn, GIn, and GI(n+1) may transmit scan signals GWn, GIn, and GI(n+1), respectively. The scan signals GWn, GIn, and GI(n+1) may conduct gate-on voltages and gate-off voltages, which may turn on / off transistors T2, T3, T4, and T7 included in each pixel PX.

[0113] The scan lines GWn, GIn, and GI(n+1) connected to one pixel PX may include a first scan line GWn that may transmit a scan signal GWn, a second scan line GIn that may transmit a scan signal GIn having a gate-on voltage at a different time from the first scan line GWn, and a third scan line GI(n+1) that may transmit a scan signal GI(n+1). In the current embodiment, an example in which the second scan line GIn transmits a gate-on voltage at an earlier time than the first scan line GWn will be mainly described. For example, when the scan signal GWn is an nth scan signal Sn (where n is a natural number greater than or equal to 1) among scan signals transmitted during one frame, the scan signal GIn may be a previous scan signal such as the (n-1)th scan signal S(n-1) and the scan signal GI(n+1) may be the nth scan signal Sn. However, the scan signal GI(n+1) may also be a scan signal other than the nth scan signal Sn.

[0114] The control line EM may transmit a control signal, specifically, an emission control signal capable of controlling light emission of the light emitting diode ED included in the pixel PX. The control signal transmitted through the control line EM may conduct a gate-on voltage and a gate-off voltage and may have a waveform different from that of the scan signal transmitted through the scan lines GWn, GIn, and GI(n+1).

[0115] The data line DL may transmit a data signal and the driving voltage line ELVDD may transmit a driving voltage. The data signal may have different voltage levels according to an image signal input to the display device 1 and the driving voltage may have a substantially constant level.

[0116] The transistors T1 to T7 may include a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , and a seventh transistor T7 . In one pixel PX, the first scan line GWn can transmit the scan signal to the second transistor T2 and the third transistor T3, the second scan line GIn can transmit the scan signal GIn to the fourth transistor T4, the third scan line GI(n+1) can transmit the scan signal GI(n+1) to the seventh transistor T7, and the control line EM can transmit the emission control signal EM to the fifth transistor T5 and the sixth transistor T6.

[0117] The gate electrode (or referred to as the driving gate electrode) G1 of the first transistor T1 is connected to the first terminal Cst1 of the capacitor Cst through the driving gate node GN, the source electrode S1 of the first transistor T1 is connected to the driving voltage line ELVDD via the fifth transistor T5, and the drain electrode D1 of the first transistor T1 is electrically connected to the anode of the light emitting diode ED via the sixth transistor T6. The first transistor T1 can receive a data signal from the data line DL and supply a driving current Id to the light emitting diode ED according to a switching operation of the second transistor T2.

[0118] The gate electrode G2 of the second transistor T2 is connected to the first scan line GWn and the source electrode S2 of the second transistor T2 is connected to the data line DL. In addition, the drain electrode D2 of the second transistor T2 is connected to the source electrode S1 of the first transistor T1 and is connected to the driving voltage line ELVDD via the fifth transistor T5. The second transistor T2 can be turned on in response to the scan signal received through the first scan line GWn and transmit the data signal received from the data line DL to the source electrode S1 of the first transistor T1.

[0119] The gate electrode G3 of the third transistor T3 is connected to the first scan line GWn, and the source electrode S3 of the third transistor T3 is connected to the drain electrode D1 of the first transistor T1 and is connected to the anode of the light emitting diode ED via the sixth transistor T6. The drain electrode D3 of the third transistor T3 is connected to the drain electrode D4 of the fourth transistor T4, the first terminal Cst1 of the capacitor Cst, and the gate electrode G1 of the first transistor T1. The third transistor T3 may be turned on in response to a scan signal received through the first scan line GWn and diode-connect the first transistor T1 by connecting the gate electrode G1 and the drain electrode D1 of the first transistor T1.

[0120] The gate electrode G4 of the fourth transistor T4 is connected to the second scan line GIn, the source electrode S4 of the fourth transistor T4 is connected to the initialization voltage terminal (ie, the initialization voltage line) Vint, and the drain electrode D4 of the fourth transistor T4 is connected to the first end Cst1 of the capacitor Cst and the gate electrode G1 of the first transistor T1 via the drain electrode D3 of the third transistor T3. The fourth transistor T4 may be turned on in response to the scan signal GIn received through the second scan line GIn and initialize the voltage of the gate electrode G1 of the first transistor T1 by transmitting the initialization voltage Vint to the gate electrode G1 of the first transistor T1.

[0121] A gate electrode G5 of the fifth transistor T5 is connected to the control line EM, a source electrode S5 of the fifth transistor T5 is connected to the driving voltage line ELVDD, and a drain electrode D5 of the fifth transistor T5 is connected to the source electrode S1 of the first transistor T1 and the drain electrode D2 of the second transistor T2.

[0122] The gate electrode G6 of the sixth transistor T6 is connected to the control line EM, the source electrode S6 of the sixth transistor T6 is connected to the drain electrode D1 of the first transistor T1 and the source electrode S3 of the third transistor T3, and the drain electrode D6 of the sixth transistor T6 is electrically connected to the anode of the light emitting diode ED. The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on in response to the emission control signal EM received through the control line EM. Therefore, the driving voltage can be compensated by the diode-connected first transistor T1 and transmitted to the light emitting diode ED.

[0123] The gate electrode G7 of the seventh transistor T7 is connected to the third scan line GI(n+1), the source electrode S7 of the seventh transistor T7 is connected to the drain electrode D6 of the sixth transistor T6 and the anode of the light emitting diode ED, and the drain electrode D7 of the seventh transistor T7 is connected to the initialization voltage terminal Vint and the source electrode S4 of the fourth transistor T4. Optionally, the gate electrode G7 of the seventh transistor T7 can be connected to the second scan line GIn (refer to Fig.11 ) or a separate control line (not shown).

[0124] The transistors T1 to T7 may be P-channel transistors such as P-channel metal oxide semiconductor (PMOS) transistors. At least one of the transistors T1 to T7 may also be an N-channel transistor.

[0125] As described above, the first terminal Cst1 of the capacitor Cst is connected to the gate electrode G1 of the first transistor T1, and the second terminal Cst2 is connected to the driving voltage line ELVDD. The cathode of the light emitting diode ED may be connected to the common voltage terminal ELVSS for transmitting the common voltage ELVSS and receive the common voltage ELVSS.

[0126] The structure of one pixel PX according to the embodiment is not limited to Fig. 9 The structure shown in FIG. 1 may be variously modified including the number of transistors and the number of capacitors in one pixel PX and the connection relationship.

[0127] Now refer to Fig.10 Together with the above Fig. 9 Here, an example in which the transistors T1 to T7 are P-channel transistors will be described and the operation of the display device 1 during one frame will be described.

[0128] Fig.10 is a timing chart of driving signals of the display device 1 according to the embodiment.

[0129] Reference Fig.10 In one frame, the scan signals S(n-2), S(n-1), Sn, etc. at a low level may be sequentially transmitted to the plurality of first scan lines GWn connected to the plurality of pixels PX.

[0130] During the initialization period, a scan signal GIn at a low level is supplied through the second scan line GIn. The scan signal GIn may be, for example, the (n-1)th scan signal S(n-1). The fourth transistor T4 is turned on in response to the scan signal GIn at a low level. The initialization voltage Vint is connected to the gate electrode G1 of the first transistor T1 through the fourth transistor T4 and the first transistor T1 is initialized by the initialization voltage Vint.

[0131] Next, when a scan signal at a low level is supplied through the first scan line GWn during the data programming and compensation period, the second transistor T2 and the third transistor T3 are turned on in response to the scan signal at a low level. For example, the scan signal may be the nth scan signal Sn. At this time, the first transistor T1 is diode-connected and forward-biased through the turned-on third transistor T3. Then, a compensation voltage DL+Vth (wherein Vth has a negative (-) value) obtained by subtracting a threshold voltage Vth of the first transistor T1 from a data signal supplied by the data line DL is applied to the gate electrode G1 of the first transistor T1. That is, the gate voltage applied to the gate electrode G1 of the first transistor T1 may be the compensation voltage DL+Vth.

[0132] The driving voltage and the compensation voltage DL+Vth may be applied to both ends of the capacitor Cst and charges corresponding to a voltage difference between the both ends may be stored in the capacitor Cst.

[0133] Next, the emission control signal EM supplied from the control line EM changes from a high level to a low level during the emission period. In one frame, the time when the emission control signal EM changes from a high level to a low level may be after the scan signal is transmitted to all the first scan lines GWn. The fifth transistor T5 and the sixth transistor T6 are turned on by the emission control signal EM at a low level during the emission period. Then, a driving current Id corresponding to the difference between the gate voltage of the gate electrode G1 of the first transistor T1 and the driving voltage is generated. The driving current Id is supplied to the light emitting diode ED through the sixth transistor T6. As a result, the current Ied flows through the light emitting diode ED. During the emission period, the gate-source voltage Vgs of the first transistor T1 is maintained at (DL+Vth)-ELVDD by the capacitor Cst. According to the current-voltage relationship of the first transistor T1, the driving current Id may be proportional to the square of the value obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs (DL-ELVDD) 2 Therefore, the driving current Id can be determined without considering the threshold voltage Vth of the first transistor T1.

[0134] During the initialization period, the seventh transistor T7 is turned on in response to the scan signal GI(n+1) at a low level received through the third scan line GI(n+1). The scan signal GI(n+1) may be the nth scan signal Sn. In this case, the seventh transistor T7 may be turned on simultaneously with the second transistor T2 and the third transistor T3. A portion of the drive current Id may flow out as a bypass current Ibp through the turned-on seventh transistor T7.

[0135] Fig.11 is a plan view of a pixel overlapped with an inclined portion of a connection wiring according to an embodiment, Fig.12 According to the embodiment Fig.11 A cross-sectional view taken along line II'. Fig.13 is a plan view of a pixel overlapped with a vertical portion of a connection wiring according to an embodiment, Fig.14 According to the embodiment Fig.13 A cross-sectional view taken along line II-II'.

[0136] The pixels PX included in the display device 1 can display different colors. For example, the pixels PX can include a red pixel capable of displaying red, a green pixel capable of displaying green, and a blue pixel capable of displaying blue. In an embodiment, at least one of the red pixel, the green pixel, and the blue pixel can display different colors. In an embodiment, pixels capable of displaying other colors besides red, green, and blue can be provided.

[0137] Reference Fig. 9 , Fig.11 , Fig.12 , Fig.13 and Fig.14 , the display device 1 may include a first conductive layer GAT1, the first conductive layer GAT1 including a first scan line GWn for transmitting a first scan signal, a second scan line GIn for transmitting a second scan signal, and a control line EM for transmitting an emission control signal. The first conductive layer GAT1 may be located on a surface of the substrate 110, may include the same material as other conductors of the first conductive layer GAT1 and / or may be formed of the same material as other conductors of the first conductive layer GAT1, and may be located on the same layer as other conductors of the first conductive layer GAT1.

[0138] The substrate 110 may include an inorganic or organic insulating material such as glass or plastic and may have one or more different degrees of flexibility.

[0139] Including GWn, GIn and GI(n+1) (in Fig. 9 A plurality of scan lines and control lines EM (shown in FIG. 1 ) may extend substantially along the second direction DR2 in a plan view of the display device 1. The first scan line GWn may be located between the second scan line GIn and the control line EM in a plan view of the display device 1. The third scan line GI(n+1) may transmit a third scan signal GI(n+1) after the second scan signal is transmitted by the second scan line GIn. When the first scan line GWn transmits the (n-2)th scan signal S(n-2), the third scan line GI(n+1) may also transmit the nth scan signal Sn. In an exemplary embodiment, the third scan line GI(n+1) may be omitted (refer to FIG. 1 ). Fig.11 ).

[0140] The display device 1 may further include a second conductive layer GAT2, the second conductive layer GAT2 including a second terminal Cst2 (at Fig. 9 The second conductive layer GAT2 is separated from the first conductive layer GAT1. For example, the second conductive layer GAT2 may be located on the first conductive layer GAT1.

[0141] The second end Cst2 of the capacitor Cst and the initialization voltage line Vint may extend substantially in the second direction DR2 in a plan view of the display device 1. The second end Cst2 of the capacitor Cst may be located between the first scan line GWn and the control line EM in a plan view of the display device 1. The second end Cst2 of the capacitor Cst may be connected to the driving voltage line ELVDD through the contact hole CNT to receive the driving voltage. A storage opening OP may be formed in the second end Cst2 of the capacitor Cst.

[0142] The initialization voltage line Vint may transmit an initialization voltage and may be located below the second scan line GIn in a plan view of the display device 1. However, the location of the initialization voltage line Vint is not limited to this location.

[0143] The display device 1 may further include a third conductive layer SD1 including a data line DL for transmitting a data signal and a driving voltage line ELVDD for transmitting a driving voltage. The third conductive layer SD1 is separated from each of the first conductive layer GAT1 and the second conductive layer GAT2. For example, the third conductive layer SD1 may be located above the second conductive layer GAT2.

[0144] The data line DL and the driving voltage line ELVDD may extend substantially in the first direction DR1 in a plan view of the display device 1 and may cross the scan lines GWn and GIn, the control line EM, the initialization voltage line Vint, and the second end Cst2 of the capacitor Cst.

[0145] Each pixel PX may include transistors T1 to T7 connected to scan lines GWn and GIn, a control line EM, a data line DL, and a driving voltage line ELVDD, a capacitor Cst, and a light emitting diode ED.

[0146] A channel of each of the transistors T1 to T7 in one pixel PX may be formed inside one active pattern ACT and the active pattern ACT may be bent in various shapes. The active pattern ACT may include a semiconductor material such as polysilicon or an oxide semiconductor.

[0147] The active pattern ACT may be located between the substrate 110 and the first conductive layer GAT1 in a cross-sectional view.

[0148] The active pattern ACT includes channel regions A1, A2, A3_1, A3_2, A4_1, A4_2, A5, A6, and A7 and conductive regions that form channels of transistors T1 to T7, respectively. Specifically, the third transistor T3 and the fourth transistor T4 may have a dual-gate structure. In this case, the third transistor T3 may include two channel regions A3_1 and A3_2, and the fourth transistor T4 may include two channel regions A4_1 and A4_2.

[0149] The conductive region of the active pattern ACT is located on both sides of each of the channel regions A1, A2, A3_1, A3_2, A4_1, A4_2, A5, A6, and A7 and has a higher carrier concentration than the channel regions A1, A2, A3_1, A3_2, A4_1, A4_2, A5, A6, and A7. Most of the portion of the active pattern ACT other than the channel regions A1, A2, A3_1, A3_2, A4_1, A4_2, A5, A6, and A7 may be a conductive region. A pair of conductive regions located on both sides of each of the channel regions A1, A2, A3_1, A3_2, A4_1, A4_2, A5, A6, and A7 of the transistors T1 to T7 may be a source region and a drain region of each of the transistors T1 to T7 and may be used as a source electrode and a drain electrode, respectively.

[0150] The first transistor T1 includes a channel region A1 , a source region S1 and a drain region D1 as conductive regions on both sides of the channel region A1 as an active pattern ACT, and a driving gate electrode G1 overlapping the channel region A1 in a plan view of the display device 1 .

[0151] The channel region A1 of the first transistor T1 may be bent at least once. For example, the channel region A1 may have a meander shape or a zigzag shape.

[0152] The source region S1 and the drain region D1 are connected to both sides of the channel region A1 in a plan view of the display device 1 .

[0153] The driving gate electrode G1 may be included in the first conductive layer GAT1 and may be connected to the connection member CM1 through the contact hole CNT and the storage opening OP. The storage opening OP surrounds the contact hole CNT. The connection member CM1 may be included in the third conductive layer SD1 in cross section. The connection member CM1 may extend substantially parallel to the direction in which the data line DL extends and may be disposed in the same layer as the data line DL, however, exemplary embodiments are not limited thereto. The connection member CM1 is connected to the driving gate electrode G1 together with the connection member CM1 in the third conductive layer SD1. Fig. 9 The driving gate node GN shown in the circuit diagram corresponds to.

[0154] The second transistor T2 includes a channel region A2, a source region S2 and a drain region D2 as conductive regions located on both sides of the channel region A2 as active patterns ACT, and a gate electrode G2 overlapping the channel region A2 in a plan view of the display device 1. The gate electrode G2 is a part of the first scan line GWn. In a plan view of the display device 1, the source region S2 is located below the first scan line GWn and is connected to the channel region A2 and is connected to the data line DL through the contact hole CNT. In a plan view of the display device 1, the drain region D2 is located above the first scan line GWn and is connected to the channel region A2 and is connected to the source region S1 of the first transistor T1.

[0155] The third transistor T3 may be composed of two parts to prevent leakage current. That is, the third transistor T3 may include a lower third transistor T3_1 and an upper third transistor T3_2 that are adjacent to and connected to each other.

[0156] The lower third transistor T3_1 includes a channel region A3_1 overlapping the first scan line GWn in a plan view of the display device 1, a source region S3_1 and a drain region D3_1 as conductive regions located on both sides of the channel region A3_1 as active patterns ACT, and a gate electrode G3_1 overlapping the channel region A3_1. The gate electrode G3_1 may be a portion of a protrusion of the first scan line GWn. The drain region D3_1 is located below the first scan line GWn in a plan view of the display device 1 and is connected to the connection member CM1 through a contact hole CNT.

[0157] The upper third transistor T3_2 includes a channel region A3_2 overlapping the first scan line GWn in a plan view of the display device 1, a source region S3_2 and a drain region D3_2 as conductive regions located on both sides of the channel region A3_2 as active patterns ACT, and a gate electrode G3_2 overlapping the channel region A3_2. The gate electrode G3_2 is a part of the first scan line GWn. The source region S3_2 of the upper third transistor T3_2 is connected to the drain region D1 of the first transistor T1 and the drain region D3_2 is connected to the source region S3_1 of the lower third transistor T3_1.

[0158] The fourth transistor T4 may also be composed of two parts to prevent leakage current. That is, the fourth transistor T4 may include a left fourth transistor T4_1 and a right fourth transistor T4_2 that are adjacent to and connected to each other.

[0159] The left fourth transistor T4_1 includes a channel region A4_1 overlapping the second scan line GIn in a plan view of the display device 1, a source region S4_1 and a drain region D4_1 as conductive regions located on both sides of the channel region A4_1 as an active pattern ACT, and a gate electrode G4_1 overlapping the channel region A4_1. The gate electrode G4_1 is a part of the second scan line GIn. The drain region D4_1 is located above the second scan line GIn in a plan view of the display device 1 and is connected to the drain region D3_1 of the lower third transistor T3_1.

[0160] The right fourth transistor T4_2 includes a channel region A4_2 overlapping the second scan line GIn in a plan view of the display device 1, a source region S4_2 and a drain region D4_2 as conductive regions on both sides of the channel region A4_2 as active patterns ACT, and a gate electrode G4_2 overlapping the channel region A4_2. The gate electrode G4_2 is a part of the second scan line GIn. The drain region D4_2 may be connected to the source region S4_1 of the left fourth transistor T4_1 and the source region S4_2 may contact the connection member CM2 through the contact hole CNT.

[0161] The connection member CM2 may be included in the third conductive layer SD1 in a cross section. The connection member CM2 may contact the initialization voltage line Vint through the contact hole CNT.

[0162] The fifth transistor T5 includes a channel region A5, a source region S5 and a drain region D5 as conductive regions located on both sides of the channel region A5 as an active pattern ACT, and a gate electrode G5 overlapping the channel region A5. The gate electrode G5 is a part of the control line EM. The source region S5 is located above the control line EM in a plan view of the display device 1, is connected to the channel region A5, and can contact the driving voltage line ELVDD through the contact hole CNT. The drain region D5 is located below the control line EM in a plan view of the display device 1, is connected to the channel region A5, and is connected to the source region S1 of the first transistor T1.

[0163] The sixth transistor T6 includes a channel region A6, a source region S6 and a drain region D6 as conductive regions on both sides of the channel region A6 as an active pattern ACT, and a gate electrode G6 overlapping the channel region A6. The gate electrode G6 is a part of the control line EM. The source region S6 is located below the control line EM in a plan view of the display device 1, connected to the channel region A6 and connected to the drain region D1 of the first transistor T1. The drain region D6 is located above the control line EM in a plan view of the display device 1, connected to the channel region A6 and can contact the anode ED_anode of the light emitting diode ED through the contact hole CNT. The anode ED_anode may be included in the third conductive layer SD1 in the cross section.

[0164] The seventh transistor T7 includes a channel region A7, a source region S7 and a drain region D7 as conductive regions located on both sides of the channel region A7 as an active pattern ACT, and a gate electrode G7 overlapping the channel region A7. The gate electrode G7 is a part of the second scan line GIn. The source region S7 is located below the second scan line GIn in a plan view of the display device 1, is connected to the channel region A7 and is connected to the drain region D6 of the sixth transistor T6. The drain region D7 is located above the second scan line GIn in a plan view of the display device 1 and contacts the connection member CM2 through the contact hole CNT to receive an initialization voltage.

[0165] The capacitor Cst may include a driving gate electrode G1 (Cst1) and a second end Cst2 of the capacitor Cst as two terminals that overlap each other in a plan view of the display device 1. The capacitor Cst may maintain a voltage difference corresponding to a difference between the second end Cst2 of the capacitor Cst to which the driving voltage is applied and the voltage of the driving gate electrode G1. The second end Cst2 of the capacitor Cst may have an area larger than the driving gate electrode G1 in a plan view of the display device 1 and cover the entire area of ​​the driving gate electrode G1.

[0166] The second conductive layer GAT2 may further include a shielding pattern CP overlapping the data line DL. The shielding pattern CP may contact the driving voltage line ELVDD through the contact hole CNT to receive the driving voltage. The shielding pattern CP may shield the space between the driving gate node GN and the data line DL to prevent a voltage change of the driving gate node GN caused by a change in the data signal. The shielding pattern CP may be omitted.

[0167] The connection wiring BR may include portions BR1_A and BR1_B overlapping the pixel PX and extending obliquely from the upper right end to the lower left end in the pixel PX. The connection wiring BR may include a connection wiring portion BR2 overlapping another pixel PX and extending straightly from the lower end to the upper end in the pixel PX.

[0168] The obliquely extending connection wiring portion BR1_A may extend from the drain region D3_2 of the third transistor T3_2 to a point between the second scan line GIn and the initialization voltage line Vint of the corresponding pixel PX. Another obliquely extending connection wiring portion BR1_B may extend from the drain region D6 of the sixth transistor T6 to a point between the control line EM and the first scan line GWn of the corresponding pixel PX. The straightly extending connection wiring portion BR2 may overlap the driving voltage line ELVDD in the thickness direction of the pixel electrode PE.

[0169] Reference Fig.12 and Fig.14 , the buffer layer 120 may be located on the substrate 110. The buffer layer 120 prevents impurities from being introduced from the substrate 110 into a layer disposed on the buffer layer 120 (specifically, the active pattern ACT), thereby improving the characteristics of the active pattern ACT and relieving stress. The buffer layer 120 may include a material such as silicon nitride (SiN x ) or silicon oxide (SiO x ) of inorganic insulating material and / or organic insulating material. At least a portion of the buffer layer 120 may be omitted.

[0170] The active pattern ACT may be located on the buffer layer 120. According to an embodiment, the active pattern ACT may include a channel region A4_1, a source region S4_1, and a drain region D4_1 of the left fourth transistor T4_1 and a drain region D3 of the third transistor T3.

[0171] The first insulating layer 130 (GI) may be located on the active pattern ACT. The thickness of the first insulating layer 130 (GI) may be at least about 1500 Å. The first conductive layer GAT1 may be located on the first insulating layer 130 (GI). The first conductive layer GAT1 may include a gate electrode G4_1 of the left fourth transistor T4_1. The first conductive layer GAT1 may include a metal such as copper (Cu), molybdenum (Mo), or an alloy.

[0172] The second insulating layer 140 (ILD1) may be disposed on the first conductive layer GAT1 and the first insulating layer 130 (GI). The second conductive layer GAT2 may be located on the second insulating layer 140 (ILD1). The second conductive layer GAT2 may include a shielding pattern CP. The second conductive layer GAT2 may include a metal such as copper (Cu), molybdenum (Mo), or an alloy.

[0173] The third insulating layer 150 (ILD2) may be disposed on the second conductive layer GAT2 and the second insulating layer 140 (ILD1). At least one of the first insulating layer 130 (GI), the second insulating layer 140 (ILD1), and the third insulating layer 150 (ILD2) may include a silicon nitride (SiN x ) or silicon oxide (SiOx ) of inorganic insulating materials and / or organic insulating materials.

[0174] The third conductive layer SD1 may be located on the third insulating layer 150 (ILD2). The third conductive layer SD1 may include a driving voltage line ELVDD and a connection member CM1. The driving voltage line ELVDD may contact the shielding pattern CP through a contact hole CNT formed in the third insulating layer 150 (ILD2). The third conductive layer SD1 may include a flexible material such as aluminum (Al) or a stacked layer of Ti / Al / Ti.

[0175] The fourth insulating layer 160 (VIA1) may be disposed on the third conductive layer SD1 and the third insulating layer 150 (ILD2). The fourth insulating layer 160 (VIA1) may include an organic insulating material such as polyacrylic resin or polyimide resin. The upper surface of the fourth insulating layer 160 (VIA1) may be substantially flat. The fourth insulating layer 160 (VIA1) may also include a silicon nitride (SiN x ) or silicon oxide (SiO x ) of inorganic insulating material. Therefore, the size of the contact hole CNT can be reduced.

[0176] The fourth conductive layer SD2 may be located on the fourth insulating layer 160 (VIA1). The fourth conductive layer SD2 may include a connection wiring BR including portions BR1_A, BR1_B, and BR2. The fourth conductive layer SD2 may include a flexible material such as aluminum (Al) and / or may include a stack structure of titanium-aluminum-titanium (Ti-Al-Ti).

[0177] The fifth insulating layer 170 (VIA2) is on the fourth conductive layer SD2 and the fourth insulating layer 160 (VIA1). The fifth insulating layer 170 (VIA2) may include an organic insulating material such as polyacrylic resin or polyimide resin and an upper surface of the fifth insulating layer 170 (VIA2) may be substantially flat.

[0178] The fifth conductive layer may be located on the fifth insulating layer 170 (VIA2). The pixel defining layer HPDL may be located on the fifth insulating layer 170 (VIA2) and the fifth conductive layer.

[0179] Although not shown, the pixel defining layer HPDL may have an opening exposing the pixel electrode PE. The light emitting layer may be located on the pixel electrode PE. The light emitting layer may be located in the opening. The light emitting layer may include an organic light emitting material or an inorganic light emitting material. The common electrode may be located on the light emitting layer. The common electrode may also be formed on the pixel defining layer HPDL and extend over a plurality of pixels PX. The corresponding portions of the pixel electrode PE, the light emitting layer, and the common electrode may form a light emitting diode ED. A sealing layer for protecting the light emitting diode ED may be located on the common electrode. The sealing layer may include inorganic layers and organic layers stacked alternately.

[0180] Fig.15 According to the embodiment Fig.11 A cross-sectional view taken along line II'. Fig.15 Some of the structures shown in Fig.12 Some structures shown in are the same or similar.

[0181] Reference Fig.15 , the pixel structure is different from Fig.12 The pixel structure of FIG. 1 is different in that the connection wiring portion BR1_A is located on the third insulating layer 150 (ILD2) and the driving voltage line ELVDD and the connection member CM1 are located on the sixth insulating layer 160_1 (ILD3).

[0182] The sixth conductive layer GAT3 may be located on the third insulating layer 150 (ILD2). The sixth conductive layer GAT3 may include a connection wiring BR including portions BR1_A, BR1_B, and BR2. The sixth conductive layer GAT3 may include a metal such as copper (Cu), molybdenum (Mo), or an alloy.

[0183] The sixth insulating layer 160_1 (ILD3) may be located on the sixth conductive layer GAT3 and the third insulating layer 150 (ILD2). At least one of the third insulating layer 150 (ILD2) and the sixth insulating layer 160_1 (ILD3) may include a material such as silicon nitride (SiN x ) or silicon oxide (SiO x ) of inorganic insulating materials and / or organic insulating materials.

[0184] The seventh conductive layer SD1_1 may be located on the sixth insulating layer 160_1 (ILD3). The seventh conductive layer SD1_1 may include a driving voltage line ELVDD and a connection member CM1. The driving voltage line ELVDD may contact the shielding pattern CP through a contact hole CNT formed in the third insulating layer 150 (ILD2) and the sixth insulating layer 160_1 (ILD3). The seventh conductive layer SD1_1 may include a flexible material such as aluminum (Al) or a stacked layer of Ti / Al / Ti.

[0185] The seventh insulating layer 170_1 (VIA1) is on the seventh conductive layer SD1_1 and the sixth insulating layer 160_1 (ILD3). The seventh insulating layer 170_1 (VIA1) may include an organic insulating material such as polyacrylic resin or polyimide resin and an upper surface of the seventh insulating layer 170_1 (VIA1) may be substantially flat.

[0186] Fig.16 According to the embodiment Fig.11 A cross-sectional view taken along line II'. Fig.16 Some of the structures shown in Fig.15 and / or Fig.12 Some structures shown in are the same or similar.

[0187] Reference Fig.16 , the pixel structure is different from Fig.15 The pixel structure is different in that the connection member CM1 is located on the seventh insulating layer 170_1 (VIA1) and an eighth insulating layer 180 (VIA2) is provided.

[0188] The seventh conductive layer SD1_1 may be located on the sixth insulating layer 160_1 (ILD3). The seventh conductive layer SD1_1 may include a driving voltage line ELVDD. The driving voltage line ELVDD may contact the shielding pattern CP through a contact hole CNT formed in the third insulating layer 150 (ILD2) and the sixth insulating layer 160_1 (ILD3). The seventh conductive layer SD1_1 may include a flexible material such as aluminum (Al) or a stacked layer of Ti / Al / Ti.

[0189] The seventh insulating layer 170_1 (VIA1) may be on the seventh conductive layer SD1_1 and the sixth insulating layer 160_1 (ILD3). The seventh insulating layer 170_1 (VIA1) may include an organic insulating material such as polyacrylic resin or polyimide resin and an upper surface of the seventh insulating layer 170_1 (VIA1) may be substantially flat.

[0190] The eighth conductive layer SD2_1 may be located on the seventh insulating layer 170_1 (VIA1). The eighth conductive layer SD2_1 may include a connection member CM1. The eighth insulating layer 180 (VIA2) may be located on the eighth conductive layer SD2_1 and the seventh insulating layer 170_1 (VIA1). The eighth insulating layer 180 (VIA2) may include an organic insulating material such as polyacrylic resin or polyimide resin and an upper surface of the eighth insulating layer 180 (VIA2) may be substantially flat.

[0191] Fig.17 According to the embodiment Fig.11 A cross-sectional view taken along line II'. Fig.17Some of the structures shown in Fig.16 , Fig.15 and / or Fig.12 Some structures shown in are the same or similar.

[0192] Reference Fig.17 , the pixel structure is different from Fig.15 The pixel structure is different in that the connection member CM1 and the connection wiring portion BR1_A are shielded by the widened driving voltage line ELVDD_1.

[0193] In the thickness direction of the pixel electrode PE, Fig.15 The driving voltage line ELVDD shown in FIG. 1 may overlap with a region extending from the gate electrode G4_1 of the left fourth transistor T4_1 to the drain region D4_1. The driving voltage line ELVDD_1 may be wider in a plan view of the display device 1. In the thickness direction, the driving voltage line ELVDD_1 may overlap with a region extending from the gate electrode G4_1 of the left fourth transistor T4_1 to the connection wiring portion BR1_A partially overlapping with the drain region D3 of the third transistor T3 in the thickness direction. Therefore, undesired coupling between the connection member CM1 and the connection wiring portion BR1_A may be minimized.

[0194] Many variations and modifications may be made to the described embodiments without departing from the scope of the claims.

Claims

1. A display device, comprising: a first pixel, a second pixel, and a third pixel, wherein each of the first pixel and the second pixel comprises a transistor and a light emitting diode in a display area of ​​the display device; a first signal line electrically connected to the first pixel and extending in a first direction; a second signal line electrically connected to the second pixel, spaced apart from the first signal line and extending in the first direction; a first wiring electrically connected to the first signal line; a second wiring electrically connected to the second signal line and extending in the first direction; as well as connecting wiring to electrically connect the second signal line to the second wiring, The connection wiring includes a first part and a second part. wherein the second portion of the connection wiring is directly connected to the first portion of the connection wiring and overlaps the first signal line, wherein the second portion of the connection wiring extends in a second direction different from the first direction, wherein the first portion of the connection wiring overlaps the third pixel, and The first portion of the connection wiring overlaps with a gate electrode of a transistor of the first pixel.

2. The display device according to claim 1, in, The first portion of the connection wiring overlaps the light emitting diode of the first pixel.

3. The display device according to claim 1, in, The first portion of the connection wiring overlaps an active layer of the first pixel.

4. The display device according to claim 1, in, The first portion of the connection wiring extends in a third direction different from the second direction, and The second portion of the connection wiring is directly connected to the first portion of the connection wiring in the display area of ​​the display device.

5. The display device according to claim 1, wherein: The first signal line includes a first edge extending in the first direction and a second edge opposite to the first edge, and Here, in a plan view of the display device, the second portion of the connection wiring intersects the first edge of the first signal line and the second edge of the first signal line.

6. The display device according to claim 1, wherein: The second portion of the connection wiring includes an overlapping portion overlapping the first signal line, and Wherein, the overlapping portion of the second portion of the connection wiring is arranged in the display area of ​​the display device.

7. The display device according to claim 1, further comprising: a driving voltage line electrically connected to the first pixel and extending in the first direction, The driving voltage line overlaps with an active layer of a transistor of the first pixel.

8. The display device according to claim 7, in, The second portion of the connection wiring overlaps the driving voltage line in the display area of ​​the display device.

9. The display device according to claim 7, in, The first portion of the connection wiring overlaps the driving voltage line in the display area of ​​the display device.

10. The display device according to claim 1, wherein: The first wiring and the second wiring are made of the same material.

11. The display device according to claim 1, wherein: The first portion of the connection wiring is parallel to the first signal line in a plan view of the display device, and wherein the second portion of the connection wiring crosses the first signal line in a plan view of the display device. 12 . The display device according to claim 1 , further comprising an insulating layer provided between the second portion of the connection wiring and each of the first signal line and the second signal line.

13. The display device according to claim 1, further comprising a pixel defining layer including an opening, in, The opening of the pixel defining layer overlaps the light emitting diode of the first pixel, and The first portion of the connection wiring overlaps the opening of the pixel defining layer.

14. The display device according to claim 1, further comprising a first control line electrically connected to the third pixel and extending in a direction different from the first direction; in, The first control line transmits a first emission control signal to the third pixel, and The first portion of the connection wiring overlaps with the first control line.

15. The display device according to claim 14, further comprising a second control line electrically connected to the first pixel and extending in the direction different from the first direction; in, The second control line transmits a second emission control signal to the first pixel, and The first portion of the connection wiring overlaps with the second control line.

16. The display device according to claim 1, in, The second portion of the connection wiring overlaps the light emitting diode of the second pixel.

17. The display device according to claim 1, wherein: The third pixel includes a transistor, and The first portion of the connection wiring overlaps a gate electrode of a transistor of the third pixel.

18. The display device according to claim 1, wherein: The second portion of the connection wiring overlaps an active layer of a transistor of the second pixel.

19. A display device, comprising: a first pixel and a second pixel, each of which includes a transistor and a light emitting diode in a display area of ​​the display device; a first signal line electrically connected to the first pixel and extending in a first direction; a second signal line electrically connected to the second pixel, spaced apart from the first signal line and extending in the first direction; a first wiring electrically connected to the first signal line; a second wiring electrically connected to the second signal line and extending in the first direction; as well as connecting wiring to electrically connect the second signal line to the second wiring, The connection wiring includes a first part and a second part. wherein the second portion of the connection wiring is directly connected to the first portion of the connection wiring and overlaps the first signal line, wherein the second portion of the connection wiring extends in a second direction different from the first direction, and The first portion of the connection wiring overlaps with an active layer of a transistor of the first pixel.

20. The display device according to claim 19, in, The first portion of the connection wiring overlaps the light emitting diode of the first pixel.

21. The display device according to claim 19, in, The first portion of the connection wiring extends in a third direction different from the second direction, and The second portion of the connection wiring is directly connected to the first portion of the connection wiring in the display area of ​​the display device.

22. The display device according to claim 19, wherein: The first signal line includes a first edge extending in the first direction and a second edge opposite to the first edge, and Here, in a plan view of the display device, the second portion of the connection wiring intersects the first edge of the first signal line and the second edge of the first signal line.

23. The display device according to claim 19, wherein: The second portion of the connection wiring includes an overlapping portion overlapping the first signal line, and Wherein, the overlapping portion of the second portion of the connection wiring is arranged in a display area of ​​the display device.

24. The display device according to claim 19, further comprising: a driving voltage line electrically connected to the first pixel and extending in the first direction, The driving voltage line overlaps with the active layer of the transistor of the first pixel.

25. The display device according to claim 24, in, The second portion of the connection wiring overlaps the driving voltage line in the display area of ​​the display device.

26. The display device according to claim 24, in, The first portion of the connection wiring overlaps the driving voltage line in the display area of ​​the display device.

27. The display device according to claim 19, wherein: The first wiring and the second wiring are made of the same material.

28. The display device according to claim 19, wherein: In a plan view of the display device, the first portion of the connection wiring is parallel to the first signal line, and wherein in a plan view of the display device, the second portion of the connection wiring crosses the first signal line.

29. The display device according to claim 19, further comprising a pixel defining layer including an opening, in, The opening of the pixel defining layer overlaps the light emitting diode of the first pixel, and The first portion of the connection wiring overlaps the opening of the pixel defining layer.

30. The display device according to claim 19, further comprising a first control line electrically connected to a third pixel different from the first pixel and the second pixel, in, The first control line extends in a direction different from the first direction; wherein the first control line transmits a first emission control signal to the third pixel, and The first portion of the connection wiring overlaps with the first control line.

31. The display device according to claim 30, further comprising a second control line electrically connected to the first pixel and extending in the direction different from the first direction; in, The second control line transmits a second emission control signal to the first pixel, and The first portion of the connection wiring overlaps with the second control line.

32. The display device according to claim 19, in, The second portion of the connection wiring overlaps the light emitting diode of the second pixel.

33. An electronic device, comprising: Display device; Wherein, the display device comprises: a first pixel, a second pixel, and a third pixel, wherein each of the first pixel and the second pixel comprises a transistor and a light emitting diode in a display area of ​​the display device; a first signal line electrically connected to the first pixel and extending in a first direction; a second signal line electrically connected to the second pixel, spaced apart from the first signal line and extending in the first direction; a first wiring electrically connected to the first signal line; a second wiring electrically connected to the second signal line and extending in the first direction; and connecting wiring to electrically connect the second signal line to the second wiring, The connection wiring includes a first part and a second part. wherein the second portion of the connection wiring is directly connected to the first portion of the connection wiring and overlaps the first signal line, wherein the second portion of the connection wiring extends in a second direction different from the first direction, wherein the first portion of the connection wiring overlaps the third pixel, and The first portion of the connection wiring overlaps with a gate electrode of a transistor of the first pixel.

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