AC voltage measuring system

Abstract

An AC voltage measuring system belongs to the technical field of electric power detection. The objective of the invention is to solve the problems of small measurement range and low measurement precision of AC voltage. The system comprises a signal conditioning network, a signal acquisition network and a master control network, the signal acquisition network comprises an ADC acquisition circuit and a time base trigger circuit, and the master control network comprises an STM32 and an FPGA; the signal conditioning network is used for processing the input to-be-tested signal, and the processed to-be-tested signal is sent to the signal acquisition network; the time base trigger circuit converts the processed signal to be detected into a square wave signal and inputs the square wave signal to the FPGA; the FPGA calculates the period of the square wave signal and calculates a sampling interval according to the period of the square wave signal; the ADC acquisition circuit performs data acquisition according to the sampling interval, sends the acquired data to the FPGA, and transmits the acquired data to the STM32 by using the FPGA; and the STM32 calculates the effective value of the AC voltage according to the collected data. The method can be applied to AC voltage measurement.

Description

Technical Field

[0001] The invention belongs to the technical field of electric power detection, and in particular relates to an AC voltage measurement system. Background Art

[0002] With the continuous progress of modern society, the demand for high-precision AC voltage measurement continues to increase in many fields such as power systems, industrial automation, and electronic equipment detection. In the power system, measuring the voltage in the AC circuit can be used to monitor the voltage conditions of key parts such as transmission lines and substations to ensure the stability and safety of power supply; in the field of industrial automation, real-time monitoring of the AC voltage in production equipment can ensure the normal operation of the equipment; in the field of electronic equipment detection, measuring the voltage in the AC circuit can be used to detect whether the power supply voltage of electronic products meets the standards and improve product quality. Moreover, these fields have their own unique requirements for the range and accuracy of AC voltage measurement. However, the measurement range and measurement accuracy of the existing AC voltage measurement system are relatively limited, and it is an urgent need to propose a new AC voltage measurement system. Summary of the invention

[0003] The purpose of the present invention is to improve the measurement range and measurement accuracy of AC voltage, and to provide an AC voltage measurement system.

[0004] The technical solution adopted by the present invention to solve the above technical problems is: an AC voltage measurement system, the system includes a signal conditioning network, a signal acquisition network and a main control network, the signal acquisition network includes an ADC acquisition circuit and a time base trigger circuit, and the main control network includes an STM32 and an FPGA; wherein:

[0005] The signal conditioning network is used to process the input signal to be tested and send the processed signal to be tested to the signal acquisition network;

[0006] The time base trigger circuit is used to convert the processed signal to be tested into a square wave signal, and input the square wave signal to the FPGA;

[0007] The FPGA is used to calculate the period of the square wave signal, and calculate the sampling interval according to the period of the square wave signal;

[0008] The ADC acquisition circuit is used to collect data according to the sampling interval, and send the collected data to the FPGA, and use the FPGA to pass the collected data to the STM32;

[0009] The STM32 is used to calculate the effective value of the AC voltage according to the collected data.

[0010] Furthermore, the time base trigger circuit converts the processed signal to be tested into a square wave signal through hysteresis comparison.

[0011] Furthermore, the FPGA communicates with the STM32 via a FSMC bus.

[0012] Furthermore, the STM32 is also used to send a data acquisition end signal to the FPGA.

[0013] Furthermore, the system also includes a step signal correction network, which is used to output a step signal and a DC signal according to the effective value of the AC voltage, and use the step signal and the DC signal to correct the system.

[0014] Furthermore, the signal conditioning network is specifically:

[0015] The input end of the JFET pair is the input end of the signal conditioning network, the output end of the JFET pair is connected to the input end of the secondary amplifier, the output end of the secondary amplifier is connected to the input end of the RCVD circuit, the output end of the DAC is connected to the input end of the RCVD circuit, the output end of the RCVD circuit is connected to the differential input end of the JFET pair, and the bias current source of the JFET pair is a V / I conversion constant current source circuit.

[0016] Furthermore, the sampling interval Δt is:

[0017] Δt=T_one / 2 M

[0018] Among them, T_one is the period of the square wave signal, 2 M Indicates the number of sampling points in each cycle.

[0019] Furthermore, the ADC acquisition circuit is used to collect data according to the sampling interval, and the number of cycles collected is 2 N , then the sampling point interval ΔC between adjacent signal cycles is:

[0020] ΔC=Δt / 2 N .

[0022] The beneficial effects of the present invention are:

[0023] The method proposed in the present invention can greatly improve the gain stability of the signal conditioning circuit under wide frequency band, reduce the demand for ADC sampling rate by repeated signal sampling and signal reconstruction, and improve the actual resolution and sampling accuracy. The effective value range of the measured signal can be 10mV to 1000V, the frequency range is 10Hz to 1MHz, and the maximum uncertainty of the basic range can reach 0.03%, which improves the measurement range and measurement accuracy of AC voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1A framework diagram of an AC voltage measurement system of the present invention;

[0025] Figure 2 Design diagrams for signal conditioning network pathways;

[0026] Figure 3 It is a structural diagram of a high-stable gain voltage divider module based on an improved resistor-capacitor voltage divider network (RCVD);

[0027] Figure 4 It is a structural schematic diagram of a high stable gain programmable amplifier module under wide frequency band;

[0028] Figure 5 Schematic diagram of the equivalent sampling method based on uniform phase sampling. DETAILED DESCRIPTION

[0029] Specific implementation method 1: Combination Figure 1 The AC voltage measurement system described in this embodiment includes a signal conditioning network, a signal acquisition network and a main control network, wherein the signal acquisition network includes an ADC acquisition circuit and a time base trigger circuit, and the main control network includes an STM32 and an FPGA; wherein:

[0030] The signal conditioning network is used to process the input signal to be tested and send the processed signal to be tested to the signal acquisition network;

[0031] The time base trigger circuit is used to convert the processed signal to be tested into a square wave signal that meets the input range of the FPGA, and input the square wave signal to the FPGA;

[0032] The FPGA is used to calculate the period of the square wave signal, and calculate the sampling interval according to the period of the square wave signal;

[0033] The ADC acquisition circuit is used to collect data according to the sampling interval, and send the collected data to the FPGA, and use the FPGA to pass the collected data to the STM32;

[0034] The STM32 is used to calculate the effective value of the AC voltage according to the collected data.

[0035] Specific implementation method 2: This implementation method is different from the specific implementation method 1 in that: the time base trigger circuit converts the processed signal to be tested into a square wave signal through hysteresis comparison.

[0036] The other steps and parameters are the same as those in the first embodiment.

[0037] Specific implementation method three: This implementation method is different from specific implementation method one or two in that: the FPGA and STM32 communicate through the FSMC bus.

[0038] The other steps and parameters are the same as those in the first or second embodiment.

[0039] Specific implementation method 4: This implementation method is different from any one of specific implementation methods 1 to 3 in that: after completing the predetermined sampling points, the STM32 is also used to send a data acquisition end signal to the FPGA.

[0040] The other steps and parameters are the same as those in Specific Embodiments 1 to 3.

[0041] Specific implementation method five: This implementation method is different from any one of specific implementation methods one to four in that: the system also includes a step signal correction network, which is used to output a step signal and a DC signal according to the effective value of the AC voltage, and use the step signal and the DC signal to correct the system.

[0042] The other steps and parameters are the same as those in Specific Embodiments 1 to 4.

[0043] Specific implementation method six: Combination Figure 2 and Figure 3 The present embodiment is described below. The present embodiment is different from the first to fifth embodiments in that the signal conditioning network is specifically:

[0044] The input end of the JFET pair is the input end of the signal conditioning network, the output end of the JFET pair is connected to the input end of the secondary amplifier, the output end of the secondary amplifier is connected to the input end of the RCVD circuit, the output end of the DAC is connected to the input end of the RCVD circuit, the output end of the RCVD circuit is connected to the differential input end of the JFET pair, and the bias current source of the JFET pair is a V / I conversion constant current source circuit.

[0045] The other steps and parameters are the same as those in Specific Implementation Methods 1 to 5.

[0046] In order to achieve the measurement of AC signals in a wide range of 10mV to 1000V, the present invention adjusts any amplitude signal in a wide range to a specified signal range, such as 0 to 2V, by setting a signal conditioning network.

[0047] The signal conditioning network includes a voltage divider module and an amplifier module:

[0048] 1. High-stable gain voltage divider module based on improved resistance-capacitance voltage divider (RCVD) under wide bandwidth

[0049] like Figure 3As shown, the parallel connection of resistor R1 and capacitor C1 constitutes the high voltage bridge arm of the RCVD network, resistors R2 and R3 are connected in series and in parallel with capacitor C2 to constitute the low voltage bridge arm of the RCVD network, R3 is a current limiting resistor, and SW1-SW3 are channel selection switches. The present invention proposes the idea of ​​using DAC to change the equivalent resistance of the low voltage bridge arm to achieve a constant voltage division ratio under a wide frequency band. The implementation method is to feed back the output voltage after voltage division to the U2 digital-to-analog converter through the voltage follower formed by U1 and use it as its reference voltage Vref+ terminal, and the Vref- terminal of U2 is grounded. By adjusting the digital value α of U2, the output V feedback And fed back to the low voltage bridge arm of RCVD through resistor R4, so as to adjust the equivalent resistance. feedback The output relationship is as follows:

[0050] V feedback =α(V ref+ -V ref- )=αV out

[0051] At this time, the equivalent resistance R2′ of the low-voltage bridge arm can be equivalent to:

[0052]

[0053] Therefore, the equivalent resistance of the low-voltage bridge arm can be adjusted by continuously adjusting the digital value of input U2 to achieve consistent gain over a wide bandwidth.

[0054] Figure 3 SW1-SW3 in the figure is used as a channel selection switch. It uses three JFETs to build a "T"-shaped structure to reduce signal leakage when the switch is turned off and improve the cutoff isolation characteristics. Its working mode is: when SW1=SW3=on and SW2=off, it is in the switch-on state; when SW1=SW3=off and SW2=on, it is in the switch-off state. When the switch is off, SW2 is turned on, so that the middle point of SW1 and SW3 is connected to GND, so the leakage of the input signal becomes less (the signal passing through SW1 flows into GND through SW2). Among them, A, B and C are the gates of JFET, and the output is controlled by the main control module.

[0055] 2. High stable gain programmable amplifier module under wide bandwidth

[0056] As a lower-stage amplifier circuit for voltage division, it must have sufficient input impedance and extremely low noise characteristics. Common integrated operational amplifiers are difficult to meet the requirements. Based on the integrated operational amplifier, the present invention uses discrete components to build an amplifier pre-circuit to increase the input impedance of the circuit, and cascades with the integrated operational amplifier to increase the amplification factor. According to the characteristic of increasing input impedance by voltage series negative feedback, a high-stable gain programmable amplifier module with a wide bandwidth is built.

[0057] like Figure 4 As shown in the figure, the JFET pair differential is used as the pre-amplifier circuit of the integrated operational amplifier by taking advantage of the good noise performance and high input impedance of the JFET pair. The mirror current source is used as the active load to replace the drain resistance of the JFET pair, further increasing the input impedance of the amplifier circuit and improving the differential mode gain. The V / I conversion constant current source circuit is used as the bias current source to further improve the common mode rejection ratio. After passing through the pre-amplifier and the secondary amplifier, the output is fed back to the differential input end of the pair through the resistor-capacitor voltage divider network to form a negative voltage feedback. The DAC is used to change the equivalent resistance of the RCVD low-voltage bridge arm to ensure that the gain of the voltage divider network is consistent under a wide bandwidth. The main control module completes the switching of the amplification gain by controlling the channel selection of the feedback through the signal.

[0058] Specific implementation method 7: This implementation method is different from any one of the specific implementation methods 1 to 6 in that: the sampling interval Δt is:

[0059] Δt=T_one / 2 M

[0060] Among them, T_one is the period of the square wave signal, 2 M Indicates the number of sampling points in each cycle.

[0061] The other steps and parameters are the same as those in Specific Embodiments 1 to 6.

[0062] Specific implementation method eight: Combination Figure 5 The present embodiment is different from the first to seventh embodiments in that the ADC acquisition circuit is used to acquire data according to the sampling interval, and the number of acquisition cycles is 2. N , then the sampling point interval ΔC between adjacent signal cycles is (that is, the interval between the last sampling point in the previous signal cycle and the first sampling point in the next signal cycle):

[0063] ΔC=Δt / 2 N

[0064] The other steps and parameters are the same as those in Specific Embodiments 1 to 7.

[0065] This implementation can accurately measure high-frequency signals at the cost of increasing measurement time, while also ensuring rapid measurement of low-frequency signals to be measured. In addition, the method of the present invention is essentially oversampling, which can improve the actual resolution of the ADC through a large number of samplings, further reduce the requirements for ADC performance, and reduce the cost of implementing the system.

[0066] Experimental Section

[0067] Fluke5700A was used as the signal input source, and the effective value and frequency of the input signal were continuously changed to test the system proposed by the present invention. The test results are shown in Table 1:

[0068] Table 1 System test results

[0069]

[0070]

[0071] The above calculation examples of the present invention are only used to explain the calculation model and calculation process of the present invention in detail, and are not intended to limit the implementation methods of the present invention. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present invention are still within the scope of protection of the present invention.

Claims

1. An AC voltage measurement system, characterized in that: The system includes a signal conditioning network, a signal acquisition network and a main control network, wherein the signal acquisition network includes an ADC acquisition circuit and a time base trigger circuit, and the main control network includes an STM32 and an FPGA; wherein: The signal conditioning network is used to process the input signal to be tested and send the processed signal to be tested to the signal acquisition network; The time base trigger circuit is used to convert the processed signal to be tested into a square wave signal, and input the square wave signal to the FPGA; The FPGA is used to calculate the period of the square wave signal, and calculate the sampling interval according to the period of the square wave signal; The ADC acquisition circuit is used to collect data according to the sampling interval, and send the collected data to the FPGA, and use the FPGA to pass the collected data to the STM32; The STM32 is used to calculate the effective value of the AC voltage according to the collected data.

2. An AC voltage measurement system according to claim 1, characterized in that: The time base trigger circuit converts the processed signal to be tested into a square wave signal through hysteresis comparison.

3. An AC voltage measurement system according to claim 2, characterized in that: The FPGA communicates with the STM32 via the FSMC bus.

4. An AC voltage measurement system according to claim 3, characterized in that: The STM32 is also used to send a data acquisition end signal to the FPGA.

5. An AC voltage measurement system according to claim 4, characterized in that: The system also includes a step signal correction network, which is used to output a step signal and a DC signal according to the effective value of the AC voltage, and use the step signal and the DC signal to correct the system.

6. An AC voltage measurement system according to claim 5, characterized in that: The signal conditioning network is specifically: The input end of the JFET pair is the input end of the signal conditioning network, the output end of the JFET pair is connected to the input end of the secondary amplifier, the output end of the secondary amplifier is connected to the input end of the RCVD circuit, the output end of the DAC is connected to the input end of the RCVD circuit, the output end of the RCVD circuit is connected to the differential input end of the JFET pair, and the bias current source of the JFET pair is a V / I conversion constant current source circuit.

7. An AC voltage measurement system according to claim 6, characterized in that: The sampling interval Δt is: Δt=T_one / 2 M Among them, T_one is the period of the square wave signal, 2 M Indicates the number of sampling points in each cycle.

8. An AC voltage measurement system according to claim 7, characterized in that: The ADC acquisition circuit is used to collect data according to the sampling interval, and the number of cycles collected is 2 N , then the sampling point interval ΔC between adjacent signal cycles is: ΔC=Δt / 2 N 。

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