Microsecond-level multichannel separation synchronism testing device and method based on STM32 chip

Abstract

The invention belongs to the technical field of aerospace, and particularly relates to a microsecond-level multichannel separation synchronism testing device and method based on an STM32 chip, and the device comprises the STM32 chip, a plurality of separation monitoring channels based on the STM32 chip, a switch module, a power-on control interface, a communication chip, and a communication interface. According to the microsecond-level multi-channel separation synchronism testing device and method based on the STM32 chip, the automation degree and the time monitoring precision of the testing device are improved, closed-loop control of an experiment can be achieved, an experiment result can be displayed in real time, and microsecond-level multi-channel separation synchronism testing is achieved in a low-cost mode.

Description

Technical Field

[0001] The invention belongs to the field of aerospace technology, and specifically relates to a multi-point synchronous separation test method, and in particular to a microsecond-level multi-channel separation synchronization test device and method based on an STM32 chip. Background Art

[0002] Currently, non-pyrotechnic connection and separation mechanisms using shape memory alloy (SMA) as the driving source are widely used in various fields. For example, the connection and separation mechanisms in the aerospace field can realize the connection and separation between the entire aircraft and its components, and between components, which has important research significance.

[0003] Generally, the connection and separation mechanism can not only be used for single-point connection, but also can be used in combination according to the different needs of the target. For example, the separation of rocket stages, the separation of satellites and rockets, and other separation requirements with large load-bearing capacity often require the combined use of multiple connection and separation mechanisms or the use of a single connection and separation mechanism in combination with a linkage mechanism to achieve, such as the rigid strap in the satellite-rocket separation, which is triggered by a connection and separation mechanism and unlocked by a linkage mechanism. During use, in order to ensure the successful separation process, the separation synchronization of multiple separation points becomes a very critical factor. If the separation synchronization is poor, the connector will deflect due to uneven force and continue to move under inertia, which poses a risk of accidental collision with other components, affecting the reliability of the separation task. Therefore, separation synchronization testing of the separation process of multiple separation points is an indispensable part of the multi-point synchronous separation task.

[0004] In the use of non-pyrotechnic connection and separation mechanisms using shape memory alloys as the driving source, it is also necessary to note that although SMA can be reused, it is sensitive to temperature. When the temperature is higher than its specific phase change temperature range, the microstructure of the SMA will undergo an irreversible phase change and even lose the shape memory effect. Therefore, the power-on process of the SMA wire needs to be strictly controlled.

[0005] At present, there are mainly two testing methods for multi-point synchronous separation:

[0006] (a) The two ends of the on-off signal adapter are connected to the separation measurement point and the four channels of the oscilloscope respectively. When the power is output, the oscilloscope is externally triggered. After separation, the separation time is read through the oscilloscope with an accuracy of up to 0.01ms.

[0007] (b) The entire separation process is filmed and captured by a high-speed camera with hundreds of thousands of frames per second. The image is then processed to determine the separation time of each point with an accuracy of up to 0.01ms.

[0008] However, both of the above two solutions have certain defects:

[0009] In the above scheme (a), on the one hand, the control logic is in an open-loop state, which means that after the separation action occurs, the system cannot effectively feedback and control the power output. Since the SMA wire has strict requirements on the power-on time and current size, over-powering may cause its performance degradation or even damage. Therefore, this lack of feedback mechanism is likely to cause over-powering of the SMA wire, thereby affecting its service life; on the other hand, the number of separation measurement points that can be monitored simultaneously by scheme (a) is limited, and it is impossible to connect and monitor enough separation measurement points at the same time, thereby limiting its application in multi-point synchronous separation testing.

[0010] In the above scheme (b), on the one hand, the system lacks direct information feedback. At the moment of separation, scheme (b) cannot immediately feedback the power output, which may cause the SMA wire to continue to be energized, resulting in over-energization. Over-energization will affect the performance and life of the SMA wire and may even cause it to be damaged. At the same time, after the experiment, scheme (b) cannot provide experimental results immediately, and a lot of time is needed for manual image processing and analysis later. This not only prolongs the experimental cycle, but also increases the uncertainty of the experiment. In addition, although high-speed cameras can provide high-frame rate images, there are blind spots in their shooting angle of view. For separation measurement points located in the blind spot of the shooting angle of view, scheme (b) cannot be effectively monitored, thereby limiting its application in complex separation scenarios. Furthermore, the cost of high-speed cameras is as high as tens of millions, and the equipment cost is expensive, which greatly increases the overall cost of the experiment. For scientific research institutions or enterprises with limited budgets, adopting scheme (b) may face greater economic pressure. Therefore, although high-speed cameras can provide high-frame rate images and more intuitively display the separation process, they also have obvious limitations in terms of cost and applicability.

[0011] Therefore, providing a microsecond-level multi-channel separation synchronization testing device and method with a simple structure, low cost, high precision, easy implementation, wide application range, and the ability to prevent SMA wire overcharging is of great significance to promoting the development of multi-point synchronous separation testing technology. Summary of the invention

[0012] The purpose of the present invention is to provide a microsecond level multi-channel separation synchronization test device and method based on STM32 chip in view of the above-mentioned technical problems.

[0013] In view of this, the present invention provides a microsecond level multi-channel separation synchronization test device based on STM32 chip, characterized in that it includes:

[0014] STM32 chip;

[0015] A plurality of separation monitoring channels based on an STM32 chip, wherein the separation monitoring channel comprises a charging power supply VDD, a resistor R and a capacitor C connected in series in sequence, the other end of the capacitor C is grounded, a GPIO interface is arranged between the resistor R and the capacitor C, the GPIO interface is connected to an external interrupt pin of the STM32 chip, one part of the separation monitoring point connected in the separation body is connected between the resistor R and the capacitor C, and the other part is connected between the capacitor C and the grounding point of the capacitor C, and it is ensured that the two parts of the separation monitoring point connected in the separation body can be turned on, and during the separation process, the test device can obtain the total time taken by the two parts of the separation monitoring point connected in the separation body from power-on to separation according to the voltage change of the capacitor C;

[0016] A switch module connected to a power input interface of the connection separation body to be tested;

[0017] A power-on control interface, which can control the switch module to open or close the circuit;

[0018] And, a communication chip and a communication interface, the STM32 chip, the communication chip and the communication interface are connected in sequence, and the communication interface can communicate with the computer host through a USB interface to perform serial port communication to receive instructions from the computer host or send information to the computer host;

[0019] The STM32 chip is also connected to the power-on control interface and the switch module, and the STM32 chip can control the power-on state of the separated monitoring points in the connected separation body during the test, and obtain the power-on state parameters.

[0020] Further, when the two parts of the separation monitoring point in the connection separation body are in a connection state, the voltage of the capacitor C is 0;

[0021] After the two parts connected to the separation monitoring point in the separation body are separated, the loop is disconnected, and the capacitor C is charged under the action of the charging power supply VDD and the resistor R, and the voltage gradually increases;

[0022] When the voltage of the capacitor C rises to the trigger voltage of the external interrupt of the STM32 chip, the STM32 chip automatically executes the external interrupt program. In the external interrupt program, the controller of the STM32 chip reads the current time and obtains the total time from power-on to separation of the two parts of the separation monitoring point connected in the separation body by calculating the interval between the current time and the power-on start time.

[0023] Furthermore, the microsecond level multi-channel separation synchronization test device also includes:

[0024] The program burning interface is an interface derived from the program download pin of the STM32 chip. Before starting to use it, it is necessary to burn the existing program into the test device through the program burning interface in advance.

[0025] The system restart interface is an interface derived from the restart pin of the STM32 chip. The system restart interface is externally connected to a mechanical restart button. Pressing the mechanical restart button can restart the system.

[0026] Furthermore, the microsecond level multi-channel separation synchronization test device also includes:

[0027] Each detection allows the use of part or all of the multiple separation monitoring channels. Before use, part or all of the channels used in the separation monitoring channels are respectively connected to the corresponding separation monitoring points.

[0028] A microsecond level multi-channel separation synchronization test method, the test method is used for the above-mentioned microsecond level multi-channel separation synchronization test device, the test method comprises the steps of:

[0029] S1, during the test, when a separation monitoring channel is interrupted and triggered, execute step S2;

[0030] S2, the STM32 chip automatically enters the interrupt function of the channel. At the same time, after the test device delays the setting time t1, it determines whether the separation monitoring point has been separated. The basis for the judgment is: if the corresponding separation monitoring point has been separated, the capacitor C is at a high level, otherwise the capacitor C is at a low level;

[0031] S3, if the corresponding separation monitoring point has been separated, obtain the current time and execute step S4; if not, end the monitoring of the channel;

[0032] S4, changing the separation flag of the separation monitoring channel to indicate that the separation of the separation monitoring channel has been completed, and ending the monitoring of the channel.

[0033] Furthermore, when the connected and separated body to be tested is a connected and separated body that uses an unlocker and is unlocked by a mechanical structure linkage, the test method further includes a step S3 located between steps S3 and S4. + , the step S3 + include:

[0034] S3 + If the corresponding separation monitoring point has been separated, it is determined whether the separation monitoring channel is the main channel, where the main channel refers to the channel connected to the micro switch inside the unlocker. If so, the switch module is controlled to disconnect the current output. If not, the separation monitoring channel is used as a normal monitoring channel, and the current time is obtained and the separation flag is changed before ending.

[0035] Furthermore, the testing method also includes:

[0036] When the experimental data sent by the user is received, the format of the experimental data is automatically determined by the program burned in the STM32 chip until the information format is correct, and then the power-on information is sent to the switch module to start powering on and perform a separation synchronization test.

[0037] Furthermore, the test method further includes: after starting the separation synchronization test, the controller of the STM32 chip periodically sends the channel numbers that have not been separated according to a set period.

[0038] Furthermore, the test method also includes: after starting the separation synchronization test, the controller of the STM32 chip monitors the test time, and after all the separation monitoring channels used by the user have completed the separation, or after the maximum test time set by the system is reached, the system automatically ends and sends the separation results of each channel.

[0039] Furthermore, the testing method also includes:

[0040] After the unlocker is powered on and the separation action is completed, the controller of the STM32 chip sends a command to stop power supply to the switch module, and the switch module cuts off the current output.

[0041] The beneficial effects of the present invention are:

[0042] The microsecond-level multi-channel separation synchronization test device and method based on the STM32 chip provided by the present invention integrates the functions of automated experimental control and multi-channel separation time monitoring, and has the following advantages:

[0043] (1) The present invention realizes the automated control of the connection and separation mechanism experiment, and the power is cut off when unlocked, which can effectively prevent the SAM wire from being overcharged and extend its service life;

[0044] (2) The present invention realizes high time precision monitoring of a single connection and separation point, with a measurement error of less than 10us, and has the advantage of high precision;

[0045] (3) The present invention integrates multi-channel separation synchronization monitoring, realizes the separation synchronization monitoring of multiple separation points, and the synchronization error in actual use is less than 2us;

[0046] In summary, the microsecond-level multi-channel separation synchronization test device and method based on the STM32 chip described in the present invention improve the degree of automation and time monitoring accuracy of the test system, can realize closed-loop control of the experiment, and can display the experimental results in real time, thereby realizing microsecond-level multi-channel separation synchronization test in a low-cost manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is the overall structural diagram of the separation synchronization testing device of the present invention;

[0048] Figure 2 is a circuit diagram of the separation monitoring channel of the present invention;

[0049] Figure 3 This is a schematic diagram of the principle of the interrupt function;

[0050] Figure 4 It is a flow chart after an interruption trigger is detected in the separation synchronization test method of the present invention;

[0051] Figure 5 It is the main flow chart of the separation synchronization test method of the present invention;

[0052] Figure 6 is an example diagram of a fitting curve of test data obtained by the present invention;

[0053] Figure 7 is the separation synchronicity test result 1 obtained in the embodiment of the present invention;

[0054] Figure 8 This is the second separation synchronization test result obtained in the embodiment of the present invention;

[0055] The symbols in the figure are:

[0056] 1. Communication interface; 2. Program burning interface; 3. Separation monitoring channel; 4. System restart interface; 5. Power-on control interface; 6. Switch module; 61. Control interface; 62. Power output interface; 63. Power input interface; 7. Communication chip; 8. STM32 chip. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0058] In the description of the present application, it should be noted that the terms used herein are only for describing specific embodiments, and are not intended to limit the exemplary embodiments according to the present application. For ease of description, the techniques, methods and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the techniques, methods and equipment should be considered as part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0059] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0060] It should be noted that, in the present application, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises one..." does not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be noted that the scope of the method and device in the embodiment of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0061] like Figure 1 As shown, a microsecond-level multi-channel separation synchronization test device based on an STM32 chip comprises:

[0062] STM32 chip 8;

[0063] Multiple separate monitoring channels 3 based on STM32 chip 8, such as Figure 2 As shown, the separation monitoring channel 3 includes a charging power supply VDD, a resistor R and a capacitor C connected in series in sequence, the other end of the capacitor C is grounded, a GPIO interface is set between the resistor R and the capacitor C, the GPIO interface is connected to the external interrupt pin of the STM32 chip 8, one part of the separation monitoring point connected in the separation body is connected between the resistor R and the capacitor C, and the other part is connected between the capacitor C and the grounding point of the capacitor C, and it is ensured that the two parts of the separation monitoring point connected in the separation body can be turned on. During the separation process, the test device can obtain the total time from power-on to separation of the two parts of the separation monitoring point connected in the separation body according to the voltage change of the capacitor C;

[0064] The power-on control interface 5 includes two pins for connecting the switch module 6, namely a signal sending pin and a GND pin. The signal sending pin is used to send a control signal to the switch module 6, and the control signal triggers the switch module 6 to perform a corresponding action, such as opening or closing the circuit; the GND pin is a reference zero potential point in the circuit, which is used to ensure that the control signal output by the signal sending pin has a stable reference potential, thereby ensuring the accuracy and reliability of the control signal;

[0065] The switch module 6 comprises a control interface 61, a power input interface 63 and a power output interface 62, wherein the control interface 61 is connected to the signal sending pin in the power-on control interface 5, the power input interface 63 is connected to the power output interface 62, the power input interface 63 is connected to an external constant current power supply, and the power output interface 62 is connected to the power input interface of the connection separation body to be tested, and the control interface 61 determines whether to open or close the circuit path between the power input interface 63 and the power output interface 62 by receiving the control signal sent by the signal sending pin, thereby controlling the on and off of the power supply through the switch module 6;

[0066] And, the communication chip 7 and the communication interface 1, the STM32 chip 8, the communication chip 7 and the communication interface 1 are connected in sequence, and the communication interface 1 can communicate with the computer host through the USB interface to receive instructions from the computer host or send information to the computer host;

[0067] In addition, the STM32 chip 8 is also connected to the power-on control interface 5 and the switch module 6. The STM32 chip 8 can control the power-on state of the separated monitoring points in the connected separation body during the test, and obtain power-on state parameters, such as power-on and power-off time.

[0068] As some examples of the present invention, the communication interface 1 is a serial communication module built using a CP2102 chip.

[0069] Generally, the STM32 chip 8 includes a plurality of external interrupt pins, and the plurality of separation monitoring channels 3 can be respectively connected to different external interrupt pins to form a multi-channel, such as an 8-channel separation synchronization test device.

[0070] As some examples of the present invention, the STM32 chip 8 may be a STM32 series chip, such as a STM32F103C8T6 chip, a STM32F103RCT6 chip, and the like.

[0071] Preferably, the STM32 chip 8 is a STM32F103C8T6 chip, which can reduce costs while meeting performance requirements.

[0072] The working process and principle of the separation monitoring channel 3 are described below by way of example:

[0073] like Figures 1-2 As shown, the two access ports in the separation monitoring channel 3 are respectively connected to the two parts Part 1 and Part 2 of the separation monitoring point in the body to be separated, and ensure that the two parts Part 1 and Part 2 can be turned on, and the GPIO (General-Purpose Input / Output) interface is connected to the external interrupt pin of the STM32 chip;

[0074] On this basis, the present invention obtains the total time from power-on to separation as follows: when the two parts of the separation monitoring point in the reception separation body are in a connected state, the voltage of the capacitor C between the two access ports connected to Part1 and Part2 is 0. After the two parts of the separation monitoring point in the reception separation body are separated, the loop is disconnected, and the capacitor C is charged under the action of the charging power supply VDD and the resistor R, and the voltage gradually increases. The increase process satisfies the RC charging law, that is, the voltage V of the capacitor C = V0*(1-e (-t / RC) ), where V is the voltage of the capacitor C at time t, V0 is the voltage of the charging power supply VDD, that is, the stable voltage value of the capacitor C after charging is completed. In the present invention, the value of V0 is preferably 5V, e is the base of the natural logarithm, t is time, t represents the time elapsed from the start of charging to the current moment, and RC is the time constant of the circuit, which is determined by the product of the resistor R and the capacitor C;

[0075] When the voltage of capacitor C rises to the trigger voltage of the external interrupt of the STM32 chip 8 (usually 0.7 times V0, when V0=3.3V, the trigger voltage is 2.31V), the STM32 chip 8 automatically executes the external interrupt program. In the external interrupt program, the controller of the STM32 chip 8 reads the current time and obtains the total time from power-on to separation of the two parts of the separation monitoring point in the connection separation body by calculating the interval between the current time and the power-on start time.

[0076] Furthermore, the microsecond level multi-channel separation synchronization test device also includes:

[0077] The program burning interface 2 is an interface derived from the program download pin of the STM32 chip 8. Generally, the code can be burned using a common ST-Link downloader.

[0078] Furthermore, the microsecond eight-channel separation synchronization test device also includes:

[0079] The system restart interface 4 is an interface derived from the restart pin of the STM32 chip 8. The system restart interface 4 is externally connected to a mechanical restart button, and the system can be restarted by pressing the mechanical restart button.

[0080] Furthermore, in the switch module 6, the control interface 61 includes two pins, namely a signal receiving pin and a GND pin; the power input interface 63 includes two pins, respectively connected to the positive and negative poles of an external constant current power supply; the power output interface 62 includes two pins, respectively connected to the positive and negative poles of an external load.

[0081] As some examples of the present invention, the switch module 6 can use a mature switch module on the market, which controls the opening and closing of the circuit through an optocoupler and a MOS tube. After the control interface 61 receives the start signal sent by the power-on control interface 5, the switch is turned on and the external load is powered by the power supply; after receiving the shutdown signal sent by the power-on control interface 5, the switch is turned off and the external load is disconnected from the power supply.

[0082] Furthermore, before use, the communication interface 1 is connected to the USB interface on the computer host, the system restart interface 4 is connected to the external mechanical restart button, the power-on control interface 5 is connected to the control interface 61 of the switch module 6, the power input interface 63 is connected to the external constant current source, the power output interface 62 is connected to the power input interface of the external separation mechanism, and some or all of the channels used in the separation monitoring channel 3 are connected to the separation monitoring point.

[0083] Furthermore, each detection allows the use of part or all of the multiple separation monitoring channels 3. Before use, part or all of the used separation monitoring channels 3 are respectively connected to the corresponding separation monitoring points.

[0084] It should be noted that, before starting to use, it is necessary to pre-burn the existing program into the test device through the program burning interface 2. This process is only required once and does not need to be performed again in subsequent use.

[0085] As some examples of the present invention, the STM32 chip 8 also includes:

[0086] A memory for storing computer programs;

[0087] The processor is used to implement the microsecond-level multi-channel separation synchronization test method based on the STM32 chip provided by the present invention when executing the program stored in the memory.

[0088] The external interrupt principle involved in the STM32 chip 8 of the present invention is as follows Figure 3 As shown, during the execution of the main function of the STM32 chip 8, the external interrupt pin captures the separation signal, triggers an interrupt, suspends the execution of the main function, maintains the current state, executes the interrupt function content, and after the execution is completed, continues to execute the main function.

[0089] In addition, the present invention also provides a microsecond level multi-channel separation synchronization test method based on STM32 chip, and the test method is used for the above-mentioned microsecond level multi-channel separation synchronization test device based on STM32 chip, such as Figure 4 As shown, the microsecond level multi-channel separation synchronization test method based on the STM32 chip includes the following steps:

[0090] S1, during the test, when a separation monitoring channel 3 is interrupted and triggered, execute step S2;

[0091] S2, the STM32 chip automatically enters the interrupt function of the channel. At the same time, after the test device delays the setting time t1, preferably t1 = 1 ~ 10us, it is judged whether the separation monitoring point has been separated. The basis for judgment is: if the corresponding separation monitoring point has been separated, the capacitor C is at a high level, otherwise the capacitor C is at a low level. The reason for doing so is that the present invention uses a capacitor integration circuit, which can absorb voltage fluctuations during the separation process, but may still be triggered by mistake. After the delay, it is judged that if it is a false trigger, it is at a low level, and if it has been separated, it is at a high level, which is more accurate.

[0092] S3, if the corresponding separation monitoring point has been separated, obtain the current time and execute step S4; if not, end the monitoring of the channel;

[0093] S4, changing the separation mark of the separation monitoring channel 3, indicating that the separation of the separation monitoring channel 3 has been completed, and ending the monitoring of the channel.

[0094] Generally, in step S2, for the capacitor C, the high level and the low level are set according to specific circumstances or tests.

[0095] As some examples of the present invention, in step S2, when the supply voltage is 3.3V, for the capacitor C, a voltage above 0.7*3.3V is a high level, and a voltage below 0.3*3.3V is a low level.

[0096] Further, for a connection separation body that uses an unlocker and is unlocked by a mechanical structure linkage, the microsecond-level multi-channel separation synchronization test method based on the STM32 chip includes step S3 located between steps S3 and S4. + , the step S3 + include:

[0097] S3 + If the corresponding separation monitoring point has been separated, it is determined whether the separation monitoring channel 3 is the main channel, where the main channel refers to the channel connected to the micro switch inside the unlocker. If so, the switch module 6 is controlled to disconnect the current output. If not, the separation monitoring channel is used as a normal monitoring channel, and the current time is obtained and the separation flag is changed before ending.

[0098] Furthermore, the microsecond-level multi-channel separation synchronization test method based on the STM32 chip also includes:

[0099] When the experimental data sent by the user is received, the format of the experimental data is automatically determined by the program burned in the STM32 chip 8. After the information format is correct, the power-on information is sent to the switch module 6 to start powering on and perform a separation synchronization test.

[0100] Furthermore, after starting the separation synchronization test, the controller of the STM32 chip 8 regularly sends the channel numbers that have not been separated according to the set period. The duration of the period can be set according to actual needs, such as a few milliseconds or seconds. By regularly sending the channel numbers that have not been separated, the test progress can be understood in time.

[0101] Furthermore, after starting the separation synchronization test, the controller of the STM32 chip 8 monitors the test time. After all the separation monitoring channels 3 used by the user have completed separation, or after reaching the maximum test time set by the system, the system automatically ends and sends the separation results of each channel: separation time or no separation. Then the next experiment can be started.

[0102] As some examples of the present invention, when inputting experimental parameters to the device through the serial port host computer on the computer side, the first parameter is the number of channels used, the second parameter is the number of the main channel, and the subsequent numbers are the numbers of other channels used, and the number must correspond to the first parameter. One of the last two parameters is the maximum power-on time, and the unit of the maximum power-on time is milliseconds. The maximum power-on time stipulates the maximum allowable power-on time when the micro switch is not triggered due to an accident in the connection and separation mechanism. The setting of the maximum power-on time can prevent over-power problems caused by accidents. The other of the last two parameters is the maximum test time, and its unit is seconds. The maximum test time stipulates the maximum waiting time when the separation test points are not completely separated. If they are all separated, the waiting will end automatically.

[0103] In the present invention, for a connected separation body that uses an unlocker and is unlocked through a mechanical structure linkage, the channel connected to the microswitch inside the unlocker is defined as the main channel, and the monitoring channels of other separation points are defined as other channels. In actual operation, the setting of the separation points can be freely set by the user, and it is only necessary to ensure that when connected, the two access ports of each channel in the separation monitoring channel 3 can be connected and conducted, and can be disconnected at the same time after separation.

[0104] The following is an example of a single connection and separation mechanism combined with a linkage mechanism to achieve the task of separating the rocket from the satellite to illustrate the microsecond-level multi-channel separation synchronization test method based on the STM32 chip of the present invention:

[0105] This example uses an unlocker and a mechanical structure linkage to achieve the connection locking of the entire connection and separation body. After the unlocker is energized, the unlocker is unlocked, and the internal microswitch changes the switch state accordingly. The device starts linear or rotational movement under the action of the spring, actuating the entire device to separate. The separation area is large, and the separation status of multiple measuring points needs to be monitored simultaneously.

[0106] After testing according to the above-mentioned microsecond-level multi-channel separation synchronization test device and method based on STM32 chip, the results obtained are as follows Figures 7-8 As shown:

[0107] Among them, the test device uses the 8 external interrupt channels of the STM32F103C8T6 chip to realize the synchronous monitoring of 8 separation monitoring points. After each separation monitoring channel 3 is triggered, two steps will be performed, namely waiting for the separation signal to stabilize and obtaining the separation time. This process takes about 7us. If other channels are triggered at this time, they will be suspended and waiting, which is the main source of error in the present invention.

[0108] The actual test results are analyzed and obtained as follows: Figure 7As shown in FIG. 1 , when the separation interval of the two channels is tens of us, the separation synchronization measurement error is only 0.4us (wherein, the oscilloscope shows that the separation time difference between the two channels is 91.6us, and the test device of the present invention shows that the separation time difference between the two channels is 92us); in addition, as Figure 8 It is shown that when the separation interval of the two channels is 10 us, the separation synchronization measurement error is about 1.2 us (wherein, the oscilloscope shows that the separation time difference between the two channels is 9.8 us, and the test device of the present invention shows that the separation time difference between the two channels is 11 us).

[0109] In the most extreme case, if all 8 channels are triggered at the same time, the maximum time interval between the first triggered channel and the last triggered channel is about 7×7=49us. For a 300ms separation experiment, the 49us error accounts for about 1 / 6000 of the total separation time. However, in actual separation experiments, due to factors such as processing errors and insufficient consistency of parts, the separation time intervals of different channels are much greater than 10us. The common synchronization requirement is at the ms level, so the measurement error of separation synchronization can be reduced to less than 2us.

[0110] In addition, in the present invention, the operating frequency of the STM32 chip 8 used in the test device is 72MHz, the timing accuracy is 1us, and the pull-up resistor R combined with the integral capacitor C can absorb the voltage jump caused by multiple contacts during separation to prevent misjudgment. The device can respond within 10us of completing the separation at the separation monitoring point and record the separation time, such as Figure 6 As shown in the figure, the measurement error of separation time increases linearly with the extension of test time. By measuring the change of error with test time in advance and compensating the measurement result, the monitoring error of separation time can be reduced to less than 10us.

[0111] After the connection and separation body is energized and the separation action is completed, the main channel monitoring its separation state transmits information to the controller of the STM32 chip 8, and the controller sends an instruction to stop power supply to the switch module 6, and the switch module 6 cuts off the current output. The whole process takes less than 100us and is carried out automatically, which can effectively prevent over-powering and extend the service life of the connection and separation mechanism.

[0112] In summary, the microsecond-level multi-channel separation synchronization test device and method based on the STM32 chip integrates the functions of automated experimental control and multi-channel separation time monitoring, and has the following advantages:

[0113] (3) The present invention realizes the automated control of the connection and separation mechanism experiment, and the power is cut off when unlocked, which can effectively prevent the SAM wire from being overcharged and extend its service life;

[0114] (4) The present invention realizes high time precision monitoring of a single connection and separation point, with a measurement error of less than 10us, and has the advantage of high precision;

[0115] (3) The present invention integrates multi-channel separation synchronization monitoring, realizes the separation synchronization monitoring of multiple separation points, and the synchronization error in actual use is less than 2us;

[0116] In summary, the microsecond-level multi-channel separation synchronization test device and method based on the STM32 chip described in the present invention improve the degree of automation and time monitoring accuracy of the test system, can realize closed-loop control of the experiment, and can display the experimental results in real time, thereby realizing microsecond-level multi-channel separation synchronization test in a low-cost manner.

[0117] The embodiments of the present application are described above in conjunction with the accompanying drawings. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A microsecond-level multi-channel separation synchronization test device based on STM32 chip, characterized in that: include: STM32 chip (8); A plurality of separation monitoring channels (3) based on an STM32 chip (8), wherein the separation monitoring channels (3) comprise a charging power source VDD, a resistor R and a capacitor C connected in series in sequence, the other end of the capacitor C being grounded, a GPIO interface being arranged between the resistor R and the capacitor C, the GPIO interface being connected to an external interrupt pin of the STM32 chip (8), one part of the separation monitoring point connected to the separation body being connected to between the resistor R and the capacitor C, the other part being connected to between the capacitor C and a grounding point of the capacitor C, and ensuring that the two parts of the separation monitoring point connected to the separation body can be turned on, and during the separation process, a test device being able to obtain the total time taken for the two parts of the separation monitoring point connected to the separation body to be energized to be separated according to a voltage change of the capacitor C; A switch module (6) connected to a power input interface of the connection separation body to be tested; A power-on control interface (5) capable of controlling a switch module (6) to open or close a circuit; And, a communication chip (7) and a communication interface (1), wherein the STM32 chip (8), the communication chip (7) and the communication interface (1) are connected in sequence, and the communication interface (1) can communicate with a computer host via a USB interface via a serial port to receive instructions from the computer host or send information to the computer host; The STM32 chip (8) is also connected to the power-on control interface (5) and the switch module (6), and the STM32 chip (8) is capable of controlling the power-on state of the separation monitoring points in the connection separation body during the test process, and obtaining power-on state parameters.

2. The microsecond level multi-channel separation synchronization test device according to claim 1, characterized in that: When the two parts of the separation monitoring point in the connection separation body are in a connected state, the voltage of the capacitor C is 0; After the two parts connected to the separation monitoring point in the separation body are separated, the loop is disconnected, and the capacitor C is charged under the action of the charging power supply VDD and the resistor R, and the voltage gradually increases; When the voltage of the capacitor C rises to the trigger voltage of the external interrupt of the STM32 chip (8), the STM32 chip (8) automatically executes the external interrupt program. In the external interrupt program, the controller of the STM32 chip (8) reads the current time and obtains the total time from power-on to separation of the two parts connecting the separation monitoring point in the separation body by calculating the interval between the current time and the power-on start time.

3. The microsecond level multi-channel separation synchronization test device according to claim 1, characterized in that: The microsecond level multi-channel separation synchronicity testing device further comprises: The program burning interface (2) is an interface derived from a program download pin of the STM32 chip (8). Before use, an existing program needs to be burned into the test device through the program burning interface (2). The system restart interface (4) is an interface derived from a restart pin of the STM32 chip (8). The system restart interface (4) is externally connected to a mechanical restart button, and the system can be restarted by pressing the mechanical restart button.

4. The microsecond level multi-channel separation synchronization test device according to claim 1, characterized in that: The microsecond multi-channel separation synchronicity testing device further comprises: Each detection allows the use of part or all of the multiple separation monitoring channels (3). Before use, part or all of the used separation monitoring channels (3) are respectively connected to the corresponding separation monitoring points.

5. A microsecond level multi-channel separation synchronization test method, characterized in that: The test method is used for the microsecond level multi-channel separation synchronization test device according to any one of claims 1 to 4 above, and the test method comprises the steps of: S1, during the test, when a separation monitoring channel is interrupted and triggered, execute step S2; S2, the STM32 chip automatically enters the interrupt function of the channel. At the same time, after the test device delays the setting time t1, it determines whether the separation monitoring point has been separated. The basis for the judgment is: if the corresponding separation monitoring point has been separated, the capacitor C is at a high level, otherwise the capacitor C is at a low level; S3, if the corresponding separation monitoring point has been separated, obtain the current time and execute step S4; if not, end the monitoring of the channel; S4, changing the separation flag of the separation monitoring channel to indicate that the separation of the separation monitoring channel has been completed, and ending the monitoring of the channel.

6. The microsecond level multi-channel separation synchronization test method according to claim 5, characterized in that: When the connected and separated body to be tested is a connected and separated body that uses an unlocker and is unlocked by a mechanical structure linkage, the test method further includes step S3 between steps S3 and S4. + , the step S3 + include: S3 + If the corresponding separation monitoring point has been separated, it is determined whether the separation monitoring channel is the main channel, where the main channel refers to the channel connected to the micro switch inside the unlocker. If so, the switch module is controlled to disconnect the current output. If not, the separation monitoring channel is used as a normal monitoring channel, and the current time is obtained and the separation flag is changed before ending.

7. The microsecond level multi-channel separation synchronization test method according to claim 5, characterized in that: The test method also includes: When the experimental data sent by the user is received, the format of the experimental data is automatically determined by the program burned in the STM32 chip until the information format is correct, and then the power-on information is sent to the switch module to start powering on and perform a separation synchronization test.

8. The microsecond level multi-channel separation synchronization test method according to claim 7, characterized in that: The test method further includes: after starting the separation synchronization test, the controller of the STM32 chip periodically sends the channel numbers that have not been separated according to a set period.

9. The microsecond level multi-channel separation synchronization test method according to claim 7, characterized in that: The test method also includes: after starting the separation synchronization test, the controller of the STM32 chip monitors the test time, and after all the separation monitoring channels used by the user have completed separation, or after the maximum test time set by the system is reached, the system automatically ends and sends the separation results of each channel.

10. The microsecond level multi-channel separation synchronization test method according to claim 5, characterized in that: The test method also includes: After the unlocker is powered on and the separation action is completed, the STM32 chip sends a command to stop power supply to the switch module, and the switch module cuts off the current output.

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