Multi-channel parallel level conversion circuit test system

Abstract

The invention discloses a multichannel parallel level conversion circuit test system, which relates to the technical field of circuit test and comprises a test host, a multichannel parallel level conversion circuit, a signal source module, a signal acquisition module, a control module and a display module. The test host performs test logic verification on the whole process of the circuit test, the multichannel parallel level conversion circuit serves as a target circuit to be subjected to circuit test, a test signal of the circuit test is generated according to the signal source module, and a test case of the test signal is constructed. The signal acquisition module acquires an output signal of the multichannel parallel level conversion circuit, and generates a circuit tuning output signal after signal gain, signal noise optimization and frequency band filtering, the control module performs circuit testing on a target circuit according to a test case and the circuit tuning output signal, and finally, the control module performs circuit testing on the target circuit according to the test case and the circuit tuning output signal. And the display module visually displays the test result.

Description

Technical Field

[0001] The invention relates to the technical field of circuit testing, in particular to a multi-channel parallel level conversion circuit testing system. Background Art

[0002] Level conversion circuits are key components in electronic systems that enable signal communication between devices with different voltage standards, and are widely used in high-speed communications, embedded systems, and multi-protocol interface scenarios. With the increase in circuit integration, the demand for multi-channel parallel level conversion circuits has increased significantly, but the complexity of their testing has also increased.

[0003] Traditional testing methods mostly use a single-channel serial test mode, which has low test efficiency and is difficult to cover the interaction between multiple channels; in addition, existing test systems have deficiencies in signal processing, such as weak noise suppression capabilities and poor dynamic signal adaptability, which limits the accuracy of test results. At the same time, the test case design is relatively simple, lacking comprehensive verification of abnormal scenarios, boundary conditions, and fault tolerance, making it difficult to meet the testing requirements of high-reliability scenarios. Therefore, there is an urgent need for an efficient, accurate, and automated verification capability multi-channel parallel level conversion circuit test system to solve the problems of low test efficiency, insufficient signal processing capabilities, and incomplete test coverage in the prior art. Summary of the invention

[0004] In order to solve the above problems, an object of the present invention is to provide a multi-channel parallel level conversion circuit testing system.

[0005] The object of the present invention can be achieved by the following technical solutions: A multi-channel parallel level conversion circuit test system includes a test host, the test host is communicatively connected to the multi-channel parallel level conversion circuit, a signal source module, a signal acquisition module, a control module and a display module; The test host is used to perform test logic verification on the entire process of circuit testing; The multi-channel parallel level conversion circuit is used as a target circuit to be tested; The signal source module is used to generate a test signal for circuit testing and construct a test case corresponding to the test signal; The signal acquisition module is used to collect the output signal of the multi-channel parallel level conversion circuit, and perform signal gain, signal-to-noise optimization and frequency band filtering on the output signal, thereby generating a corresponding circuit tuning output signal; The control module performs circuit testing on the target circuit according to the test case and the circuit tuning output signal; The display module is used to visually display the test results of the circuit test.

[0006] Furthermore, the process of the test host performing test logic verification on the entire process of the circuit test includes: Set the verification working period of the test host; The multi-channel parallel level conversion circuit, the signal source module, the signal acquisition module, the control module and the display module which are interconnected and communicated with the test host respectively edit their own test script files, and transmit the test script files to the test host; During the verification work period, the test host constructs the corresponding test logic according to the belonging object of the test script file. If the test script file is executed correctly according to the test logic, the belonging object corresponding to the test script file is judged to be in a logically correct state; otherwise, the belonging object corresponding to the test script file is judged to be in a logically incorrect state.

[0007] Furthermore, the multi-channel parallel level conversion circuit is used as a target circuit to be tested, and its structure includes: The multi-channel parallel level conversion circuit includes a plurality of high-level circuits and a plurality of low-level circuits, the low-level circuits and the high-level circuits are connected in parallel, and each high-level circuit or low-level circuit is composed of an input interface, a level converter, a channel isolation unit and an output interface; A number of high-level circuits are sequentially numbered and recorded as i, i=1, 2, 3, ..., n, and a number of low-level circuits are sequentially numbered and recorded as j, j=1, 2, 3, ..., m, wherein n and m are both natural numbers greater than 0.

[0008] Furthermore, the signal source module generates a test signal for circuit testing and constructs a test case corresponding to the test signal, including: The signal source module configures a test scenario for circuit testing, the test scenario including a normal working scenario and an abnormal working scenario, and sets a first test sub-case, a second test sub-case, and a third test sub-case corresponding to the test scenario; The first test sub-case is used to control the test scenario to cover all channels, voltage combinations and signal types in the multi-channel parallel level conversion circuit; The second test sub-case is used to control the amplitude, frequency, duty cycle and edge rate of the test signal in the multi-channel parallel level conversion circuit; The third test sub-case is used to control the test signal for repeated testing; Construct a test signal according to the use case contents of the first test sub-case, the second test sub-case and the third test sub-case, integrate the first test sub-case, the second test sub-case and the third test sub-case, construct a regular test case corresponding to the test signal, synchronously construct an auxiliary test case corresponding to the test signal, and integrate the regular test case and the auxiliary test case as the final test case.

[0009] Furthermore, the signal acquisition module acquires the output signal of the multi-channel parallel level conversion circuit, and performs signal gain, signal-to-noise optimization, and frequency band filtering on the output signal converted from the test signal, thereby generating a corresponding circuit tuning output signal. The process includes: When the multi-channel parallel level conversion circuit inputs a test signal, the multi-channel parallel level conversion circuit synchronously generates an output signal after the test signal is converted, and the signal acquisition module acquires the output signal converted from the test signal, obtains the signal peak value of the output signal converted from the test signal and normalizes it, and sets the gain multiple of the output signal converted from the test signal according to the normalized signal peak value, thereby performing signal gain on the output signal converted from the test signal; Perform signal-to-noise optimization and frequency band filtering on the output signal converted from the test signal after signal gain; converting the output signal converted from the test signal into a low mean noise output signal through signal-to-noise optimization; The low-average noise output signal is converted into a circuit tuning signal through frequency band filtering.

[0010] Furthermore, the signal-to-noise optimization process includes: Setting a number of sampling points, dividing the output signal converted from the test signal into a number of local sampling signals according to a preset signal frame length and a number of sampling points, sampling the signal-to-noise ratio of the corresponding local sampling signal at each sampling point, and then obtaining the signal-to-noise ratio of each local sampling signal; Determine whether the signal-to-noise ratio of the local sampling signal meets the standard; If so, no action is taken; If not, further analyze the signal frequency value of the local sampling signal, divide the local sampling signal into a low-frequency signal, an intermediate-frequency signal and a high-frequency signal according to the signal frequency value, and use a sliding average filtering method, a multi-channel joint noise reduction method or a wavelet threshold denoising method for noise processing; Integrate the low-frequency signal, intermediate-frequency signal and high-frequency signal after noise processing to construct a low-mean noise output signal.

[0011] Furthermore, the process of the control module performing circuit testing on the target circuit according to the test case and the circuit tuning output signal includes: The control module sets the test period and edits the test instructions; During the test period, the control module obtains the test case and the circuit tuning output signal as a test start sample, and performs circuit testing on the target circuit according to the edited different test instructions, wherein the test instructions include P1 and P2; Types of circuit testing include circuit function testing and circuit performance testing; When the test instruction is P1, the circuit function test is performed on the target circuit; When the test instruction is P2, a circuit performance test is performed on the target circuit.

[0012] Furthermore, the process of visually displaying the test results of the circuit test by the display module includes: The display module is composed of a display area, a display module 1 and a display module 2; The display area is used for dynamic visual looping display module 1 and display module 2; The display module 1 is used to display the test results of the circuit function test; The display module 2 is used to display the test results of the circuit performance test.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: through multi-channel parallel level conversion circuit and modular design, it supports synchronous testing of multiple channels and significantly improves the test efficiency; the signal acquisition module adopts signal gain, signal-to-noise optimization and frequency band filtering technology, adaptively adjusts the gain multiple according to the signal peak, and adopts sliding average filtering, multi-channel joint noise reduction and wavelet threshold denoising methods for low-frequency, medium-frequency and high-frequency signals respectively, which effectively suppresses noise interference and improves the signal-to-noise ratio and accuracy of the test signal; by constructing conventional test cases and auxiliary test cases, multi-dimensional verification of circuit function, performance and reliability is achieved to ensure that the test covers strict scenarios; the test host automatically verifies the logical correctness by receiving the test script files of each module, performs logical reset on the abnormal module, reduces manual intervention and enhances the robustness of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the present invention. DETAILED DESCRIPTION

[0015] like Figure 1 As shown, a multi-channel parallel level conversion circuit test system includes a test host, the test host is communicatively connected to a multi-channel parallel level conversion circuit, a signal source module, a signal acquisition module, a control module and a display module; The test host is used to perform test logic verification on the entire process of circuit testing; The multi-channel parallel level conversion circuit is used as a target circuit to be tested; The signal source module is used to generate a test signal for circuit testing and construct a test case corresponding to the test signal; The signal acquisition module is used to collect the output signal of the multi-channel parallel level conversion circuit, and perform signal gain, signal-to-noise optimization and frequency band filtering on the output signal, thereby generating a corresponding circuit tuning output signal; The control module performs circuit testing on the target circuit according to the test case and the circuit tuning output signal; The display module is used to visually display the test results of the circuit test.

[0016] It should be further explained that, in the specific implementation process, the test host performs test logic verification on the entire process of circuit testing, including: Set the verification working period of the test host; The multi-channel parallel level conversion circuit, the signal source module, the signal acquisition module, the control module and the display module which are interconnected with the test host respectively edit their own test script files, and transmit the test script files to the test host through the communication between each of them and the test host; During the verification work period, the test host receives all the test script files and builds the corresponding test logic according to the belonging objects of the test script files. If the test script files are correctly executed according to the test logic, it is determined that the belonging objects corresponding to the test script files are in a logically correct state; otherwise, it is determined that the belonging objects corresponding to the test script files are in a logically incorrect state. The belonging object in a logically correct state can correctly execute the corresponding functional part of the circuit test it is responsible for without performing any operation. The belonging object in a logically incorrect state cannot correctly execute the corresponding functional part of the circuit test it is responsible for. The corresponding belonging object is logically reset until the belonging object is restored to a logically correct state.

[0017] It should be noted that the channel parallel level conversion circuit, signal source module, signal acquisition module, control module and display module that communicate with the test host are all belonging objects.

[0018] It should be further explained that, in a specific implementation process, the multi-channel parallel level conversion circuit is used as a target circuit to be tested, and its structure includes: The multi-channel parallel level conversion circuit as the target circuit includes a plurality of high-level circuits and a plurality of low-level circuits, the low-level circuits and the high-level circuits are connected in parallel, and each high-level circuit or low-level circuit is composed of an input interface, a level converter, a channel isolation unit and an output interface; A plurality of high-level circuits are sequentially numbered in sequence, and the number is recorded as i, then i=1, 2, 3, ..., n, where n is a natural number greater than 0; a plurality of low-level circuits are sequentially numbered in sequence, and the number is recorded as j, then j=1, 2, 3, ..., m, where m is a natural number greater than 0; Input interface: used to receive signals from source devices, which may be of different level standards; Level converter: It is the core part of the circuit. Each channel will have one or more level converters. They can be implemented using the following technologies: Transistor level converter: Use NPN or PNP transistors, MOSFET, etc. to convert levels; Dedicated level conversion chips: Such as the 74LVC series, these chips are designed to convert between different levels, such as TTL to CMOS, Resistor divider network: In some cases, a resistor network can be used to adjust the level.

[0019] Channel isolation unit: To ensure that the channels do not interfere with each other, it specifically includes isolation elements such as optocouplers, transformers or capacitor isolation; Output interface: used to output the converted signal from here to the target device.

[0020] It should be further explained that, in a specific implementation process, the signal source module generates a test signal for circuit testing, and the process of constructing a test case corresponding to the test signal includes: The signal source module configures a test scenario for circuit testing, the test scenario including a normal working scenario and an abnormal working scenario, and sets a first test sub-case, a second test sub-case, and a third test sub-case corresponding to the test scenario; The first test sub-case is used to control the test scenario to cover all channels, voltage combinations and signal types in the multi-channel parallel level conversion circuit, wherein the signal type includes static signals and dynamic signals; The second test sub-case is used to control the amplitude, frequency, duty cycle and edge rate of the test signal in the multi-channel parallel level conversion circuit; The third test sub-case is used to control the test signal to perform repeated testing; Constructing a test signal for a final circuit test according to the test case contents of the first test sub-case, the second test sub-case, and the third test sub-case, integrating the first test sub-case, the second test sub-case, and the third test sub-case to construct a conventional test case corresponding to the test signal; Synchronously build functional test cases, boundary condition test cases, and exception and fault tolerance test cases corresponding to the test signal, and use the functional test cases, boundary condition test cases, and exception and fault tolerance test cases as auxiliary test cases for the test signal; Integrate conventional test cases and auxiliary test cases as the final test cases for circuit signals.

[0021] It should be noted that the functional test cases are used for basic conversion verification, multi-channel parallel testing and bidirectional conversion testing. The basic conversion verification includes static testing and dynamic testing; the boundary condition test cases are used for voltage limit testing, temperature drift testing and load capacity testing; the abnormality and fault tolerance test cases are used for overvoltage / undervoltage protection testing, ESD immunity testing and hot plug testing.

[0022] It should be further explained that, in the specific implementation process, the signal acquisition module acquires the output signal of the multi-channel parallel level conversion circuit, and performs signal gain, signal-to-noise optimization and frequency band filtering on the output signal, and then generates the corresponding circuit tuning output signal. The process includes: When the multi-channel parallel level conversion circuit inputs a test signal, the multi-channel parallel level conversion circuit synchronously generates an output signal obtained by converting the test signal, and the signal acquisition module acquires the output signal converted from the test signal, thereby obtaining a signal peak value corresponding to the output signal converted from the test signal, and normalizing the signal peak value, setting a gain multiple corresponding to the output signal converted from the test signal according to the normalized signal peak value, and then performing signal gain on the output signal converted from the test signal; Setting a peak intensity interval, the peak intensity interval includes a peak-valley intensity interval, a flat-peak intensity interval, and a peak-wave intensity interval, and the peak-valley intensity interval, the flat-peak intensity interval, and the peak-wave intensity interval are respectively denoted as Ω1, Ω2, and Ω3; Among them, Ω1=(0, 0.3], Ω2=(0.3, 0.7], Ω3=(0.7, 1); The normalized signal peak is recorded as τ, and the following operations are performed: If τ∈Ω1, the gain multiple of the output signal converted from the test signal is set to 2 times; If τ∈Ω2, the gain multiple of the output signal converted from the test signal is set to 1.5 times; If τ∈Ω3, the gain multiple of the output signal converted from the test signal is set to 1; Perform signal-to-noise optimization and frequency band filtering on the output signal converted from the test signal after signal gain; converting the output signal converted from the test signal into a low mean noise output signal through signal-to-noise optimization; The content of the signal-to-noise optimization is as follows: Setting a number of sampling points, dividing the output signal converted from the test signal into a number of local sampling signals according to a preset signal frame length and a number of sampling points, sampling the signal-to-noise ratio of the corresponding local sampling signal at each sampling point, and then obtaining the signal-to-noise ratio of each local sampling signal; Determine whether the signal-to-noise ratio of the local sampling signal meets the standard; If so, no action is taken; If not, further analyzing the signal frequency value of the local sampling signal, and dividing the local sampling signal into a low-frequency signal, an intermediate-frequency signal and a high-frequency signal according to the signal frequency value; When the local sampling signal is a low-frequency signal, a sliding average filtering method is used to perform noise processing on the local sampling signal; When the local sampling signal is an intermediate frequency signal, a multi-channel joint noise reduction method is used to process the noise of the local sampling signal; When the local sampling signal is a high-frequency signal, the wavelet threshold denoising method is used to process the noise of the local sampling signal; Integrate the low-frequency signal, intermediate-frequency signal and high-frequency signal after noise processing to construct a low-mean noise output signal; Convert low-mean noise output signals into circuit tuning signals through frequency band filtering; The contents of the frequency band filtering are as follows: Set the impedance mismatch correction interval and signal edge optimization interval; If a certain frequency band of the low-mean noise signal is in the impedance mismatch correction interval, all low-mean noise signals in the corresponding frequency band are integrated as the first subset of signals to be tuned; if a certain frequency band of the low-mean noise signal is in the signal edge optimization interval, all low-mean noise signals in the corresponding frequency band are integrated as the second subset of signals to be tuned; The problem phenomenon of the first subset of signals to be tuned is: signal overshoot / vibration; The corresponding tuning actions are: identifying the overshoot frequency through a low-pass filter, calculating the termination resistance of the multi-channel parallel level conversion circuit, and then locating the frequency band where the termination resistance does not meet the requirements for filtering; The problem phenomenon of the second subset of signals to be tuned is: the signal edge is blurred; The corresponding tuning actions are: reducing the cutoff frequency corresponding to the low-pass filter, shortening the signal path or adding a buffer, thereby converting the low-mean noise signal into a circuit-tuned output signal.

[0023] It should be further explained that, in a specific implementation process, the process in which the control module performs circuit testing on the target circuit according to the test case and the circuit tuning output signal includes: The control module sets the test period and edits the test instructions; During the test period, the control module obtains the test case and the circuit tuning output signal as a test start sample, and performs circuit testing on the target circuit according to the edited different test instructions, wherein the test instructions include P1 and P2; Types of circuit testing include circuit function testing and circuit performance testing; The correspondence between different test instructions and circuit test types is as follows: When the test instruction is P1, the target circuit is tested for circuit function. The content of the circuit function test is: testing the logic function of the target circuit, verifying whether the logic gates, triggers and state machines of the digital circuit are working properly (such as whether the output is 1 when input A=1 and B=0), testing the signal integrity of the target circuit, for example, checking whether the bandwidth and distortion of the circuit signal meet expectations; testing whether the protocol of the corresponding communication interface of the target circuit is compatible, and testing whether the data transmission is correct; When the test instruction is P2, the target circuit is subjected to circuit performance test, and the contents of the circuit performance test are as follows: testing the timing characteristic parameters of the target circuit, which include rise time, fall time and propagation delay; testing the frequency response parameters of the target circuit, which include bandwidth, phase margin and group delay; testing the power consumption of the target circuit, which includes static power consumption and dynamic power consumption.

[0024] It should be further explained that, in a specific implementation process, the process of the display module visually displaying the test results of the circuit test includes: The display module is composed of a display area, a display module 1 and a display module 2; The display area is used for dynamic visual looping display module 1 and display module 2; The display module 1 is used to display the test results of the circuit function test; The display module 2 is used to display the test results of the circuit performance test; The display duration set by display module 1 is recorded as Time1; The display duration set by display module 2 is recorded as Time2; The transition duration between display module 1 and display module 2 is recorded as Time3.

[0025] Among them, Time1, Time2 and Time3 are all timestamps greater than 0; Only one of display module 1 or display module 2 is displayed in the display area in the same period of time. When the display time of display module 1 in the display area reaches Time1, display module 2 is switched to the display area according to the countdown of transition time Time3. When the display time of display module 2 in the display area reaches Time2, display module 1 is directly jumped to the display area.

[0026] The above embodiments are only used to illustrate the technical method of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical method of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical method of the present invention.

Claims

1. A multi-channel parallel level conversion circuit test system, comprising a test host, characterized in that: The test host is communicatively connected to a multi-channel parallel level conversion circuit, a signal source module, a signal acquisition module, a control module and a display module; The test host is used to perform test logic verification on the entire process of circuit testing; The multi-channel parallel level conversion circuit is used as a target circuit to be tested; The signal source module is used to generate a test signal for circuit testing and construct a test case corresponding to the test signal; The signal acquisition module is used to collect the output signal of the multi-channel parallel level conversion circuit, and perform signal gain, signal-to-noise optimization and frequency band filtering on the output signal, thereby generating a corresponding circuit tuning output signal; The control module performs circuit testing on the target circuit according to the test case and the circuit tuning output signal; The display module is used to visually display the test results of the circuit test.

2. A multi-channel parallel level conversion circuit testing system according to claim 1, characterized in that: The test host performs test logic verification on the entire process of circuit testing, including: Set the verification working period of the test host; The multi-channel parallel level conversion circuit, the signal source module, the signal acquisition module, the control module and the display module which are interconnected and communicated with the test host respectively edit their own test script files, and transmit the test script files to the test host; During the verification work period, the test host constructs the corresponding test logic according to the belonging object of the test script file. If the test script file is executed correctly according to the test logic, the belonging object corresponding to the test script file is judged to be in a logically correct state; otherwise, the belonging object corresponding to the test script file is judged to be in a logically incorrect state.

3. A multi-channel parallel level conversion circuit test system according to claim 2, characterized in that: The multi-channel parallel level conversion circuit is used as the target circuit to be tested, and its structure includes: The multi-channel parallel level conversion circuit includes a plurality of high-level circuits and a plurality of low-level circuits, the low-level circuits and the high-level circuits are connected in parallel, and each high-level circuit or low-level circuit is composed of an input interface, a level converter, a channel isolation unit and an output interface; A number of high-level circuits are sequentially numbered and recorded as i, i=1, 2, 3, ..., n, and a number of low-level circuits are sequentially numbered and recorded as j, j=1, 2, 3, ..., m, wherein n and m are both natural numbers greater than 0.

4. A multi-channel parallel level conversion circuit testing system according to claim 3, characterized in that: The signal source module generates a test signal for circuit testing and constructs a test case corresponding to the test signal, including: The signal source module configures a test scenario for circuit testing, the test scenario including a normal working scenario and an abnormal working scenario, and sets a first test sub-case, a second test sub-case, and a third test sub-case corresponding to the test scenario; The first test sub-case is used to control the test scenario to cover all channels, voltage combinations and signal types in the multi-channel parallel level conversion circuit; The second test sub-case is used to control the amplitude, frequency, duty cycle and edge rate of the test signal in the multi-channel parallel level conversion circuit; The third test sub-case is used to control the test signal for repeated testing; Construct a test signal according to the use case contents of the first test sub-case, the second test sub-case and the third test sub-case, integrate the first test sub-case, the second test sub-case and the third test sub-case, construct a regular test case corresponding to the test signal, synchronously construct an auxiliary test case corresponding to the test signal, and integrate the regular test case and the auxiliary test case as the final test case.

5. A multi-channel parallel level conversion circuit test system according to claim 4, characterized in that: The signal acquisition module collects the output signal of the multi-channel parallel level conversion circuit, and performs signal gain, signal-to-noise optimization and frequency band filtering on the output signal converted from the test signal, thereby generating the corresponding circuit tuning output signal. The process includes: When the multi-channel parallel level conversion circuit inputs a test signal, the multi-channel parallel level conversion circuit synchronously generates an output signal after the test signal is converted, and the signal acquisition module acquires the output signal converted from the test signal, obtains the signal peak value of the output signal converted from the test signal and normalizes it, and sets the gain multiple of the output signal converted from the test signal according to the normalized signal peak value, thereby performing signal gain on the output signal converted from the test signal; Perform signal-to-noise optimization and frequency band filtering on the output signal converted from the test signal after signal gain; converting the output signal converted from the test signal into a low mean noise output signal through signal-to-noise optimization; The low-average noise output signal is converted into a circuit tuning signal through frequency band filtering.

6. A multi-channel parallel level conversion circuit test system according to claim 5, characterized in that: The signal-to-noise optimization process includes: Setting a number of sampling points, dividing the output signal converted from the test signal into a number of local sampling signals according to a preset signal frame length and a number of sampling points, sampling the signal-to-noise ratio of the corresponding local sampling signal at each sampling point, and then obtaining the signal-to-noise ratio of each local sampling signal; Determine whether the signal-to-noise ratio of the local sampling signal meets the standard; If so, no action is taken; If not, further analyze the signal frequency value of the local sampling signal, divide the local sampling signal into a low-frequency signal, an intermediate-frequency signal and a high-frequency signal according to the signal frequency value, and use a sliding average filtering method, a multi-channel joint noise reduction method or a wavelet threshold denoising method for noise processing; Integrate the low-frequency signal, intermediate-frequency signal and high-frequency signal after noise processing to construct a low-mean noise output signal.

7. A multi-channel parallel level conversion circuit test system according to claim 6, characterized in that: The process of the control module performing circuit testing on the target circuit according to the test case and the circuit tuning output signal includes: The control module sets the test period and edits the test instructions; During the test period, the control module obtains the test case and the circuit tuning output signal as a test start sample, and performs circuit testing on the target circuit according to the edited different test instructions, wherein the test instructions include P1 and P2; Types of circuit testing include circuit function testing and circuit performance testing; When the test instruction is P1, the circuit function test is performed on the target circuit; When the test instruction is P2, a circuit performance test is performed on the target circuit.

8. A multi-channel parallel level conversion circuit test system according to claim 7, characterized in that: The process of displaying the test results of the circuit test visually by the display module includes: The display module is composed of a display area, a display module 1 and a display module 2; The display area is used for dynamic visual looping display module 1 and display module 2; The display module 1 is used to display the test results of the circuit function test; The display module 2 is used to display the test results of the circuit performance test.

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