Test instruction generation method, chip test method and device

Abstract

The invention provides a test instruction generation method and device and a chip test method and device, and relates to the technical field of chip test. According to the specific implementation scheme, the test instruction generation method comprises the steps that initial memory access addresses, first memory access instructions and initial instruction parameters for multiple threads in a target thread group are obtained; generating a second memory access instruction based on the initial instruction parameter, the initial memory access addresses of the plurality of threads and randomly generated address offset information; and in response to determining that at least two threads in the plurality of threads are abnormal when executing the first memory access instruction and the second memory access instruction at the same time, configuring a synchronization instruction between the first memory access instruction and the second memory access instruction to generate a test instruction for testing the chip, the synchronization instruction indicates an execution sequence of the plurality of threads for the first memory access instruction and the second memory access instruction.

Description

Technical Field

[0001] The present disclosure relates to the field of chip testing technology, and in particular to a test instruction generating method, a chip testing method and a device. Background Art

[0002] In a multi-threaded chip, all threads can access memory data in parallel, achieving high-speed, high-bandwidth data interaction between the computing unit and the storage unit. Therefore, during chip testing, whether the random combination and memory access range of memory access instructions can be covered becomes the key to effectively testing chip functions. Summary of the invention

[0003] The present disclosure provides a test instruction generation method, device, electronic device and storage medium.

[0004] According to one aspect of the present disclosure, a test instruction generation method is provided, comprising: obtaining initial memory access addresses, a first memory access instruction and initial instruction parameters for multiple threads in a target thread group; generating a second memory access instruction based on the initial instruction parameters, the initial memory access addresses of the multiple threads and randomly generated address offset information; and in response to determining that at least two of the multiple threads will have an exception when executing the first memory access instruction and the second memory access instruction at the same time, configuring a synchronization instruction between the first memory access instruction and the second memory access instruction to generate a test instruction for a test chip; the synchronization instruction indicates the execution order of the multiple threads for the first memory access instruction and the second memory access instruction.

[0005] According to another aspect of the present disclosure, a chip testing method is provided, comprising: executing a test instruction using a chip to be tested to obtain a first execution result; executing the test instruction using a simulator to obtain a second execution result; and generating a test result of the chip to be tested based on the first execution result and the second execution result; wherein the test instruction is generated based on the test instruction generation method described above.

[0006] According to another aspect of the present disclosure, a test instruction generating device is provided, including: an acquisition module, a first generating module and a second generating module.

[0007] The acquisition module is used to obtain initial memory access addresses, first memory access instructions and initial instruction parameters for multiple threads in the target thread group; wherein the initial memory access addresses of the multiple threads are randomly generated based on the capacity of the shared memory space.

[0008] The first generating module is used to generate a second memory access instruction based on an initial instruction parameter, initial memory access addresses of multiple threads and randomly generated address offset information.

[0009] The second generation module is used to configure a synchronization instruction between the first memory access instruction and the second memory access instruction in response to determining that at least two threads among the multiple threads will have an exception when executing the first memory access instruction and the second memory access instruction to generate a test instruction for testing the chip; the synchronization instruction indicates the execution order of the multiple threads for the first memory access instruction and the second memory access instruction.

[0010] According to another aspect of the present disclosure, a chip testing device is provided, including: a first execution module, a second execution module and a generation module.

[0011] The first execution module is used to execute the test instruction using the chip to be tested to obtain a first execution result.

[0012] The second execution module is used to execute the test instruction using the simulator to obtain a second execution result.

[0013] A generation module is used to generate a test result of the chip based on the first execution result and the second execution result; wherein the test instruction is generated based on the test instruction generation method described above.

[0014] According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method described above.

[0015] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable the computer to execute the method described above.

[0016] According to another aspect of the present disclosure, a computer program product is provided, comprising a computer program, wherein the computer program implements the method described above when executed by a processor.

[0017] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0019] Figure 1 An exemplary system architecture to which a test instruction generation method or a chip testing method and apparatus according to an embodiment of the present disclosure can be applied is schematically shown;

[0020] Figure 2A A schematic diagram schematically shows the allocation of shared storage space to each thread of a related example;

[0021] Figure 2B A schematic diagram schematically shows the allocation of shared storage space to each thread in an embodiment of the present disclosure;

[0022] Figure 3 A flowchart of a test instruction generating method according to an embodiment of the present disclosure is schematically shown;

[0023] Figure 4 A schematic diagram schematically shows a method of randomly generating a memory access address for a memory access instruction according to an embodiment of the present disclosure;

[0024] Figure 5 A schematic diagram schematically shows test instruction generation according to an embodiment of the present disclosure;

[0025] Fig. 6A A schematic diagram schematically shows a configuration synchronization instruction according to an embodiment of the present disclosure;

[0026] Figure 6B A schematic diagram schematically shows a configuration synchronization instruction according to another embodiment of the present disclosure;

[0027] Figure 6C A schematic diagram schematically shows a configuration synchronization instruction and an operation instruction according to an embodiment of the present disclosure;

[0028] Fig.6D A schematic diagram schematically shows a configuration synchronization instruction and an operation instruction according to another embodiment of the present disclosure;

[0029] Figure 7 A flowchart of a chip testing method according to an embodiment of the present disclosure is schematically shown;

[0030] Figure 8 A block diagram of a test instruction generating device according to an embodiment of the present disclosure is schematically shown;

[0031] Fig. 9 A block diagram schematically shows a chip testing device according to an embodiment of the present disclosure; and

[0032] Fig.10 A block diagram of an electronic device suitable for implementing a test instruction generating method according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0033] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0034] Since all threads in a multi-threaded bundle chip can access memory data in parallel and realize high-speed, high-bandwidth data interaction between computing power units and storage units, when using multi-threaded bundle chips, it is necessary to strictly manage the memory access addresses of each thread and control the memory access data flow of each thread to avoid unexpected address trampling. Address trampling refers to different threads performing different types of memory access operations on the same memory access address at the same time, causing memory address conflicts.

[0035] Therefore, during the chip testing process, how to cover the random combination and memory access range of memory access instructions becomes a difficulty in multi-threaded chip testing.

[0036] In view of this, the embodiment of the present disclosure provides a test instruction generation method, which uses the shared memory space as the random range of the memory access address, so that each thread can access the maximum address range supported by the hardware, and through the random combination of memory access instructions and memory access addresses, the full range of chip capabilities can be tested as much as possible. In addition, by accurately configuring synchronization instructions, data synchronization between different threads is achieved, thereby meeting the test requirements of data dependency scenarios between threads.

[0037] Figure 1 An exemplary system architecture to which the test instruction generation method and apparatus according to an embodiment of the present disclosure can be applied is schematically shown.

[0038] It should be noted that Figure 1 The examples shown are only examples of system architectures to which the embodiments of the present disclosure can be applied, in order to help those skilled in the art understand the technical content of the present disclosure, but do not mean that the embodiments of the present disclosure cannot be used in other devices, systems, environments or scenarios. For example, in another embodiment, an exemplary system architecture to which the test instruction generation method and apparatus can be applied may include a terminal device, but the terminal device may implement the test instruction generation method and apparatus provided by the embodiments of the present disclosure without interacting with the server.

[0039] like Figure 1 As shown, the system architecture 100 according to this embodiment may include: a terminal device 110 , a simulator 120 and a chip under test 130 .

[0040] The test instruction generation method provided in the embodiment of the present disclosure may be executed by the terminal device 110 to generate a test instruction for testing the function of the chip under test 130 .

[0041] Then, the simulator 120 is used to execute the test instruction and obtain the execution result R a At the same time, the chip under test 130 is used to execute the test instruction to obtain the execution result R b .

[0042] Next, by comparing the execution results R a And the execution result R b , and the test result is 101.

[0043] It should be understood that Figure 1 The number of simulators and terminal devices in the embodiment is only for illustration. Any number of simulators and terminal devices may be provided according to the implementation requirements.

[0044] In related examples, memory access is usually performed in a thread-exclusive manner, and memory access addresses between threads are controlled to be isolated from each other.

[0045] Figure 2A The diagram schematically shows the allocation of shared storage space to threads in a related example.

[0046] like Figure 2A As shown, the storage space that thread 1 can access is completely isolated from the storage space that other threads (thread 2 to thread n) can access. Therefore, when generating memory access instructions, there will be no address trampling problem between the memory access addresses of each memory access instruction.

[0047] However, the shared memory space in the chip is usually small. In the relevant examples, each thread is forced to allocate an independent memory space, and the shared memory space is used serially, which reduces the utilization rate of the shared memory space. In addition, the memory space that each thread can access is limited, and it cannot access the full range of address space supported by the hardware.

[0048] In addition, in actual application scenarios, there may be data dependencies between the threads of the chip. In this case, the test instructions generated in the relevant examples by isolating the memory access addresses between the threads will not be applicable to the scenario of verifying storage data dependencies.

[0049] In view of this, the embodiment of the present disclosure adopts a method in which all threads in a thread block share storage space, thereby improving the utilization rate of the shared storage space and meeting the testing requirements of scenarios in which there is data dependency between threads.

[0050] Figure 2B The diagram schematically shows the allocation of shared storage space to each thread according to an embodiment of the present disclosure.

[0051] like Figure 2B As shown, in the shared memory space, the memory space is no longer divided, and the memory access address range of thread 1 to thread n is the entire shared memory space.

[0052] Since there is a certain regularity in the intervals between the memory access addresses of each thread in the relevant examples, the randomness verification of the memory access addresses is not sufficient.

[0053] Therefore, the embodiments of the present disclosure can further improve the randomness of the memory access address by dividing the random initial memory access address range in the shared storage space and reserving some space before and after the initial memory access address range so as to randomly offset the memory access address.

[0054] Figure 3 The flowchart of the test instruction generating method according to the embodiment of the present disclosure is schematically shown.

[0055] like Figure 3 As shown, the method 300 may include operations S310 to S330.

[0056] In operation S310 , initial memory access addresses, first memory access instructions, and initial instruction parameters for a plurality of threads in a target thread group are obtained.

[0057] In operation S320 , a second memory access instruction is generated based on the initial instruction parameter, initial memory access addresses of the plurality of threads, and randomly generated address offset information.

[0058] In operation S330, in response to determining that an exception will occur when at least two threads among the plurality of threads execute the first memory access instruction and the second memory access instruction simultaneously, a synchronization instruction is configured between the first memory access instruction and the second memory access instruction to generate a test instruction for testing the chip.

[0059] According to an embodiment of the present disclosure, the target thread group may be a thread block or a thread warp. A thread block may include multiple thread warps. A thread warp may include multiple threads.

[0060] In some embodiments, the initial memory access addresses of the multiple threads are randomly generated based on the capacity of the shared memory space. The capacity of the shared memory space can be expressed as sm_size, and the random range of the initial memory access addresses can be controlled to be reserved_size~sm_size-reserved_size.

[0061] For example, the capacity of the shared storage space can be 100, and the reserved offset space (reserved_size) can be 20. The reserved offset space can share both ends of the memory space so that the initial memory access address can be offset positively or negatively. The random range of the initial memory access address can be 20~100.

[0062] According to an embodiment of the present disclosure, the initial instruction parameter may be a memory access instruction parameter randomly determined from a memory access instruction pool. The initial instruction parameter may include an instruction type, such as load or store.

[0063] In the embodiment of the present disclosure, the randomly generated address offset information may include: a positive address offset or a negative address offset. The target memory access address may be calculated according to formula (1):

[0064] T_addr=init_addr+rand_offset (1)

[0065] Among them, init_addr represents the initial memory access address, rand_offset represents the address offset, and T_addr represents the target memory access address.

[0066] It should be noted that the address offset information of each thread is the same, but the initial memory access address of each thread is random. Therefore, it is necessary to constrain the random range of the address offset so that the target memory access address of each thread is still within the maximum memory access range of each thread, which can be 0~sm_size-1. The constraint condition can be 0≤init_addr+rand_offset≤sm_size-1.

[0067] For example, if the capacity of the shared storage space is 100, the initial memory access address of thread 0 is 36, and the initial memory access address of thread 1 is 78, according to the above constraints, the random range of the address offset for thread 0 is -36≤rand_offset≤63; the random range of the address offset for thread 1 is -78≤rand_offset≤21. Then, the random range of the address offset of each thread can be determined by taking the intersection of the random ranges of the address offsets of each thread: -36≤rand_offset≤21.

[0068] In an embodiment of the present disclosure, the test instruction may include multiple memory access instructions, and the first memory access instruction may be a memory access instruction that has been generated before the second memory access instruction is generated. Since the initial memory access address of each thread is randomly generated within the same range, based on the randomly generated address offset, the target memory access addresses of two threads may be the same.

[0069] For example, for the first memory access instruction, the initial memory access address of thread 0 may be 20, and the initial memory access address of thread 1 may be 30. Based on the randomly generated address offset +10, the target memory access address of thread 0 may be 30, and the target memory access address of thread 1 may be 40. For the second memory access instruction, the initial memory access address of thread 0 may be 40, and the initial memory access address of thread 1 may be 50. Based on the randomly generated address offset -20, the target memory access address of thread 0 may be 20, and the target memory access address of thread 1 may be 30.

[0070] At this time, the target memory access address of thread 0 in the first memory access instruction and the target memory access address of thread 1 in the second memory access instruction are both 30, which means that at the same time, when thread 0 executes the first memory access instruction and thread 1 executes the second memory access instruction, they will simultaneously access the data in the storage space with the target memory access address 30, which may cause address trampling and cause abnormal instruction execution.

[0071] Therefore, a synchronization instruction may be configured between the first memory access instruction and the second memory access instruction to generate a test instruction for testing the chip. The synchronization instruction indicates the execution order of the first memory access instruction and the second memory access instruction of multiple threads.

[0072] For example, the synchronization instruction may indicate that the second memory access instruction must wait until all threads have completed executing the first memory access instruction before it can be executed.

[0073] By randomly generating the initial memory access address and address offset information in the shared memory space, the utilization rate of the shared memory space is improved, the randomness of the memory access instruction is increased, and the test instruction can verify the all-round capabilities of the chip. When it is determined that at least two threads among multiple threads will have an exception when executing the first memory access instruction and the second memory access instruction at the same time, a synchronization instruction is configured to achieve data synchronization between different threads, so that the test instruction can be executed normally and can meet the test requirements of application scenarios with data dependence.

[0074] In some embodiments, the method also includes performing the following operations before obtaining the initial memory access addresses for multiple threads in the same thread group: determining the range of the memory access address of each thread based on the capacity of the shared storage space and the reserved space parameters of the target thread group; randomly generating the initial memory access address for each thread based on the range of the memory access address of each thread; and storing the initial memory access address for each thread in the global storage space based on a predetermined mapping relationship.

[0075] For example, the capacity of the shared storage space can be 100, the reserved space parameter can be 30, and the range of the memory access address of each thread can be determined to be 30 to 70. Then, an address parameter can be randomly generated for each thread from the range of the memory access address, and the address parameter of each thread can be different. For example, the random address parameter of thread 1 can be 30, and the random address parameter of thread 2 can be 34.

[0076] According to an embodiment of the present disclosure, the predetermined mapping relationship indicates a corresponding relationship between an address parameter of a shared storage space and a memory access address of a global storage space.

[0077] For example, the memory access address of the global storage space corresponding to address parameter 30 may be A, and the memory access address of the global storage space corresponding to address parameter 34 may be A+4. When the global load instruction is executed, thread 1 can load the data in the memory access address A to obtain the initial memory access address and complete the initialization operation. All threads in the target thread group share the shared memory space, further improving the utilization of the shared memory space. The obtained initial memory access address can be stored in a register, further reducing the number of memory accesses.

[0078] According to an embodiment of the present disclosure, generating a second memory access instruction based on initial instruction parameters, initial memory access addresses of multiple threads and randomly generated address offset information may include the following operations: randomly generating address offset information based on the initial memory access addresses of multiple threads and the capacity of a shared storage space of multiple threads; generating target memory access addresses of multiple threads based on the initial memory access addresses of multiple threads and the randomly generated address offset information by executing calculation instructions; and generating a second memory access instruction based on the initial instruction parameters and the target memory access addresses of multiple threads.

[0079] In some embodiments, the initial memory access address may be an array including the initial memory access addresses of all threads. The address offset information randomly generated for each thread may be the same. The target memory access address may be an array including the target memory access addresses of all threads.

[0080] Figure 4 A schematic diagram of randomly generating a memory access address for a memory access instruction according to an embodiment of the present disclosure is schematically shown.

[0081] like Figure 4 As shown, the initial instruction parameter 412 of the memory access instruction In1 may include: an instruction type and an instruction name. The instruction type of the memory access instruction In1 is load.

[0082] First, in the shared storage space 411, the reserved address offset space size may be 20, and the random range of the initial memory access address may be 20 to 100. A random initial memory access address may be allocated to each thread within the random range. The random initial memory access addresses of each thread may not be exactly the same. For example, the initial memory access address of thread 0 is 20, the initial memory access address of thread 1 is 65, and the initial memory access address of thread n is 27.

[0083] Then, based on the constraints described above, the randomly generated address offset can be -10. Then, the target memory access address can be generated by executing the calculation instruction: the target memory access address of thread 0 is 10, the target memory access address of thread 1 is 55, and the initial memory access address of thread n is 17.

[0084] Finally, the target memory access address is combined with the initial instruction parameter 412 of the memory access instruction In1 to generate a memory access instruction 413 .

[0085] Since the initial memory access address and address offset information are randomly generated, the randomness of the memory access address and the randomness of the memory access instruction combination are increased, so that the test instruction can test the full range of processing capabilities of the chip as much as possible.

[0086] In some embodiments, the first memory access instruction includes a first operation type and a plurality of first memory addresses to be accessed; the second memory access instruction includes a second operation type and a plurality of second memory addresses to be accessed. When the operation types of the first memory access instruction and the second memory access instruction are data dependent, it is necessary to consider whether there is an address trampling problem.

[0087] For example, the operation type of the memory access instruction In1 is load, and the operation type of the memory access instruction In2 is load. Even if different threads execute load operations on data in the same storage area at the same time, it will not cause address trampling problems.

[0088] Therefore, the embodiment of the present disclosure jointly determines whether an exception will occur when different threads execute the first memory access instruction and the second memory access instruction simultaneously from two dimensions: data dependency and memory access address.

[0089] According to an embodiment of the present disclosure, determining that at least two threads among a plurality of threads will have an exception when executing a first memory access instruction and a second memory access instruction simultaneously may include the following operations: determining whether there is a data dependency between the first memory access instruction and the second memory access instruction based on a first operation type and a second operation type; and in response to determining that there is a data dependency between the first memory access instruction and the second memory access instruction, and at least one first memory address to be accessed among a plurality of first memory access addresses is the same as at least one second memory address to be accessed among a plurality of second memory addresses to be accessed, determining that at least two threads will have an exception when executing the first memory access instruction and the second memory access instruction.

[0090] Figure 5 A schematic diagram of test instruction generation according to an embodiment of the present disclosure is schematically shown.

[0091] like Figure 5 As shown, in S330, for the memory access instruction In1531 and the memory access instruction In2532, operation S331 is first performed to determine whether there is data dependency.

[0092] For example, when the operation type of the memory access instruction In1531 and the operation type of the memory access instruction In2532 satisfy the instruction types that are different and are load types, it can be determined that there is data dependency.

[0093] If it is determined that there is data dependency, operation S332 is performed. If it is determined that there is no data class, it is determined that at least two threads will not have an exception when executing the first memory access instruction and the second memory access instruction. The memory access instruction In1531 and the memory access instruction In2532 are directly combined to obtain a test instruction TIn1533.

[0094] In operation S332, it is determined whether there is at least one set of the same memory access addresses in the memory access address array in the first memory access instruction and the memory access address array in the second memory access instruction. If so, it is determined that at least two threads will have an exception when executing the first memory access instruction and the second memory access instruction. In addition, a synchronization instruction is configured between the memory access instruction In1531 and the memory access instruction In2532 to limit the execution order of the memory access instructions In1531 and the memory access instructions In2532 of each thread, and a test instruction TIn2534 is generated.

[0095] If not, it is determined that at least two threads will not have an exception when executing the first memory access instruction and the second memory access instruction. In addition, the memory access instruction In1531 and the memory access instruction In2532 are directly combined to obtain a test instruction TIn1533.

[0096] By using the two dimensions of data dependency and memory access address to determine whether exceptions will occur when different threads execute different memory access instructions at the same time, the abnormal conditions that may occur during the execution of the test instructions are verified in advance, further improving the executable degree of the test instructions.

[0097] The synchronization instruction indicates the execution order of multiple threads for the first memory access instruction and the second memory access instruction. In some embodiments, the synchronization instruction can be generated based on the data dependency between the first memory access instruction and the second memory access instruction and the identifiers of multiple threads.

[0098] For example, WAW (Write After Write), WAR (Write After Read), and RAW (Read After Write) are three types of data dependencies in the instruction pipeline, which describe the conflicts that may arise between instructions due to data dependencies.

[0099] Taking RAW as an example, the memory access instruction InA needs to read the data written by the memory access instruction InB, but the memory access instruction InB has not completed the writing operation, resulting in address trampling. Therefore, the configured synchronization instruction is: wait for the memory access instruction InB to complete the data writing operation for the storage area corresponding to a certain memory access address before executing the memory access instruction InB.

[0100] In some embodiments, the synchronization instruction may be directed to all threads involved in the memory access instruction InA and the memory access instruction InB, or may be directed only to target threads that may cause conflicts.

[0101] Based on the data dependency configuration, synchronization instructions are configured between each memory access instruction to achieve data synchronization between different threads, thereby meeting the testing requirements of scenarios with data dependencies.

[0102] According to an embodiment of the present disclosure, generating a synchronization instruction based on the data dependency between a first memory access instruction and a second memory access instruction and the identifiers of multiple threads may include the following operations: determining the identifiers of at least two first target threads from the identifiers of multiple threads; wherein the first memory address to be accessed and the second memory address to be accessed for at least two first target threads are the same; and generating a synchronization instruction based on the data dependency and the identifiers of at least two first target threads.

[0103] For example, in the memory access instruction InA, thread 1 performs a load operation on the storage area corresponding to the target memory access address 35, and in the memory access instruction InB, thread 2 performs a store operation on the storage area corresponding to the target memory access address 35. When a synchronization instruction is configured between the memory access instruction InB and the memory access instruction InA, the synchronization instruction can only limit thread 2 to wait for thread 1 to complete the execution of the memory access instruction InA when executing the memory access instruction InB.

[0104] Synchronization instructions are configured for threads with the same memory access address, which reduces the waiting time consumed by other threads to achieve data synchronization and further improves test efficiency.

[0105] The following is based on Figure 6A to Figure 6D Detailed description of the configuration location of the synchronization instruction in the test instruction.

[0106] In some embodiments, configuring a synchronization instruction between a first memory access instruction and a second memory access instruction to generate a test instruction for testing a chip may include the following operations: generating a test instruction by configuring the synchronization instruction after the first memory access instruction and adjacent to the first memory access instruction.

[0107] Fig. 6A A schematic diagram of configuring synchronization instructions according to an embodiment of the present disclosure is schematically shown.

[0108] like Fig. 6A As shown, in embodiment 600A, for threads 0 to n: the memory addresses to be accessed of memory access instruction In1 are 35, 30, ..., 66 respectively; the memory addresses to be accessed of memory access instruction In2 are 10, 40, ..., 100 respectively. In the case where there is data dependency between memory access instruction In1 and memory access instruction In3, when randomly generating a memory access address for memory access In3, since the memory address to be accessed for thread 0 in memory access instruction In3 is 30, which is the same as the memory address to be accessed for thread 1 of memory access instruction In1, a synchronization instruction can be configured between memory access instruction In1 and memory access instruction In2 to generate a test instruction 534A, so as to restrict each thread to execute memory access instruction In2 only after executing memory access instruction In1. Data consistency between threads before executing memory access instruction In2 is achieved, and the predictability of the execution result of the test instruction is further improved.

[0109] In some embodiments, configuring a synchronization instruction between a first memory access instruction and a second memory access instruction to generate a test instruction for testing a chip may include the following operations: generating a test instruction by configuring the synchronization instruction before the second memory access instruction and adjacent to the second memory access instruction.

[0110] Figure 6B A schematic diagram of configuring synchronization instructions according to another embodiment of the present disclosure is schematically shown.

[0111] like Figure 6B As shown, in embodiment 600B, the difference from embodiment 600A is that a synchronization instruction is configured between memory access instruction In2 and memory access instruction In3 to generate a test instruction 534B, so as to restrict each thread to execute memory access instruction In3 only after completing execution of memory access instruction In1 and memory access instruction In2. It can be understood that in the test instruction 534B, each thread can execute memory access instruction In1 and memory access instruction In2 in parallel at the same time.

[0112] In this embodiment 600B, the memory access address of each thread in the memory access instruction In2 is different from the memory access address of each thread in the memory access instruction In1, so there is no need to perform data synchronization. Since the configuration position of the synchronization instruction will affect the cache efficiency, only performing data synchronization on the previous memory access instruction before the memory access instruction that needs to perform data synchronization is executed can effectively improve the cache efficiency.

[0113] In some embodiments, based on the requirements of the test scenario, certain test instructions only need to be executed by some threads. Therefore, based on the initial instruction parameters, at least two second target threads to execute the second memory access instruction can be determined from multiple threads; based on the identifiers of the at least two second target threads, an operation instruction is generated; and based on the initial instruction parameters, the initial memory access addresses of the at least two target threads and the randomly generated address offset information, a second memory access instruction is generated.

[0114] According to an embodiment of the present disclosure, the operation instruction is used to shut down threads other than at least two second target threads among the multiple threads.

[0115] In some embodiments, the initial instruction parameter may include a target thread for executing the memory access instruction, for example, thread 0 and thread 1. The target thread group may include threads 0 to N, and the operation instruction is used to shut down threads 2 to N, which can be understood as threads 2 to N not needing to execute the memory access instruction.

[0116] Therefore, the second memory access instruction only includes the target memory access addresses of thread 0 and thread 1.

[0117] Figure 6C A schematic diagram schematically shows configuration synchronization instructions and operation instructions according to an embodiment of the present disclosure.

[0118] like Figure 6C As shown, in this embodiment 600C, the memory addresses to be accessed in the memory access instruction In3 include: the memory address to be accessed for thread 0 is 30, and the memory address to be accessed for thread 1 is 35. In the case where the memory access instruction In3 and the memory access instruction In1 are data dependent, since the memory address to be accessed for thread 0 in the memory access instruction In3 is the same as the memory address to be accessed in the memory access instruction In1, in addition to configuring the synchronization instruction, the operation instruction also needs to be configured to generate the test instruction 534C.

[0119] It should be noted that since the operation instruction is used to close the thread, the closed thread will no longer execute any subsequent memory access instruction for any memory access instruction following the operation instruction. Therefore, the location of the operation instruction can be configured according to actual test requirements.

[0120] In this embodiment 600C, the synchronization instruction is configured after the memory access instruction In2, indicating that each thread needs to wait for the memory access instruction In1 and the memory access instruction In2 before executing the operation instruction. At this time, thread 0~thread N can all execute the memory access instruction In1 and the memory access instruction In2. The insertion of the operation instruction will not affect the memory access instructions other than the memory access instruction In3, which not only meets the memory access test requirements for special threads in special test scenarios, but also reduces the impact of special test scenarios on universal memory access instructions.

[0121] In some embodiments, the test instruction may be generated by configuring the operation instruction before the second memory access instruction and adjacent to the second instruction to be generated.

[0122] Fig.6D A schematic diagram schematically shows configuration synchronization instructions and operation instructions according to another embodiment of the present disclosure.

[0123] like Fig.6D As shown, the difference between the embodiment 600D and the embodiment 600C is that the memory access instruction In2 and the memory access instruction In3 are only executed by thread 0 and thread 1. At this time, the operation instruction can be configured before the memory access instruction In2, and the synchronization instruction can be configured before the memory access instruction In3 to generate the test instruction 534D.

[0124] By configuring the operation instruction to close a specific thread, in the subsequent memory access instruction generation process, only whether there is address trampling between the specific thread and the specific thread can be checked, which further improves the generation efficiency of the test instruction.

[0125] Figure 7 The flowchart of the chip testing method according to the embodiment of the present disclosure is schematically shown.

[0126] like Figure 7 As shown, the method 700 may include operations S710 to S730.

[0127] In operation S710, a test instruction is executed using a chip to be tested to obtain a first execution result.

[0128] In operation S720, the test instruction is executed by using the simulator to obtain a second execution result.

[0129] In operation S730 , a test result of the chip to be tested is generated based on the first execution result and the second execution result.

[0130] According to an embodiment of the present disclosure, a test instruction is generated based on the method in any of the embodiments described above.

[0131] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision, disclosure and application of user personal information involved comply with the provisions of relevant laws and regulations, take necessary confidentiality measures, and do not violate public order and good morals.

[0132] When the difference between the first execution result and the second execution result is smaller than a predetermined threshold or the number of items in which the first execution result and the second execution result differ is smaller than a predetermined threshold, it can be determined that the test result is that the chip to be tested is qualified.

[0133] Since the test instruction has verified whether there is a conflict in the memory access addresses between threads during the generation process, the test efficiency is further improved.

[0134] Since the memory access addresses of each memory access instruction are randomly generated in the shared memory space during the test instruction generation process, the coverage of memory access data in the test process is expanded, so that the comprehensive processing capabilities of the chip under test can be tested and the accuracy of the test is improved.

[0135] Figure 8 The block diagram of a test instruction generating device according to an embodiment of the present disclosure is schematically shown.

[0136] like Figure 8 As shown, the test instruction generating device 800 may include: an acquisition module 810 , a first generating module 820 and a second generating module 830 .

[0137] The acquisition module 810 is used to acquire initial memory access addresses, first memory access instructions and initial instruction parameters for multiple threads in the target thread group; wherein the initial memory access addresses of the multiple threads are randomly generated based on the capacity of the shared storage space.

[0138] The first generating module 820 is used to generate a second memory access instruction based on the initial instruction parameters, the initial memory access addresses of multiple threads and the randomly generated address offset information.

[0139] The second generation module 830 is used to configure a synchronization instruction between the first memory access instruction and the second memory access instruction in response to determining that an exception will occur when at least two threads among the multiple threads execute the first memory access instruction and the second memory access instruction at the same time, so as to generate a test instruction for testing the chip; the synchronization instruction indicates the execution order of the multiple threads for the first memory access instruction and the second memory access instruction.

[0140] According to an embodiment of the present disclosure, the first memory access instruction includes a first operation type and a plurality of first memory addresses to be accessed; the second operation type and the second memory access instruction include a plurality of second memory addresses to be accessed.

[0141] The second generating module includes a first determining submodule and a second determining submodule.

[0142] The first determining submodule is used to determine whether there is a data dependency relationship between the first memory access instruction and the second memory access instruction based on the first operation type and the second operation type.

[0143] The second determination submodule is used to determine that an exception will occur when at least two threads execute the first memory access instruction and the second memory access instruction in response to determining that there is a data dependency between the first memory access instruction and the second memory access instruction, and at least one first memory address to be accessed among the multiple first memory access addresses is the same as at least one second memory address to be accessed among the multiple second memory addresses to be accessed.

[0144] According to an embodiment of the present disclosure, the test instruction generating device 1000 further includes: a third generating module, configured to generate a synchronization instruction based on a data dependency relationship between the first memory access instruction and the second memory access instruction and identifiers of multiple threads.

[0145] According to an embodiment of the present disclosure, the third generating module includes: a third determining submodule and a first generating submodule.

[0146] The third determining submodule is used to determine the identifiers of at least two first target threads from the identifiers of the multiple threads; wherein the first memory address to be accessed and the second memory address to be accessed for the at least two first target threads are the same.

[0147] The first generating submodule is used to generate a synchronization instruction based on the data dependency and the identifiers of at least two first target threads.

[0148] According to an embodiment of the present disclosure, the second generation module includes: a second generation submodule, configured to generate a test instruction by configuring a synchronization instruction before the second memory access instruction and adjacent to the second memory access instruction.

[0149] According to an embodiment of the present disclosure, the second generation module includes: a third generation submodule, configured to generate a test instruction by configuring a synchronization instruction after the first memory access instruction and adjacent to the first memory access instruction.

[0150] According to an embodiment of the present disclosure, the first generation module includes: a random submodule, a calculation submodule and a fourth generation submodule.

[0151] The random submodule is used to randomly generate address offset information based on the initial memory access addresses of multiple threads and the capacity of the shared storage space of multiple threads.

[0152] The calculation submodule is used to generate target memory access addresses of multiple threads based on initial memory access addresses of multiple threads and randomly generated address offset information by executing calculation instructions.

[0153] The fourth generating submodule is used to generate a second memory access instruction based on the initial instruction parameter and the target memory access addresses of the multiple threads.

[0154] According to an embodiment of the present disclosure, the test instruction generating device further includes: a first determining module, a fourth generating module and a fifth generating module.

[0155] The first determination module is used to determine at least two second target threads to execute the second memory access instruction from multiple threads based on the initial instruction parameters.

[0156] The fourth generating module is used to generate an operation instruction based on the identifiers of the at least two second target threads; wherein the operation instruction is used to close threads other than the at least two second target threads in the multiple threads.

[0157] The fifth generating module is used to generate a second memory access instruction based on the initial instruction parameter, the initial memory access addresses of at least two target threads and the randomly generated address offset information.

[0158] According to an embodiment of the present disclosure, the test instruction generating device further includes: a fifth generating module, configured to generate a test instruction by configuring the operation instruction at a position before the second memory access instruction and adjacent to the second instruction to be generated.

[0159] According to an embodiment of the present disclosure, the test instruction generating device further includes: a first determining module, a random module and a mapping module.

[0160] The first determination module is used to determine the range of the memory access address of each thread based on the capacity of the shared storage space and the reserved space parameter of the target thread group.

[0161] The random module is used to randomly generate an initial memory access address for each thread based on the range of the memory access address of each thread.

[0162] A mapping module is used to store the initial memory access address for each thread in the global memory space based on a predetermined mapping relationship; wherein the predetermined mapping relationship indicates the corresponding relationship between the initial memory access address of the shared memory space and the memory access address of the global memory space.

[0163] Fig. 9 The block diagram of a chip testing device according to an embodiment of the present disclosure is schematically shown.

[0164] like Fig. 9 As shown, the chip testing device 900 includes: a first execution module 910 , a second execution module 920 and a comparison module 930 .

[0165] The first execution module 910 is used to execute the test instruction using the chip to be tested to obtain a first execution result.

[0166] The second execution module 920 is used to execute the test instruction using the simulator to obtain a second execution result.

[0167] The comparison module 930 is used to generate a test result of the chip to be tested based on the first execution result and the second execution result; wherein the test instruction is generated based on the test instruction generation method described above.

[0168] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0169] According to an embodiment of the present disclosure, an electronic device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method as described above.

[0170] According to an embodiment of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause a computer to execute the method as described above.

[0171] According to an embodiment of the present disclosure, a computer program product includes a computer program, and when the computer program is executed by a processor, the computer program implements the method as described above.

[0172] Fig.10 A schematic block diagram of an example electronic device 1000 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0173] like Fig.10 As shown, the device 1000 includes a computing unit 1001, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1002 or a computer program loaded from a storage unit 1008 into a random access memory (RAM) 1003. In the RAM 1003, various programs and data required for the operation of the device 1000 can also be stored. The computing unit 1001, the ROM 1002, and the RAM 1003 are connected to each other via a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0174] A number of components in the device 1000 are connected to the I / O interface 1005, including: an input unit 1006, such as a keyboard, a mouse, etc.; an output unit 1007, such as various types of displays, speakers, etc.; a storage unit 1008, such as a disk, an optical disk, etc.; and a communication unit 1009, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 1009 allows the device 1000 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0175] The computing unit 1001 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 1001 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 1001 performs the various methods and processes described above, such as a method for generating a test instruction or a chip testing method. For example, in some embodiments, the method for generating a test instruction or a chip testing method may be implemented as a computer software program, which is tangibly included in a machine-readable medium, such as a storage unit 1008. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 1000 via the ROM 1002 and / or the communication unit 1009. When the computer program is loaded into the RAM 1003 and executed by the computing unit 1001, one or more steps of the method for generating a test instruction or a chip testing method described above may be executed. Alternatively, in other embodiments, the computing unit 1001 may be configured to execute the test instruction generation method or the chip testing method in any other appropriate manner (for example, by means of firmware).

[0176] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0177] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0178] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0179] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0180] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0181] A computer system may include a client and a server. The client and the server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises through computer programs running on respective computers and having a client-server relationship to each other. The server may be a cloud server, a server in a distributed system, or a server combined with a blockchain.

[0182] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0183] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A test instruction generation method, comprising: Obtaining initial memory access addresses, first memory access instructions, and initial instruction parameters for multiple threads in the target thread group; wherein the initial memory access addresses of the multiple threads are randomly generated based on the capacity of the shared storage space; Generate a second memory access instruction based on the initial instruction parameter, the initial memory access addresses of the plurality of threads and the randomly generated address offset information; In response to determining that at least two of the multiple threads will have an exception when executing the first memory access instruction and the second memory access instruction at the same time, a synchronization instruction is configured between the first memory access instruction and the second memory access instruction to generate a test instruction for testing the chip; the synchronization instruction indicates the execution order of the multiple threads for the first memory access instruction and the second memory access instruction.

2. The method according to claim 1, wherein: The first memory access instruction includes a first operation type and a plurality of first memory addresses to be accessed; the second operation type and the second memory access instruction include a plurality of second memory addresses to be accessed; The determining that an exception will occur when at least two threads among the plurality of threads execute the first memory access instruction and the second memory access instruction simultaneously includes: Based on the first operation type and the second operation type, determining whether there is a data dependency relationship between the first memory access instruction and the second memory access instruction; In response to determining that there is a data dependency between the first memory access instruction and the second memory access instruction, and at least one first memory address to be accessed among the multiple first memory access addresses is the same as at least one second memory address to be accessed among the multiple second memory addresses to be accessed, it is determined that an exception will occur when the at least two threads execute the first memory access instruction and the second memory access instruction.

3. The method according to claim 1 or 2, wherein: The method further comprises: The synchronization instruction is generated based on a data dependency relationship between the first memory access instruction and the second memory access instruction and identifiers of the multiple threads.

4. The method according to claim 3, wherein: The generating the synchronization instruction based on the data dependency relationship between the first memory access instruction and the second memory access instruction and the identifiers of the multiple threads includes: Determining the identifiers of at least two first target threads from the identifiers of the plurality of threads; wherein the first memory address to be accessed and the second memory address to be accessed for the at least two first target threads are the same; and The synchronization instruction is generated based on the data dependency and the identifiers of the at least two first target threads.

5. The method according to any one of claims 1 to 4, wherein: The step of configuring a synchronization instruction between the first memory access instruction and the second memory access instruction to generate a test instruction for testing the chip includes: The test instruction is generated by configuring the synchronization instruction before the second memory access instruction and at a position adjacent to the second memory access instruction.

6. The method according to any one of claims 1 to 4, wherein: The step of configuring a synchronization instruction between the first memory access instruction and the second memory access instruction to generate a test instruction for testing a chip function includes: The test instruction is generated by configuring the synchronization instruction at a position after the first memory access instruction and adjacent to the first memory access instruction.

7. The method according to claim 1, wherein: The generating a second memory access instruction based on the initial instruction parameter, the initial memory access addresses of the plurality of threads and the randomly generated address offset information comprises: Randomly generating the address offset information based on the initial memory access addresses of the multiple threads and the capacity of the shared memory space of the multiple threads; Generate target memory access addresses of the plurality of threads based on initial memory access addresses of the plurality of threads and randomly generated address offset information by executing a calculation instruction; and The second memory access instruction is generated based on the initial instruction parameter and the target memory access addresses of the multiple threads.

8. The method according to any one of claims 1 to 6, further comprising: Based on the initial instruction parameter, determining at least two second target threads to execute the second memory access instruction from the multiple threads; Based on the identifiers of the at least two second target threads, an operation instruction is generated; wherein the operation instruction is used to close threads other than the at least two second target threads among the multiple threads; as well as The second memory access instruction is generated based on the initial instruction parameter, the initial memory access addresses of the at least two target threads and the randomly generated address offset information.

9. The method according to claim 8, further comprising: The test instruction is generated by configuring the operation instruction at a position before the second memory access instruction and adjacent to the second waiting instruction.

10. The method according to any one of claims 1 to 9, further comprising, before obtaining the initial memory access addresses for multiple threads in the same thread group: Determining a memory access address range of each thread based on the capacity of the shared memory space and the reserved space parameter of the target thread group; Based on the range of memory access addresses of each thread, randomly generate an initial memory access address for each thread; and Based on a predetermined mapping relationship, the initial memory access address for each thread is stored in the global memory space; wherein, The predetermined mapping relationship indicates the corresponding relationship between the initial memory access address of the shared memory space and the memory access address of the global memory space.

11. A chip testing method, comprising: Executing the test instruction using the chip to be tested to obtain a first execution result; Executing the test instruction using a simulator to obtain a second execution result; Based on the first execution result and the second execution result, a test result of the chip to be tested is generated; wherein the test instruction is generated based on the method described in any one of claims 1 to 12.

12. A test instruction generating device, comprising: An acquisition module, used to acquire initial memory access addresses, first memory access instructions and initial instruction parameters for multiple threads in a target thread group; wherein the initial memory access addresses of the multiple threads are randomly generated based on the capacity of the shared memory space; A first generating module, configured to generate a second memory access instruction based on an initial instruction parameter, initial memory access addresses of the plurality of threads and randomly generated address offset information; A second generation module is used to configure a synchronization instruction between the first memory access instruction and the second memory access instruction in response to determining that at least two threads among the multiple threads will have an exception when executing the first memory access instruction and the second memory access instruction, so as to generate a test instruction for testing the chip; the synchronization instruction indicates the execution order of the multiple threads for the first memory access instruction and the second memory access instruction.

13. A chip testing device, comprising: A first execution module, used to execute the test instruction using the chip to be tested to obtain a first execution result; A second execution module, used for executing the test instruction by using a simulator to obtain a second execution result; A comparison module, used to generate a test result of the chip based on the first execution result and the second execution result; wherein the test instruction is generated based on the method described in any one of claims 1 to 10.

14. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 11.

15. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-11.

16. A computer program product comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 11.

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