Demodulation circuit and demodulation method of Hall sensor self-calibration loop

Abstract

The invention discloses a demodulation circuit of a Hall sensor self-calibration loop and a demodulation method thereof, and relates to the technical field of Hall sensor design. The demodulation circuit is composed of a differential operational amplifier, a plurality of control switches, a capacitor and a resistor, on and off of the switches are controlled through different switch control signals, and the demodulation circuit can work in a sampling mode and an extraction mode respectively. In a voltage acquisition mode, different acquisition branches are matched with a plurality of sampling phases to store combined information of a target voltage component and an interference voltage component in capacitors of different acquisition branches, and operation output of acquired voltage is realized in a voltage extraction mode. According to the demodulation circuit, mismatch in the charge transfer process is reduced, and the sampling precision of the demodulation circuit is improved.

Description

Technical Field

[0001] The invention relates to the technical field of Hall sensor design, and in particular to a demodulation circuit and a demodulation method of a Hall sensor self-calibration loop. Background Art

[0002] Conventional open-loop sensor architectures are unable to meet the low-sensitivity error requirements under different environments and working conditions, and require real-time adjustment of the self-calibration loop to achieve high-precision sensitivity performance. The demodulation circuit used in the self-calibration loop is the key module responsible for extracting the voltage related to the Hall sensitivity detection.

[0003] In the application of Hall sensor integrated circuit chips, in order to achieve high-precision sensitivity performance under different working conditions, the Hall sensor chip can adjust the Hall sensitivity in real time through a self-calibration loop to suppress the impact of the chip environment and working conditions on the performance. In order to adjust the Hall sensitivity in real time, the self-calibration loop needs to continuously detect electrical information that can characterize the Hall sensitivity. The Hall voltage output by the Hall disk depends on its ability to sense the magnetic field and the magnitude of the sensed magnetic field. Since the external magnetic field of the chip will change during application, the self-calibration loop architecture needs to generate a relatively constant reference magnetic field internally, and then use the demodulation circuit to extract the voltage component and other components related to the reference magnetic field, and finally complete the detection and adjustment.

[0004] Therefore, in the entire loop calibration process, a demodulation circuit that meets reasonable demodulation logic and low demodulation error is urgently needed to achieve high-precision sensitivity performance of the Hall sensor. Summary of the invention

[0005] The present invention provides a demodulation circuit and a demodulation method of a Hall sensor self-calibration loop, so as to solve the problem of how to accurately extract the reference magnetic field related voltage of the self-calibration loop.

[0006] The present invention is achieved through the following technical solutions:

[0007] In a first aspect of the present invention, a demodulation circuit of a Hall sensor self-calibration loop is provided, comprising a differential operational amplifier, two groups of acquisition circuits, and two groups of output circuits; each group of the acquisition circuits comprises two input control switches, four acquisition branches and a first output control switch;

[0008] In each group of the acquisition circuits, one input control switch is connected between the demodulation circuit inp input node and the input end of each acquisition branch, and another input control switch is connected between the demodulation circuit inn input node and the input end of each acquisition branch;

[0009] Each of the acquisition branches includes a capacitor and four power switches S5 to S8, one end of the power switch S5 is connected to the input control switch as the input end of the acquisition branch, and the other end is connected in series with the capacitor and the power switch S6 in sequence, the other end of the power switch S6 is used as the output end of the acquisition branch, the power switch S7 is connected in parallel with the power switch S6, and one end of the power switch S8 is connected between the power switch S5 and the capacitor;

[0010] In one group of acquisition circuits, the output end of each acquisition branch is connected to the positive input end of the differential operational amplifier, the other end of the power switch S8 is connected to the negative output end of the differential operational amplifier, and the first output control switch is connected between the output end of each acquisition branch and the negative output end of the differential operational amplifier;

[0011] In another group of acquisition circuits, the output end of each acquisition branch is connected to the negative input end of the differential operational amplifier, the other end of the power switch S8 is connected to the positive output end of the differential operational amplifier, and the first output control switch is connected between the output end of each acquisition branch and the positive output end of the differential operational amplifier;

[0012] Each group of the output circuits includes a resistor and a second output control switch connected in series, wherein one group of the output circuits is connected between the negative output terminal of the differential operational amplifier and the outn output node of the demodulation circuit, and the other group of the output circuits is connected between the positive output terminal of the differential operational amplifier and the outp output node of the demodulation circuit.

[0013] The demodulation circuit of the present invention is composed of a differential operational amplifier, multiple control switches, capacitors, and resistors. The switch is controlled to close and open by different switch control signals, and multiple phase working modes of the demodulation circuit can be realized. In the voltage acquisition mode, the combination information of the target voltage component and the interference voltage component is stored in the capacitors of different acquisition branches through different acquisition branches with multiple sampling phases, and the operation output of the acquisition voltage is realized in the voltage extraction mode. Such a demodulation logic has the ability to extract the target voltage component from multiple voltage components, and compared with the demodulation logic in which sampling and extraction are performed simultaneously, the demodulation circuit of the present invention reduces the mismatch in the charge transfer process and improves the sampling accuracy of the demodulation circuit.

[0014] Furthermore, the input control switch, the first output control switch, the power switches S5 to S8 in each group of the acquisition circuits, and the second output control switch in each group of the output circuits are the same MOS switch tubes.

[0015] Furthermore, the capacitance of each acquisition branch in each group of the acquisition circuits is the same, and the resistance of each group of the output circuits is the same.

[0016] Furthermore, the output circuit also includes a grounding capacitor, wherein one end of the grounding capacitor of one group of output circuits is grounded and the other end is connected to the demodulation circuit outn output node, and one end of the grounding capacitor of another group of output circuits is grounded and the other end is connected to the demodulation circuit outp output node.

[0017] A second aspect of the present invention provides a demodulation method for a demodulation circuit of a Hall sensor self-calibration loop according to any one of the first aspects of the present invention, characterized in that it comprises:

[0018] The on and off of the power switches S5 and S6 of the first acquisition branches L1 and L1' in the two acquisition circuits are simultaneously controlled by the clock signal ck1;

[0019] The on and off of the power switches S5 and S6 of the second acquisition branches L2 and L2' in the two groups of acquisition circuits are simultaneously controlled by the clock signal ck2;

[0020] The on and off of the power switches S5 and S6 of the third acquisition branches L3 and L3' in the two acquisition circuits are simultaneously controlled by the clock signal ck3;

[0021] The on and off of the power switches S5 and S6 of the fourth acquisition branches L4 and L4' in the two acquisition circuits are simultaneously controlled by the clock signal ck4;

[0022] The on and off of the second output control switches S4 and S4' of the two groups of output circuits are simultaneously controlled by the clock signal ck6;

[0023] The on and off of the first output control switches S3 and S3' in the two groups of acquisition circuits are simultaneously controlled by the clock signal ckr;

[0024] The input control switches S1 and S1' in the two sets of acquisition circuits are simultaneously controlled to be on and off by the clock signal ckpos;

[0025] The input control switches S2 and S2' in the two sets of acquisition circuits are simultaneously controlled to be on and off by the clock signal ckneg;

[0026] The on and off of the power switches S7 and S8 of all the acquisition branches L1 to L4 and L1' to L4' in the two acquisition circuits are simultaneously controlled by the clock signal ckflip;

[0027] By controlling the pulse timing of each clock signal, voltage sampling and voltage extraction are achieved respectively.

[0028] Furthermore, each clock signal uses a reference clock signal as a reference, and the reference clock signal is divided into 12 continuous phases of equal length A1-A6 and B1-B6, of which A1-A4 and B1-B4 are sampling phases, and A6 and B6 are extraction phases.

[0029] Furthermore, the clock signal ck1 is at a high level in phases A1 and B2, and at a low level at other times;

[0030] The clock signal ck2 is high in phases A2 and B1 and low at other times;

[0031] The clock signal ck3 is high in phases A3 and B4 and low at other times;

[0032] The clock signal ck4 is high in phases A4 and B3 and low at other times;

[0033] The clock signal ck6 is high in the A6 and B6 phases and low at the rest of the time;

[0034] The clock signal ckr is high in the A1-A4 and B1-B4 phases and low at other times;

[0035] The clock signal ckpos is high in phases A1, A2, B1, and B2, and low at other times;

[0036] The clock signal ckneg is high in phases A3, A4, B3, and B4, and low at other times;

[0037] The clock signal ckflip is high in the A5, A6, B5, and B6 phases, and is low at the rest of the time.

[0038] Furthermore, in the sampling phase, the difference between the amount of charge stored in the capacitors in the two sets of acquisition branches is expressed as:

[0039] Q i =C*V i

[0040] Where C represents the capacitance value, V i Indicates the differential input voltage of the demodulation circuit at acquisition phase i, Q i It represents the difference in the amount of charge stored in the capacitors of the two sets of acquisition branches at acquisition phase i, where i represents the phase A1, A2, A3, A4, B1, B2, B3 or B4.

[0041] Furthermore, in the extraction phase A6, the differential voltage between the positive output terminal and the negative output terminal of the differential operational amplifier, i.e., the extraction voltage, is expressed as:

[0042] V A6 =(V A1 +V A2 -V A3 -V A4 ) / 4;

[0043] V B6 =(VB1 +V B2 -V B3 -V B4 ) / 4;

[0044] Among them, V A6 、V B6 Respectively represent the extraction voltage in extraction phase A6 and B6, V A1 、V A2 、V A3 、V A4 Respectively represent the differential input voltage of the demodulation circuit under the acquisition phase A1, A2, A3, and A4, V B1 、V B2 、V B3 、V B4 They respectively represent the differential input voltage of the demodulation circuit in acquisition phases B1, B2, B3, and B4.

[0045] A third aspect of the present invention provides a Hall sensor self-calibration loop, characterized in that it comprises a demodulation circuit of the Hall sensor self-calibration loop as described in any one of the first aspects of the present invention.

[0046] Compared with the prior art, the present invention has the following advantages and beneficial effects: the present invention utilizes multiple phase working modes to realize combined sampling of target voltage components and interference voltage components, and then performs calculation processing to extract the target voltage components; utilizes the staggered phase control logic of the switching signal to realize the suppression of capacitor mismatch and improve the sampling accuracy of the demodulation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without creative work. In the drawings:

[0048] Figure 1 is a schematic diagram of a demodulation circuit of a Hall sensor self-calibration loop according to an embodiment of the present invention;

[0049] Figure 2 is a switch signal timing diagram of an embodiment of the present invention;

[0050] Figure 3 is a working principle diagram of a demodulation circuit in a sampling phase A1 according to an embodiment of the present invention;

[0051] Figure 4 It is a working principle diagram of a demodulation circuit in an embodiment of the present invention under extraction phase A6. DETAILED DESCRIPTION

[0052] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The exemplary embodiments of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention.

[0053] It should be noted that the terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to or inherent to other steps or units of the device.

[0054] The terms used in various embodiments of the present invention are only used for the purpose of describing specific embodiments and are not intended to limit various embodiments of the present invention. As used herein, the singular form is intended to also include the plural form, unless the context clearly indicates otherwise. Unless otherwise limited, all terms used here (including technical terms and scientific terms) have the same meaning as the meaning generally understood by those of ordinary skill in the art to which the various embodiments of the present invention belong. The terms (such as the terms defined in the dictionary generally used) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning, unless clearly defined in various embodiments of the present invention.

[0055] Example 1

[0056] like Figure 1 The figure shows a schematic diagram of a demodulation circuit of a Hall sensor self-calibration loop of the present invention. The demodulation circuit is composed of a differential operational amplifier OP, multiple control switches, multiple capacitors and resistors. The demodulation circuit structure is symmetrical, and all switches preferably use power switch tubes of the same specification, with the same capacitor size and the same resistor size.

[0057] Specifically, the structurally symmetrical demodulation circuit includes a differential operational amplifier, two sets of acquisition circuits and two sets of output circuits. The two sets of acquisition circuits use the same components, and the two sets of output circuits use the same components. Figure 1 Taking the first group (located at the top) of the acquisition circuit as an example, the acquisition circuit includes two input control switches S1 and S2, four identical acquisition branches L1-L4, and a first output control switch S3.

[0058] In the first group of acquisition circuits, one input control switch S1 is connected between the demodulation circuit inp input node and the input end of each acquisition branch (L1, L2, L3, L4), and the other input control switch S2 is connected between the demodulation circuit inn input node and the input end of each acquisition branch (L1, L2, L3, L4).

[0059] The second group of acquisition circuits also includes two input control switches S1' and S2', four identical acquisition branches L1' to L4', and a first output control switch S3'. One of the input control switches S2' is connected between the demodulation circuit inp input node and the input end of each acquisition branch (L1', L2', L3', L4'), and the other input control switch S1' is connected between the demodulation circuit inn input node and the input end of each acquisition branch (L1', L2', L3', L4').

[0060] Each group of acquisition circuits is provided with four acquisition branches, and each acquisition branch uses the same components, including a capacitor and four power switches S5 to S8. Taking the first acquisition branch L1 in the first group of acquisition circuits as an example, one end of the power switch S5 is used as the input end of the acquisition branch, connected to the input control switches S1 and S2, the other end of the power switch S5 is connected in series with the capacitor C and the power switch S6 in sequence, the other end of the power switch S6 is used as the output end of the acquisition branch, the power switch S7 is connected in parallel with the power switch S6, and one end of the power switch S8 is connected between the power switch S5 and the capacitor C.

[0061] What is different about each acquisition branch is the connection mode of the input and output ends. In the first group of acquisition circuits, the input end of each acquisition branch (L1, L2, L3, L4) is connected to the input control switches S1 and S2, the output end of each acquisition branch is connected to the positive input end pos of the differential operational amplifier OP, and is connected to one end of the first output control switch S3, the other end of the power switch S8 is connected to the negative output end vn of the differential operational amplifier OP, and the other end of the first output control switch S3 is connected to the negative output end vn of the differential operational amplifier OP. In the second group of acquisition circuits, the input end of each acquisition branch (L1', L2', L3', L4') is connected to the input control switches S1', S2', the output end of each acquisition branch is connected to the negative input end neg of the differential operational amplifier OP, and is connected to one end of the first output control switch S3', the other end of the power switch S8 is connected to the positive output end vp of the differential operational amplifier OP, and the other end of the first output control switch S3' is connected to the positive output end vp of the differential operational amplifier OP.

[0062] The two groups of output circuits are respectively connected between the two output terminals (vn, vp) of the differential operational amplifier OP and the two output nodes (outn, outp) of the demodulation circuit, and are used to output the voltage data sampled by the acquisition circuit. Figure 1 The upper one is the first output circuit, and the lower one is the second output circuit. Both the first output circuit and the second output circuit include a resistor R and a second output control switch (S4, S4') connected in series. The first group of output circuits is connected between the negative output terminal vn of the differential operational amplifier OP and the output node outn of the demodulation circuit, and the second group of output circuits is connected between the positive output terminal vp of the differential operational amplifier OP and the output node outp of the demodulation circuit.

[0063] The inp and inn input nodes of the demodulation circuit are connected to the differential output of the pre-amplifier in the Hall sensor signal chain to receive the modulated and amplified voltage signal; the outp and outn output nodes are connected to the differential input of the analog-to-digital converter (ADC) to convert the demodulated useful voltage signal into a corresponding digital signal for subsequent calibration.

[0064] Furthermore, the input control switches (S1, S2, S1', S2'), the first output control switches (S3, S3'), the second output control switches (S4, S4') and the power switches S5-S8 of each acquisition branch (L1-L4, L1'-L4') in the above-mentioned demodulation circuit all adopt MOS switch tubes.

[0065] Furthermore, the first group of output circuits and the second group of output circuits also include a grounding capacitor C1, one end of the grounding capacitor of the first group of output circuits is grounded, and the other end is connected to the demodulation circuit outn output node, and one end of the grounding capacitor of the second group of output circuits is grounded, and the other end is connected to the demodulation circuit outp output node.

[0066] The state of the MOS switch in the circuit depends on the switch control signal. When the switch control signal is at a high level, the two sides of the MOS switch can be regarded as a short circuit state, and when the switch control signal is at a low level, the two sides of the MOS switch can be regarded as an open circuit state. Therefore, the working mode of the above demodulation circuit can be realized by controlling the switch control signal.

[0067] In one implementation, in order to simplify the switch control logic, 9 different switch control signals are provided to control the switches of the above demodulation circuit. Figure 1 The relationship between the switch control signals and the switches shown in FIG. 1 is as follows. The nine switch control signals are ck1, ck2, ck3, ck4, ck6, ckr, ckpos, ckneg and ckflip. Specifically, each switch is controlled as follows.

[0068] The power switches S5 and S6 of the first acquisition branch L1 of the first acquisition circuit group and the power switches S5 and S6 of the first acquisition branch L1' of the second acquisition circuit group are controlled by the switch control signal ck1;

[0069] The power switches S5 and S6 of the second acquisition branch L2 of the first group of acquisition circuits and the power switches S5 and S6 of the second acquisition branch L2' of the second group of acquisition circuits are controlled by the switch control signal ck2;

[0070] The power switches S5 and S6 of the third acquisition branch L3 of the first acquisition circuit group and the power switches S5 and S6 of the third acquisition branch L3' of the second acquisition circuit group are controlled by the switch control signal ck3;

[0071] The power switches S5 and S6 of the fourth acquisition branch L4 of the first acquisition circuit group and the power switches S5 and S6 of the fourth acquisition branch L4' of the second acquisition circuit group are controlled by the switch control signal ck4;

[0072] The second output control switch S4 of the first group of output circuits and the second output control switch S4' of the second group of output circuits are both controlled by the switch control signal ck6;

[0073] The first output control switch S3' of the first group of acquisition circuits and the first output control switch S3' of the second group of acquisition circuits are both controlled by the switch control signal ckr;

[0074] The input control switches S1' of the first group of acquisition circuits and the input control switches S1' of the second group of acquisition circuits are controlled by the switch control signal ckpos;

[0075] The input control switch S2 of the first group of acquisition circuits and the input control switch S2' of the second group of acquisition circuits are both controlled by the switch control signal ckneg;

[0076] The power switches S7 and S8 in all the acquisition branches L1 to L4 and L1 ′ to L4 ′ in the first acquisition circuit group and the second acquisition circuit group are controlled by the switch control signal ckflip.

[0077] Different lines are connected through different switch control signals, so that the demodulation circuit works in two different modes: voltage acquisition and voltage extraction. The conduction and shutdown of different branches are controlled respectively through ck1, ck2, ck3, and ck4. The interlaced phase control logic of the switch signal is used to suppress capacitor mismatch and improve the sampling accuracy of the demodulation circuit.

[0078] Example 2

[0079] This embodiment provides a demodulation method of a demodulation circuit of a Hall sensor self-calibration loop, which is applied to the demodulation circuit of the Hall sensor self-calibration loop of embodiment 1. Figure 1 In this embodiment, 9 different switch control signals are used to control the on and off of each switch device in the demodulation circuit to realize the voltage collection and voltage extraction process of the demodulation circuit. The following methods are included:

[0080] The on and off of the power switches S5 and S6 of the first acquisition branches L1 and L1' in the two acquisition circuits are simultaneously controlled by the switch control signal ck1;

[0081] The on and off of the power switches S5 and S6 of the second acquisition branches L2 and L2' in the two groups of acquisition circuits are simultaneously controlled by the switch control signal ck2;

[0082] The switching control signal ck3 is used to simultaneously control the on and off of the power switches S5 and S6 of the third acquisition branches L3 and L3' in the two groups of acquisition circuits;

[0083] The on and off of the power switches S5 and S6 of the fourth acquisition branches L4 and L4' in the two acquisition circuits are simultaneously controlled by the switch control signal ck4;

[0084] The on and off of the second output control switches S4 and S4' of the two groups of output circuits are simultaneously controlled by the switch control signal ck6;

[0085] The on and off of the first output control switches S3 and S3' in the two groups of acquisition circuits are simultaneously controlled by the switch control signal ckr;

[0086] The on and off of the input control switches S1 and S1' in the two sets of acquisition circuits are simultaneously controlled by the switch control signal ckpos;

[0087] The on and off of the input control switches S2 and S2' in the two sets of acquisition circuits are simultaneously controlled by the switch control signal ckneg;

[0088] The on and off of the power switches S7 and S8 of all the acquisition branches L1 to L4 and L1' to L4' in the two groups of acquisition circuits are simultaneously controlled by the switch control signal ckflip.

[0089] On the basis of the above settings, by controlling the pulse timing of each switch control signal, the conduction and shutdown of each acquisition branch and output circuit are realized, thereby realizing voltage sampling and voltage extraction respectively.

[0090] Further, providing Figure 2As shown in the switch signal timing diagram, the switch control signals ckpos, ckneg, ck1, ck2, ck3, ck4, ck6, ckflip, and ckr all use the clock signal ck0 as a reference. The switch signal works periodically. Taking one cycle as an example, within one cycle, the reference switch control signal ck0 is divided into 12 continuous phases of equal length, A1-A6 and B1-B6, of which A1-A4 and B1-B4 are sampling phases, and A6 and B6 are extraction phases. With reference to the phase of ck0, the levels of each switch control signal are as follows.

[0091] The switch control signal ck1 is high level in phases A1 and B2, and low level at other times;

[0092] The switch control signal ck2 is high level in phases A2 and B1, and low level at other times;

[0093] The switch control signal ck3 is high level in phases A3 and B4, and low level at other times;

[0094] The switch control signal ck4 is high level in phases A4 and B3, and low level at other times;

[0095] The switch control signal ck6 is high level in the A6 and B6 phases and low level at other times;

[0096] The switch control signal ckr is high in the A1-A4 and B1-B4 phases and low in the rest of the time;

[0097] The switch control signal ckpos is high in phases A1, A2, B1, and B2, and low at other times;

[0098] The switch control signal ckneg is high in phases A3, A4, B3, and B4, and low at other times;

[0099] The switch control signal ckflip is at a high level in the A5, A6, B5, and B6 phases, and is at a low level at other times.

[0100] That is, in the sampling phases A1-A4 and B1-B4, each acquisition branch works separately, and the capacitor stores charge at this time. Taking the sampling phase A1 as an example, the working principle diagram of the demodulation circuit in the A1 phase is as follows: Figure 3 As shown. Since the output terminal vn of the differential operational amplifier OP is connected to the input terminal pos, and the output terminal vp is connected to the input terminal neg, the voltage difference information between inp and inn is stored in the capacitors C of the two first acquisition branches L1 and L1' in the form of charge. The expression of the difference in charge stored in the two capacitors C is:

[0101] Q A1 =C*V A1

[0102] Where C represents the capacitance of capacitor C, V A1 is the differential input voltage of the demodulation circuit at phase A1, Q A1 It represents the difference between the capacitance storage charges of the two first acquisition branches L1 and L1'.

[0103] Similarly, the expressions of charge storage information of sampling phases A2, A3, and A4 are:

[0104] Q A2 =C*V A2

[0105] Q A3 =C*V A3

[0106] Q A4 =C*V A4

[0107] Among them, V A2 、V A3 、V A4 Respectively represent the differential input voltage of the demodulation circuit at phases A2, A3, and A4, Q A2 The difference between the capacitance storage charges of the two second acquisition branches L2 and L2', Q A3 represents the difference in the capacitance storage charge of the two third acquisition branches L3 and L3', Q A4 It represents the difference between the capacitance storage charges of the two fourth acquisition branches L4 and L4'.

[0108] In phase A3 and phase A4, since the ckpos signal is low level and the ckneg signal is high level, the connection positions of the input terminals inp and inn are interchanged, and the storage polarity changes. The same is true for phases B3 and B4.

[0109] In the extraction phase, taking the extraction phase A6 as an example, the switch control signals ck6, ckflip, and ckpos are high level, and the other control signals are low level. The working principle diagram of the demodulation circuit in the extraction phase A6 is shown in FIG. Figure 4 As shown. Since the capacitors of each acquisition branch of the first acquisition circuit are simultaneously connected across the pos terminal and vn terminal of the differential operational amplifier OP, and the capacitors of each acquisition branch of the second acquisition circuit are simultaneously connected across the neg terminal and vp terminal of the differential operational amplifier OP, the phase A6 stage will release the charges stored in the sampling phases of phases A1 to A4 at the same time and concentrate them at the vp terminal and vn terminal. The differential voltage between the vp terminal and the vn terminal under the extraction phase is the extraction voltage, and the expression is:

[0110] V A6 =(Q A1 +Q A2 +QA3 +Q A4 ) / 4C=(V A1 +V A2 -V A3 -V A4 ) / 4

[0111] The demodulation circuit output voltage obtained in the extraction phase A6 includes the addition, subtraction and averaging operations of the information of the first four sampling phases. Such demodulation logic has the ability to extract the target voltage from multiple voltage components. Table 1 shows the demodulation results in the self-calibration loop using the demodulation circuit. Under this demodulation scheme, the demodulation circuit can extract the reference magnetic field voltage from multiple voltage components including the external magnetic field voltage, the reference magnetic field voltage and the offset voltage.

[0112] Table 1 Extraction phase working principle diagram

[0113]

[0114] The working state of the demodulation circuit in phase B1-B6 is similar to that in phase A1-A6. Four independent samplings are completed in B1-B4, and extraction is performed in B6. The calculation formula for the B6 extraction voltage can be expressed as:

[0115] V B6 =(V B1 +V B2 -V B3 -V B4 ) / 4

[0116] Among them, V B1 、V B2 、V B3 、V B4 They represent the differential input voltages of the demodulation circuit at phases B1, B2, B3, and B4 respectively.

[0117] The difference is that during phases B1 and B2, the order in which the control signals ck1 and ck2 are high is swapped compared to that during phases A1 and A2, and during phases B3 and B4, the order in which the control signals ck3 and ck4 are high is swapped compared to that during phases A1 and A2. Such interleaved control logic can make the first sampling and second sampling voltage information interleavedly stored in the two groups of capacitors C of the two first acquisition branches L1 and L1' and the two groups of capacitors C of the two second acquisition branches L2 and L2', and the third sampling and fourth sampling voltage information interleavedly stored in the two groups of capacitors C of the two third acquisition branches L3 and L3' and the two groups of capacitors C of the two fourth acquisition branches L4 and L4', further suppressing the capacitor mismatch effect between the same group of working capacitors.

[0118] A1~A6+B1~B6 is one extraction cycle, which is equivalent to the demodulation circuit alternately outputting the extraction results of A6 and B6 to the subsequent modules within one extraction cycle. The advantage of this is that the influence of capacitor mismatch is suppressed.

[0119] In the A5 and B5 phases, the outputs vp and vn of the differential operational amplifier OP also obtain the extracted voltage, but are not transmitted to outp and outn through the second output control switches S4 and S4'. This is done to ensure that the extraction time is sufficient, and there are two phase times of A5+A6 and B5+B6. Secondly, in terms of circuit implementation, it is easier to subdivide a small cycle A1~A6, B1~B6 in an extraction into an even number of continuous phases than an odd number of continuous phases.

[0120] Example 3

[0121] This embodiment provides a Hall sensor self-calibration loop, which includes the demodulation circuit of the Hall sensor self-calibration loop in Embodiment 1.

[0122] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A demodulation circuit for a Hall sensor self-calibration loop, characterized in that: It includes a differential operational amplifier, two groups of acquisition circuits and two groups of output circuits; each group of the acquisition circuits includes two input control switches (S1, S2, S1', S2'), four acquisition branches (L1-L4, L1'-L4') and a first output control switch (S3, S3'); In each group of the acquisition circuits, one input control switch (S1, S2') is connected between the demodulation circuit inp input node and the input end of each acquisition branch (L1-L4, L1'-L4'), and the other input control switch (S2, S1') is connected between the demodulation circuit inn input node and the input end of each acquisition branch (L1-L4, L1'-L4'); Each of the acquisition branches includes a capacitor and four power switches S5 to S8, one end of the power switch S5 is connected to the input control switch as the input end of the acquisition branch, and the other end is connected in series with the capacitor and the power switch S6 in sequence, the other end of the power switch S6 is used as the output end of the acquisition branch, the power switch S7 is connected in parallel with the power switch S6, and one end of the power switch S8 is connected between the power switch S5 and the capacitor; In one group of acquisition circuits, the output end of each acquisition branch (L1-L4) is connected to the positive input end (pos) of the differential operational amplifier, the other end of the power switch S8 is connected to the negative output end (vn) of the differential operational amplifier, and the first output control switch (S3) is connected between the output end of each acquisition branch (L1-L4) and the negative output end (vn) of the differential operational amplifier; In another group of acquisition circuits, the output end of each acquisition branch (L1'-L4') is connected to the negative input end (neg) of the differential operational amplifier, the other end of the power switch S8 is connected to the positive output end (vp) of the differential operational amplifier, and the first output control switch (S3') is connected between the output end of each acquisition branch (L1'-L4') and the positive output end (vp) of the differential operational amplifier; Each group of the output circuits includes a resistor and a second output control switch (S4, S4') connected in series, wherein one group of the output circuits is connected between the negative output terminal (vn) of the differential operational amplifier and the outn output node of the demodulation circuit, and the other group of the output circuits is connected between the positive output terminal (vp) of the differential operational amplifier and the outp output node of the demodulation circuit.

2. The demodulation circuit of the Hall sensor self-calibration loop according to claim 1, characterized in that: The input control switches (S1, S2, S1', S2'), the first output control switches (S3, S3'), the power switches S5-S8 in each group of the acquisition circuits, and the second output control switches (S4, S4') in each group of the output circuits are identical MOS switch tubes.

3. The demodulation circuit of the Hall sensor self-calibration loop according to claim 1, characterized in that: The capacitance of each acquisition branch (L1-L4, L1'-L4') in each group of the acquisition circuits is the same, and the resistance of each group of the output circuits is the same.

4. The demodulation circuit of the Hall sensor self-calibration loop according to claim 1, characterized in that: The output circuit also includes grounding capacitors, one end of which is grounded and the other end is connected to the demodulation circuit outn output node, and the other end of which is grounded and the other end is connected to the demodulation circuit outp output node.

5. A demodulation method for a demodulation circuit of a Hall sensor self-calibration loop according to any one of claims 1 to 4, characterized in that: include: The on and off of the power switches S5 and S6 of the first acquisition branches L1 and L1' in the two acquisition circuits are simultaneously controlled by the switch control signal ck1; The on and off of the power switches S5 and S6 of the second acquisition branches L2 and L2' in the two groups of acquisition circuits are simultaneously controlled by the switch control signal ck2; The switching control signal ck3 is used to simultaneously control the on and off of the power switches S5 and S6 of the third acquisition branches L3 and L3' in the two groups of acquisition circuits; The on and off of the power switches S5 and S6 of the fourth acquisition branches L4 and L4' in the two acquisition circuits are simultaneously controlled by the switch control signal ck4; The on and off of the second output control switches S4 and S4' of the two groups of output circuits are simultaneously controlled by the switch control signal ck6; The on and off of the first output control switches S3 and S3' in the two groups of acquisition circuits are simultaneously controlled by the switch control signal ckr; The on and off of the input control switches S1 and S1' in the two sets of acquisition circuits are simultaneously controlled by the switch control signal ckpos; The on and off of the input control switches S2 and S2' in the two sets of acquisition circuits are simultaneously controlled by the switch control signal ckneg; The on and off of the power switches S7 and S8 of all the acquisition branches L1 to L4 and L1' to L4' in the two acquisition circuits are simultaneously controlled by the switch control signal ckflip; Voltage sampling and voltage extraction are achieved by controlling the pulse timing of each switch control signal.

6. The demodulation method of the demodulation circuit of the Hall sensor self-calibration loop according to claim 5, characterized in that: Each switch control signal uses a reference switch control signal as a reference. The reference switch control signal is divided into 12 continuous phases of equal length A1-A6 and B1-B6, of which A1-A4 and B1-B4 are sampling phases, and A6 and B6 are extraction phases.

7. The demodulation method of the demodulation circuit of the Hall sensor self-calibration loop according to claim 6, characterized in that: The switch control signal ck1 is at a high level in phases A1 and B2, and is at a low level at other times; The switch control signal ck2 is high level in phases A2 and B1, and low level at other times; The switch control signal ck3 is high level in phases A3 and B4, and low level at other times; The switch control signal ck4 is high level in phases A4 and B3, and low level at other times; The switch control signal ck6 is high level in the A6 and B6 phases and low level at other times; The switch control signal ckr is high in the A1-A4 and B1-B4 phases and low in the rest of the time; The switch control signal ckpos is high in phases A1, A2, B1, and B2, and low at other times; The switch control signal ckneg is high in phases A3, A4, B3, and B4, and low at other times; The switch control signal ckflip is at a high level in the A5, A6, B5, and B6 phases, and is at a low level at other times.

8. The demodulation method of the demodulation circuit of the Hall sensor self-calibration loop according to claim 7, characterized in that: In the sampling phase, the difference between the amount of charge stored in the capacitors in the two sets of acquisition branches is expressed as: Q i =C*V i Where C represents the capacitance value, V i Indicates the differential input voltage of the demodulation circuit at acquisition phase i, Q i It represents the difference in the amount of charge stored in the capacitors of the two sets of acquisition branches at acquisition phase i, where i represents the phase A1, A2, A3, A4, B1, B2, B3 or B4.

9. The demodulation method of the demodulation circuit of the Hall sensor self-calibration loop according to claim 2, characterized in that: In the extraction phase, the differential voltage between the positive output terminal (vp) and the negative output terminal (vn) of the differential operational amplifier is the extraction voltage, which is expressed as: V A6 =(V A1 +V A2 -V A3 -V A4 ) / 4; V B6 =(V B1 +V B2 -V B3 -V B4 ) / 4; Among them, V A6 、V B6 Respectively represent the extraction voltage in extraction phase A6 and B6, V A1 、V A2 、V A3 、V A4 Respectively represent the differential input voltage of the demodulation circuit under the acquisition phase A1, A2, A3, and A4, V B1 、V B2 、V B3 、V B4 They respectively represent the differential input voltage of the demodulation circuit in acquisition phases B1, B2, B3, and B4.

10. A Hall sensor self-calibration loop, characterized in that: A demodulation circuit comprising a Hall sensor self-calibration loop as claimed in any one of claims 1 to 4.

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