Display device

Abstract

The embodiment of the invention provides a display device. The display device comprises a substrate, a transistor, a pixel electrode, a first conductive layer and a second conductive layer, the transistor and the pixel electrode are arranged on the substrate. The pixel electrode is electrically connected to the transistor. The first conductive layer and the second conductive layer are arranged on the pixel electrode. The second conductive layer is disposed between the pixel electrode and the first conductive layer. The first conductive layer has a first slit. The second conductive layer has a second slit. The two ends of the first slit and the two ends of the second slit comprise arc-shaped edges. The first slit and the second slit overlap the pixel electrode.

Description

[0001] Related divisional applications

[0002] This disclosure is a divisional application of the invention patent application with application number 202110179323.1 filed on February 9, 2021 and invention name “Display Device”. Technical Field

[0003] The present disclosure relates to an electronic device, and more particularly to an electronic display device with a display function. Background Art

[0004] As the application of electronic devices continues to expand, the development of display technology is also changing with each passing day. With the application of electronic devices and the habits or needs of users, the requirements for the structure and quality of electronic devices are getting higher and higher, and electronic devices are facing different problems. Therefore, the research and development of electronic devices must be continuously updated and adjusted. Summary of the invention

[0005] The present disclosure is directed to a display device having good display quality.

[0006] According to an embodiment of the present disclosure, a display device includes a substrate, a transistor, a pixel electrode, a first conductive layer, and a second conductive layer. The transistor is disposed on the substrate. The pixel electrode is disposed on the substrate. The pixel electrode is electrically connected to the transistor. The first conductive layer is disposed on the pixel electrode. The first conductive layer has a first slit. The second conductive layer is disposed on the pixel electrode. The second conductive layer has a second slit. The second conductive layer is disposed between the pixel electrode and the first conductive layer. Both ends of the first slit and both ends of the second slit include arc-shaped edges. The first slit and the second slit overlap the pixel electrode.

[0007] According to an embodiment of the present disclosure, a display device includes a substrate, a semiconductor, an electrode, a first conductive layer, and a second conductive layer. The semiconductor is disposed on the substrate. The electrode is disposed on the substrate. The electrode is electrically connected to the semiconductor. The first conductive layer overlaps the electrode. The first conductive layer has a first opening. The second conductive layer overlaps the electrode. The second conductive layer has a second opening. The second conductive layer is closer to the substrate than the first conductive layer. The area of ​​the second opening is greater than the area of ​​the first opening.

[0008] In summary, in a display device according to an embodiment of the present disclosure, since the first slit spans from the first pixel electrode to the second pixel electrode, the lateral horizontal electric field generated by the first slit and the first pixel electrode or the second pixel electrode can be increased, or the vertical horizontal electric field generated by the first slit and the first pixel electrode or the second pixel electrode can be reduced. Therefore, the liquid crystal efficiency of the pixel can be improved, thereby increasing the bright line area of ​​the pixel. The display device can have good display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic top view of a display device according to an embodiment of the present disclosure;

[0010] Figure 2 is a schematic top view of a display device according to an embodiment of the present disclosure;

[0011] Figure 3 for Figure 1 A schematic cross-sectional view of a display device along a section line AA';

[0012] Figure 4 A schematic top view of an active element according to an embodiment of the present disclosure;

[0013] Figure 5 is a schematic top view of a pixel array of a display device according to an embodiment of the present disclosure;

[0014] Figure 6 for Figure 5 A schematic top view of a region R of a pixel array;

[0015] Figure 7 FIG. 4 is a bar graph of liquid crystal efficiency of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that in order to make it easier for readers to understand and for the simplicity of the drawings, the multiple drawings in the present disclosure only depict a portion of the electronic device, and the specific elements in the drawings are not drawn according to the actual scale. In addition, the number and size of each element in the figure are only for illustration and are not intended to limit the scope of the present disclosure.

[0017] Certain words are used throughout the disclosure and in the claims that follow to refer to specific components. It will be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following description and claims, the words "include", "contain", "have" and the like are open-ended words, and therefore should be interpreted as "including but not limited to..." Therefore, when the terms "include", "contain" and / or "have" are used in the description of the present disclosure, they specify the presence of corresponding features, regions, steps, operations and / or components, but do not exclude the presence of one or more corresponding features, regions, steps, operations and / or components.

[0018] Directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only with reference to the directions of the accompanying drawings. Therefore, the directional terms used are for illustration and not for limiting the present disclosure. In the accompanying drawings, each figure shows the general characteristics of the methods, structures and / or materials used in a particular embodiment. However, these drawings should not be interpreted as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative size, thickness and position of each film layer, region and / or structure may be reduced or enlarged.

[0019] In the present disclosure, the length and width may be measured by using an optical microscope, and the thickness may be measured by using a cross-sectional image in an electron microscope, but the present invention is not limited thereto.

[0020] The terms "approximately," "equal," "equal," or "same," "substantially," or "approximately" are generally interpreted as meaning within a range of 20% of a given value, or within a range of 10%, 5%, 3%, 2%, 1% or 0.5% of a given value.

[0021] A structure (or layer, component, substrate) described in the present disclosure is located on another structure (or layer, element, substrate), which may mean that the two structures are adjacent and directly connected, or may mean that the two structures are adjacent but not directly connected. Indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate component, intermediate substrate, intermediate interval) between the two structures, the lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single-layer or multi-layer physical structure or a non-physical structure, without limitation. In the present disclosure, when a certain structure is arranged "on" another structure, it may mean that the certain structure is "directly" on the other structure, or that the certain structure is "indirectly" on the other structure, that is, at least one structure is sandwiched between the certain structure and the other structure. In the present disclosure, "connection" may mean that a certain structure is "directly" in contact with another structure, or that a certain structure is "not directly" in contact with another structure, but is "connected" to another structure through other elements. In the present disclosure, “electrically connected” may mean that a certain structure is “directly” electrically in contact with another structure, or that a certain structure is “not directly” electrically in contact with another structure but is “electrically connected” to another structure through other elements.

[0022] The "first", "second" ... etc. in this disclosure specification can be used to describe various elements, components, regions, layers and / or parts in this article, but these elements, components, regions, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the "first element", "component", "region", "layer" or "part" discussed below is used to distinguish from the "second element", "component", "region", "layer" or "part", rather than to limit the order or specific elements, components, regions, layers and / or parts. And the "first" element referred to in the description paragraph may be renamed as the "second" element in the claims.

[0023] The electronic device may have a display function, wherein the electronic display device of the disclosed embodiment may include a display device, an antenna device, a sensing device, a splicing device or a transparent display device, but is not limited thereto. The electronic device may be a rollable, stretchable, bendable or flexible electronic device. The electronic device may, for example, include liquid crystal, light emitting diode (LED), quantum dot (QD), fluorescence, phosphorescence or other suitable materials and the materials may be arranged and combined in any way or other suitable display media, or a combination of the foregoing; the light emitting diode may, for example, include an organic light emitting diode (OLED), a millimeter / sub-millimeter light emitting diode (mini LED), a micro LED or a quantum dot light emitting diode (QD, which may be, for example, QLED, QDLED), but is not limited thereto. The antenna device may, for example, be a liquid crystal antenna, but is not limited thereto. The splicing device may, for example, be a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any arrangement and combination of the foregoing, but is not limited thereto. In addition, the appearance of the electronic device can be rectangular, circular, polygonal, with curved edges or other suitable shapes. The electronic device can have peripheral systems such as a drive system, a control system, a light source system, a shelf system, etc. to support a display device, an antenna device or a splicing device. The following will illustrate the content of the disclosure with an electronic display device having a display function, but the disclosure is not limited thereto.

[0024] In the present disclosure, the various embodiments described below may be mixed and matched without departing from the spirit and scope of the present disclosure. For example, some features of one embodiment may be combined with some features of another embodiment to form another embodiment.

[0025] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0026] Figure 1 This is a top view of a display device according to an embodiment of the present disclosure. The embodiment may be, for example, a display panel or a spliced ​​display panel. For the sake of clarity and convenience of description, Figure 1 Several elements are omitted from illustration. Figure 2 FIG. 1 is a schematic top view of a display device according to an embodiment of the present disclosure. Figure 2 and Figure 1 The difference is that Figure 1 The common electrode layer CE and the first slit 193 are shown, and for the sake of clarity and convenience of description, Figure 2 Some elements (such as the common electrode layer CE and the first slit 193) are omitted. Figure 2 The conductive layer 180 , the second slit 183 , the bridge layer 150 , and the conductive vias V1 , V2 , V3 are shown. Figure 3 for Figure 2 A schematic cross-sectional view of a display device along the section line AA'. Please refer to Figure 1 , Figure 2 and Figure 3, the display device disclosed in the present invention may include a display panel, but is not limited thereto. Taking an embodiment of the present invention as an example, the display device 10 includes a substrate 100, a first transistor TFT1, a second transistor TFT2, a first pixel electrode PE1, a second pixel electrode PE2 and a common electrode layer CE. In some embodiments, the first transistor TFT1 and the second transistor TFT2 are disposed on the substrate 100. The display device 10 also includes a plurality of pixels arranged in a pixel array on an X-axis and a Y-axis perpendicular to the X-axis. The Z-axis is perpendicular to the X-axis and the Y-axis. The plurality of pixels include a first pixel PX1 and a second pixel PX2. The first pixel electrode PE1 is electrically connected to the first transistor TFT1, and the second pixel electrode PE2 is electrically connected to the second transistor TFT2. Each pixel (e.g., the first pixel PX1) is defined as an area (such as a virtual frame) where a pixel electrode (e.g., the first pixel electrode PE1) is disposed, and at least a portion of the area can emit a single color of light. In the present embodiment, the first pixel PX1 and the second pixel PX2 can emit the same color of light, but this is not a limitation. The first pixel electrode PE1 of the first pixel PX1 is disposed adjacent to the second pixel electrode PE2 of the second pixel PX2 on the Y axis. In some embodiments, in the normal direction (i.e., the Z axis) of the substrate 100, the common electrode layer CE overlaps a portion of the first pixel electrode PE1 and a portion of the second pixel electrode PE2. The common electrode layer CE has a first slit 193. In a direction substantially along the Y axis, the first slit 193 spans from the first pixel electrode PE1 to the second pixel electrode PE2. In some embodiments, "spanning" can be defined as a structure that is continuously disposed and overlaps two elements at the same time. For example, the first slit 193 is disposed on the first pixel electrode PE1 and the second pixel electrode PE2, and overlaps with the first pixel electrode PE1 and the second pixel electrode PE2 at the same time. Under the above-mentioned configuration, the first slit 193 can reduce the influence of the fringe field in the vertical direction (e.g., the Y axis) on the driving of the liquid crystal molecules, thereby improving the liquid crystal efficiency. In this way, the transmittance or contrast of the pixels of the display device 10 can be improved. The display device 10 can have good display quality.

[0027] Please refer to Figure 1 , Figure 2 and Figure 3 The display device 10 includes a substrate 100. The substrate 100 includes a hard substrate, a soft substrate, or a combination thereof. For example, the substrate 100 includes glass, quartz, sapphire, acrylic resin, polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), other suitable transparent materials, or a combination thereof, but is not limited thereto.

[0028] The display device 10 includes an insulating layer 111 and an insulating layer 112 disposed on a substrate 100. The insulating layer 111 is disposed on the substrate 100. The insulating layer 112 is disposed on the insulating layer 111. The material of the insulating layer 111 includes silicon nitride, but is not limited thereto. The material of the insulating layer 112 includes silicon oxide, but is not limited thereto.

[0029] In some embodiments, the display device 10 may further selectively include a light shielding layer LS (eg Figure 3 As shown). The light shielding layer LS is disposed between the substrate 100 and the insulating layer 111. In some embodiments, the light shielding layer LS may be disposed on the buffer layer, but is not limited thereto. The material of the light shielding layer LS includes metal or other suitable light shielding materials, but is not limited thereto. For example, the material of the light shielding layer LS is molybdenum. In some embodiments, the light shielding layer LS is, for example, disposed to overlap the semiconductor layer of a transistor to reduce light leakage current or improve flicker problems. The configuration of the transistor will be briefly described in the subsequent paragraphs.

[0030] In other embodiments, the light shielding layer LS can also be used as the bottom gate of the transistor. That is, the thin film transistor in the disclosed embodiment may include a top gate type, a bottom gate type, a double gate type or a dual gate type, or other suitable types of thin film transistors, but is not limited thereto.

[0031] In some embodiments, before the insulating layer 111 and the light shielding layer LS are provided, another insulating layer (not shown) may be selectively provided between the light shielding layer LS and the substrate 100 to function as a buffer. In other embodiments, when the light shielding layer LS is not provided, the insulating layer 111 and the insulating layer 112 may be applied as buffer layers.

[0032] The display device 10 further includes a plurality of insulating layers sequentially disposed on the substrate 100 on the Z axis. For example, the display device 10 includes a gate insulating layer GI, an insulating layer 120, an insulating layer 130, an insulating layer 140, an insulating layer 160, and an insulating layer 170 sequentially stacked on the Z axis. The gate insulating layer GI, the insulating layer 120, the insulating layer 130, the insulating layer 140, the insulating layer 160, and the insulating layer 170 may be a single layer or a multi-layer structure, and the material thereof may be, for example, an insulating material. For example, it may include an organic material, an inorganic material, or a combination thereof. The organic material may include polyethylene terephthalate (PET), polyethylene (PE), polyethersulfone (PES), polycarbonate (PC), polymethylmethacrylate (PMMA), polyimide (PI), photosensitive polyimide (PSPI), or a combination thereof, and the inorganic material may include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof, but is not limited thereto.

[0033] The display device 10 includes a transistor array disposed on a substrate 100. The transistor array includes a plurality of transistors, for example: a first transistor TFT1 and a second transistor TFT2. The transistor is, for example, a thin film transistor (TFT), but is not limited thereto. In some embodiments, the transistors (for example: a first transistor TFT1 and a second transistor TFT2) are arranged in an array along the X-axis and the Y-axis, respectively. For example, a plurality of first transistors TFT1 can be arranged in a plurality of rows along the X-axis. A plurality of second transistors TFT2 can be arranged in a plurality of rows along the X-axis. Figure 1 or Figure 2 For example, a plurality of transistors may be arranged in another horizontal row above the first transistor TFT1 on the Y axis. In addition, a plurality of transistors may be arranged in another horizontal row below the second transistor TFT2 on the Y axis. In other words, transistors in two horizontal rows may be arranged adjacent to each other, but are not limited thereto. In the embodiments disclosed herein, the definition of being adjacent is, for example, that no other identical elements are arranged between two identical elements (e.g., two transistors).

[0034] The transistor (for example, the first transistor TFT1 or the second transistor TFT2) includes a semiconductor layer SE, a gate G, a source S and a drain D. The semiconductor layer SE is disposed on the insulating layer 112. In some embodiments, in the normal direction of the substrate 100 (i.e., the Z axis), the semiconductor layer SE overlaps the light shielding layer LS. The material of the semiconductor layer SE is, for example, low temperature polysilicon (LTPS) or amorphous silicon, but is not limited thereto. In other embodiments, the material of the semiconductor layer SE includes amorphous silicon, polycrystalline silicon, single crystal silicon, germanium (Ge) or other suitable compound semiconductors or other suitable alloy semiconductors. Compound semiconductors may include gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and / or indium antimonide (InSb). The alloy semiconductor may include a silicon germanium (SiGe) alloy, a gallium arsenide phosphide (GaAsP) alloy, an aluminum indium arsenide (AlInAs) alloy, an aluminum gallium arsenide (AlGaAs) alloy, a gallium indium arsenide (GaInAs) alloy, a gallium indium phosphide (GaInP) alloy, a gallium indium arsenide phosphide (GaInAsP) alloy, or a combination thereof. In some other embodiments, the material of the semiconductor layer SE further includes cadmium telluride (CdTe) or cadmium sulfide (CdS). The material of the semiconductor layer SE may also include, but is not limited to, a metal oxide, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZTO), or an organic semiconductor including a polycyclic aromatic compound, or a combination thereof. In some embodiments, the semiconductor layer 112 may be doped with a p-type or n-type dopant.

[0035] In some embodiments, the light shielding layer LS can be used as a gate of a transistor, but is not limited thereto. The types of transistors have been described in the above paragraphs, so they will not be described again here.

[0036] In some embodiments, the semiconductor layer SE may include a source doping region SA, a drain doping region DA, and a channel region CH located therebetween. The two ends of the semiconductor layer SE may be doped to form a source doping region SA and a drain doping region DA, respectively. The source doping region SA and the drain doping region DA may be electrically connected to the source S and / or the drain D, respectively, but are not limited thereto.

[0037] The gate insulating layer GI is disposed on the semiconductor layer SE. The gate G is disposed on the gate insulating layer GI. The material of the gate G may include molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), hafnium (Hf), nickel (Ni), chromium (Cr), cobalt (Co), zirconium (Zr), tungsten (W), aluminum (Al), silver (Ag), gold (Au), or other suitable metals, or alloys or combinations of the above materials, but is not limited thereto.

[0038] The insulating layer 120 is disposed on the gate G, and the insulating layer 130 is disposed on the insulating layer 120 . The insulating layer 120 and the insulating layer 130 may be penetrated by the conductive through hole V1 , but the present invention is not limited thereto.

[0039] The source electrode S and the drain electrode D are disposed on the insulating layer 130. The source electrode S and the drain electrode D may be electrically connected to the source doping region SA and / or the drain doping region DA of the semiconductor layer SE through the conductive vias V1 penetrating the insulating layer 120 and the insulating layer 130. The materials of the source electrode S and the drain electrode D may be similar to those of the gate electrode G, and thus will not be described in detail herein.

[0040] In some embodiments, the gate G may be a portion of the scan line SL. Specifically, the gate G may be a portion where the scan line SL overlaps the semiconductor layer SE, but is not limited thereto. The plurality of scan lines SL and SL' extend, for example, along the X axis. Figure 1 or Figure 2 As shown, the scan line SL is disposed adjacent to the scan line SL'.

[0041] The source electrode S may be a part of the data line DL. The data lines DL and DL' extend substantially along the Y axis, for example. In some embodiments, the extending direction of the scan line SL (i.e., the X axis) is substantially perpendicular to the extending direction of the data line DL (i.e., the Y axis). The data line DL and the scan line SL may be arranged crosswise on the substrate 100, but the present invention is not limited thereto.

[0042] In some embodiments, the data line DL extends roughly along the Y axis and may include a main body DLC, a first bending portion DLA and a second bending portion DLB. The main body DLC may be arranged parallel to the Y axis. The first bending portion DLA and the second bending portion DLB are located between the main body DLC, and may be respectively connected to the main body DLC and extend along the first direction N1 and the second direction N2. The second bending portion DLB may be connected to the first bending portion DLA. The first direction N1 and the second direction N2 are not parallel to the X axis or the Y axis, and the first direction N1 and the second direction N2 have angles θ1 and θ2 with the Y axis respectively, and the first direction N1 intersects with the second direction N2. In some embodiments, the angle θ1 between the first direction N1 and the Y axis may be the same as the angle θ2 between the second direction N2 and the Y axis, or may be different, but the present disclosure is not limited thereto. In the present embodiment, the angle θ1 is the same as the angle θ2. The angle θ1 and the angle θ2 are greater than zero and less than 90 degrees. In this example, the angle θ1 and the angle θ2 are 10 degrees, but not limited thereto. In this way, at least a portion of the data line DL, such as the first bending portion DLA and the second bending portion DLB, can form a ">" shape.

[0043] In some embodiments, the drain D can be formed by patterning a conductive material with the source S or the data line DL through the same mask, but the invention is not limited thereto. In other embodiments, the drain D and the source S can also be formed in layers in different steps of the manufacturing process. In some embodiments, the drain D is electrically connected to the drain doping area DA of the semiconductor layer SE through a conductive via V1 that penetrates the insulating layer 120, the insulating layer 130 and the insulating layer 140, but the invention is not limited thereto. In the embodiments disclosed herein, the conductive via V1 that penetrates the insulating layer 120, the insulating layer 130 and the insulating layer 140 means that the insulating layer 120, the insulating layer 130 and the insulating layer 140 have a conductive via V1. In the subsequent paragraphs of this article, the definition of other conductive vias is similar to the definition of the conductive via V1 described above and so on, so they will not be repeated in the subsequent paragraphs.

[0044] The insulating layer 140 is disposed on the insulating layer 130 and covers the data line DL and the drain electrode D. The conductive via V1 penetrates the insulating layer 120, the insulating layer 130 and the insulating layer 140. The drain electrode D is electrically connected to the semiconductor layer SE through the conductive via V1.

[0045] The display device 10 may further optionally include a bridge layer 150. The bridge layer 150 is disposed on the insulating layer 140 and is electrically connected to the drain electrode D of the transistor (e.g., the first transistor TFT1 or the second transistor TFT2) through the conductive via V2. The conductive via V2 penetrates the insulating layer 140. The bridge layer 150 may be electrically connected to the drain electrode D through the conductive via V2. The material of the bridge layer 150 may be similar to that of the gate electrode G, the source electrode S, or the drain electrode D, and thus will not be described in detail herein.

[0046] The insulating layer 160 is disposed on the insulating layer 140 and covers the bridge layer 150. A portion of the insulating layer 160 is filled into the conductive via V1, but the present invention is not limited thereto. The conductive via V3 penetrates the insulating layer 160, and the bridge layer 150 overlaps the conductive via V3.

[0047] The pixel electrode is disposed on the insulating layer 160. The pixel electrode includes, for example, a first pixel electrode PE1 and a second pixel electrode PE2. The material of the first pixel electrode PE1 and the second pixel electrode PE2 includes a transparent conductive material, such as indium tin oxide (ITO), but is not limited thereto. The first pixel electrode PE1 (or the second pixel electrode PE2) is electrically connected to the bridge layer 150 through a conductive through hole V3. In some embodiments, the second pixel electrode PE2 is electrically connected to another bridge layer 150 and the second transistor TFT2. In some embodiments, the first pixel electrode PE1 is electrically connected to the first transistor TFT1 through the bridge layer 150. Thereby, the quality of the electrical connection between the pixel electrode and the transistor can be improved. The electrical quality of the display device 10 can be improved.

[0048] In other embodiments, the first pixel electrode PE1 (or the second pixel electrode PE2) may also be directly electrically connected to the transistor through the conductive via V3 without passing through the bridge layer 150, but the present invention is not limited thereto. With the above configuration, the manufacturing method of the display device 10 may be simplified or the cost may be saved.

[0049] In some embodiments, the first pixel PX1 and the second pixel PX2 may be arranged adjacent to each other on the Y axis. From another perspective, a plurality of first pixels PX1 may be arranged in a horizontal row on the X axis. A plurality of second pixels PX2 may be arranged in a horizontal row on the X axis. Two scan lines SL overlap portions of the plurality of first pixels PX1 or portions of the plurality of second pixels PX2, respectively. The first pixel electrodes PE1 of the plurality of first pixels PX1 in two adjacent horizontal rows and the second pixel electrodes PE2 of the plurality of second pixels PX2 are located between the above-mentioned two scan lines SL. In addition, the first pixel PX1 and the second pixel PX2 are located between the adjacent data lines DL and DL'.

[0050] The insulating layer 170 is disposed on the pixel electrode. A portion of the insulating layer 170 may be filled into the conductive through hole V3, but the present invention is not limited thereto.

[0051] The display device 10 may further optionally include a conductive layer 180. The conductive layer 180 is disposed on the insulating layer 170. A portion of the conductive layer 180 is filled into the conductive via V3, but the present invention is not limited thereto. The material of the conductive layer 180 may be similar to that of the gate G, the source S or the drain D, and therefore will not be described in detail herein.

[0052] like Figure 2As shown, in the normal direction of the substrate 100 (i.e., the Z axis), the conductive layer 180 is disposed on the scan lines SL, SL' and the data lines DL, DL'. The conductive layer 180 may overlap the scan lines SL, SL', the data lines DL, DL', the transistors and the pixel electrodes. Thereby, the conductive layer 180 has the effect of shielding the scan lines SL, the data lines DL and the transistors. Therefore, the display quality of the display device 10 can be improved. The conductive layer 180 has a second slit 183. In a direction substantially along the Y axis, the second slit 183 spans from the first pixel electrode PE1 to the second pixel electrode PE2.

[0053] The common electrode layer CE is disposed on the conductive layer 180. In some embodiments, the common electrode layer CE is disposed on the pixel electrodes and has different potentials. In this way, an electric field can be generated between the pixel electrode and the common electrode layer CE to drive the liquid crystal molecules (not shown). According to some embodiments of the present disclosure, the display device 10 is, for example, a liquid crystal display device using fringe field switching (FFS) technology, but is not limited to this. The material of the common electrode layer CE is, for example, a transparent oxide electrode (Transparent Conducting Oxide, TCO), such as an indium tin oxide (Indiumtin oxide, ITO) electrode or an indium zinc oxide (Indium Doped Zinc Oxide, IZO) electrode, but is not limited to this.

[0054] Please refer to Figure 1 and Figure 2 , the first pixel PX1 and the second pixel PX2 are arranged adjacent to each other. In detail, the first pixel electrode PE1 and the second pixel electrode PE2 have two opposite ends respectively. One end PE1' of the first pixel electrode PE1 is electrically connected to the first transistor TFT1, wherein the other end PE1" is adjacent to the second pixel electrode PE2. One end PE2' of the second pixel electrode PE2 is electrically connected to the second transistor TFT2, wherein the other end PE2" is adjacent to the first pixel electrode PE1. In one embodiment of the present disclosure, one end can be defined as starting from the point where the width of the element begins to change. In this way, under the demand for high-resolution display, the display device 10 can maintain the aperture ratio. Therefore, the display device 10 has good display quality.

[0055] In some embodiments, the first slit 193 of the common electrode layer CE may overlap a portion of the adjacent first pixel PX1 and a portion of the second pixel PX2. In the embodiments disclosed herein, unless otherwise specified, the overlap may be defined as two elements completely overlapping, a portion of one element overlapping a portion of another element, or a portion of one element being completely overlapped by another element.

[0056] The extension direction of the first slit 193 is substantially parallel to the Y axis. It is worth noting that in the present embodiment, the first slit 193 has a first portion 191 and a second portion 192 connected to the first portion 191, and the extension direction of the first portion 191 is different from the extension direction of the second portion 192. For example, the edge 191S of the first portion 191 can extend along the first direction N1 in parallel with the first bending portion DLA of the data line DL. The edge 192S of the second portion 192 can extend along the second direction N2 in parallel with the second bending portion DLB of the data line DL. The extension direction of the first portion 191 and the extension direction of the second portion 192 can have angles θ1 and θ2 with the Y axis respectively, and the extension directions intersect with each other, so that the first portion 191 and the second portion 192 can form a ">" shape. The angle θ1 and the angle θ2 are greater than zero and less than 90 degrees. In the present example, the angle θ1 and the angle θ2 are 10 degrees, but are not limited thereto. In the normal direction of the substrate 100, the first portion 191 overlaps the first pixel electrode PE1, and the second portion 192 overlaps the second pixel electrode PE2. It is worth noting that the first slit 193 spans from the first pixel electrode PE1 of the first pixel PX1 to the second pixel electrode PE2 of the second pixel PX2.

[0057] Since the first slit 193 overlaps a portion of the first pixel electrode PE1 and a portion of the second pixel electrode PE2, the area between the first pixel electrode PE1 and the second pixel electrode PE2 is less affected by the electric field generated by the common electrode layer CE and the pixel electrode. In other words, under the above-mentioned setting, the lateral horizontal electric field (i.e., the X-axis direction) generated by the first slit 193 and the first pixel electrode PE1 or the second pixel electrode PE2 can be increased, or the vertical horizontal electric field (i.e., the Y-axis direction) generated by the first slit 193 and the first pixel electrode PE1 or the second pixel electrode PE2 can be reduced. Therefore, the liquid crystal efficiency of the pixel can be improved, thereby increasing the bright line area of ​​the pixel. The display device 10 can have good display quality.

[0058] In addition, in the normal direction of the substrate 100 (i.e., the Z axis), the first slit 193 has a turning portion 194 connecting the first portion 191 and the second portion 192, and the turning portion 194 is located between the first pixel electrode PE1 and the second pixel electrode PE2. In the present embodiment, the turning portion 194 may be defined as a point where the first portion 191 extending in the first direction N1 and the second portion 192 extending in the second direction N2 intersect. In other embodiments, the turning portion 194 may be defined as a region from the edge of the first portion 191 extending in the first direction N1 to the second direction N2 to the beginning of the second portion 192 extending in the second direction N2. In the present embodiment, the first slit 193 has two opposite ends 1911 and 1921. The first transistor TFT1 overlaps one end 1911 of the first slit 193. The second transistor TFT2 overlaps the other end 1921 of the first slit 193. In some embodiments, the two ends 1911 and 1921 of the first slit 193 may include arc-shaped edges, but are not limited thereto.

[0059] The main body DLC of the data line DL or the data line DL' may extend along the Y-axis direction, but a first bending portion DLA extending along the first direction N1 and a second bending portion DLB extending along the second direction N2 are provided near the first slit 193. The first direction N1 and the second direction N2 are not parallel to the X-axis or the Y-axis, and the first direction N1 and the second direction N2 have angles θ1 and θ2 with the Y-axis respectively, and the first direction N1 intersects with the second direction N2. The edge 191S of the first portion 191 is adjacent to the first bending portion DLA, and the edge 191S is parallel to the first bending portion DLA. The edge 192S of the second portion 192 is adjacent to the second bending portion DLB, and the edge 192S is parallel to the second bending portion DLB. In other embodiments, the first slit 193 may include a rectangle, a quadrangle or other suitable shapes, but is not limited thereto.

[0060] Please also refer to Figure 1 and Figure 2 , on the normal line (and Z-axis) of the substrate 100, the second slit 183 overlaps the first slit 193. The second slit 183 has two opposite ends 1811, 1821. The first transistor TFT1 overlaps one end 1811 of the second slit 183. The second transistor TFT2 overlaps the other end 1821 of the second slit 183 opposite to the one end 1811. In other words, one end 1811 of the second slit 183 is disposed adjacent to one end 1911 of the first slit 193. One end 1821 of the second slit 183 is disposed adjacent to one end 1921 of the first slit 193. In some embodiments, the two ends 1811, 1821 of the second slit 183 may include arc-shaped edges, but are not limited thereto.

[0061] In more detail, the extension direction of the second slit 183 is substantially parallel to the Y axis. The second slit 183 has a first portion 181 and a second portion 182. The first portion 181 is connected to the second portion 182, and the second slit 183 has a turning portion 184 connecting the first portion 181 and the second portion 182, and the turning portion 184 is located between the first pixel electrode PE1 and the second pixel electrode PE2. The extension direction of the first portion 181 is different from the extension direction of the second portion 182. The extension direction of the first portion 181 and the extension direction of the second portion 182 can form angles θ1 and θ2 with the Y axis respectively, and the extension directions intersect with each other, so that the first portion 181 and the second portion 182 can form a “>” shape. The angle θ1 and the angle θ2 are greater than zero and less than 90 degrees. In this example, the angle θ1 and the angle θ2 are 10 degrees, but are not limited thereto. The edge 181S of the first portion 181 is adjacent to the first bending portion DLA, and the edge 181S is parallel to the first bending portion DLA. The edge 182S of the second portion 182 is adjacent to the second bending portion DLB, and the edge 182S is parallel to the second bending portion DLB. In other embodiments, the second slit 183 may include a rectangle, a quadrangle, or other suitable shapes, but is not limited thereto.

[0062] In some embodiments, the edge of the second slit 183 may be substantially parallel to the edge of the first slit 193, for example, but not limited thereto. For example, the first portion 181 of the second slit 183 may be parallel to the first portion 191 of the first slit 193, but not limited thereto. In the normal direction (and the Z axis) of the substrate 100, the edge of the first slit 193 is located within the edge of the second slit 183, but not limited thereto. In this way, the aperture ratio of the display device 10 can be maintained within a suitable range, so that the display device 10 has good display quality.

[0063] Figure 4 FIG. 1 is a schematic top view of a transistor according to an embodiment of the present disclosure. Figure 4 The transistor shown is, for example, a thin film transistor TFT of one embodiment of the present disclosure. The thin film transistor TFT is electrically connected to the scan line SL or the data line DL. For example, the semiconductor layer SE of the thin film transistor TFT may overlap a portion of the scan line SL. The portion of the scan line SL that overlaps the semiconductor layer SE is, for example, the gate G. The semiconductor layer SE may be electrically connected to the data line DL or the source S (for example, the source S may be a portion of the data line DL) through a conductive through hole V4. In the present embodiment, the semiconductor layer SE may be directly electrically connected to the drain D through the conductive through hole V1. The drain D may be electrically connected to the pixel electrode PE through the conductive through hole V3'. In other embodiments, the drain D of the semiconductor layer SE may also be selectively connected to the bridging layer 150 (such as Figure 1 and Figure 3 As shown), and then connected to the pixel electrode PE through the bridge layer 150.

[0064] It should be noted that Figure 4 The present disclosure only shows possible configurations of transistors in one embodiment, and is not intended to limit the shape or connection relationship of the transistors. In other embodiments, the transistors may have different configurations, which still fall within the scope of protection of the present disclosure.

[0065] Figure 5 FIG. 1 is a schematic top view of a pixel array of a display device according to an embodiment of the present disclosure. Figure 5 Several elements are omitted from illustration. Figure 6 for Figure 5 Schematic top view of region R of the pixel array. Figure 6 Several elements are omitted from illustration.

[0066] Please refer to Figure 5 , Figure 5 The display device shown includes a pixel array. The pixel array includes a plurality of first pixels PX1 arranged in a horizontal row along the X axis and a plurality of second pixels PX2 arranged in a horizontal row along the X axis. The first pixel PX1 and the second pixel PX2 are arranged adjacent to each other on the Y axis. One end of the first pixel electrode PE1 and one end of the second pixel electrode PE2 are electrically connected to different transistors through different conductive through holes V3, respectively. From another perspective, one end of the first pixel electrode PE1 (away from the conductive through hole V3) is arranged adjacent to one end of the second pixel electrode PE2 (away from the conductive through hole V3). In addition, in the present embodiment, the transistors electrically connected to the pixels of different horizontal rows can share a semiconductor layer, that is, one end of the pixel electrode (near the conductive through hole V3) and one end of another pixel electrode (near the conductive through hole V3) can be arranged adjacent to each other. In this way, under the display requirement of high resolution, the display device 10 can maintain the aperture ratio. Therefore, the display device 10 has good display quality.

[0067] In some embodiments, the display device 10 further includes a spacer SP. The spacer SP may overlap the position where the pixel electrode is connected to the conductive through hole V3, but the present invention is not limited thereto. The material of the spacer SP includes an insulating material, but the present invention is not limited thereto.

[0068] Figure 6The region R shown, for example, includes three pairs of first pixel electrodes PE1 and second pixel electrodes PE2 arranged in pairs on the Y axis. The first slit 193 and the second slit 183 span from the first pixel electrode PE1 to the second pixel electrode PE2, respectively. The second slit 183 overlaps the first slit 193. More specifically, the edge of the first slit 193 may be located within the edge of the second slit 183. One end 1911 of the first slit 193 is disposed close to one end 1811 of the second slit 183. The other end 1921 of the first slit 193 is disposed close to the other end 1821 of the second slit 183. The conductive vias V3 are respectively located outside the opposite ends of the first slit 193 (e.g., one end 1911 and the other end 1921).

[0069] One end PE1' of the first pixel electrode PE1 is electrically connected to the thin film transistor through the conductive through hole V3. One end PE2' of the second pixel electrode PE2 is electrically connected to the thin film transistor (not shown) through the conductive through hole V3. The other end PE1" of the first pixel electrode PE1 is disposed adjacent to the other end PE2" of the second pixel electrode PE2. One end 1911 of the first slit 193 is disposed adjacent to the one end PE1' of the first pixel electrode PE1, and the other end 1921 of the first slit 193 is disposed adjacent to the one end PE2' of the second pixel electrode PE2. The turning portion 194 between the first portion 191 and the second portion 192 and the turning portion 184 between the first portion 181 and the second portion 182 are disposed between the other end PE1" of the first pixel electrode PE1 and the other end PE2" adjacent to the second pixel electrode PE2. In the present embodiment, the turning portion 194 may be defined as a region between the edge of the first portion 191 extending in the first direction N1 and the change toward the second direction N2 to the beginning of the second portion 192 extending in the second direction N2. In addition, the definition of the turning portion 184 may be the same as the definition of the turning portion 194 , but is not limited thereto.

[0070] In some embodiments, one end 1911 and the other end 1921 of the first slit 193 are Figure 6 In the embodiment, the one end 1911 and the other end 1921 may be defined as starting from where the width starts to change and have arc-shaped edges. The first slit 193 has a turning portion 194 connecting the first portion 191 and the second portion 192. In addition, the definition of one end PE1' of the first pixel electrode PE1, one end PE2' of the second pixel electrode PE2, and two ends 1811 and 1821 of the second slit 183 may be the same as the definition of the one end 1911 and the other end 1921 described above, which are starting from where the width starts to change and have arc-shaped edges, but are not limited thereto.

[0071] In some embodiments, an edge 181S of the first portion 181 of the second slit 183 is parallel to an edge 191S of the first portion 191 of the first slit 193 and extends in the first direction N1. An edge 182S of the second portion 182 of the second slit 183 is parallel to an edge 192S of the second portion 192 of the first slit 193 and extends in the second direction N2. That is, the first slit 193 and the second slit 183 may be two parallel slits, but are not limited thereto.

[0072] Under the above settings, the aperture ratio of the display device 10 can be maintained within a suitable range, so that the display device 10 has good display quality.

[0073] Figure 7 FIG. 4 is a bar graph of liquid crystal efficiency of a display device according to an embodiment of the present disclosure.

[0074] In some embodiments, a method for measuring liquid crystal efficiency is briefly described as follows.

[0075] First, an upper polarizer and a lower polarizer are respectively disposed on the upper and lower sides of the display device 10. The optical axis of the upper polarizer is perpendicular to the optical axis of the lower polarizer.

[0076] Next, power is supplied to the display device 10 to drive the liquid crystal molecules.

[0077] Then, a backlight module is provided and the transmittance of light penetrating the display device 10 is measured. The measured transmittance is a first transmittance W.

[0078] Next, after removing the upper polarizer, the upper polarizer is reinstalled, and at this time, the optical axis of the upper polarizer is parallel to the optical axis of the lower polarizer.

[0079] Then, a backlight module is provided and the transmittance of light penetrating the display device 10 is measured. The measured transmittance is a second transmittance C. When measuring the second transmittance C, the display device 10 is not powered on. That is, the second transmittance C is used as a reference.

[0080] Next, the liquid crystal efficiency is obtained by calculating using Formula 1.

[0081]

[0082] W is the first light transmittance, C is the second light transmittance, and LCeff is the liquid crystal efficiency. The second light transmittance C is, for example, a constant value, which depends on the manufacturing process and materials of the display device 10 .

[0083] It can be seen from Formula 1 that the greater the first light transmittance W is, the higher the liquid crystal efficiency is and the better the display quality of the display device 10 is.

[0084] In the present disclosure, the liquid crystal efficiency of the pixel structure PX' of Comparative Example 1 is taken as a reference value (that is, the liquid crystal efficiency of Comparative Example 1 is set to 100%), and the liquid crystal efficiency of the pixel structure PX of Example 1 is higher than that of Comparative Example 1 under computer simulation, for example, about 120%. Under actual product measurement, the liquid crystal efficiency of the pixel structure PX of Example 1 is higher than that of Comparative Example 1. Thereby, the bright line area of ​​the pixel can be increased. The display device 10 can have good display quality. In the present disclosure, the liquid crystal efficiency of the pixel structure PX can be improved by about 20%. In other embodiments, this effect can be achieved when the liquid crystal efficiency of the embodiment is higher than the reference value.

[0085] In summary, in a display device according to an embodiment of the present disclosure, since the first slit spans from the first pixel electrode to the second pixel electrode, the lateral horizontal electric field generated by the first slit and the first pixel electrode or the second pixel electrode can be increased, or the vertical horizontal electric field generated by the first slit and the first pixel electrode or the second pixel electrode can be reduced. Therefore, the liquid crystal efficiency of the pixel can be improved, thereby increasing the bright line area of ​​the pixel. The display device can have good display quality.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display device, characterized in that: include: substrate; A transistor is disposed on the substrate; A pixel electrode, disposed on the substrate and electrically connected to the transistor; A first conductive layer, disposed on the pixel electrode and having a first slit; as well as The second conductive layer is disposed on the pixel electrode and has a second slit. wherein the second conductive layer is disposed between the pixel electrode and the first conductive layer; Two ends of the first slit and two ends of the second slit include arc-shaped edges, and the first slit and the second slit overlap the pixel electrode.

2. The display device according to claim 1, characterized in that An area of ​​the second slit is greater than an area of ​​the first slit.

3. The display device according to claim 1, characterized in that Also includes: The data line and the scan line are arranged on the substrate and electrically connected to the transistor. The second conductive layer overlaps the scan line and the data line.

4. The display device according to claim 1, characterized in that Also includes: A first scan line is disposed on the substrate and electrically connected to the transistor; as well as a second scanning line, disposed on the substrate and adjacent to the first scanning line, The first slit and the second slit are arranged between the first scanning line and the second scanning line.

5. The display device according to claim 1, characterized in that The maximum length of the first slit is smaller than the maximum length of the second slit.

6. A display device, characterized in that: include: substrate; A semiconductor disposed on the substrate; An electrode, disposed on the substrate and electrically connected to the semiconductor; A first conductive layer overlapping the electrode and having a first opening; as well as a second conductive layer, overlapping the electrode and having a second opening, The second conductive layer is closer to the substrate than the first conductive layer, and the area of ​​the second opening is larger than the area of ​​the first opening.

7. The display device according to claim 6, characterized in that: Also includes: an insulating layer, disposed between the electrode and the semiconductor, a conductive through hole that does not overlap the first opening and penetrates the insulating layer, The electrode is electrically connected to the semiconductor through the conductive via.

8. The display device according to claim 6, characterized in that: The first opening at least partially overlaps the second opening.

9. The display device according to claim 6, characterized in that: The first conductive layer directly contacts the second conductive layer.

10. The display device according to claim 6, characterized in that: The second conductive layer is closer to the electrode than the first conductive layer.

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