Array substrate, driving method thereof, display panel and display device

Abstract

The invention provides an array substrate, a driving method thereof, a display panel and a display device. The array substrate comprises a substrate; a plurality of pixel electrodes arranged in an array on the substrate; the plurality of grid lines extend along the first direction at the gaps of the pixel electrodes, each grid line comprises a bending part protruding towards the side where the adjacent pixel electrode is located, two grid lines are arranged at the gaps of two pixel electrodes arranged along the second direction, the bending parts of the two grid lines are opposite to form an accommodating space, and the second direction is intersected with the first direction; the plurality of data lines extend in the second direction at the gaps of the pixel electrodes, and the orthographic projection of the data lines on the substrate penetrates through the orthographic projection of the accommodating space; the plurality of transistors are positioned in a gap between two adjacent pixel electrodes arranged along the second direction, and orthographic projections of the transistors on the substrate and orthographic projections of the grid lines are mutually overlapped; the first electrode of the transistor is coupled with the data line, and the partial orthographic projection of the first electrode of the transistor on the substrate is located in the orthographic projection of the accommodating space.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a driving method thereof, a display panel and a display device. Background Art

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small size, low power consumption, high image quality, no radiation and easy to carry. It has been rapidly developed in recent years and has gradually replaced the traditional cathode ray tube display (CRT) and has occupied a dominant position in the current flat panel display market. At present, TFT-LCD has been widely used in various large, medium and small sized products, covering almost all major electronic products in today's information society, such as LCD TV, high-definition digital TV, computer (desktop and notebook), mobile phone, tablet computer, navigation system, car display, projection display, video camera, digital camera, electronic watch, calculator, electronic instrument, meter, public display and virtual display, etc. Summary of the invention

[0003] The present disclosure provides an array substrate, a driving method thereof, a display panel and a display device, and the specific solutions are as follows:

[0004] In one aspect, an embodiment of the present disclosure provides an array substrate, comprising:

[0005] substrate substrate;

[0006] A plurality of pixel electrodes are arranged in an array on the base substrate;

[0007] A plurality of gate lines extending along a first direction at the gap between the pixel electrodes, the gate lines comprising a bent portion protruding toward the side where the adjacent pixel electrode is located, two gate lines are provided at the gap between two adjacent pixel electrodes arranged along a second direction, the bent portions of the two gate lines are arranged opposite to each other to form an accommodation space, and the second direction intersects with the first direction;

[0008] A plurality of data lines extending along the second direction at the gaps between the pixel electrodes, wherein the orthographic projections of the data lines on the base substrate penetrate the orthographic projections of the accommodation spaces on the base substrate;

[0009] A plurality of transistors are located in the gap between two adjacent pixel electrodes arranged along the second direction, and the orthographic projection of the transistor on the substrate overlaps with the orthographic projection of the gate line on the substrate; the first electrode of the transistor is coupled to the data line, and a part of the orthographic projection of the first electrode of the transistor on the substrate is located within the orthographic projection of the accommodating space on the substrate.

[0010] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure further includes at least one bridge wire, the orthographic projection of the data line on the base substrate and the orthographic projection of the gate line on the base substrate have multiple overlapping areas, at least one of the data lines is missing in at least one of the overlapping areas, and the bridge wire is connected to the data line in the accommodating space and the data line between two adjacent pixel electrodes arranged along the first direction.

[0011] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, at least one of the first electrode, the second electrode, and the active layer of at least one of the transistors is short-circuited with the gate line, and the first electrode of at least one of the transistors is disconnected in the accommodating space.

[0012] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, in the area where the same accommodating space is located, the data line is coupled to the first electrodes of the two transistors, and the coupling positions of the first electrodes of the two transistors and the data line are separated on both sides of the data line and staggered with each other in the second direction.

[0013] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure further includes a common voltage line and a plurality of compensation lines, wherein the plurality of compensation lines are coupled between the second poles of at least part of the transistors and at least part of the pixel electrodes, and the orthographic projections of the plurality of compensation lines on the base substrate at least partially overlap with the orthographic projections of the common voltage lines on the base substrate.

[0014] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, the base substrate includes a plurality of red sub-pixel regions, a plurality of green sub-pixel regions, and a plurality of blue sub-pixel regions, and the plurality of pixel electrodes are located in the plurality of red sub-pixel regions, the plurality of green sub-pixel regions, and the plurality of blue sub-pixel regions;

[0015] The plurality of compensation lines are coupled to the plurality of red sub-pixel regions and the pixel electrodes in the plurality of green sub-pixel regions.

[0016] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a plurality of connection lines, wherein the connection lines are coupled between the second electrode of the transistor and the pixel electrode, and the compensation line is integrally arranged with at least part of the connection lines.

[0017] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the connection line includes a first sub-connection line extending along the first direction, and the first sub-connection line is coupled between the second electrode of the transistor and the pixel electrode;

[0018] The compensation line is located on an extension line of at least one end of the first sub-connection line, and the compensation line is integrally arranged with the first sub-connection line.

[0019] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the connecting line also includes a second sub-connecting line extending along the second direction, the second sub-connecting line is coupled between the first sub-connecting line and the pixel electrode, and the extension line of the second sub-connecting line passes through the central area of ​​the pixel electrode.

[0020] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, the common voltage line includes the first sub-common voltage line extending along the first direction, and the extension line of the first sub-common voltage line passes through the central area of ​​the pixel electrode.

[0021] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the common voltage line also includes a hollow structure extending along the second direction, and the orthographic projection of the hollow structure on the base substrate covers the orthographic projection of the data line between adjacent pixel electrodes on the base substrate.

[0022] On the other hand, an embodiment of the present disclosure provides a display panel, including the above-mentioned array substrate provided by an embodiment of the present disclosure.

[0023] In some embodiments, the display panel provided in the embodiments of the present disclosure further includes an opposite substrate disposed opposite to the array substrate, wherein the opposite substrate includes a common electrode.

[0024] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, the opposing substrate further comprises a plurality of red color resists, a plurality of green color resists and a plurality of blue color resists located on the side of the common electrode away from the array substrate; wherein, in the vertical direction of the base substrate: the size of the blue color resist is larger than the size of the red color resist and the size of the green color resist, and the size of the red color resist is approximately the same as the size of the green color resist.

[0025] On the other hand, an embodiment of the present disclosure further provides a display device, comprising the above-mentioned display panel provided by an embodiment of the present disclosure.

[0026] On the other hand, an embodiment of the present disclosure further provides a driving method for the array substrate, wherein the nth (n is a positive integer)th gate line and the (n+j)th gate line are a gate line group, j is greater than or equal to 2, and the same data line corresponding to the gate line group is connected to sub-pixels of the same color, and the driving method includes:

[0027] The gate line groups are sequentially driven, and the gate lines of the same gate line group are synchronously driven, and the driving time lengths of two adjacent gate line groups are partially the same; wherein,

[0028] During the driving process of the current gate line group, data signals are input to the data lines, and the input of data signals is stopped after the driving of the current gate line group is completed.

[0029] On the other hand, the embodiment of the present disclosure further provides a driving method for the above array substrate, wherein four adjacent gate lines are formed into a gate line group, the same data line corresponding to the odd-numbered gate lines is connected to the sub-pixels of the same color, and the same data line corresponding to the even-numbered gate lines is connected to the sub-pixels of the same color, and the driving method includes:

[0030] The gate line groups are sequentially driven, and the first gate line, the third gate line, the second gate line, and the fourth gate line are sequentially driven in the same gate line group; the driving time lengths of two adjacent gate lines are partially the same; wherein,

[0031] Before the first gate line is driven and during the third gate line driving process, the first data signal starts to be input to the data line, and the input of the first data signal is stopped after the third gate line is driven; and before the second gate line is driven and during the fourth gate line driving process, the second data signal starts to be input to the data line, and the input of the second data signal is stopped after the fourth gate line is driven, and the input time of the first data signal and the input time of the second data signal are staggered. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of pixel arrangement of a dual-gate product provided in an embodiment of the present disclosure;

[0033] Figure 2 A schematic diagram of another structure of an array substrate provided in an embodiment of the present disclosure;

[0034] Figure 3 for Figure 2 Schematic diagram of the enlarged structure of the middle Z region;

[0035] Figure 4 For along Figure 2 Schematic diagram of the cross-sectional structure of line I-II;

[0036] Figure 5 for Figure 2 A schematic diagram of the structure of the layer where the middle grid line is located;

[0037] Figure 6 for Figure 2 Schematic diagram of the structure of the active layer;

[0038] Figure 7 for Figure 2 The structural diagram of the layer where the data line is located;

[0039] Figure 8 for Figure 2 Schematic diagram of the structure of the layer where the via is located;

[0040] Fig. 9 for Figure 2 A schematic diagram of the structure of the layer where the pixel electrode is located;

[0041] Fig.10 A structural schematic diagram of a repair data line provided in an embodiment of the present disclosure;

[0042] Fig.11 For along Fig.10 Schematic diagram of the cross-sectional structure of line III-IV;

[0043] Fig.12 A schematic diagram of the structure of the first pole of the disconnect transistor provided in an embodiment of the present disclosure;

[0044] Fig.13 A light effect simulation diagram of a sub-pixel area provided in an embodiment of the present disclosure;

[0045] Fig.14 A schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure;

[0046] Fig.15 A schematic diagram of the structure of a display device provided in an embodiment of the present disclosure;

[0047] Fig.16 A working timing diagram of the array substrate provided in the embodiment of the present disclosure;

[0048] Fig.17 A schematic diagram of the structure of a gate drive circuit provided in an embodiment of the present disclosure;

[0049] Fig.18 Another working timing diagram of the array substrate provided in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the embodiment of the present disclosure clearer, the technical solution of the embodiment of the present disclosure will be clearly and completely described in conjunction with the drawings of the embodiment of the present disclosure. It should be noted that in order to make the purpose, technical solution and advantages of the embodiment of the present disclosure clearer, the technical solution of the embodiment of the present disclosure will be clearly and completely described in conjunction with the drawings of the embodiment of the present disclosure. It should be noted that in the drawings, the thickness of the layers, films, panels, regions, etc. is magnified for clarity. Exemplary embodiments are described in the present disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. In this way, deviations from the shape of the figure as a result of, for example, manufacturing technology and / or tolerances will be expected. Therefore, the embodiments described in the present disclosure should not be interpreted as being limited to the specific shapes of the regions shown in the present disclosure, but include deviations in shape caused by, for example, manufacturing. For example, an area illustrated or described as flat may typically have rough and / or nonlinear features; the sharp corners illustrated may be rounded, etc. Therefore, the areas shown in the figures are schematic in nature, and their sizes and shapes are not intended to illustrate the exact shape of the area, do not reflect the true proportion, and the purpose is only to illustrate the content of the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0051] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" and the like mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0052] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer may be directly on, directly connected to, or there may be an intermediate element or intermediate layer. When an element or layer is referred to as being "disposed on one side of" another element or layer, the element or layer may be directly on one side of, directly connected to, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intermediate elements or intermediate layers. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0053] At present, competition in the display field is becoming increasingly fierce, and the cost reduction concept is implemented throughout the display field. Compared with the conventional solution of using one data line to drive one column of sub-pixels, the dual gate product uses one data line to drive multiple columns of sub-pixels at the same time, thereby reducing the number of data lines, reducing the total number of driver chips (ICs), and greatly reducing material costs. It is especially suitable for medium and large-sized products such as car displays and TVs.

[0054] Figure 1 FIG. 1 is a schematic diagram showing the pixel arrangement of a dual-gate product provided by an embodiment of the present disclosure. Figure 1It can be seen that the dual-gate product includes data lines (such as D1, D2, D3, etc.), transistors (TFT), and gate lines (such as G1, G2, G3, G4, G5, G6, G7, G8, etc.), and the data lines (such as D1, D2, D3, etc.) and transistors (TFT) have overlapping areas with the gate lines (such as G1, G2, G3, G4, G5, G6, G7, G8, etc.). In some embodiments, the source / drain of the transistor (TFT) is arranged in the same layer and the same material as the data line (e.g., D1, D2, D3, etc.), the gate of the transistor (TFT) is arranged in the same layer and the same material as the gate line (e.g., G1, G2, G3, G4, G5, G6, G7, G8, etc.), and there is an insulating layer between the layer where the data line (e.g., D1, D2, D3, etc.) is located and the layer where the gate line (e.g., G1, G2, G3, G4, G5, G6, G7, G8, etc.) is located; however, there is an insulating layer between the data line (e.g., D1, D2, D3, etc.) and the gate line (e.g., G1, G2, G3, G4, G5, G6, G7, G8, etc.); 3. In the process of manufacturing the first transistor (G4, G5, G6, G7, G8, etc.), conductive particles may remain due to incomplete development and etching. The conductive particles pierce the insulating layer, which may cause the overlapping data lines (such as D1, D2, D3, etc.) and gate lines (such as G1, G2, G3, G4, G5, G6, G7, G8, etc.) to short-circuit, or cause the overlapping transistors (TFT) and gate lines (such as G1, G2, G3, G4, G5, G6, G7, G8, etc.) to short-circuit, causing the product to malfunction and affecting the product yield.

[0055] In order to solve the above technical problems existing in the related art, the present disclosure provides an array substrate, such as Figures 2 to 9 As shown, including:

[0056] Base substrate 101, optionally, the base substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, plastic, etc.;

[0057] A plurality of pixel electrodes 102 are arranged in an array on the base substrate 101; optionally, the pixel electrodes 102 are made of the same material, such as a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), etc.;

[0058] A plurality of gate lines 103 extend along a first direction X at the gap between the pixel electrodes 102, the first direction X being a row direction or a column direction, and the present disclosure takes the first direction X as an example for illustration as the row direction; the gate line 103 includes a bent portion 1031 protruding toward the side where the adjacent pixel electrode 102 is located, and two gate lines 103 are provided at the gap between two adjacent pixel electrodes 102 arranged along the second direction Y, and the bent portions 1031 of the two gate lines 103 are oppositely arranged to form an accommodating space AS, and the second direction Y intersects with the first direction X, and the present disclosure takes the second direction Y as an example for illustration as the column direction; optionally, the material of the gate line 103 may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni), and the gate line 103 may be a single-layer structure or a laminated structure, for example, the gate line 103 is a single-layer structure composed of a copper metal layer;

[0059] A plurality of data lines 104 extend along the second direction Y at the gaps between the pixel electrodes 102; the orthographic projections of the data lines 104 on the base substrate 101 penetrate the orthographic projections of the accommodation spaces AS on the base substrate 101; optionally, the material of the data lines 104 may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni), and the data lines 104 may be a single-layer structure or a laminated structure, for example, the data lines 103 are a laminated structure consisting of a titanium metal layer / an aluminum metal layer / a titanium metal layer;

[0060] A plurality of transistors 105 are located at a gap between two adjacent pixel electrodes 102 arranged along a second direction Y, an orthographic projection of the transistor 105 on the substrate 101 overlaps with an orthographic projection of the gate line 103 on the substrate 101, illustratively, a portion of the gate line 103 serves as a gate g of the transistor 105, an orthographic projection of the active layer a of the transistor 105 on the substrate 101 is located within the orthographic projection of the gate line 103 on the substrate 101, an orthographic projection of the first electrode s of the transistor 105 on the substrate 101 intersects with an orthographic projection of the gate line 103 on the substrate 101, an orthographic projection of the second electrode d of the transistor 105 on the substrate 101 intersects with an orthographic projection of the gate line 103 on the substrate 101, optionally, the first electrode s is a source electrode and the second electrode d is a drain electrode, or the first electrode s is a drain electrode and the second electrode d is a source electrode, the material of the active layer a may be amorphous silicon a-Si, polycrystalline silicon Poly, indium gallium zinc oxide IGZO, etc., and the transistor 105 may be Figure 4The bottom-gate transistor shown may also be a top-gate transistor or a double-gate transistor, and the transistor 105 may be a P-type transistor or an N-type transistor, which is not limited here; in some embodiments, the first electrode d of the transistor 105 is coupled to the data line 104 (for example, the first electrode d and the data line 104 are integrally arranged), and a partial orthographic projection of the first electrode d of the transistor 105 on the substrate 101 is located within the orthographic projection of the accommodating space AS on the substrate 101.

[0061] In the above-mentioned array substrate provided by the embodiment of the present disclosure, since the bending portions 1031 contained in the two gate lines 103 are arranged opposite to each other at the same gap extending along the first direction X to form a larger accommodation space AS, when the data line 104 and the gate line 103 are short-circuited, the data line 104 at the short-circuited position can be removed (for example, by laser cutting), and holes are respectively punched (for example, by laser drilling) in the larger accommodation space AS and in the larger area between two adjacent pixel electrodes 102 arranged along the first direction X, and then a conductive material is sprayed between the two holes to form a bridge line 106, so that the data line 104 disconnected due to being cut off at the short-circuited position is connected through the bridge line 106 to ensure smooth data signal. Based on this, Fig.10 and Fig.11 As shown, the array substrate may further include at least one bridge line 106, at least one data line 104 is missing in at least one overlapping region between the data line 104 and the gate line 103, and the bridge line 106 is connected to the data line 104 in the accommodating space AS and the data line 104 between two adjacent pixel electrodes 102 arranged along the first direction X. In this way, the short circuit problem between the gate line 103 and the data line 104 can be solved, thereby improving the product yield.

[0062] In addition, when the first electrode s and / or the second electrode d of the transistor 105 is short-circuited with the gate line 103, the first electrode s can be cut off in a larger accommodation space AS, ensuring that the scanning signal of the gate line 103 is not disturbed; optionally, the present disclosure uses the pixel electrode 102 coupled to the transistor 105 with the first electrode s cut off as a dark spot, and since there are fewer dark spots, it hardly affects the display effect. In this way, the problem of the first electrode s and / or the second electrode d of the transistor 105 being short-circuited with the gate line 103 is solved, and the product yield is improved. In addition, by Figure 3 and Figure 4It can be seen that the positive projection of the active layer a of the transistor 105 on the base substrate 101 is located within the positive projection of the gate line 103 on the base substrate 101. Therefore, the active layer a may also be short-circuited with the gate line 103 due to the residual conductive particles. At this time, the first pole s may be cut off in a larger accommodating space AS to ensure that the scanning signal of the gate line 103 is not disturbed. In some embodiments, the pixel electrode 102 coupled to the transistor 105 with the first pole s cut off can be used as a dark spot. Since there are fewer dark spots, the display effect is hardly affected. In this way, the problem of the short circuit between the active layer a of the transistor 105 and the gate line 103 is solved, and the product yield is improved. Based on this, Fig.12 As shown, in the above-mentioned array substrate provided in the embodiment of the present disclosure, at least one of the first electrode s, the second electrode d, and the active layer a of at least one transistor 105 may be short-circuited with the gate line 103, and the first electrode s of the transistor 105 is disconnected in the accommodating space AS.

[0063] In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, if Figure 3 As shown, in the region where the same accommodation space AS is located, the data line 104 is coupled to the first electrodes s of the two transistors 105, and the coupling positions of the first electrodes s of the two transistors 105 and the data line 104 are separated on both sides of the data line 104 and staggered in the second direction Y. The coupling positions of the first electrodes s of the two transistors 105 and the data line 104 are collinear in the first direction X (for example Figure 3 In the case of the setting of the L line shown in the figure, the right transistor 105 needs to be moved upward accordingly, so the width of the line gap needs to be increased accordingly, which affects the pixel aperture ratio; the present disclosure staggers the coupling positions of the first electrodes s of the two transistors 105 and the data line 104 in the second direction Y, so that the positive projections of the two transistors 105 in the second direction Y can overlap, thereby reasonably utilizing the line gap and facilitating improving the aperture ratio.

[0064] In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, if Figure 2 , Figure 5 and Figure 7 As shown, it also includes a common voltage line 107 and multiple compensation lines 108, the multiple compensation lines 108 are coupled between the second pole d of at least part of the transistor 105 and at least part of the pixel electrode 102, and the orthographic projections of the multiple compensation lines 108 on the substrate 101 at least partially overlap with the orthographic projection of the common voltage line 107 on the substrate 101. Optionally, the orthographic projection of the compensation line 108 on the substrate 101 is located within the orthographic projection of the common voltage line 107 on the substrate 101, so that a compensation capacitor is formed between the compensation line 108 and the common voltage line 107, ensuring that the signal pull-down degree (Feed through) of different sub-pixels is consistent, thereby improving the flickering problem.

[0065] In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, if Figure 2 , Figure 7 and Fig. 9 As shown, the base substrate 101 includes multiple red sub-pixel areas R, multiple green sub-pixel areas G and multiple blue sub-pixel areas B, and multiple pixel electrodes 102 are located in the multiple red sub-pixel areas R, multiple green sub-pixel areas G and multiple blue sub-pixel areas B; multiple compensation lines 108 are coupled to the pixel electrodes 102 in the multiple red sub-pixel areas R and the multiple green sub-pixel areas G.

[0066] The opposite substrate (also referred to as a color film substrate CF) includes a plurality of red color resistors corresponding to a plurality of red sub-pixel regions R, a plurality of green color resistors corresponding to a plurality of green sub-pixel regions G, a plurality of blue color resistors corresponding to a plurality of blue sub-pixel regions, and a common electrode located on the side of the plurality of red color resistors, the plurality of green color resistors, and the plurality of blue color resistors facing the array substrate. Since the thickness of the red color resistor is similar to that of the green color resistor (for example, the thickness is exactly the same or within the ±5% error range caused by factors such as manufacturing and measurement), and the thickness of the blue color resistor is greater than that of the red color resistor, the liquid crystal cell gap (Cell gap) in the blue sub-pixel region B is smaller, and the capacitance between the pixel electrode 102 and the common electrode in the blue sub-pixel region B is larger, so that the signal pull-down degree of the pixel electrode 102 in the blue sub-pixel region B is greater than the signal pull-down degree of the pixel electrode 102 in the red sub-pixel region B and the green sub-pixel region G. When the adjacent sub-pixels are flip-driven by alternately loading positive (+) and negative (-) signals, the screen flickers poorly. The present disclosure sets compensation lines 108 coupled to pixel electrodes 102 in multiple red sub-pixel regions R and multiple green sub-pixel regions G. The compensation capacitor formed by the compensation lines 108 and the common voltage line 107 can be used to compensate the pixel electrodes 102, thereby ensuring that the pull-down degree of the signal of the pixel electrode 102 in the blue sub-pixel region B is similar to the pull-down degree of the signal of the pixel electrode 102 in the red sub-pixel region B and the green sub-pixel region G after compensation, thereby improving or even avoiding poor screen flickering.

[0067] In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, if Figure 2 , Figures 7 to 9As shown, it may also include a plurality of connecting lines 109, which are coupled between the second pole d of the transistor 105 and the pixel electrode 102. Optionally, the connecting line 109 is integrally arranged with the second pole d of the transistor 105, and is coupled to the pixel electrode 102 through a first via h1 that penetrates the first insulating layer; and in order to simplify the manufacturing process, in the present disclosure, a plurality of compensation lines 108 are integrally arranged with at least part of the connecting lines 109. Exemplarily, in the present disclosure, a plurality of compensation lines 108 are integrally arranged with a plurality of connecting lines 109 of a plurality of red sub-pixel areas B and a plurality of green sub-pixel areas G, so as to compensate for a plurality of pixel electrodes 102 of a plurality of red sub-pixel areas B and a plurality of green sub-pixel areas G through compensation capacitors formed by a plurality of compensation lines 108 and a common voltage line 107.

[0068] In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, if Figure 2 , Figure 5 , Figure 7 and Fig. 9 As shown, the connection line 109 includes a first sub-connection line 1091 extending along a first direction X, and the first sub-connection line 1091 is coupled between the second electrode d of the transistor 105 and the pixel electrode 102. Optionally, the first sub-connection line 1091 is integrally arranged with the second electrode d of the transistor 105, and the orthographic projection of the first sub-connection line 1091 on the substrate 101 is located within the orthographic projection of the common voltage line 107 on the substrate 101; to avoid affecting the aperture ratio, the compensation line 109 can be arranged on an extension line of at least one end of the first sub-connection line 1091. The present disclosure takes the example of the compensation line 109 being located on the extension lines of both ends of the first sub-connection line 1091 as an example; optionally, the compensation line 109 is integrally arranged with the first sub-connection line 1091.

[0069] In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, if Figure 2 , Figure 7 and Fig. 9 As shown, the connection line 109 further includes a second sub-connection line 1092 extending along the second direction Y, the second sub-connection line 1092 is coupled between the first sub-connection line 1091 and the pixel electrode 102, and the extension line of the second sub-connection line 1092 passes through the central area of ​​the pixel electrode 102. Fig.13 As shown, the central area of ​​the pixel electrode 102 has dark lines due to disordered liquid crystal arrangement. The present disclosure allows the second sub-connection line 1092 to be located in the dark line area by passing the extension line of the second sub-connection line 1092 through the central area of ​​the pixel electrode 102, thereby avoiding affecting the transmittance of the pixel electrode 102. Figure 2 , Figure 5 , Figures 7 to 9As shown, the second sub-connection line 1092 is integrally arranged with the first sub-connection line 1091, and the second sub-connection line 1092 is coupled to the pixel electrode 102 through the first via hole h1; at the first via hole h1, the second sub-connection line 1092 is a widened block structure, and the common voltage line 107 (specifically the first sub-common voltage line 1071) is also a widened block structure, forming a storage capacitor between the two.

[0070] In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, if Figure 2 , Figure 5 and Fig. 9 As shown, the common voltage line 107 includes a first sub-common voltage line 1071 extending along the first direction X, and the extension line of the first sub-common voltage line 1071 passes through the central area of ​​the pixel electrode 102. Since the central area of ​​the pixel electrode 102 has dark lines (such as Fig.13 As shown, the present disclosure allows the first sub-common voltage line 1071 to be located in the dark-line area by extending the first sub-common voltage line 1071 through the central area of ​​the pixel electrode 102, thereby avoiding affecting the transmittance of the pixel electrode 102.

[0071] In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, if Figure 2 , Figure 5 and Figure 7 As shown, the common voltage line 107 can be provided in the same layer and the same material as the gate line 103, and the common voltage line 107 can also include a hollow structure HS extending along the second direction Y, and the orthographic projection of the hollow structure HS on the base substrate 101 covers the orthographic projection of the data line 104 between the adjacent pixel electrodes 102 on the base substrate 101, so as to reduce the overlapping area of ​​the common voltage line 107 and the data line 104, thereby reducing the parasitic capacitance between the common voltage line 107 and the data line 104, and reducing the probability of short circuit between the common voltage line 107 and the data line 104. Figure 2 , Figure 5 , Figures 7 to 9 It can be seen that the common voltage line 107 of adjacent rows is disconnected at the gate line 103 and is electrically connected through the jumper line 110; optionally, the jumper line 110 is set in the same layer and material as the pixel electrode 102, and the jumper line 110 is coupled to the common voltage line 107 through the second via h2 of the first insulating layer 111 and the second insulating layer 112.

[0072] In some embodiments, the material of the first insulating layer 111 may be an inorganic insulating material and / or an organic insulating material, wherein the inorganic insulating material includes but is not limited to at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the organic insulating material includes but is not limited to at least one of polyacrylic resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, and phenolic epoxy acrylic resin. The material of the second insulating layer 112 may be at least one of inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0073] Based on the same inventive concept, the embodiment of the present disclosure provides a display panel, such as Fig.14 As shown, it includes the above-mentioned array substrate 001 provided in the embodiment of the present disclosure, and the opposite substrate 002 arranged opposite to the array substrate 001. Optionally, the opposite substrate 002 includes a common electrode 201, and the common electrode 201 can be arranged on the entire surface of the display area AA. In some embodiments, the opposite substrate 002 also includes a plurality of red color resists 203, a plurality of green color resists (not shown in the figure) and a plurality of blue color resists (not shown in the figure) located between the substrate 202 and the layer where the common electrode 201 is located, and two adjacent color resists can be separated from each other by a black matrix 204; wherein, in the vertical direction of the base substrate 101: the size of the blue color resist is larger than the size of the red color resist, and the size of the green color resist, and the size of the red color resist is substantially the same as the size of the green color resist.

[0074] It should be noted that in the embodiments provided in the present disclosure, due to the limitations of process conditions or the influence of other factors such as measurement, "substantially the same" may be completely equivalent, or there may be some deviations (for example, a deviation of ±5%). Therefore, as long as the "substantially the same" relationship between related features satisfies the error allowance, it falls within the scope of protection of the present disclosure.

[0075] In some embodiments, Fig.14 As shown, in the display panel provided by the embodiment of the present disclosure, a liquid crystal layer 003 may be further provided between the array substrate 001 and the opposite substrate 002, a first alignment layer may be provided on the side of the array substrate 001 facing the opposite substrate 002, a first polarizer may be provided on the side of the array substrate 001 away from the opposite substrate 002, a second alignment layer may be provided on the side of the opposite substrate 002 away from the array substrate 001, a second polarizer may be provided on the side of the opposite substrate 002 away from the array substrate 001, and a polarization direction of the first polarizer is perpendicular to a polarization direction of the second polarizer. Other essential components in the display panel should be understood by those skilled in the art, and will not be described in detail here, nor should they be used as limitations to the present disclosure.

[0076] Based on the same inventive concept, the present disclosure provides a display device, such as Fig.15 As shown, it includes the above-mentioned display panel PNL provided by the embodiment of the present disclosure, and a backlight module BLU located on the light incident side of the display panel PNL. The backlight module BLU can be a direct-type backlight module or an edge-type backlight module. Optionally, the edge-type backlight module may include a light bar, a reflective sheet, a light guide plate, a diffuser, a prism group, etc., which are stacked, and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightness enhancement film, etc., which are stacked on the light emitting side of the matrix light source, and the reflective sheet includes an opening that is arranged opposite to the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source can be light-emitting devices (LEDs), such as quantum dot light-emitting devices (QLEDs), micro light-emitting devices (such as Mini LEDs, Micro LEDs), etc.

[0077] Among them, submillimeter or even micron-scale micro-light-emitting devices are self-luminous devices like organic light-emitting devices (OLEDs). Like organic light-emitting devices, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because the light emission of inorganic light-emitting devices is based on metal semiconductors with more stable properties and lower resistance, compared with organic light-emitting devices based on organic matter, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life. And when micro-light-emitting devices are used as backlight sources, more precise dynamic backlight effects can be achieved. While effectively improving the brightness and contrast of the screen, it can also solve the glare caused by traditional dynamic backlighting between the bright and dark areas of the screen, optimizing the visual experience.

[0078] In some embodiments, the above-mentioned display device provided in the embodiments of the present disclosure may be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, and any other product or component with a display function. Optionally, the display device provided by the present disclosure includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip. Optionally, the control chip is a central processing unit, a digital signal processor, a system chip (SoC), and the like. For example, the control chip may also include a memory, and may also include a power module, and the like, and realize power supply and signal input and output functions through additionally provided wires, signal lines, and the like. For example, the control chip may also include a hardware circuit and a computer executable code, and the like. The hardware circuit may include a conventional very large scale integration (VLSI) circuit or gate array and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include a field programmable gate array, a programmable array logic, a programmable logic device, and the like. In addition, those skilled in the art will appreciate that the above structure does not constitute a limitation on the above display device provided in the embodiment of the present disclosure. In other words, the above display device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.

[0079] In some embodiments, Figure 1 It can be seen that the same data line (such as D1, D2 or D3) corresponding to two gate lines at the same row gap (such as G2 and G3, G4 and G5, G6 and G7) connects sub-pixels of different colors. When driving the product, if the DLG driving method is adopted, there will be a cross-color problem. Therefore, it is difficult to use the DLG driving method to improve the refresh rate. Therefore, the refresh rate of ultra-high resolution dual-gate products is relatively low and cannot meet the market demand for ultra-high refresh rates.

[0080] In order to solve the above technical problems existing in the related art, the embodiment of the present disclosure further provides a DLG driving method of the above array substrate, wherein the nth (n is a positive integer)th gate line and the (n+j)th gate line are a gate line group, j is greater than or equal to 2, and the same data line corresponding to the gate line group is connected to sub-pixels of the same color, and the DLG driving method includes:

[0081] In one frame display time, each gate line group is driven sequentially, and the gate lines of the same gate line group are driven synchronously, and the driving time lengths of two adjacent gate line groups are partially the same; wherein,

[0082] During the driving process of the current gate line group, data signals start to be input to the data lines, and the input of data signals stops after the current gate line group is driven.

[0083] In the above driving method, since the same data line corresponding to the same gate line group is connected to sub-pixels of the same color, when the DLG driving method is used to synchronously drive the gate lines of the same gate line group, there will be no cross-color problem. Compared with the method of driving the gate lines one by one within a frame display time, the present invention can shorten the total time of the gate line driving, thereby facilitating the improvement of the refresh rate, and is suitable for fast refresh of ultra-high-resolution dual-gate products.

[0084] The following takes j equal to 2 as an example to describe the DLG driving method provided by the embodiment of the present disclosure in detail. Figure 1 , Fig.16 and Fig.17 As shown, the first gate line GL1 connected by the first clock signal CLK1 through the first-level shift register unit GOA1, and the third gate line GL3 connected by the third clock signal CLK3 through the third-level shift register unit GOA3 are the first gate line group, the second gate line GL2 connected by the second clock signal CLK2 through the second-level shift register unit GOA2, and the fourth gate line GL4 connected by the fourth clock signal CLK4 through the fourth-level shift register unit GOA4 are the second gate line group, the fifth gate line GL5 connected by the fifth clock signal CLK5 through the fifth-level shift register unit GOA5, and the seventh gate line GL7 connected by the seventh clock signal CLK7 through the seventh-level shift register unit GOA7 are the third gate line group, the sixth gate line GL6 connected by the sixth clock signal CLK6 through the sixth-level shift register unit GOA6, and the eighth gate line GL8 connected by the eighth clock signal CLK8 through the eighth-level shift register unit GOA8 are the fourth gate line group.

[0085] In some embodiments, Fig.16 As shown, G1 represents the first scanning signal loaded on the first gate line GL1, G2 represents the second scanning signal loaded on the second gate line GL2, G3 represents the third scanning signal loaded on the third gate line GL3, G4 represents the fourth scanning signal loaded on the fourth gate line GL4, G5 represents the fifth scanning signal loaded on the fifth gate line GL5, G5 represents the sixth scanning signal loaded on the sixth gate line GL6, G7 represents the seventh scanning signal loaded on the seventh gate line GL7, G8 represents the eighth scanning signal loaded on the eighth gate line GL8, and DA represents a data line (for example, Figure 1 The data signals loaded on the first data line DL1, the second data line DL2, the third data line DL3, etc. shown in the figure, H represents the driving time of a row of sub-pixels. Optionally, the high level of the scanning signals G1 to G6 can be used as a gate-on signal to control the transistor (TFT) in the sub-pixel to turn on.

[0086] exist Figure 1 , Fig.16 and Fig.17 In the process, the first scanning signal G1 is first loaded on the first gate line GL1 in the first gate line group, and the third scanning signal G3 is synchronously loaded on the third gate line GL3, so that the transistors (TFTs) connected to the first gate line GL1 and the third gate line GL3 are synchronously turned on under the high level of the scanning signals G1 and G3; and during the high level loading process of the scanning signals G1 and G3, the data signal DA is input to the data lines (such as the first data line DL1, the second data line DL2, the third data line DL3, etc.), and the input of the data signal DA is stopped after the scanning signals G1 and G3 are changed from high level to low level, so that the sub-pixels corresponding to the first gate line GL1 and the third gate line GL3 are written with the data signal DA. Combined with Figure 1 It can be seen that the sub-pixels connected to the first gate line GL1 and the third gate line GL3 through the same data line corresponding to the transistor TFT (for example, the first data line DL1, the second data line DL2 or the third data line DL3, etc.) have the same color. Therefore, synchronously driving the first gate line GL1 and the third gate line GL3 will not cause the problem of cross-color.

[0087] Based on the same driving method, the synchronous driving of the second gate line GL2 and the fourth gate line GL4 in the second gate line group, the synchronous driving of the fifth gate line GL5 and the seventh gate line GL7 in the third gate line group, and the synchronous driving of the sixth gate line GL6 and the eighth gate line GL8 in the fourth gate line group can be completed in sequence; and in the driving process of the current gate line group, the data signal is input to the data line, and the input of the data signal is stopped after the current gate line group is driven. The implementation methods of the remaining sub-pixels are deduced in this way until the sub-pixels in the entire display panel are charged with data signals, which will not be described in detail here.

[0088] In addition, see Figure 1 , Fig.16 and Fig.17 It can be seen that the driving durations of two adjacent gate line groups are partially the same. For example, the high-level loading durations of the first scanning signal G1 of the first gate line GL1 in the first gate line group and the third scanning signal G3 of the third gate line GL3 overlap with the high-level loading durations of the second scanning signal G2 of the second gate line GL2 in the second gate line group and the fourth scanning signal G4 of the fourth gate line GL4. During the overlapping duration, the data signals provided to the sub-pixels corresponding to the first gate line GL1 and the third gate line GL3 can be written into the sub-pixels corresponding to the second gate line GL2 and the fourth gate line GL4 to pre-charge the sub-pixels corresponding to the second gate line GL2 and the fourth gate line GL4, thereby improving the charging rates of the sub-pixels corresponding to the second gate line GL2 and the fourth gate line GL4.

[0089] It should be noted that Fig.17 There are two frame start signals, STV0 and STV1, in the circuit. Because the frame start signal may be lost during the use of the product, the two frame start signals STV0 and STV1 are used to achieve double insurance and ensure the normal startup of the gate drive circuit.

[0090] On the other hand, in order to improve the refresh rate, the embodiment of the present disclosure further provides another HSR driving method of the above array substrate, for example, four adjacent gate lines are used as a gate line group, the same data line corresponding to the odd-numbered gate lines is connected to the sub-pixels of the same color, and the same data line corresponding to the even-numbered gate lines is connected to the sub-pixels of the same color, and the HSR driving method includes:

[0091] In one frame display time, each gate line group is driven sequentially, and the first gate line, the third gate line, the second gate line, and the fourth gate line in the same gate line group are driven sequentially; the driving time lengths of two adjacent gate lines are partially the same; wherein,

[0092] Before the first gate line is driven and during the third gate line driving process, the first data signal starts to be input to the data line, and the input of the first data signal is stopped after the third gate line is driven; and before the second gate line is driven and during the fourth gate line driving process, the second data signal starts to be input to the data line, and the input of the second data signal is stopped after the fourth gate line is driven, and the input time of the first data signal and the input time of the second data signal are staggered.

[0093] In the above-mentioned HSR driving method, since the same data line corresponding to the first gate line and the third gate line is connected to the sub-pixels of the same color, and the same data line corresponding to the second gate line and the fourth gate line is connected to the sub-pixels of the same color, therefore, when the HSR driving method is adopted to sequentially drive the first gate line, the third gate line, the second gate line, and the fourth gate line of the same gate line group, and synchronously input the first data signal to the sub-pixels of the same color corresponding to the first gate line and the third gate line, and synchronously input the second data signal to the sub-pixels of the same color corresponding to the second gate line and the fourth gate line, this will only make the charging time of the sub-pixel corresponding to the first gate line short and the charging time of the sub-pixel corresponding to the third gate line long, and the charging time of the sub-pixel corresponding to the second gate line short and the charging time of the sub-pixel corresponding to the fourth gate line long, that is, there is only a difference in charging rate, and there will be no cross-color problem. Furthermore, compared to a driving method in which the times for loading data signals on sub-pixels corresponding to different gate lines are staggered, the present invention can shorten the total loading time of data signals within one frame, thereby improving the refresh rate, and is suitable for fast refresh of ultra-high-resolution dual-gate products.

[0094] The following takes two gate line groups as an example to describe the driving method provided by the embodiment of the present disclosure in detail. Figure 1 and Fig.18 As shown, the first gate line GL1, the second gate line GL2, the third gate line GL3, and the fourth gate line GL4 are a first gate line group, and the fifth gate line GL5, the sixth gate line GL6, the eighth gate line GL7, and the eighth gate line GL8 are a second gate line group. CLK1 represents the first clock signal provided to the first-level shift register unit GOA1 connected to the first gate line GL1, CLK2 represents the second clock signal provided to the second-level shift register unit GOA2 connected to the second gate line GL2, CLK3 represents the third clock signal provided to the third-level shift register unit GOA3 connected to the third gate line GL3, CLK4 represents the fourth clock signal provided to the fourth-level shift register unit GOA4 connected to the fourth gate line GL4, CLK5 represents the fifth clock signal provided to the fifth-level shift register unit GOA5 connected to the fifth gate line GL5, CLK6 represents the sixth clock signal provided to the sixth-level shift register unit GOA6 connected to the sixth gate line GL6, CLK7 represents the seventh clock signal provided to the seventh-level shift register unit GOA7 connected to the seventh gate line GL7, and CLK8 represents the eighth clock signal provided to the eighth-level shift register unit GOA8 connected to the eighth gate line GL8. G1 represents a first scanning signal loaded on the first gate line GL1, G2 represents a second scanning signal loaded on the second gate line GL2, G3 represents a third scanning signal loaded on the third gate line GL3, G4 represents a fourth scanning signal loaded on the fourth gate line GL4, G5 represents a fifth scanning signal loaded on the fifth gate line GL5, G5 represents a sixth scanning signal loaded on the sixth gate line GL6, G7 represents a seventh scanning signal loaded on the seventh gate line GL7, G8 represents an eighth scanning signal loaded on the eighth gate line GL8, DA1 represents a data line (e.g. Figure 1 The first data line DL1, the second data line DL2, the third data line DL3, etc. shown in FIG. 1A , and DA2 represents the first data signal loaded on the data line (eg, Figure 1 The second data signal loaded on the first data line DL1, the second data line DL2, the third data line DL3, etc. shown in FIG. 1 , H represents the driving time of a row of sub-pixels. Optionally, the high level of the scanning signals G1 to G6 can be used as a gate-on signal to control the transistor (TFT) in the sub-pixel to turn on.

[0095] exist Fig.18In the process, first, the first gate line GL1 in the first gate line group is loaded with the first scanning signal G1, the third gate line GL3 is loaded with the third scanning signal G3, the second gate line GL2 is loaded with the second scanning signal G2, and the fourth gate line GL4 is loaded with the fourth scanning signal G4, so that the transistors (TFTs) corresponding to the first gate line GL1, the third gate line GL3, the second gate line GL2, and the fourth gate line GL4 are turned on in sequence under the high level of the corresponding scanning signals G1, G3, G2, and G4; and before the first scanning signal G1 changes from a high level to a low level, and while the third scanning signal G3 remains at a high level, the data lines (for example, the first data line DL1, The first data signal DA1 is input to the second data line DL2, the third data line DL3, etc.) until the third scanning signal G3 changes from a high level to a low level, at which time the input of the first data signal DA1 is stopped; and before the second scanning signal G2 changes from a high level to a low level, and while the fourth scanning signal G4 remains at a high level, the second data signal DA2 is input to the data lines (for example, the first data line DL1, the second data line DL2, the third data line DL3, etc.), until the fourth scanning signal G4 changes from a high level to a low level, at which time the input of the second data signal DA2 is stopped, and the input time of the first data signal DA1 and the input time of the second data signal DA2 are staggered. Combination Figure 1 It can be seen that the sub-pixels connected to the same data line (for example, the first data line DL1, the second data line DL2 or the third data line DL3, etc.) corresponding to the first gate line GL1 and the third gate line GL3 through the transistor TFT have the same color. Therefore, synchronously providing the first data signal DA1 to the sub-pixels connected to the same data line (for example, the first data line DL1) corresponding to the first gate line GL1 and the third gate line GL3 will not cause the problem of cross-color. In addition, the sub-pixels connected to the same data line (for example, the first data line DL1) corresponding to the second gate line GL2 and the fourth gate line GL4 through the transistor TFT have the same color. Therefore, synchronously providing the second data signal DA2 to the sub-pixels connected to the same data line (for example, the first data line DL1, the second data line DL2 or the third data line DL3, etc.) corresponding to the first gate line GL1 and the third gate line GL3 will not cause the problem of cross-color.

[0096] Based on the same driving method, the fifth gate line GL5, the seventh gate line GL7, the sixth gate line GL6, and the eighth gate line GL8 in the second gate line group can be driven in sequence; and before the driving of the fifth gate line GL5 is completed and during the driving of the seventh gate line GL7, the third data signal is started to be input to the data line (for example, the first data line DL1, the second data line DL2, the third data line DL3, etc.), until the seventh gate line GL7 is driven and the input of the third data signal is stopped; and before the driving of the sixth gate line GL6 is completed and during the driving of the eighth gate line GL8, the fourth data signal is started to be input to the data line (for example, the first data line DL1, the second data line DL2, the third data line DL3, etc.), until the eighth gate line GL8 is driven and the input of the fourth data signal is stopped, and the input time of the third data signal is staggered with the input time of the fourth data signal; the implementation methods of the remaining sub-pixels are analogous until the sub-pixels in the entire display panel are completely charged with data signals, which will not be repeated here.

[0097] In addition, see Figure 1 and Fig.18 It can be seen that the driving durations of two adjacent gate lines are partially the same. For example, the high-level loading durations of the first scanning signal G1 of the first gate line GL1 and the second scanning signal G3 of the second gate line GL2 partially overlap, and within the overlapping duration, the first data signal DA1 provided to the sub-pixel corresponding to the first gate line GL1 can be written into the sub-pixel corresponding to the second gate line GL2 to pre-charge the sub-pixel corresponding to the second gate line GL2, thereby improving the charging rate of the second gate line GL2 and the corresponding sub-pixel.

[0098] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0099] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein: include: substrate substrate; A plurality of pixel electrodes are arranged in an array on the base substrate; A plurality of gate lines extending along a first direction at the gap between the pixel electrodes, the gate lines comprising a bent portion protruding toward the side where the adjacent pixel electrode is located, two gate lines are provided at the gap between two adjacent pixel electrodes arranged along a second direction, the bent portions of the two gate lines are arranged opposite to each other to form an accommodation space, and the second direction intersects with the first direction; A plurality of data lines extending along the second direction at the gaps between the pixel electrodes, wherein the orthographic projections of the data lines on the base substrate penetrate the orthographic projections of the accommodation spaces on the base substrate; A plurality of transistors are located in the gap between two adjacent pixel electrodes arranged along the second direction, and the orthographic projection of the transistor on the substrate overlaps with the orthographic projection of the gate line on the substrate; the first electrode of the transistor is coupled to the data line, and a part of the orthographic projection of the first electrode of the transistor on the substrate is located within the orthographic projection of the accommodating space on the substrate.

2. The array substrate according to claim 1, wherein: It also includes at least one bridge wire, the orthographic projection of the data line on the substrate and the orthographic projection of the gate line on the substrate have multiple overlapping areas, at least one of the data lines is missing in at least one of the overlapping areas, and the bridge wire is connected to the data line in the accommodating space and the data line between two adjacent pixel electrodes arranged along the first direction.

3. The array substrate according to claim 1 or 2, wherein: At least one of the first electrode, the second electrode, and the active layer of at least one of the transistors is short-circuited with the gate line, and the first electrode of at least one of the transistors is disconnected in the accommodating space.

4. The array substrate according to any one of claims 1 to 3, wherein: In the same area where the accommodating space is located, the data line is coupled to the first electrodes of the two transistors, and the coupling positions of the first electrodes of the two transistors and the data line are separated on both sides of the data line and staggered with each other in the second direction.

5. The array substrate according to any one of claims 1 to 4, wherein: It also includes a common voltage line and a plurality of compensation lines, wherein the plurality of compensation lines are coupled between the second poles of at least part of the transistors and at least part of the pixel electrodes, and the orthographic projections of the plurality of compensation lines on the substrate at least partially overlap with the orthographic projections of the common voltage lines on the substrate.

6. The array substrate according to claim 5, wherein: The base substrate comprises a plurality of red sub-pixel regions, a plurality of green sub-pixel regions and a plurality of blue sub-pixel regions, and the plurality of pixel electrodes are located in the plurality of red sub-pixel regions, the plurality of green sub-pixel regions and the plurality of blue sub-pixel regions; The plurality of compensation lines are coupled to the plurality of red sub-pixel regions and the pixel electrodes in the plurality of green sub-pixel regions.

7. The array substrate according to claim 5 or 6, wherein: It also includes a plurality of connection lines, wherein the connection lines are coupled between the second electrode of the transistor and the pixel electrode, and the compensation line is integrally arranged with at least part of the connection lines.

8. The array substrate according to claim 7, wherein: The connection line comprises a first sub-connection line extending along the first direction, and the first sub-connection line is coupled between the second electrode of the transistor and the pixel electrode; The compensation line is located on an extension line of at least one end of the first sub-connection line, and the compensation line is integrally arranged with the first sub-connection line.

9. The array substrate according to claim 8, wherein: The connection line further includes a second sub-connection line extending along the second direction, the second sub-connection line is coupled between the first sub-connection line and the pixel electrode, and an extension line of the second sub-connection line passes through a central area of ​​the pixel electrode.

10. The array substrate according to any one of claims 5 to 9, wherein: The common voltage line includes a first sub-common voltage line extending along the first direction, and an extended line of the first sub-common voltage line passes through a central area of ​​the pixel electrode.

11. The array substrate according to any one of claims 5 to 10, wherein: The common voltage line further includes a hollow structure extending along the second direction, and the orthographic projection of the hollow structure on the base substrate covers the orthographic projection of the data line between adjacent pixel electrodes on the base substrate.

12. A display panel, wherein: It comprises the array substrate as claimed in any one of claims 1 to 11.

13. The display panel according to claim 12, wherein: The invention also includes an opposite substrate arranged opposite to the array substrate, and the opposite substrate includes a common electrode.

14. The display panel according to claim 13, wherein: The opposing substrate also includes a plurality of red color resists, a plurality of green color resists and a plurality of blue color resists located on a side of the common electrode away from the array substrate; wherein, in the vertical direction of the base substrate: the size of the blue color resist is larger than the size of the red color resist and the size of the green color resist, and the size of the red color resist is approximately the same as the size of the green color resist.

15. A display device, wherein: It comprises the display panel as claimed in any one of claims 12 to 14.

16. A method for driving an array substrate according to any one of claims 1 to 11, wherein: The nth (n is a positive integer) gate line and the (n+j)th gate line are a gate line group, j is greater than or equal to 2, and the same data line corresponding to the gate line group is connected to sub-pixels of the same color, and the driving method includes: The gate line groups are sequentially driven, and the gate lines of the same gate line group are synchronously driven, and the driving time lengths of two adjacent gate line groups are partially the same; wherein, During the driving process of the current gate line group, data signals are input to the data lines, and the input of data signals is stopped after the driving of the current gate line group is completed.

17. A method for driving an array substrate according to any one of claims 1 to 11, wherein: Four adjacent gate lines are formed into a gate line group, the same data line corresponding to the odd-numbered gate lines is connected to sub-pixels of the same color, and the same data line corresponding to the even-numbered gate lines is connected to sub-pixels of the same color, and the driving method includes: The gate line groups are sequentially driven, and the first gate line, the third gate line, the second gate line, and the fourth gate line are sequentially driven in the same gate line group; the driving time lengths of two adjacent gate lines are partially the same; wherein, Before the first gate line is driven and during the third gate line driving process, the first data signal starts to be input to the data line, and the input of the first data signal is stopped after the third gate line is driven; and before the second gate line is driven and during the fourth gate line driving process, the second data signal starts to be input to the data line, and the input of the second data signal is stopped after the fourth gate line is driven, and the input time of the first data signal and the input time of the second data signal are staggered.

Images